MdeModulePkg/Bus/Ata/AtaAtapiPassThru/IdeMode.h

   1 /** @file
   2   Header file for IDE mode of ATA host controller.
   3
   4   Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14 #ifndef __ATA_HC_IDE_MODE_H__
  15 #define __ATA_HC_IDE_MODE_H__
  16
  17 typedef enum {
  18   EfiIdePrimary    = 0,
  19   EfiIdeSecondary  = 1,
  20   EfiIdeMaxChannel = 2
  21 } EFI_IDE_CHANNEL;
  22
  23 typedef enum {
  24   EfiIdeMaster    = 0,
  25   EfiIdeSlave     = 1,
  26   EfiIdeMaxDevice = 2
  27 } EFI_IDE_DEVICE;
  28
  29 ///
  30 /// PIO mode definition
  31 ///
  32 typedef enum {
  33   EfiAtaPioModeBelow2,
  34   EfiAtaPioMode2,
  35   EfiAtaPioMode3,
  36   EfiAtaPioMode4
  37 } EFI_ATA_PIO_MODE;
  38
  39 //
  40 // Multi word DMA definition
  41 //
  42 typedef enum {
  43   EfiAtaMdmaMode0,
  44   EfiAtaMdmaMode1,
  45   EfiAtaMdmaMode2
  46 } EFI_ATA_MDMA_MODE;
  47
  48 //
  49 // UDMA mode definition
  50 //
  51 typedef enum {
  52   EfiAtaUdmaMode0,
  53   EfiAtaUdmaMode1,
  54   EfiAtaUdmaMode2,
  55   EfiAtaUdmaMode3,
  56   EfiAtaUdmaMode4,
  57   EfiAtaUdmaMode5
  58 } EFI_ATA_UDMA_MODE;
  59
  60 //
  61 // Bus Master Reg
  62 //
  63 #define BMIC_NREAD      BIT3
  64 #define BMIC_START      BIT0
  65 #define BMIS_INTERRUPT  BIT2
  66 #define BMIS_ERROR      BIT1
  67
  68 #define BMIC_OFFSET    0x00
  69 #define BMIS_OFFSET    0x02
  70 #define BMID_OFFSET    0x04
  71
  72 //
  73 // IDE transfer mode
  74 //
  75 #define EFI_ATA_MODE_DEFAULT_PIO 0x00
  76 #define EFI_ATA_MODE_FLOW_PIO    0x01
  77 #define EFI_ATA_MODE_MDMA        0x04
  78 #define EFI_ATA_MODE_UDMA        0x08
  79
  80 typedef struct {
  81   UINT32  RegionBaseAddr;
  82   UINT16  ByteCount;
  83   UINT16  EndOfTable;
  84 } EFI_ATA_DMA_PRD;
  85
  86 typedef struct {
  87   UINT8 ModeNumber   : 3;
  88   UINT8 ModeCategory : 5;
  89 } EFI_ATA_TRANSFER_MODE;
  90
  91 typedef struct {
  92   UINT8 Sector;
  93   UINT8 Heads;
  94   UINT8 MultipleSector;
  95 } EFI_ATA_DRIVE_PARMS;
  96
  97 //
  98 // IDE registers set
  99 //
 100 typedef struct {
 101   UINT16                          Data;
 102   UINT16                          ErrOrFeature;
 103   UINT16                          SectorCount;
 104   UINT16                          SectorNumber;
 105   UINT16                          CylinderLsb;
 106   UINT16                          CylinderMsb;
 107   UINT16                          Head;
 108   UINT16                          CmdOrStatus;
 109   UINT16                          AltOrDev;
 110
 111   UINT16                          BusMasterBaseAddr;
 112 } EFI_IDE_REGISTERS;
 113
 114 //
 115 // Bit definitions in Programming Interface byte of the Class Code field
 116 // in PCI IDE controller's Configuration Space
 117 //
 118 #define IDE_PRIMARY_OPERATING_MODE            BIT0
 119 #define IDE_PRIMARY_PROGRAMMABLE_INDICATOR    BIT1
 120 #define IDE_SECONDARY_OPERATING_MODE          BIT2
 121 #define IDE_SECONDARY_PROGRAMMABLE_INDICATOR  BIT3
 122
 123 /**
 124   Get IDE i/o port registers' base addresses by mode.
 125
 126   In 'Compatibility' mode, use fixed addresses.
 127   In Native-PCI mode, get base addresses from BARs in the PCI IDE controller's
 128   Configuration Space.
 129
 130   The steps to get IDE i/o port registers' base addresses for each channel
 131   as follows:
 132
 133   1. Examine the Programming Interface byte of the Class Code fields in PCI IDE
 134   controller's Configuration Space to determine the operating mode.
 135
 136   2. a) In 'Compatibility' mode, use fixed addresses shown in the Table 1 below.
 137    ___________________________________________
 138   |           | Command Block | Control Block |
 139   |  Channel  |   Registers   |   Registers   |
 140   |___________|_______________|_______________|
 141   |  Primary  |  1F0h - 1F7h  |  3F6h - 3F7h  |
 142   |___________|_______________|_______________|
 143   | Secondary |  170h - 177h  |  376h - 377h  |
 144   |___________|_______________|_______________|
 145
 146   Table 1. Compatibility resource mappings
 147
 148   b) In Native-PCI mode, IDE registers are mapped into IO space using the BARs
 149   in IDE controller's PCI Configuration Space, shown in the Table 2 below.
 150    ___________________________________________________
 151   |           |   Command Block   |   Control Block   |
 152   |  Channel  |     Registers     |     Registers     |
 153   |___________|___________________|___________________|
 154   |  Primary  | BAR at offset 0x10| BAR at offset 0x14|
 155   |___________|___________________|___________________|
 156   | Secondary | BAR at offset 0x18| BAR at offset 0x1C|
 157   |___________|___________________|___________________|
 158
 159   Table 2. BARs for Register Mapping
 160
 161   @param[in]      PciIo          Pointer to the EFI_PCI_IO_PROTOCOL instance
 162   @param[in, out] IdeRegisters   Pointer to EFI_IDE_REGISTERS which is used to
 163                                  store the IDE i/o port registers' base addresses
 164
 165   @retval EFI_UNSUPPORTED        Return this value when the BARs is not IO type
 166   @retval EFI_SUCCESS            Get the Base address successfully
 167   @retval Other                  Read the pci configureation data error
 168
 169 **/
 170 EFI_STATUS
 171 EFIAPI
 172 GetIdeRegisterIoAddr (
 173   IN     EFI_PCI_IO_PROTOCOL         *PciIo,
 174   IN OUT EFI_IDE_REGISTERS           *IdeRegisters
 175   );
 176
 177 /**
 178   This function is used to send out ATAPI commands conforms to the Packet Command
 179   with PIO Data In Protocol.
 180
 181   @param[in] PciIo          Pointer to the EFI_PCI_IO_PROTOCOL instance
 182   @param[in] IdeRegisters   Pointer to EFI_IDE_REGISTERS which is used to
 183                             store the IDE i/o port registers' base addresses
 184   @param[in] Channel        The channel number of device.
 185   @param[in] Device         The device number of device.
 186   @param[in] Packet         A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET data structure.
 187
 188   @retval EFI_SUCCESS       send out the ATAPI packet command successfully
 189                             and device sends data successfully.
 190   @retval EFI_DEVICE_ERROR  the device failed to send data.
 191
 192 **/
 193 EFI_STATUS
 194 EFIAPI
 195 AtaPacketCommandExecute (
 196   IN  EFI_PCI_IO_PROTOCOL                           *PciIo,
 197   IN  EFI_IDE_REGISTERS                             *IdeRegisters,
 198   IN  UINT8                                         Channel,
 199   IN  UINT8                                         Device,
 200   IN  EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET    *Packet
 201   );
 202
 203 #endif
 204