MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h

   1 /** @file
   2
   3 Copyright (c) 2006 - 2007, Intel Corporation
   4 All rights reserved. This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 Module Name:
  13
  14     Ehci.h
  15
  16 Abstract:
  17
  18
  19 Revision History
  20
  21 **/
  22
  23 #ifndef _EFI_EHCI_H_
  24 #define _EFI_EHCI_H_
  25
  26
  27 #include <PiDxe.h>
  28
  29 #include <Protocol/Usb2HostController.h>
  30 #include <Protocol/PciIo.h>
  31
  32 #include <Library/DebugLib.h>
  33 #include <Library/BaseMemoryLib.h>
  34 #include <Library/UefiDriverEntryPoint.h>
  35 #include <Library/UefiBootServicesTableLib.h>
  36 #include <Library/UefiLib.h>
  37 #include <Library/BaseLib.h>
  38 #include <Library/MemoryAllocationLib.h>
  39
  40
  41 #include <IndustryStandard/Pci22.h>
  42
  43 typedef struct _USB2_HC_DEV  USB2_HC_DEV;
  44
  45 #include "UsbHcMem.h"
  46 #include "EhciReg.h"
  47 #include "EhciUrb.h"
  48 #include "EhciSched.h"
  49 #include "EhciDebug.h"
  50
  51 enum {
  52   EHC_1_MICROSECOND            = 1,
  53   EHC_1_MILLISECOND            = 1000 * EHC_1_MICROSECOND,
  54   EHC_1_SECOND                 = 1000 * EHC_1_MILLISECOND,
  55
  56   //
  57   // EHCI register operation timeout, set by experience
  58   //
  59   EHC_RESET_TIMEOUT            = 1 * EHC_1_SECOND,
  60   EHC_GENERIC_TIMEOUT          = 10 * EHC_1_MILLISECOND,
  61
  62   //
  63   // Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]
  64   //
  65   EHC_ROOT_PORT_RECOVERY_STALL = 20 * EHC_1_MILLISECOND,
  66
  67   //
  68   // Sync and Async transfer polling interval, set by experience,
  69   // and the unit of Async is 100us, means 50ms as interval.
  70   //
  71   EHC_SYNC_POLL_INTERVAL       = 20 * EHC_1_MICROSECOND,
  72   EHC_ASYNC_POLL_INTERVAL      = 50 * 10000U,
  73
  74   //
  75   // EHC raises TPL to TPL_NOTIFY to serialize all its operations
  76   // to protect shared data structures.
  77   //
  78   EHC_TPL                      = TPL_NOTIFY,
  79
  80   USB2_HC_DEV_SIGNATURE        = EFI_SIGNATURE_32 ('e', 'h', 'c', 'i')
  81 };
  82
  83 //
  84 //Iterate through the doule linked list. NOT delete safe
  85 //
  86 #define EFI_LIST_FOR_EACH(Entry, ListHead)    \
  87   for(Entry = (ListHead)->ForwardLink; Entry != (ListHead); Entry = Entry->ForwardLink)
  88
  89 //
  90 //Iterate through the doule linked list. This is delete-safe.
  91 //Don't touch NextEntry
  92 //
  93 #define EFI_LIST_FOR_EACH_SAFE(Entry, NextEntry, ListHead)            \
  94   for(Entry = (ListHead)->ForwardLink, NextEntry = Entry->ForwardLink;\
  95       Entry != (ListHead); Entry = NextEntry, NextEntry = Entry->ForwardLink)
  96
  97 #define EFI_LIST_CONTAINER(Entry, Type, Field) _CR(Entry, Type, Field)
  98
  99
 100 #define EHC_LOW_32BIT(Addr64)     ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
 101 #define EHC_HIGH_32BIT(Addr64)    ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
 102 #define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
 103
 104 #define EHC_REG_BIT_IS_SET(Ehc, Offset, Bit) \
 105           (EHC_BIT_IS_SET(EhcReadOpReg ((Ehc), (Offset)), (Bit)))
 106
 107 #define EHC_FROM_THIS(a)   CR(a, USB2_HC_DEV, Usb2Hc, USB2_HC_DEV_SIGNATURE)
 108
 109 struct _USB2_HC_DEV {
 110   UINTN                     Signature;
 111   EFI_USB2_HC_PROTOCOL      Usb2Hc;
 112
 113   EFI_PCI_IO_PROTOCOL       *PciIo;
 114   USBHC_MEM_POOL            *MemPool;
 115
 116   //
 117   // Schedule data shared between asynchronous and periodic
 118   // transfers:
 119   // ShortReadStop, as its name indicates, is used to terminate
 120   // the short read except the control transfer. EHCI follows
 121   // the alternative next QTD point when a short read happens.
 122   // For control transfer, even the short read happens, try the
 123   // status stage.
 124   //
 125   EHC_QTD                  *ShortReadStop;
 126   EFI_EVENT                 PollTimer;
 127
 128   //
 129   // Asynchronous(bulk and control) transfer schedule data:
 130   // ReclaimHead is used as the head of the asynchronous transfer
 131   // list. It acts as the reclamation header.
 132   //
 133   EHC_QH                   *ReclaimHead;
 134
 135   //
 136   // Peroidic (interrupt) transfer schedule data:
 137   //
 138   VOID                      *PeriodFrame;     // Mapped as common buffer
 139   VOID                      *PeriodFrameHost;
 140   VOID                      *PeriodFrameMap;
 141
 142   EHC_QH                    *PeriodOne;
 143   LIST_ENTRY                AsyncIntTransfers;
 144
 145   //
 146   // EHCI configuration data
 147   //
 148   UINT32                    HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET
 149   UINT32                    HcCapParams;    // Cache of HC capability parameter, HCCPARAMS
 150   UINT32                    CapLen;         // Capability length
 151   UINT32                    High32bitAddr;
 152
 153   //
 154   // Misc
 155   //
 156   EFI_UNICODE_STRING_TABLE  *ControllerNameTable;
 157 };
 158
 159
 160 extern EFI_DRIVER_BINDING_PROTOCOL      gEhciDriverBinding;
 161 extern EFI_COMPONENT_NAME_PROTOCOL      gEhciComponentName;
 162 extern EFI_COMPONENT_NAME2_PROTOCOL     gEhciComponentName2;
 163
 164 #endif