MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h

   1 /** @file
   2
   3 Copyright (c) 2007, Intel Corporation
   4 All rights reserved. This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 Module Name:
  13
  14   EhciReg.h
  15
  16 Abstract:
  17
  18   This file contains the definination for host controller register operation routines
  19
  20 Revision History
  21
  22 **/
  23
  24 #ifndef _EFI_EHCI_REG_H_
  25 #define _EFI_EHCI_REG_H_
  26
  27
  28 enum {
  29   //
  30   // Capability register offset
  31   //
  32   EHC_CAPLENGTH_OFFSET    = 0,    // Capability register length offset
  33   EHC_HCSPARAMS_OFFSET    = 0x04, // Structural Parameters 04-07h
  34   EHC_HCCPARAMS_OFFSET    = 0x08, // Capability parameters offset
  35
  36   //
  37   // Capability register bit definition
  38   //
  39   HCSP_NPORTS             = 0x0F, // Number of root hub port
  40   HCCP_64BIT              = 0x01, // 64-bit addressing capability
  41
  42   //
  43   // Operational register offset
  44   //
  45   EHC_USBCMD_OFFSET       = 0x0,  // USB command register offset
  46   EHC_USBSTS_OFFSET       = 0x04, // Statue register offset
  47   EHC_USBINTR_OFFSET      = 0x08, // USB interrutp offset
  48   EHC_FRINDEX_OFFSET      = 0x0C, // Frame index offset
  49   EHC_CTRLDSSEG_OFFSET    = 0x10, // Control data structure segment offset
  50   EHC_FRAME_BASE_OFFSET   = 0x14, // Frame list base address offset
  51   EHC_ASYNC_HEAD_OFFSET   = 0x18, // Next asynchronous list address offset
  52   EHC_CONFIG_FLAG_OFFSET  = 0x40, // Configure flag register offset
  53   EHC_PORT_STAT_OFFSET    = 0x44, // Port status/control offset
  54
  55   EHC_FRAME_LEN           = 1024,
  56
  57   //
  58   // Register bit definition
  59   //
  60   CONFIGFLAG_ROUTE_EHC    = 0x01, // Route port to EHC
  61
  62   USBCMD_RUN              = 0x01,   // Run/stop
  63   USBCMD_RESET            = 0x02,   // Start the host controller reset
  64   USBCMD_ENABLE_PERIOD    = 0x10,   // Enable periodic schedule
  65   USBCMD_ENABLE_ASYNC     = 0x20,   // Enable asynchronous schedule
  66   USBCMD_IAAD             = 0x40,   // Interrupt on async advance doorbell
  67
  68   USBSTS_IAA              = 0x20,   // Interrupt on async advance
  69   USBSTS_PERIOD_ENABLED   = 0x4000, // Periodic schedule status
  70   USBSTS_ASYNC_ENABLED    = 0x8000, // Asynchronous schedule status
  71   USBSTS_HALT             = 0x1000, // Host controller halted
  72   USBSTS_SYS_ERROR        = 0x10,   // Host system error
  73   USBSTS_INTACK_MASK      = 0x003F, // Mask for the interrupt ACK, the WC
  74                                     // (write clean) bits in USBSTS register
  75
  76   PORTSC_CONN             = 0x01,   // Current Connect Status
  77   PORTSC_CONN_CHANGE      = 0x02,   // Connect Status Change
  78   PORTSC_ENABLED          = 0x04,   // Port Enable / Disable
  79   PORTSC_ENABLE_CHANGE    = 0x08,   // Port Enable / Disable Change
  80   PORTSC_OVERCUR          = 0x10,   // Over current Active
  81   PORTSC_OVERCUR_CHANGE   = 0x20,   // Over current Change
  82   PORSTSC_RESUME          = 0x40,   // Force Port Resume
  83   PORTSC_SUSPEND          = 0x80,   // Port Suspend State
  84   PORTSC_RESET            = 0x100,  // Port Reset
  85   PORTSC_LINESTATE_K      = 0x400,  // Line Status K-state
  86   PORTSC_LINESTATE_J      = 0x800,  // Line Status J-state
  87   PORTSC_POWER            = 0x1000, // Port Power
  88   PORTSC_OWNER            = 0x2000, // Port Owner
  89   PORTSC_CHANGE_MASK      = 0x2A,   // Mask of the port change bits,
  90                                     // they are WC (write clean)
  91   //
  92   // PCI Configuration Registers
  93   //
  94   EHC_PCI_CLASSC          = 0x09,
  95   EHC_PCI_CLASSC_PI       = 0x20,
  96   EHC_BAR_INDEX           = 0, /* how many bytes away from USB_BASE to 0x10 */
  97 };
  98
  99 #define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
 100
 101 #define EHC_ADDR(High, QhHw32)   \
 102         ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))
 103
 104 #define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
 105
 106 //
 107 // Structure to map the hardware port states to the
 108 // UEFI's port states.
 109 //
 110 typedef struct {
 111   UINT16                  HwState;
 112   UINT16                  UefiState;
 113 } USB_PORT_STATE_MAP;
 114
 115 //
 116 // Ehci Data and Ctrl Structures
 117 //
 118 #pragma pack(1)
 119 typedef struct {
 120   UINT8                   PI;
 121   UINT8                   SubClassCode;
 122   UINT8                   BaseCode;
 123 } USB_CLASSC;
 124 #pragma pack()
 125
 126
 127 UINT32
 128 EhcReadCapRegister (
 129   IN  USB2_HC_DEV         *Ehc,
 130   IN  UINT32              Offset
 131   )
 132 /*++
 133
 134 Routine Description:
 135
 136   Read  EHCI capability register
 137
 138 Arguments:
 139
 140   Ehc     - The Ehc device
 141   Offset  - Capability register address
 142
 143 Returns:
 144
 145   The register content read
 146
 147 --*/
 148 ;
 149
 150
 151 /**
 152   Read  Ehc Operation register
 153
 154   @param  Ehc      The EHCI device
 155   @param  Offset   The operation register offset
 156
 157   @return The register content read
 158
 159 **/
 160 UINT32
 161 EhcReadOpReg (
 162   IN  USB2_HC_DEV         *Ehc,
 163   IN  UINT32              Offset
 164   )
 165 ;
 166
 167
 168 /**
 169   Write  the data to the EHCI operation register
 170
 171   @param  Ehc      The EHCI device
 172   @param  Offset   EHCI operation register offset
 173   @param  Data     The data to write
 174
 175   @return None
 176
 177 **/
 178 VOID
 179 EhcWriteOpReg (
 180   IN USB2_HC_DEV          *Ehc,
 181   IN UINT32               Offset,
 182   IN UINT32               Data
 183   )
 184 ;
 185
 186
 187 /**
 188   Add support for UEFI Over Legacy (UoL) feature, stop
 189   the legacy USB SMI support
 190
 191   @param  Ehc      The EHCI device.
 192
 193   @return None
 194
 195 **/
 196 VOID
 197 EhcClearLegacySupport (
 198   IN USB2_HC_DEV          *Ehc
 199   )
 200 ;
 201
 202
 203
 204 /**
 205   Set door bell and wait it to be ACKed by host controller.
 206   This function is used to synchronize with the hardware.
 207
 208   @param  Ehc      The EHCI device
 209   @param  Timeout  The time to wait before abort (in millisecond, ms)
 210
 211   @return EFI_SUCCESS : Synchronized with the hardware
 212   @return EFI_TIMEOUT : Time out happened while waiting door bell to set
 213
 214 **/
 215 EFI_STATUS
 216 EhcSetAndWaitDoorBell (
 217   IN  USB2_HC_DEV         *Ehc,
 218   IN  UINT32               Timeout
 219   )
 220 ;
 221
 222
 223 /**
 224   Clear all the interrutp status bits, these bits
 225   are Write-Clean
 226
 227   @param  Ehc      The EHCI device
 228
 229   @return None
 230
 231 **/
 232 VOID
 233 EhcAckAllInterrupt (
 234   IN  USB2_HC_DEV         *Ehc
 235   )
 236 ;
 237
 238
 239
 240 /**
 241   Whether Ehc is halted
 242
 243   @param  Ehc      The EHCI device
 244
 245   @return TRUE  : The controller is halted
 246   @return FALSE : It isn't halted
 247
 248 **/
 249 BOOLEAN
 250 EhcIsHalt (
 251   IN USB2_HC_DEV          *Ehc
 252   )
 253 ;
 254
 255
 256 /**
 257   Whether system error occurred
 258
 259   @param  Ehc      The EHCI device
 260
 261   @return TRUE  : System error happened
 262   @return FALSE : No system error
 263
 264 **/
 265 BOOLEAN
 266 EhcIsSysError (
 267   IN USB2_HC_DEV          *Ehc
 268   )
 269 ;
 270
 271
 272
 273 /**
 274   Reset the host controller
 275
 276   @param  Ehc      The EHCI device
 277   @param  Timeout  Time to wait before abort (in millisecond, ms)
 278
 279   @return EFI_SUCCESS : The host controller is reset
 280   @return Others      : Failed to reset the host
 281
 282 **/
 283 EFI_STATUS
 284 EhcResetHC (
 285   IN USB2_HC_DEV          *Ehc,
 286   IN UINT32               Timeout
 287   )
 288 ;
 289
 290
 291
 292 /**
 293   Halt the host controller
 294
 295   @param  Ehc      The EHCI device
 296   @param  Timeout  Time to wait before abort
 297
 298   @return EFI_SUCCESS : The EHCI is halt
 299   @return EFI_TIMEOUT : Failed to halt the controller before Timeout
 300
 301 **/
 302 EFI_STATUS
 303 EhcHaltHC (
 304   IN USB2_HC_DEV         *Ehc,
 305   IN UINT32              Timeout
 306   )
 307 ;
 308
 309
 310
 311 /**
 312   Set the EHCI to run
 313
 314   @param  Ehc      The EHCI device
 315   @param  Timeout  Time to wait before abort
 316
 317   @return EFI_SUCCESS : The EHCI is running
 318   @return Others      : Failed to set the EHCI to run
 319
 320 **/
 321 EFI_STATUS
 322 EhcRunHC (
 323   IN USB2_HC_DEV          *Ehc,
 324   IN UINT32               Timeout
 325   )
 326 ;
 327
 328
 329
 330 /**
 331   Initialize the HC hardware.
 332   EHCI spec lists the five things to do to initialize the hardware
 333   1. Program CTRLDSSEGMENT
 334   2. Set USBINTR to enable interrupts
 335   3. Set periodic list base
 336   4. Set USBCMD, interrupt threshold, frame list size etc
 337   5. Write 1 to CONFIGFLAG to route all ports to EHCI
 338
 339   @param  Ehc      The EHCI device
 340
 341   @return EFI_SUCCESS : The EHCI has come out of halt state
 342   @return EFI_TIMEOUT : Time out happened
 343
 344 **/
 345 EFI_STATUS
 346 EhcInitHC (
 347   IN USB2_HC_DEV          *Ehc
 348   )
 349 ;
 350
 351 #endif