MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h

   1 /** @file
   2
   3   This file contains the definination for host controller register operation routines.
   4
   5 Copyright (c) 2007 - 2010, Intel Corporation
   6 All rights reserved. This program and the accompanying materials
   7 are licensed and made available under the terms and conditions of the BSD License
   8 which accompanies this distribution.  The full text of the license may be found at
   9 http://opensource.org/licenses/bsd-license.php
  10
  11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef _EFI_EHCI_REG_H_
  17 #define _EFI_EHCI_REG_H_
  18
  19 //
  20 // EHCI register offset
  21 //
  22
  23
  24 //
  25 // Capability register offset
  26 //
  27 #define EHC_CAPLENGTH_OFFSET    0    // Capability register length offset
  28 #define EHC_HCSPARAMS_OFFSET    0x04 // Structural Parameters 04-07h
  29 #define EHC_HCCPARAMS_OFFSET    0x08 // Capability parameters offset
  30
  31 //
  32 // Capability register bit definition
  33 //
  34 #define HCSP_NPORTS             0x0F // Number of root hub port
  35 #define HCCP_64BIT              0x01 // 64-bit addressing capability
  36
  37 //
  38 // Operational register offset
  39 //
  40 #define EHC_USBCMD_OFFSET       0x0  // USB command register offset
  41 #define EHC_USBSTS_OFFSET       0x04 // Statue register offset
  42 #define EHC_USBINTR_OFFSET      0x08 // USB interrutp offset
  43 #define EHC_FRINDEX_OFFSET      0x0C // Frame index offset
  44 #define EHC_CTRLDSSEG_OFFSET    0x10 // Control data structure segment offset
  45 #define EHC_FRAME_BASE_OFFSET   0x14 // Frame list base address offset
  46 #define EHC_ASYNC_HEAD_OFFSET   0x18 // Next asynchronous list address offset
  47 #define EHC_CONFIG_FLAG_OFFSET  0x40 // Configure flag register offset
  48 #define EHC_PORT_STAT_OFFSET    0x44 // Port status/control offset
  49
  50 #define EHC_FRAME_LEN           1024
  51
  52 //
  53 // Register bit definition
  54 //
  55 #define CONFIGFLAG_ROUTE_EHC    0x01 // Route port to EHC
  56
  57 #define USBCMD_RUN              0x01   // Run/stop
  58 #define USBCMD_RESET            0x02   // Start the host controller reset
  59 #define USBCMD_ENABLE_PERIOD    0x10   // Enable periodic schedule
  60 #define USBCMD_ENABLE_ASYNC     0x20   // Enable asynchronous schedule
  61 #define USBCMD_IAAD             0x40   // Interrupt on async advance doorbell
  62
  63 #define USBSTS_IAA              0x20   // Interrupt on async advance
  64 #define USBSTS_PERIOD_ENABLED   0x4000 // Periodic schedule status
  65 #define USBSTS_ASYNC_ENABLED    0x8000 // Asynchronous schedule status
  66 #define USBSTS_HALT             0x1000 // Host controller halted
  67 #define USBSTS_SYS_ERROR        0x10   // Host system error
  68 #define USBSTS_INTACK_MASK      0x003F // Mask for the interrupt ACK, the WC
  69                                        // (write clean) bits in USBSTS register
  70
  71 #define PORTSC_CONN             0x01   // Current Connect Status
  72 #define PORTSC_CONN_CHANGE      0x02   // Connect Status Change
  73 #define PORTSC_ENABLED          0x04   // Port Enable / Disable
  74 #define PORTSC_ENABLE_CHANGE    0x08   // Port Enable / Disable Change
  75 #define PORTSC_OVERCUR          0x10   // Over current Active
  76 #define PORTSC_OVERCUR_CHANGE   0x20   // Over current Change
  77 #define PORSTSC_RESUME          0x40   // Force Port Resume
  78 #define PORTSC_SUSPEND          0x80   // Port Suspend State
  79 #define PORTSC_RESET            0x100  // Port Reset
  80 #define PORTSC_LINESTATE_K      0x400  // Line Status K-state
  81 #define PORTSC_LINESTATE_J      0x800  // Line Status J-state
  82 #define PORTSC_POWER            0x1000 // Port Power
  83 #define PORTSC_OWNER            0x2000 // Port Owner
  84 #define PORTSC_CHANGE_MASK      0x2A   // Mask of the port change bits,
  85                                        // they are WC (write clean)
  86 //
  87 // PCI Configuration Registers
  88 //
  89 #define EHC_BAR_INDEX           0      // how many bytes away from USB_BASE to 0x10
  90
  91 #define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
  92
  93 #define EHC_ADDR(High, QhHw32)   \
  94         ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))
  95
  96 #define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
  97
  98 //
  99 // Structure to map the hardware port states to the
 100 // UEFI's port states.
 101 //
 102 typedef struct {
 103   UINT16                  HwState;
 104   UINT16                  UefiState;
 105 } USB_PORT_STATE_MAP;
 106
 107 //
 108 // Ehci Data and Ctrl Structures
 109 //
 110 #pragma pack(1)
 111 typedef struct {
 112   UINT8                   ProgInterface;
 113   UINT8                   SubClassCode;
 114   UINT8                   BaseCode;
 115 } USB_CLASSC;
 116 #pragma pack()
 117
 118 /**
 119   Read EHCI capability register.
 120
 121   @param  Ehc     The EHCI device.
 122   @param  Offset  Capability register address.
 123
 124   @return The register content.
 125
 126 **/
 127 UINT32
 128 EhcReadCapRegister (
 129   IN  USB2_HC_DEV         *Ehc,
 130   IN  UINT32              Offset
 131   );
 132
 133
 134 /**
 135   Read EHCI Operation register.
 136
 137   @param  Ehc      The EHCI device.
 138   @param  Offset   The operation register offset.
 139
 140   @return The register content.
 141
 142 **/
 143 UINT32
 144 EhcReadOpReg (
 145   IN  USB2_HC_DEV         *Ehc,
 146   IN  UINT32              Offset
 147   );
 148
 149
 150 /**
 151   Write  the data to the EHCI operation register.
 152
 153   @param  Ehc      The EHCI device.
 154   @param  Offset   EHCI operation register offset.
 155   @param  Data     The data to write.
 156
 157 **/
 158 VOID
 159 EhcWriteOpReg (
 160   IN USB2_HC_DEV          *Ehc,
 161   IN UINT32               Offset,
 162   IN UINT32               Data
 163   );
 164
 165 /**
 166   Set one bit of the operational register while keeping other bits.
 167
 168   @param  Ehc          The EHCI device.
 169   @param  Offset       The offset of the operational register.
 170   @param  Bit          The bit mask of the register to set.
 171
 172 **/
 173 VOID
 174 EhcSetOpRegBit (
 175   IN USB2_HC_DEV          *Ehc,
 176   IN UINT32               Offset,
 177   IN UINT32               Bit
 178   );
 179
 180 /**
 181   Clear one bit of the operational register while keeping other bits.
 182
 183   @param  Ehc          The EHCI device.
 184   @param  Offset       The offset of the operational register.
 185   @param  Bit          The bit mask of the register to clear.
 186
 187 **/
 188 VOID
 189 EhcClearOpRegBit (
 190   IN USB2_HC_DEV          *Ehc,
 191   IN UINT32               Offset,
 192   IN UINT32               Bit
 193   );
 194
 195 /**
 196   Add support for UEFI Over Legacy (UoL) feature, stop
 197   the legacy USB SMI support.
 198
 199   @param  Ehc      The EHCI device.
 200
 201 **/
 202 VOID
 203 EhcClearLegacySupport (
 204   IN USB2_HC_DEV          *Ehc
 205   );
 206
 207
 208
 209 /**
 210   Set door bell and wait it to be ACKed by host controller.
 211   This function is used to synchronize with the hardware.
 212
 213   @param  Ehc          The EHCI device.
 214   @param  Timeout      The time to wait before abort (in millisecond, ms).
 215
 216   @retval EFI_SUCCESS  Synchronized with the hardware.
 217   @retval EFI_TIMEOUT  Time out happened while waiting door bell to set.
 218
 219 **/
 220 EFI_STATUS
 221 EhcSetAndWaitDoorBell (
 222   IN  USB2_HC_DEV         *Ehc,
 223   IN  UINT32               Timeout
 224   );
 225
 226
 227 /**
 228   Clear all the interrutp status bits, these bits are Write-Clean.
 229
 230   @param  Ehc      The EHCI device.
 231
 232 **/
 233 VOID
 234 EhcAckAllInterrupt (
 235   IN  USB2_HC_DEV         *Ehc
 236   );
 237
 238
 239
 240 /**
 241   Whether Ehc is halted.
 242
 243   @param  Ehc     The EHCI device.
 244
 245   @retval TRUE    The controller is halted.
 246   @retval FALSE   It isn't halted.
 247
 248 **/
 249 BOOLEAN
 250 EhcIsHalt (
 251   IN USB2_HC_DEV          *Ehc
 252   );
 253
 254
 255 /**
 256   Whether system error occurred.
 257
 258   @param  Ehc      The EHCI device.
 259
 260   @retval TRUE     System error happened.
 261   @retval FALSE    No system error.
 262
 263 **/
 264 BOOLEAN
 265 EhcIsSysError (
 266   IN USB2_HC_DEV          *Ehc
 267   );
 268
 269
 270 /**
 271   Reset the host controller.
 272
 273   @param  Ehc          The EHCI device.
 274   @param  Timeout      Time to wait before abort (in millisecond, ms).
 275
 276   @retval EFI_SUCCESS  The host controller is reset.
 277   @return Others       Failed to reset the host.
 278
 279 **/
 280 EFI_STATUS
 281 EhcResetHC (
 282   IN USB2_HC_DEV          *Ehc,
 283   IN UINT32               Timeout
 284   );
 285
 286
 287 /**
 288   Halt the host controller.
 289
 290   @param  Ehc          The EHCI device.
 291   @param  Timeout      Time to wait before abort.
 292
 293   @return EFI_SUCCESS  The EHCI is halt.
 294   @return EFI_TIMEOUT  Failed to halt the controller before Timeout.
 295
 296 **/
 297 EFI_STATUS
 298 EhcHaltHC (
 299   IN USB2_HC_DEV         *Ehc,
 300   IN UINT32              Timeout
 301   );
 302
 303
 304 /**
 305   Set the EHCI to run.
 306
 307   @param  Ehc          The EHCI device.
 308   @param  Timeout      Time to wait before abort.
 309
 310   @return EFI_SUCCESS  The EHCI is running.
 311   @return Others       Failed to set the EHCI to run.
 312
 313 **/
 314 EFI_STATUS
 315 EhcRunHC (
 316   IN USB2_HC_DEV          *Ehc,
 317   IN UINT32               Timeout
 318   );
 319
 320
 321
 322 /**
 323   Initialize the HC hardware.
 324   EHCI spec lists the five things to do to initialize the hardware:
 325   1. Program CTRLDSSEGMENT
 326   2. Set USBINTR to enable interrupts
 327   3. Set periodic list base
 328   4. Set USBCMD, interrupt threshold, frame list size etc
 329   5. Write 1 to CONFIGFLAG to route all ports to EHCI
 330
 331   @param  Ehc          The EHCI device.
 332
 333   @return EFI_SUCCESS  The EHCI has come out of halt state.
 334   @return EFI_TIMEOUT  Time out happened.
 335
 336 **/
 337 EFI_STATUS
 338 EhcInitHC (
 339   IN USB2_HC_DEV          *Ehc
 340   );
 341
 342 #endif