MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h

   1 /** @file
   2
   3   This file contains the definination for host controller register operation routines.
   4
   5 Copyright (c) 2007, Intel Corporation
   6 All rights reserved. This program and the accompanying materials
   7 are licensed and made available under the terms and conditions of the BSD License
   8 which accompanies this distribution.  The full text of the license may be found at
   9 http://opensource.org/licenses/bsd-license.php
  10
  11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef _EFI_EHCI_REG_H_
  17 #define _EFI_EHCI_REG_H_
  18
  19
  20 typedef enum {
  21   //
  22   // Capability register offset
  23   //
  24   EHC_CAPLENGTH_OFFSET    = 0,    // Capability register length offset
  25   EHC_HCSPARAMS_OFFSET    = 0x04, // Structural Parameters 04-07h
  26   EHC_HCCPARAMS_OFFSET    = 0x08, // Capability parameters offset
  27
  28   //
  29   // Capability register bit definition
  30   //
  31   HCSP_NPORTS             = 0x0F, // Number of root hub port
  32   HCCP_64BIT              = 0x01, // 64-bit addressing capability
  33
  34   //
  35   // Operational register offset
  36   //
  37   EHC_USBCMD_OFFSET       = 0x0,  // USB command register offset
  38   EHC_USBSTS_OFFSET       = 0x04, // Statue register offset
  39   EHC_USBINTR_OFFSET      = 0x08, // USB interrutp offset
  40   EHC_FRINDEX_OFFSET      = 0x0C, // Frame index offset
  41   EHC_CTRLDSSEG_OFFSET    = 0x10, // Control data structure segment offset
  42   EHC_FRAME_BASE_OFFSET   = 0x14, // Frame list base address offset
  43   EHC_ASYNC_HEAD_OFFSET   = 0x18, // Next asynchronous list address offset
  44   EHC_CONFIG_FLAG_OFFSET  = 0x40, // Configure flag register offset
  45   EHC_PORT_STAT_OFFSET    = 0x44, // Port status/control offset
  46
  47   EHC_FRAME_LEN           = 1024,
  48
  49   //
  50   // Register bit definition
  51   //
  52   CONFIGFLAG_ROUTE_EHC    = 0x01, // Route port to EHC
  53
  54   USBCMD_RUN              = 0x01,   // Run/stop
  55   USBCMD_RESET            = 0x02,   // Start the host controller reset
  56   USBCMD_ENABLE_PERIOD    = 0x10,   // Enable periodic schedule
  57   USBCMD_ENABLE_ASYNC     = 0x20,   // Enable asynchronous schedule
  58   USBCMD_IAAD             = 0x40,   // Interrupt on async advance doorbell
  59
  60   USBSTS_IAA              = 0x20,   // Interrupt on async advance
  61   USBSTS_PERIOD_ENABLED   = 0x4000, // Periodic schedule status
  62   USBSTS_ASYNC_ENABLED    = 0x8000, // Asynchronous schedule status
  63   USBSTS_HALT             = 0x1000, // Host controller halted
  64   USBSTS_SYS_ERROR        = 0x10,   // Host system error
  65   USBSTS_INTACK_MASK      = 0x003F, // Mask for the interrupt ACK, the WC
  66                                     // (write clean) bits in USBSTS register
  67
  68   PORTSC_CONN             = 0x01,   // Current Connect Status
  69   PORTSC_CONN_CHANGE      = 0x02,   // Connect Status Change
  70   PORTSC_ENABLED          = 0x04,   // Port Enable / Disable
  71   PORTSC_ENABLE_CHANGE    = 0x08,   // Port Enable / Disable Change
  72   PORTSC_OVERCUR          = 0x10,   // Over current Active
  73   PORTSC_OVERCUR_CHANGE   = 0x20,   // Over current Change
  74   PORSTSC_RESUME          = 0x40,   // Force Port Resume
  75   PORTSC_SUSPEND          = 0x80,   // Port Suspend State
  76   PORTSC_RESET            = 0x100,  // Port Reset
  77   PORTSC_LINESTATE_K      = 0x400,  // Line Status K-state
  78   PORTSC_LINESTATE_J      = 0x800,  // Line Status J-state
  79   PORTSC_POWER            = 0x1000, // Port Power
  80   PORTSC_OWNER            = 0x2000, // Port Owner
  81   PORTSC_CHANGE_MASK      = 0x2A,   // Mask of the port change bits,
  82                                     // they are WC (write clean)
  83   //
  84   // PCI Configuration Registers
  85   //
  86   EHC_PCI_CLASSC          = 0x09,
  87   EHC_PCI_CLASSC_PI       = 0x20,
  88   EHC_BAR_INDEX           = 0 /* how many bytes away from USB_BASE to 0x10 */
  89 }EHCI_REGISTER_OFFSET;
  90
  91 #define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
  92
  93 #define EHC_ADDR(High, QhHw32)   \
  94         ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))
  95
  96 #define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
  97
  98 //
  99 // Structure to map the hardware port states to the
 100 // UEFI's port states.
 101 //
 102 typedef struct {
 103   UINT16                  HwState;
 104   UINT16                  UefiState;
 105 } USB_PORT_STATE_MAP;
 106
 107 //
 108 // Ehci Data and Ctrl Structures
 109 //
 110 #pragma pack(1)
 111 typedef struct {
 112   UINT8                   PI;
 113   UINT8                   SubClassCode;
 114   UINT8                   BaseCode;
 115 } USB_CLASSC;
 116 #pragma pack()
 117
 118 /**
 119   Read EHCI capability register.
 120
 121   @param  Ehc     The EHCI device.
 122   @param  Offset  Capability register address.
 123
 124   @return The register content.
 125
 126 **/
 127 UINT32
 128 EhcReadCapRegister (
 129   IN  USB2_HC_DEV         *Ehc,
 130   IN  UINT32              Offset
 131   );
 132
 133
 134 /**
 135   Read EHCI Operation register.
 136
 137   @param  Ehc      The EHCI device.
 138   @param  Offset   The operation register offset.
 139
 140   @return The register content.
 141
 142 **/
 143 UINT32
 144 EhcReadOpReg (
 145   IN  USB2_HC_DEV         *Ehc,
 146   IN  UINT32              Offset
 147   );
 148
 149
 150 /**
 151   Write  the data to the EHCI operation register.
 152
 153   @param  Ehc      The EHCI device.
 154   @param  Offset   EHCI operation register offset.
 155   @param  Data     The data to write.
 156
 157   @return None.
 158
 159 **/
 160 VOID
 161 EhcWriteOpReg (
 162   IN USB2_HC_DEV          *Ehc,
 163   IN UINT32               Offset,
 164   IN UINT32               Data
 165   );
 166
 167
 168 /**
 169   Add support for UEFI Over Legacy (UoL) feature, stop
 170   the legacy USB SMI support.
 171
 172   @param  Ehc      The EHCI device.
 173
 174   @return None.
 175
 176 **/
 177 VOID
 178 EhcClearLegacySupport (
 179   IN USB2_HC_DEV          *Ehc
 180   );
 181
 182
 183
 184 /**
 185   Set door bell and wait it to be ACKed by host controller.
 186   This function is used to synchronize with the hardware.
 187
 188   @param  Ehc          The EHCI device.
 189   @param  Timeout      The time to wait before abort (in millisecond, ms).
 190
 191   @retval EFI_SUCCESS  Synchronized with the hardware.
 192   @retval EFI_TIMEOUT  Time out happened while waiting door bell to set.
 193
 194 **/
 195 EFI_STATUS
 196 EhcSetAndWaitDoorBell (
 197   IN  USB2_HC_DEV         *Ehc,
 198   IN  UINT32               Timeout
 199   );
 200
 201
 202 /**
 203   Clear all the interrutp status bits, these bits are Write-Clean.
 204
 205   @param  Ehc      The EHCI device.
 206
 207   @return None.
 208
 209 **/
 210 VOID
 211 EhcAckAllInterrupt (
 212   IN  USB2_HC_DEV         *Ehc
 213   );
 214
 215
 216
 217 /**
 218   Whether Ehc is halted.
 219
 220   @param  Ehc     The EHCI device.
 221
 222   @retval TRUE    The controller is halted.
 223   @retval FALSE   It isn't halted.
 224
 225 **/
 226 BOOLEAN
 227 EhcIsHalt (
 228   IN USB2_HC_DEV          *Ehc
 229   );
 230
 231
 232 /**
 233   Whether system error occurred.
 234
 235   @param  Ehc      The EHCI device.
 236
 237   @retval TRUE     System error happened.
 238   @retval FALSE    No system error.
 239
 240 **/
 241 BOOLEAN
 242 EhcIsSysError (
 243   IN USB2_HC_DEV          *Ehc
 244   );
 245
 246
 247 /**
 248   Reset the host controller.
 249
 250   @param  Ehc          The EHCI device.
 251   @param  Timeout      Time to wait before abort (in millisecond, ms).
 252
 253   @retval EFI_SUCCESS  The host controller is reset.
 254   @return Others       Failed to reset the host.
 255
 256 **/
 257 EFI_STATUS
 258 EhcResetHC (
 259   IN USB2_HC_DEV          *Ehc,
 260   IN UINT32               Timeout
 261   );
 262
 263
 264 /**
 265   Halt the host controller.
 266
 267   @param  Ehc          The EHCI device.
 268   @param  Timeout      Time to wait before abort.
 269
 270   @return EFI_SUCCESS  The EHCI is halt.
 271   @return EFI_TIMEOUT  Failed to halt the controller before Timeout.
 272
 273 **/
 274 EFI_STATUS
 275 EhcHaltHC (
 276   IN USB2_HC_DEV         *Ehc,
 277   IN UINT32              Timeout
 278   );
 279
 280
 281 /**
 282   Set the EHCI to run.
 283
 284   @param  Ehc          The EHCI device.
 285   @param  Timeout      Time to wait before abort.
 286
 287   @return EFI_SUCCESS  The EHCI is running.
 288   @return Others       Failed to set the EHCI to run.
 289
 290 **/
 291 EFI_STATUS
 292 EhcRunHC (
 293   IN USB2_HC_DEV          *Ehc,
 294   IN UINT32               Timeout
 295   );
 296
 297
 298
 299 /**
 300   Initialize the HC hardware.
 301   EHCI spec lists the five things to do to initialize the hardware:
 302   1. Program CTRLDSSEGMENT
 303   2. Set USBINTR to enable interrupts
 304   3. Set periodic list base
 305   4. Set USBCMD, interrupt threshold, frame list size etc
 306   5. Write 1 to CONFIGFLAG to route all ports to EHCI
 307
 308   @param  Ehc          The EHCI device.
 309
 310   @return EFI_SUCCESS  The EHCI has come out of halt state.
 311   @return EFI_TIMEOUT  Time out happened.
 312
 313 **/
 314 EFI_STATUS
 315 EhcInitHC (
 316   IN USB2_HC_DEV          *Ehc
 317   );
 318
 319 #endif