MdeModulePkg/Bus/Pci/EhciPei/EhciReg.h

   1 /** @file
   2 Private Header file for Usb Host Controller PEIM
   3
   4 Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
   5
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #ifndef _EFI_EHCI_REG_H_
  11 #define _EFI_EHCI_REG_H_
  12
  13
  14
  15 //
  16 // Capability register offset
  17 //
  18 #define EHC_CAPLENGTH_OFFSET    0    // Capability register length offset
  19 #define EHC_HCSPARAMS_OFFSET    0x04 // Structural Parameters 04-07h
  20 #define EHC_HCCPARAMS_OFFSET    0x08 // Capability parameters offset
  21
  22 //
  23 // Capability register bit definition
  24 //
  25 #define HCSP_NPORTS             0x0F // Number of root hub port
  26 #define HCCP_64BIT              0x01 // 64-bit addressing capability
  27
  28 //
  29 // Operational register offset
  30 //
  31 #define EHC_USBCMD_OFFSET       0x0  // USB command register offset
  32 #define EHC_USBSTS_OFFSET       0x04 // Statue register offset
  33 #define EHC_USBINTR_OFFSET      0x08 // USB interrutp offset
  34 #define EHC_FRINDEX_OFFSET      0x0C // Frame index offset
  35 #define EHC_CTRLDSSEG_OFFSET    0x10 // Control data structure segment offset
  36 #define EHC_FRAME_BASE_OFFSET   0x14 // Frame list base address offset
  37 #define EHC_ASYNC_HEAD_OFFSET   0x18 // Next asynchronous list address offset
  38 #define EHC_CONFIG_FLAG_OFFSET  0x40 // Configure flag register offset
  39 #define EHC_PORT_STAT_OFFSET    0x44 // Port status/control offset
  40
  41 #define EHC_FRAME_LEN           1024
  42
  43 //
  44 // Register bit definition
  45 //
  46 #define CONFIGFLAG_ROUTE_EHC    0x01 // Route port to EHC
  47
  48 #define USBCMD_RUN              0x01   // Run/stop
  49 #define USBCMD_RESET            0x02   // Start the host controller reset
  50 #define USBCMD_ENABLE_PERIOD    0x10   // Enable periodic schedule
  51 #define USBCMD_ENABLE_ASYNC     0x20   // Enable asynchronous schedule
  52 #define USBCMD_IAAD             0x40   // Interrupt on async advance doorbell
  53
  54 #define USBSTS_IAA              0x20   // Interrupt on async advance
  55 #define USBSTS_PERIOD_ENABLED   0x4000 // Periodic schedule status
  56 #define USBSTS_ASYNC_ENABLED    0x8000 // Asynchronous schedule status
  57 #define USBSTS_HALT             0x1000 // Host controller halted
  58 #define USBSTS_SYS_ERROR        0x10   // Host system error
  59 #define USBSTS_INTACK_MASK      0x003F // Mask for the interrupt ACK, the WC
  60                                        // (write clean) bits in USBSTS register
  61
  62 #define PORTSC_CONN             0x01   // Current Connect Status
  63 #define PORTSC_CONN_CHANGE      0x02   // Connect Status Change
  64 #define PORTSC_ENABLED          0x04   // Port Enable / Disable
  65 #define PORTSC_ENABLE_CHANGE    0x08   // Port Enable / Disable Change
  66 #define PORTSC_OVERCUR          0x10   // Over current Active
  67 #define PORTSC_OVERCUR_CHANGE   0x20   // Over current Change
  68 #define PORSTSC_RESUME          0x40   // Force Port Resume
  69 #define PORTSC_SUSPEND          0x80   // Port Suspend State
  70 #define PORTSC_RESET            0x100  // Port Reset
  71 #define PORTSC_LINESTATE_K      0x400  // Line Status K-state
  72 #define PORTSC_LINESTATE_J      0x800  // Line Status J-state
  73 #define PORTSC_POWER            0x1000 // Port Power
  74 #define PORTSC_OWNER            0x2000 // Port Owner
  75 #define PORTSC_CHANGE_MASK      0x2A   // Mask of the port change bits,
  76                                        // they are WC (write clean)
  77 //
  78 // PCI Configuration Registers
  79 //
  80 #define EHC_BAR_INDEX           0      // how many bytes away from USB_BASE to 0x10
  81
  82 #define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
  83
  84 #define EHC_ADDR(High, QhHw32)   \
  85         ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))
  86
  87 #define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
  88
  89 //
  90 // Structure to map the hardware port states to the
  91 // UEFI's port states.
  92 //
  93 typedef struct {
  94   UINT16                  HwState;
  95   UINT16                  UefiState;
  96 } USB_PORT_STATE_MAP;
  97
  98 //
  99 // Ehci Data and Ctrl Structures
 100 //
 101 #pragma pack(1)
 102 typedef struct {
 103   UINT8                   Pi;
 104   UINT8                   SubClassCode;
 105   UINT8                   BaseCode;
 106 } USB_CLASSC;
 107 #pragma pack()
 108
 109
 110 /**
 111   Read EHCI capability register.
 112
 113   @param  Ehc       The EHCI device.
 114   @param  Offset    Capability register address.
 115
 116   @retval the register content read.
 117
 118 **/
 119 UINT32
 120 EhcReadCapRegister (
 121   IN  PEI_USB2_HC_DEV     *Ehc,
 122   IN  UINT32              Offset
 123   )
 124 ;
 125
 126 /**
 127   Read Ehc Operation register.
 128
 129   @param  Ehc       The EHCI device.
 130   @param  Offset    The operation register offset.
 131
 132   @retval the register content read.
 133
 134 **/
 135 UINT32
 136 EhcReadOpReg (
 137   IN  PEI_USB2_HC_DEV     *Ehc,
 138   IN  UINT32              Offset
 139   )
 140 ;
 141
 142 /**
 143   Write the data to the EHCI operation register.
 144
 145   @param  Ehc       The EHCI device.
 146   @param  Offset    EHCI operation register offset.
 147   @param  Data      The data to write.
 148
 149 **/
 150 VOID
 151 EhcWriteOpReg (
 152   IN PEI_USB2_HC_DEV      *Ehc,
 153   IN UINT32               Offset,
 154   IN UINT32               Data
 155   )
 156 ;
 157
 158 /**
 159   Stop the legacy USB SMI support.
 160
 161   @param  Ehc       The EHCI device.
 162
 163 **/
 164 VOID
 165 EhcClearLegacySupport (
 166   IN PEI_USB2_HC_DEV      *Ehc
 167   )
 168 ;
 169
 170 /**
 171   Set door bell and wait it to be ACKed by host controller.
 172   This function is used to synchronize with the hardware.
 173
 174   @param  Ehc       The EHCI device.
 175   @param  Timeout   The time to wait before abort (in millisecond, ms).
 176
 177   @retval EFI_TIMEOUT       Time out happened while waiting door bell to set.
 178   @retval EFI_SUCCESS       Synchronized with the hardware.
 179
 180 **/
 181 EFI_STATUS
 182 EhcSetAndWaitDoorBell (
 183   IN  PEI_USB2_HC_DEV      *Ehc,
 184   IN  UINT32               Timeout
 185   )
 186 ;
 187
 188 /**
 189   Clear all the interrutp status bits, these bits
 190   are Write-Clean.
 191
 192   @param  Ehc       The EHCI device.
 193
 194 **/
 195 VOID
 196 EhcAckAllInterrupt (
 197   IN  PEI_USB2_HC_DEV     *Ehc
 198   )
 199 ;
 200
 201 /**
 202   Check whether Ehc is halted.
 203
 204   @param  Ehc       The EHCI device.
 205
 206   @retval TRUE      The controller is halted.
 207   @retval FALSE     The controller isn't halted.
 208
 209 **/
 210 BOOLEAN
 211 EhcIsHalt (
 212   IN PEI_USB2_HC_DEV      *Ehc
 213   )
 214 ;
 215
 216 /**
 217   Check whether system error occurred.
 218
 219   @param  Ehc       The EHCI device.
 220
 221   @retval TRUE      System error happened.
 222   @retval FALSE     No system error.
 223
 224 **/
 225 BOOLEAN
 226 EhcIsSysError (
 227   IN PEI_USB2_HC_DEV      *Ehc
 228   )
 229 ;
 230
 231 /**
 232   Reset the host controller.
 233
 234   @param  Ehc             The EHCI device.
 235   @param  Timeout         Time to wait before abort (in millisecond, ms).
 236
 237   @retval EFI_TIMEOUT     The transfer failed due to time out.
 238   @retval Others          Failed to reset the host.
 239
 240 **/
 241 EFI_STATUS
 242 EhcResetHC (
 243   IN PEI_USB2_HC_DEV      *Ehc,
 244   IN UINT32               Timeout
 245   )
 246 ;
 247
 248 /**
 249   Halt the host controller.
 250
 251   @param  Ehc             The EHCI device.
 252   @param  Timeout         Time to wait before abort.
 253
 254   @retval EFI_TIMEOUT     Failed to halt the controller before Timeout.
 255   @retval EFI_SUCCESS     The EHCI is halt.
 256
 257 **/
 258 EFI_STATUS
 259 EhcHaltHC (
 260   IN PEI_USB2_HC_DEV     *Ehc,
 261   IN UINT32              Timeout
 262   )
 263 ;
 264
 265 /**
 266   Set the EHCI to run
 267
 268   @param  Ehc             The EHCI device.
 269   @param  Timeout         Time to wait before abort.
 270
 271   @retval EFI_SUCCESS     The EHCI is running.
 272   @retval Others          Failed to set the EHCI to run.
 273
 274 **/
 275 EFI_STATUS
 276 EhcRunHC (
 277   IN PEI_USB2_HC_DEV      *Ehc,
 278   IN UINT32               Timeout
 279   )
 280 ;
 281
 282 /**
 283   Initialize the HC hardware.
 284   EHCI spec lists the five things to do to initialize the hardware.
 285   1. Program CTRLDSSEGMENT.
 286   2. Set USBINTR to enable interrupts.
 287   3. Set periodic list base.
 288   4. Set USBCMD, interrupt threshold, frame list size etc.
 289   5. Write 1 to CONFIGFLAG to route all ports to EHCI.
 290
 291   @param  Ehc             The EHCI device.
 292
 293   @retval EFI_SUCCESS     The EHCI has come out of halt state.
 294   @retval EFI_TIMEOUT     Time out happened.
 295
 296 **/
 297 EFI_STATUS
 298 EhcInitHC (
 299   IN PEI_USB2_HC_DEV      *Ehc
 300   )
 301 ;
 302
 303 #endif