MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceIo.h

   1 /** @file
   2
   3   Copyright (C) 2016, Linaro Ltd. All rights reserved.<BR>
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9 #ifndef __NON_DISCOVERABLE_PCI_DEVICE_IO_H__
  10 #define __NON_DISCOVERABLE_PCI_DEVICE_IO_H__
  11
  12 #include <PiDxe.h>
  13
  14 #include <Library/BaseMemoryLib.h>
  15 #include <Library/DebugLib.h>
  16 #include <Library/MemoryAllocationLib.h>
  17 #include <Library/UefiBootServicesTableLib.h>
  18 #include <Library/UefiLib.h>
  19
  20 #include <IndustryStandard/Pci.h>
  21
  22 #include <Protocol/ComponentName.h>
  23 #include <Protocol/NonDiscoverableDevice.h>
  24 #include <Protocol/Cpu.h>
  25 #include <Protocol/PciIo.h>
  26
  27 #define NON_DISCOVERABLE_PCI_DEVICE_SIG SIGNATURE_32 ('P', 'P', 'I', 'D')
  28
  29 #define NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(PciIoPointer) \
  30         CR (PciIoPointer, NON_DISCOVERABLE_PCI_DEVICE, PciIo, \
  31             NON_DISCOVERABLE_PCI_DEVICE_SIG)
  32
  33 #define PCI_ID_VENDOR_UNKNOWN         0xffff
  34 #define PCI_ID_DEVICE_DONTCARE        0x0000
  35
  36 #define PCI_MAX_BARS                  6
  37
  38 extern EFI_CPU_ARCH_PROTOCOL      *mCpu;
  39
  40 typedef struct {
  41   //
  42   // The linked-list next pointer
  43   //
  44   LIST_ENTRY          List;
  45   //
  46   // The address of the uncached allocation
  47   //
  48   VOID                *HostAddress;
  49   //
  50   // The number of pages in the allocation
  51   //
  52   UINTN               NumPages;
  53   //
  54   // The attributes of the allocation
  55   //
  56   UINT64              Attributes;
  57 } NON_DISCOVERABLE_DEVICE_UNCACHED_ALLOCATION;
  58
  59 typedef struct {
  60   UINT32                    Signature;
  61   //
  62   // The bound non-discoverable device protocol instance
  63   //
  64   NON_DISCOVERABLE_DEVICE   *Device;
  65   //
  66   // The exposed PCI I/O protocol instance.
  67   //
  68   EFI_PCI_IO_PROTOCOL       PciIo;
  69   //
  70   // The emulated PCI config space of the device. Only the minimally required
  71   // items are assigned.
  72   //
  73   PCI_TYPE00                ConfigSpace;
  74   //
  75   // The first virtual BAR to assign based on the resources described
  76   // by the non-discoverable device.
  77   //
  78   UINT32                    BarOffset;
  79   //
  80   // The number of virtual BARs we expose based on the number of
  81   // resources
  82   //
  83   UINT32                    BarCount;
  84   //
  85   // The PCI I/O attributes for this device
  86   //
  87   UINT64                    Attributes;
  88   //
  89   // Whether this device has been enabled
  90   //
  91   BOOLEAN                   Enabled;
  92   //
  93   // Linked list to keep track of uncached allocations performed
  94   // on behalf of this device
  95   //
  96   LIST_ENTRY                UncachedAllocationList;
  97   //
  98   // Unique ID for this device instance: needed so that we can report unique
  99   // segment/bus/device number for each device instance. Note that this number
 100   // may change when disconnecting/reconnecting the driver.
 101   //
 102   UINTN                     UniqueId;
 103 } NON_DISCOVERABLE_PCI_DEVICE;
 104
 105 /**
 106   Initialize PciIo Protocol.
 107
 108   @param  Device      Point to NON_DISCOVERABLE_PCI_DEVICE instance.
 109
 110 **/
 111 VOID
 112 InitializePciIoProtocol (
 113   NON_DISCOVERABLE_PCI_DEVICE     *Device
 114   );
 115
 116 extern EFI_COMPONENT_NAME_PROTOCOL gComponentName;
 117 extern EFI_COMPONENT_NAME2_PROTOCOL gComponentName2;
 118
 119 #endif