MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c

   1 /** @file
   2   NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows
   3   NVM Express specification.
   4
   5   (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
   6   Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
   7   This program and the accompanying materials
   8   are licensed and made available under the terms and conditions of the BSD License
   9   which accompanies this distribution.  The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php.
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 #include "NvmExpress.h"
  18
  19 /**
  20   Dump the execution status from a given completion queue entry.
  21
  22   @param[in]     Cq               A pointer to the NVME_CQ item.
  23
  24 **/
  25 VOID
  26 NvmeDumpStatus (
  27   IN NVME_CQ             *Cq
  28   )
  29 {
  30   DEBUG ((EFI_D_VERBOSE, "Dump NVMe Completion Entry Status from [0x%x]:\n", Cq));
  31
  32   DEBUG ((EFI_D_VERBOSE, "  SQ Identifier : [0x%x], Phase Tag : [%d], Cmd Identifier : [0x%x]\n", Cq->Sqid, Cq->Pt, Cq->Cid));
  33
  34   DEBUG ((EFI_D_VERBOSE, "  NVMe Cmd Execution Result - "));
  35
  36   switch (Cq->Sct) {
  37     case 0x0:
  38       switch (Cq->Sc) {
  39         case 0x0:
  40           DEBUG ((EFI_D_VERBOSE, "Successful Completion\n"));
  41           break;
  42         case 0x1:
  43           DEBUG ((EFI_D_VERBOSE, "Invalid Command Opcode\n"));
  44           break;
  45         case 0x2:
  46           DEBUG ((EFI_D_VERBOSE, "Invalid Field in Command\n"));
  47           break;
  48         case 0x3:
  49           DEBUG ((EFI_D_VERBOSE, "Command ID Conflict\n"));
  50           break;
  51         case 0x4:
  52           DEBUG ((EFI_D_VERBOSE, "Data Transfer Error\n"));
  53           break;
  54         case 0x5:
  55           DEBUG ((EFI_D_VERBOSE, "Commands Aborted due to Power Loss Notification\n"));
  56           break;
  57         case 0x6:
  58           DEBUG ((EFI_D_VERBOSE, "Internal Device Error\n"));
  59           break;
  60         case 0x7:
  61           DEBUG ((EFI_D_VERBOSE, "Command Abort Requested\n"));
  62           break;
  63         case 0x8:
  64           DEBUG ((EFI_D_VERBOSE, "Command Aborted due to SQ Deletion\n"));
  65           break;
  66         case 0x9:
  67           DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Failed Fused Command\n"));
  68           break;
  69         case 0xA:
  70           DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Missing Fused Command\n"));
  71           break;
  72         case 0xB:
  73           DEBUG ((EFI_D_VERBOSE, "Invalid Namespace or Format\n"));
  74           break;
  75         case 0xC:
  76           DEBUG ((EFI_D_VERBOSE, "Command Sequence Error\n"));
  77           break;
  78         case 0xD:
  79           DEBUG ((EFI_D_VERBOSE, "Invalid SGL Last Segment Descriptor\n"));
  80           break;
  81         case 0xE:
  82           DEBUG ((EFI_D_VERBOSE, "Invalid Number of SGL Descriptors\n"));
  83           break;
  84         case 0xF:
  85           DEBUG ((EFI_D_VERBOSE, "Data SGL Length Invalid\n"));
  86           break;
  87         case 0x10:
  88           DEBUG ((EFI_D_VERBOSE, "Metadata SGL Length Invalid\n"));
  89           break;
  90         case 0x11:
  91           DEBUG ((EFI_D_VERBOSE, "SGL Descriptor Type Invalid\n"));
  92           break;
  93         case 0x80:
  94           DEBUG ((EFI_D_VERBOSE, "LBA Out of Range\n"));
  95           break;
  96         case 0x81:
  97           DEBUG ((EFI_D_VERBOSE, "Capacity Exceeded\n"));
  98           break;
  99         case 0x82:
 100           DEBUG ((EFI_D_VERBOSE, "Namespace Not Ready\n"));
 101           break;
 102         case 0x83:
 103           DEBUG ((EFI_D_VERBOSE, "Reservation Conflict\n"));
 104           break;
 105       }
 106       break;
 107
 108     case 0x1:
 109       switch (Cq->Sc) {
 110         case 0x0:
 111           DEBUG ((EFI_D_VERBOSE, "Completion Queue Invalid\n"));
 112           break;
 113         case 0x1:
 114           DEBUG ((EFI_D_VERBOSE, "Invalid Queue Identifier\n"));
 115           break;
 116         case 0x2:
 117           DEBUG ((EFI_D_VERBOSE, "Maximum Queue Size Exceeded\n"));
 118           break;
 119         case 0x3:
 120           DEBUG ((EFI_D_VERBOSE, "Abort Command Limit Exceeded\n"));
 121           break;
 122         case 0x5:
 123           DEBUG ((EFI_D_VERBOSE, "Asynchronous Event Request Limit Exceeded\n"));
 124           break;
 125         case 0x6:
 126           DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Slot\n"));
 127           break;
 128         case 0x7:
 129           DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Image\n"));
 130           break;
 131         case 0x8:
 132           DEBUG ((EFI_D_VERBOSE, "Invalid Interrupt Vector\n"));
 133           break;
 134         case 0x9:
 135           DEBUG ((EFI_D_VERBOSE, "Invalid Log Page\n"));
 136           break;
 137         case 0xA:
 138           DEBUG ((EFI_D_VERBOSE, "Invalid Format\n"));
 139           break;
 140         case 0xB:
 141           DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires Conventional Reset\n"));
 142           break;
 143         case 0xC:
 144           DEBUG ((EFI_D_VERBOSE, "Invalid Queue Deletion\n"));
 145           break;
 146         case 0xD:
 147           DEBUG ((EFI_D_VERBOSE, "Feature Identifier Not Saveable\n"));
 148           break;
 149         case 0xE:
 150           DEBUG ((EFI_D_VERBOSE, "Feature Not Changeable\n"));
 151           break;
 152         case 0xF:
 153           DEBUG ((EFI_D_VERBOSE, "Feature Not Namespace Specific\n"));
 154           break;
 155         case 0x10:
 156           DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires NVM Subsystem Reset\n"));
 157           break;
 158         case 0x80:
 159           DEBUG ((EFI_D_VERBOSE, "Conflicting Attributes\n"));
 160           break;
 161         case 0x81:
 162           DEBUG ((EFI_D_VERBOSE, "Invalid Protection Information\n"));
 163           break;
 164         case 0x82:
 165           DEBUG ((EFI_D_VERBOSE, "Attempted Write to Read Only Range\n"));
 166           break;
 167       }
 168       break;
 169
 170     case 0x2:
 171       switch (Cq->Sc) {
 172         case 0x80:
 173           DEBUG ((EFI_D_VERBOSE, "Write Fault\n"));
 174           break;
 175         case 0x81:
 176           DEBUG ((EFI_D_VERBOSE, "Unrecovered Read Error\n"));
 177           break;
 178         case 0x82:
 179           DEBUG ((EFI_D_VERBOSE, "End-to-end Guard Check Error\n"));
 180           break;
 181         case 0x83:
 182           DEBUG ((EFI_D_VERBOSE, "End-to-end Application Tag Check Error\n"));
 183           break;
 184         case 0x84:
 185           DEBUG ((EFI_D_VERBOSE, "End-to-end Reference Tag Check Error\n"));
 186           break;
 187         case 0x85:
 188           DEBUG ((EFI_D_VERBOSE, "Compare Failure\n"));
 189           break;
 190         case 0x86:
 191           DEBUG ((EFI_D_VERBOSE, "Access Denied\n"));
 192           break;
 193       }
 194       break;
 195
 196     default:
 197       break;
 198   }
 199 }
 200
 201 /**
 202   Create PRP lists for data transfer which is larger than 2 memory pages.
 203   Note here we calcuate the number of required PRP lists and allocate them at one time.
 204
 205   @param[in]     PciIo               A pointer to the EFI_PCI_IO_PROTOCOL instance.
 206   @param[in]     PhysicalAddr        The physical base address of data buffer.
 207   @param[in]     Pages               The number of pages to be transfered.
 208   @param[out]    PrpListHost         The host base address of PRP lists.
 209   @param[in,out] PrpListNo           The number of PRP List.
 210   @param[out]    Mapping             The mapping value returned from PciIo.Map().
 211
 212   @retval The pointer to the first PRP List of the PRP lists.
 213
 214 **/
 215 VOID*
 216 NvmeCreatePrpList (
 217   IN     EFI_PCI_IO_PROTOCOL          *PciIo,
 218   IN     EFI_PHYSICAL_ADDRESS         PhysicalAddr,
 219   IN     UINTN                        Pages,
 220      OUT VOID                         **PrpListHost,
 221   IN OUT UINTN                        *PrpListNo,
 222      OUT VOID                         **Mapping
 223   )
 224 {
 225   UINTN                       PrpEntryNo;
 226   UINT64                      PrpListBase;
 227   UINTN                       PrpListIndex;
 228   UINTN                       PrpEntryIndex;
 229   UINT64                      Remainder;
 230   EFI_PHYSICAL_ADDRESS        PrpListPhyAddr;
 231   UINTN                       Bytes;
 232   EFI_STATUS                  Status;
 233
 234   //
 235   // The number of Prp Entry in a memory page.
 236   //
 237   PrpEntryNo = EFI_PAGE_SIZE / sizeof (UINT64);
 238
 239   //
 240   // Calculate total PrpList number.
 241   //
 242   *PrpListNo = (UINTN)DivU64x64Remainder ((UINT64)Pages, (UINT64)PrpEntryNo - 1, &Remainder);
 243   if (*PrpListNo == 0) {
 244     *PrpListNo = 1;
 245   } else if ((Remainder != 0) && (Remainder != 1)) {
 246     *PrpListNo += 1;
 247   } else if (Remainder == 1) {
 248     Remainder = PrpEntryNo;
 249   } else if (Remainder == 0) {
 250     Remainder = PrpEntryNo - 1;
 251   }
 252
 253   Status = PciIo->AllocateBuffer (
 254                     PciIo,
 255                     AllocateAnyPages,
 256                     EfiBootServicesData,
 257                     *PrpListNo,
 258                     PrpListHost,
 259                     0
 260                     );
 261
 262   if (EFI_ERROR (Status)) {
 263     return NULL;
 264   }
 265
 266   Bytes = EFI_PAGES_TO_SIZE (*PrpListNo);
 267   Status = PciIo->Map (
 268                     PciIo,
 269                     EfiPciIoOperationBusMasterCommonBuffer,
 270                     *PrpListHost,
 271                     &Bytes,
 272                     &PrpListPhyAddr,
 273                     Mapping
 274                     );
 275
 276   if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (*PrpListNo))) {
 277     DEBUG ((EFI_D_ERROR, "NvmeCreatePrpList: create PrpList failure!\n"));
 278     goto EXIT;
 279   }
 280   //
 281   // Fill all PRP lists except of last one.
 282   //
 283   ZeroMem (*PrpListHost, Bytes);
 284   for (PrpListIndex = 0; PrpListIndex < *PrpListNo - 1; ++PrpListIndex) {
 285     PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
 286
 287     for (PrpEntryIndex = 0; PrpEntryIndex < PrpEntryNo; ++PrpEntryIndex) {
 288       if (PrpEntryIndex != PrpEntryNo - 1) {
 289         //
 290         // Fill all PRP entries except of last one.
 291         //
 292         *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;
 293         PhysicalAddr += EFI_PAGE_SIZE;
 294       } else {
 295         //
 296         // Fill last PRP entries with next PRP List pointer.
 297         //
 298         *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PrpListPhyAddr + (PrpListIndex + 1) * EFI_PAGE_SIZE;
 299       }
 300     }
 301   }
 302   //
 303   // Fill last PRP list.
 304   //
 305   PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
 306   for (PrpEntryIndex = 0; PrpEntryIndex < Remainder; ++PrpEntryIndex) {
 307     *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;
 308     PhysicalAddr += EFI_PAGE_SIZE;
 309   }
 310
 311   return (VOID*)(UINTN)PrpListPhyAddr;
 312
 313 EXIT:
 314   PciIo->FreeBuffer (PciIo, *PrpListNo, *PrpListHost);
 315   return NULL;
 316 }
 317
 318
 319 /**
 320   Aborts the asynchronous PassThru requests.
 321
 322   @param[in] Private        The pointer to the NVME_CONTROLLER_PRIVATE_DATA
 323                             data structure.
 324
 325   @retval EFI_SUCCESS       The asynchronous PassThru requests have been aborted.
 326   @return EFI_DEVICE_ERROR  Fail to abort all the asynchronous PassThru requests.
 327
 328 **/
 329 EFI_STATUS
 330 AbortAsyncPassThruTasks (
 331   IN NVME_CONTROLLER_PRIVATE_DATA    *Private
 332   )
 333 {
 334   EFI_PCI_IO_PROTOCOL                *PciIo;
 335   LIST_ENTRY                         *Link;
 336   LIST_ENTRY                         *NextLink;
 337   NVME_BLKIO2_SUBTASK                *Subtask;
 338   NVME_BLKIO2_REQUEST                *BlkIo2Request;
 339   NVME_PASS_THRU_ASYNC_REQ           *AsyncRequest;
 340   EFI_BLOCK_IO2_TOKEN                *Token;
 341   EFI_TPL                            OldTpl;
 342   EFI_STATUS                         Status;
 343
 344   PciIo  = Private->PciIo;
 345   OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
 346
 347   //
 348   // Cancel the unsubmitted subtasks.
 349   //
 350   for (Link = GetFirstNode (&Private->UnsubmittedSubtasks);
 351        !IsNull (&Private->UnsubmittedSubtasks, Link);
 352        Link = NextLink) {
 353     NextLink      = GetNextNode (&Private->UnsubmittedSubtasks, Link);
 354     Subtask       = NVME_BLKIO2_SUBTASK_FROM_LINK (Link);
 355     BlkIo2Request = Subtask->BlockIo2Request;
 356     Token         = BlkIo2Request->Token;
 357
 358     BlkIo2Request->UnsubmittedSubtaskNum--;
 359     if (Subtask->IsLast) {
 360       BlkIo2Request->LastSubtaskSubmitted = TRUE;
 361     }
 362     Token->TransactionStatus = EFI_ABORTED;
 363
 364     RemoveEntryList (Link);
 365     InsertTailList (&BlkIo2Request->SubtasksQueue, Link);
 366     gBS->SignalEvent (Subtask->Event);
 367   }
 368
 369   //
 370   // Cleanup the resources for the asynchronous PassThru requests.
 371   //
 372   for (Link = GetFirstNode (&Private->AsyncPassThruQueue);
 373        !IsNull (&Private->AsyncPassThruQueue, Link);
 374        Link = NextLink) {
 375     NextLink = GetNextNode (&Private->AsyncPassThruQueue, Link);
 376     AsyncRequest = NVME_PASS_THRU_ASYNC_REQ_FROM_THIS (Link);
 377
 378     if (AsyncRequest->MapData != NULL) {
 379       PciIo->Unmap (PciIo, AsyncRequest->MapData);
 380     }
 381     if (AsyncRequest->MapMeta != NULL) {
 382       PciIo->Unmap (PciIo, AsyncRequest->MapMeta);
 383     }
 384     if (AsyncRequest->MapPrpList != NULL) {
 385       PciIo->Unmap (PciIo, AsyncRequest->MapPrpList);
 386     }
 387     if (AsyncRequest->PrpListHost != NULL) {
 388       PciIo->FreeBuffer (
 389                PciIo,
 390                AsyncRequest->PrpListNo,
 391                AsyncRequest->PrpListHost
 392                );
 393     }
 394
 395     RemoveEntryList (Link);
 396     gBS->SignalEvent (AsyncRequest->CallerEvent);
 397     FreePool (AsyncRequest);
 398   }
 399
 400   if (IsListEmpty (&Private->AsyncPassThruQueue) &&
 401       IsListEmpty (&Private->UnsubmittedSubtasks)) {
 402     Status = EFI_SUCCESS;
 403   } else {
 404     Status = EFI_DEVICE_ERROR;
 405   }
 406
 407   gBS->RestoreTPL (OldTpl);
 408
 409   return Status;
 410 }
 411
 412
 413 /**
 414   Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports
 415   both blocking I/O and non-blocking I/O. The blocking I/O functionality is required, and the non-blocking
 416   I/O functionality is optional.
 417
 418
 419   @param[in]     This                A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
 420   @param[in]     NamespaceId         A 32 bit namespace ID as defined in the NVMe specification to which the NVM Express Command
 421                                      Packet will be sent.  A value of 0 denotes the NVM Express controller, a value of all 0xFF's
 422                                      (all bytes are 0xFF) in the namespace ID specifies that the command packet should be sent to
 423                                      all valid namespaces.
 424   @param[in,out] Packet              A pointer to the NVM Express Command Packet.
 425   @param[in]     Event               If non-blocking I/O is not supported then Event is ignored, and blocking I/O is performed.
 426                                      If Event is NULL, then blocking I/O is performed. If Event is not NULL and non-blocking I/O
 427                                      is supported, then non-blocking I/O is performed, and Event will be signaled when the NVM
 428                                      Express Command Packet completes.
 429
 430   @retval EFI_SUCCESS                The NVM Express Command Packet was sent by the host. TransferLength bytes were transferred
 431                                      to, or from DataBuffer.
 432   @retval EFI_BAD_BUFFER_SIZE        The NVM Express Command Packet was not executed. The number of bytes that could be transferred
 433                                      is returned in TransferLength.
 434   @retval EFI_NOT_READY              The NVM Express Command Packet could not be sent because the controller is not ready. The caller
 435                                      may retry again later.
 436   @retval EFI_DEVICE_ERROR           A device error occurred while attempting to send the NVM Express Command Packet.
 437   @retval EFI_INVALID_PARAMETER      NamespaceId or the contents of EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET are invalid. The NVM
 438                                      Express Command Packet was not sent, so no additional status information is available.
 439   @retval EFI_UNSUPPORTED            The command described by the NVM Express Command Packet is not supported by the NVM Express
 440                                      controller. The NVM Express Command Packet was not sent so no additional status information
 441                                      is available.
 442   @retval EFI_TIMEOUT                A timeout occurred while waiting for the NVM Express Command Packet to execute.
 443
 444 **/
 445 EFI_STATUS
 446 EFIAPI
 447 NvmExpressPassThru (
 448   IN     EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL          *This,
 449   IN     UINT32                                      NamespaceId,
 450   IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET    *Packet,
 451   IN     EFI_EVENT                                   Event OPTIONAL
 452   )
 453 {
 454   NVME_CONTROLLER_PRIVATE_DATA   *Private;
 455   EFI_STATUS                     Status;
 456   EFI_STATUS                     PreviousStatus;
 457   EFI_PCI_IO_PROTOCOL            *PciIo;
 458   NVME_SQ                        *Sq;
 459   NVME_CQ                        *Cq;
 460   UINT16                         QueueId;
 461   UINT32                         Bytes;
 462   UINT16                         Offset;
 463   EFI_EVENT                      TimerEvent;
 464   EFI_PCI_IO_PROTOCOL_OPERATION  Flag;
 465   EFI_PHYSICAL_ADDRESS           PhyAddr;
 466   VOID                           *MapData;
 467   VOID                           *MapMeta;
 468   VOID                           *MapPrpList;
 469   UINTN                          MapLength;
 470   UINT64                         *Prp;
 471   VOID                           *PrpListHost;
 472   UINTN                          PrpListNo;
 473   UINT32                         Attributes;
 474   UINT32                         IoAlign;
 475   UINT32                         MaxTransLen;
 476   UINT32                         Data;
 477   NVME_PASS_THRU_ASYNC_REQ       *AsyncRequest;
 478   EFI_TPL                        OldTpl;
 479
 480   //
 481   // check the data fields in Packet parameter.
 482   //
 483   if ((This == NULL) || (Packet == NULL)) {
 484     return EFI_INVALID_PARAMETER;
 485   }
 486
 487   if ((Packet->NvmeCmd == NULL) || (Packet->NvmeCompletion == NULL)) {
 488     return EFI_INVALID_PARAMETER;
 489   }
 490
 491   if (Packet->QueueType != NVME_ADMIN_QUEUE && Packet->QueueType != NVME_IO_QUEUE) {
 492     return EFI_INVALID_PARAMETER;
 493   }
 494
 495   //
 496   // 'Attributes' with neither EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL nor
 497   // EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL set is an illegal
 498   // configuration.
 499   //
 500   Attributes  = This->Mode->Attributes;
 501   if ((Attributes & (EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL |
 502     EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL)) == 0) {
 503     return EFI_INVALID_PARAMETER;
 504   }
 505
 506   //
 507   // Buffer alignment check for TransferBuffer & MetadataBuffer.
 508   //
 509   IoAlign     = This->Mode->IoAlign;
 510   if (IoAlign > 0 && (((UINTN) Packet->TransferBuffer & (IoAlign - 1)) != 0)) {
 511     return EFI_INVALID_PARAMETER;
 512   }
 513
 514   if (IoAlign > 0 && (((UINTN) Packet->MetadataBuffer & (IoAlign - 1)) != 0)) {
 515     return EFI_INVALID_PARAMETER;
 516   }
 517
 518   Private     = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
 519
 520   //
 521   // Check NamespaceId is valid or not.
 522   //
 523   if ((NamespaceId > Private->ControllerData->Nn) &&
 524       (NamespaceId != (UINT32) -1)) {
 525     return EFI_INVALID_PARAMETER;
 526   }
 527
 528   //
 529   // Check whether TransferLength exceeds the maximum data transfer size.
 530   //
 531   if (Private->ControllerData->Mdts != 0) {
 532     MaxTransLen = (1 << (Private->ControllerData->Mdts)) *
 533                   (1 << (Private->Cap.Mpsmin + 12));
 534     if (Packet->TransferLength > MaxTransLen) {
 535       Packet->TransferLength = MaxTransLen;
 536       return EFI_BAD_BUFFER_SIZE;
 537     }
 538   }
 539
 540   PciIo       = Private->PciIo;
 541   MapData     = NULL;
 542   MapMeta     = NULL;
 543   MapPrpList  = NULL;
 544   PrpListHost = NULL;
 545   PrpListNo   = 0;
 546   Prp         = NULL;
 547   TimerEvent  = NULL;
 548   Status      = EFI_SUCCESS;
 549
 550   if (Packet->QueueType == NVME_ADMIN_QUEUE) {
 551     QueueId = 0;
 552   } else {
 553     if (Event == NULL) {
 554       QueueId = 1;
 555     } else {
 556       QueueId = 2;
 557
 558       //
 559       // Submission queue full check.
 560       //
 561       if ((Private->SqTdbl[QueueId].Sqt + 1) % (NVME_ASYNC_CSQ_SIZE + 1) ==
 562           Private->AsyncSqHead) {
 563         return EFI_NOT_READY;
 564       }
 565     }
 566   }
 567   Sq  = Private->SqBuffer[QueueId] + Private->SqTdbl[QueueId].Sqt;
 568   Cq  = Private->CqBuffer[QueueId] + Private->CqHdbl[QueueId].Cqh;
 569
 570   if (Packet->NvmeCmd->Nsid != NamespaceId) {
 571     return EFI_INVALID_PARAMETER;
 572   }
 573
 574   ZeroMem (Sq, sizeof (NVME_SQ));
 575   Sq->Opc  = (UINT8)Packet->NvmeCmd->Cdw0.Opcode;
 576   Sq->Fuse = (UINT8)Packet->NvmeCmd->Cdw0.FusedOperation;
 577   Sq->Cid  = Private->Cid[QueueId]++;
 578   Sq->Nsid = Packet->NvmeCmd->Nsid;
 579
 580   //
 581   // Currently we only support PRP for data transfer, SGL is NOT supported.
 582   //
 583   ASSERT (Sq->Psdt == 0);
 584   if (Sq->Psdt != 0) {
 585     DEBUG ((EFI_D_ERROR, "NvmExpressPassThru: doesn't support SGL mechanism\n"));
 586     return EFI_UNSUPPORTED;
 587   }
 588
 589   Sq->Prp[0] = (UINT64)(UINTN)Packet->TransferBuffer;
 590   //
 591   // If the NVMe cmd has data in or out, then mapping the user buffer to the PCI controller specific addresses.
 592   // Note here we don't handle data buffer for CreateIOSubmitionQueue and CreateIOCompletionQueue cmds because
 593   // these two cmds are special which requires their data buffer must support simultaneous access by both the
 594   // processor and a PCI Bus Master. It's caller's responsbility to ensure this.
 595   //
 596   if (((Sq->Opc & (BIT0 | BIT1)) != 0) &&
 597       !((Packet->QueueType == NVME_ADMIN_QUEUE) && ((Sq->Opc == NVME_ADMIN_CRIOCQ_CMD) || (Sq->Opc == NVME_ADMIN_CRIOSQ_CMD)))) {
 598     if ((Packet->TransferLength == 0) || (Packet->TransferBuffer == NULL)) {
 599       return EFI_INVALID_PARAMETER;
 600     }
 601
 602     if ((Sq->Opc & BIT0) != 0) {
 603       Flag = EfiPciIoOperationBusMasterRead;
 604     } else {
 605       Flag = EfiPciIoOperationBusMasterWrite;
 606     }
 607
 608     MapLength = Packet->TransferLength;
 609     Status = PciIo->Map (
 610                       PciIo,
 611                       Flag,
 612                       Packet->TransferBuffer,
 613                       &MapLength,
 614                       &PhyAddr,
 615                       &MapData
 616                       );
 617     if (EFI_ERROR (Status) || (Packet->TransferLength != MapLength)) {
 618       return EFI_OUT_OF_RESOURCES;
 619     }
 620
 621     Sq->Prp[0] = PhyAddr;
 622     Sq->Prp[1] = 0;
 623
 624     if((Packet->MetadataLength != 0) && (Packet->MetadataBuffer != NULL)) {
 625       MapLength = Packet->MetadataLength;
 626       Status = PciIo->Map (
 627                         PciIo,
 628                         Flag,
 629                         Packet->MetadataBuffer,
 630                         &MapLength,
 631                         &PhyAddr,
 632                         &MapMeta
 633                         );
 634       if (EFI_ERROR (Status) || (Packet->MetadataLength != MapLength)) {
 635         PciIo->Unmap (
 636                  PciIo,
 637                  MapData
 638                  );
 639
 640         return EFI_OUT_OF_RESOURCES;
 641       }
 642       Sq->Mptr = PhyAddr;
 643     }
 644   }
 645   //
 646   // If the buffer size spans more than two memory pages (page size as defined in CC.Mps),
 647   // then build a PRP list in the second PRP submission queue entry.
 648   //
 649   Offset = ((UINT16)Sq->Prp[0]) & (EFI_PAGE_SIZE - 1);
 650   Bytes  = Packet->TransferLength;
 651
 652   if ((Offset + Bytes) > (EFI_PAGE_SIZE * 2)) {
 653     //
 654     // Create PrpList for remaining data buffer.
 655     //
 656     PhyAddr = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);
 657     Prp = NvmeCreatePrpList (PciIo, PhyAddr, EFI_SIZE_TO_PAGES(Offset + Bytes) - 1, &PrpListHost, &PrpListNo, &MapPrpList);
 658     if (Prp == NULL) {
 659       goto EXIT;
 660     }
 661
 662     Sq->Prp[1] = (UINT64)(UINTN)Prp;
 663   } else if ((Offset + Bytes) > EFI_PAGE_SIZE) {
 664     Sq->Prp[1] = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);
 665   }
 666
 667   if(Packet->NvmeCmd->Flags & CDW2_VALID) {
 668     Sq->Rsvd2 = (UINT64)Packet->NvmeCmd->Cdw2;
 669   }
 670   if(Packet->NvmeCmd->Flags & CDW3_VALID) {
 671     Sq->Rsvd2 |= LShiftU64 ((UINT64)Packet->NvmeCmd->Cdw3, 32);
 672   }
 673   if(Packet->NvmeCmd->Flags & CDW10_VALID) {
 674     Sq->Payload.Raw.Cdw10 = Packet->NvmeCmd->Cdw10;
 675   }
 676   if(Packet->NvmeCmd->Flags & CDW11_VALID) {
 677     Sq->Payload.Raw.Cdw11 = Packet->NvmeCmd->Cdw11;
 678   }
 679   if(Packet->NvmeCmd->Flags & CDW12_VALID) {
 680     Sq->Payload.Raw.Cdw12 = Packet->NvmeCmd->Cdw12;
 681   }
 682   if(Packet->NvmeCmd->Flags & CDW13_VALID) {
 683     Sq->Payload.Raw.Cdw13 = Packet->NvmeCmd->Cdw13;
 684   }
 685   if(Packet->NvmeCmd->Flags & CDW14_VALID) {
 686     Sq->Payload.Raw.Cdw14 = Packet->NvmeCmd->Cdw14;
 687   }
 688   if(Packet->NvmeCmd->Flags & CDW15_VALID) {
 689     Sq->Payload.Raw.Cdw15 = Packet->NvmeCmd->Cdw15;
 690   }
 691
 692   //
 693   // Ring the submission queue doorbell.
 694   //
 695   if ((Event != NULL) && (QueueId != 0)) {
 696     Private->SqTdbl[QueueId].Sqt =
 697       (Private->SqTdbl[QueueId].Sqt + 1) % (NVME_ASYNC_CSQ_SIZE + 1);
 698   } else {
 699     Private->SqTdbl[QueueId].Sqt ^= 1;
 700   }
 701   Data = ReadUnaligned32 ((UINT32*)&Private->SqTdbl[QueueId]);
 702   Status = PciIo->Mem.Write (
 703                PciIo,
 704                EfiPciIoWidthUint32,
 705                NVME_BAR,
 706                NVME_SQTDBL_OFFSET(QueueId, Private->Cap.Dstrd),
 707                1,
 708                &Data
 709                );
 710
 711   if (EFI_ERROR (Status)) {
 712     goto EXIT;
 713   }
 714
 715   //
 716   // For non-blocking requests, return directly if the command is placed
 717   // in the submission queue.
 718   //
 719   if ((Event != NULL) && (QueueId != 0)) {
 720     AsyncRequest = AllocateZeroPool (sizeof (NVME_PASS_THRU_ASYNC_REQ));
 721     if (AsyncRequest == NULL) {
 722       Status = EFI_DEVICE_ERROR;
 723       goto EXIT;
 724     }
 725
 726     AsyncRequest->Signature     = NVME_PASS_THRU_ASYNC_REQ_SIG;
 727     AsyncRequest->Packet        = Packet;
 728     AsyncRequest->CommandId     = Sq->Cid;
 729     AsyncRequest->CallerEvent   = Event;
 730     AsyncRequest->MapData       = MapData;
 731     AsyncRequest->MapMeta       = MapMeta;
 732     AsyncRequest->MapPrpList    = MapPrpList;
 733     AsyncRequest->PrpListNo     = PrpListNo;
 734     AsyncRequest->PrpListHost   = PrpListHost;
 735
 736     OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
 737     InsertTailList (&Private->AsyncPassThruQueue, &AsyncRequest->Link);
 738     gBS->RestoreTPL (OldTpl);
 739
 740     return EFI_SUCCESS;
 741   }
 742
 743   Status = gBS->CreateEvent (
 744                   EVT_TIMER,
 745                   TPL_CALLBACK,
 746                   NULL,
 747                   NULL,
 748                   &TimerEvent
 749                   );
 750   if (EFI_ERROR (Status)) {
 751     goto EXIT;
 752   }
 753
 754   Status = gBS->SetTimer(TimerEvent, TimerRelative, Packet->CommandTimeout);
 755
 756   if (EFI_ERROR(Status)) {
 757     goto EXIT;
 758   }
 759
 760   //
 761   // Wait for completion queue to get filled in.
 762   //
 763   Status = EFI_TIMEOUT;
 764   while (EFI_ERROR (gBS->CheckEvent (TimerEvent))) {
 765     if (Cq->Pt != Private->Pt[QueueId]) {
 766       Status = EFI_SUCCESS;
 767       break;
 768     }
 769   }
 770
 771   //
 772   // Check the NVMe cmd execution result
 773   //
 774   if (Status != EFI_TIMEOUT) {
 775     if ((Cq->Sct == 0) && (Cq->Sc == 0)) {
 776       Status = EFI_SUCCESS;
 777     } else {
 778       Status = EFI_DEVICE_ERROR;
 779       //
 780       // Copy the Respose Queue entry for this command to the callers response buffer
 781       //
 782       CopyMem(Packet->NvmeCompletion, Cq, sizeof(EFI_NVM_EXPRESS_COMPLETION));
 783
 784       //
 785       // Dump every completion entry status for debugging.
 786       //
 787       DEBUG_CODE_BEGIN();
 788         NvmeDumpStatus(Cq);
 789       DEBUG_CODE_END();
 790     }
 791   } else {
 792     //
 793     // Timeout occurs for an NVMe command. Reset the controller to abort the
 794     // outstanding commands.
 795     //
 796     DEBUG ((DEBUG_ERROR, "NvmExpressPassThru: Timeout occurs for an NVMe command.\n"));
 797
 798     //
 799     // Disable the timer to trigger the process of async transfers temporarily.
 800     //
 801     Status = gBS->SetTimer (Private->TimerEvent, TimerCancel, 0);
 802     if (EFI_ERROR (Status)) {
 803       goto EXIT;
 804     }
 805
 806     //
 807     // Reset the NVMe controller.
 808     //
 809     Status = NvmeControllerInit (Private);
 810     if (!EFI_ERROR (Status)) {
 811       Status = AbortAsyncPassThruTasks (Private);
 812       if (!EFI_ERROR (Status)) {
 813         //
 814         // Re-enable the timer to trigger the process of async transfers.
 815         //
 816         Status = gBS->SetTimer (Private->TimerEvent, TimerPeriodic, NVME_HC_ASYNC_TIMER);
 817         if (!EFI_ERROR (Status)) {
 818           //
 819           // Return EFI_TIMEOUT to indicate a timeout occurs for NVMe PassThru command.
 820           //
 821           Status = EFI_TIMEOUT;
 822         }
 823       }
 824     } else {
 825       Status = EFI_DEVICE_ERROR;
 826     }
 827
 828     goto EXIT;
 829   }
 830
 831   if ((Private->CqHdbl[QueueId].Cqh ^= 1) == 0) {
 832     Private->Pt[QueueId] ^= 1;
 833   }
 834
 835   Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[QueueId]);
 836   PreviousStatus = Status;
 837   Status = PciIo->Mem.Write (
 838                PciIo,
 839                EfiPciIoWidthUint32,
 840                NVME_BAR,
 841                NVME_CQHDBL_OFFSET(QueueId, Private->Cap.Dstrd),
 842                1,
 843                &Data
 844                );
 845   // The return status of PciIo->Mem.Write should not override
 846   // previous status if previous status contains error.
 847   Status = EFI_ERROR (PreviousStatus) ? PreviousStatus : Status;
 848
 849   //
 850   // For now, the code does not support the non-blocking feature for admin queue.
 851   // If Event is not NULL for admin queue, signal the caller's event here.
 852   //
 853   if (Event != NULL) {
 854     ASSERT (QueueId == 0);
 855     gBS->SignalEvent (Event);
 856   }
 857
 858 EXIT:
 859   if (MapData != NULL) {
 860     PciIo->Unmap (
 861              PciIo,
 862              MapData
 863              );
 864   }
 865
 866   if (MapMeta != NULL) {
 867     PciIo->Unmap (
 868              PciIo,
 869              MapMeta
 870              );
 871   }
 872
 873   if (MapPrpList != NULL) {
 874     PciIo->Unmap (
 875              PciIo,
 876              MapPrpList
 877              );
 878   }
 879
 880   if (Prp != NULL) {
 881     PciIo->FreeBuffer (PciIo, PrpListNo, PrpListHost);
 882   }
 883
 884   if (TimerEvent != NULL) {
 885     gBS->CloseEvent (TimerEvent);
 886   }
 887   return Status;
 888 }
 889
 890 /**
 891   Used to retrieve the next namespace ID for this NVM Express controller.
 892
 893   The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNextNamespace() function retrieves the next valid
 894   namespace ID on this NVM Express controller.
 895
 896   If on input the value pointed to by NamespaceId is 0xFFFFFFFF, then the first valid namespace
 897   ID defined on the NVM Express controller is returned in the location pointed to by NamespaceId
 898   and a status of EFI_SUCCESS is returned.
 899
 900   If on input the value pointed to by NamespaceId is an invalid namespace ID other than 0xFFFFFFFF,
 901   then EFI_INVALID_PARAMETER is returned.
 902
 903   If on input the value pointed to by NamespaceId is a valid namespace ID, then the next valid
 904   namespace ID on the NVM Express controller is returned in the location pointed to by NamespaceId,
 905   and EFI_SUCCESS is returned.
 906
 907   If the value pointed to by NamespaceId is the namespace ID of the last namespace on the NVM
 908   Express controller, then EFI_NOT_FOUND is returned.
 909
 910   @param[in]     This           A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
 911   @param[in,out] NamespaceId    On input, a pointer to a legal NamespaceId for an NVM Express
 912                                 namespace present on the NVM Express controller. On output, a
 913                                 pointer to the next NamespaceId of an NVM Express namespace on
 914                                 an NVM Express controller. An input value of 0xFFFFFFFF retrieves
 915                                 the first NamespaceId for an NVM Express namespace present on an
 916                                 NVM Express controller.
 917
 918   @retval EFI_SUCCESS           The Namespace ID of the next Namespace was returned.
 919   @retval EFI_NOT_FOUND         There are no more namespaces defined on this controller.
 920   @retval EFI_INVALID_PARAMETER NamespaceId is an invalid value other than 0xFFFFFFFF.
 921
 922 **/
 923 EFI_STATUS
 924 EFIAPI
 925 NvmExpressGetNextNamespace (
 926   IN     EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL          *This,
 927   IN OUT UINT32                                      *NamespaceId
 928   )
 929 {
 930   NVME_CONTROLLER_PRIVATE_DATA     *Private;
 931   NVME_ADMIN_NAMESPACE_DATA        *NamespaceData;
 932   UINT32                           NextNamespaceId;
 933   EFI_STATUS                       Status;
 934
 935   if ((This == NULL) || (NamespaceId == NULL)) {
 936     return EFI_INVALID_PARAMETER;
 937   }
 938
 939   NamespaceData = NULL;
 940   Status        = EFI_NOT_FOUND;
 941
 942   Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
 943   //
 944   // If the NamespaceId input value is 0xFFFFFFFF, then get the first valid namespace ID
 945   //
 946   if (*NamespaceId == 0xFFFFFFFF) {
 947     //
 948     // Start with the first namespace ID
 949     //
 950     NextNamespaceId = 1;
 951     //
 952     // Allocate buffer for Identify Namespace data.
 953     //
 954     NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));
 955
 956     if (NamespaceData == NULL) {
 957       return EFI_NOT_FOUND;
 958     }
 959
 960     Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);
 961     if (EFI_ERROR(Status)) {
 962       goto Done;
 963     }
 964
 965     *NamespaceId = NextNamespaceId;
 966   } else {
 967     if (*NamespaceId > Private->ControllerData->Nn) {
 968       return EFI_INVALID_PARAMETER;
 969     }
 970
 971     NextNamespaceId = *NamespaceId + 1;
 972     if (NextNamespaceId > Private->ControllerData->Nn) {
 973       return EFI_NOT_FOUND;
 974     }
 975
 976     //
 977     // Allocate buffer for Identify Namespace data.
 978     //
 979     NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));
 980     if (NamespaceData == NULL) {
 981       return EFI_NOT_FOUND;
 982     }
 983
 984     Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);
 985     if (EFI_ERROR(Status)) {
 986       goto Done;
 987     }
 988
 989     *NamespaceId = NextNamespaceId;
 990   }
 991
 992 Done:
 993   if (NamespaceData != NULL) {
 994     FreePool(NamespaceData);
 995   }
 996
 997   return Status;
 998 }
 999
1000 /**
1001   Used to translate a device path node to a namespace ID.
1002
1003   The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNamespace() function determines the namespace ID associated with the
1004   namespace described by DevicePath.
1005
1006   If DevicePath is a device path node type that the NVM Express Pass Thru driver supports, then the NVM Express
1007   Pass Thru driver will attempt to translate the contents DevicePath into a namespace ID.
1008
1009   If this translation is successful, then that namespace ID is returned in NamespaceId, and EFI_SUCCESS is returned
1010
1011   @param[in]  This                A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
1012   @param[in]  DevicePath          A pointer to the device path node that describes an NVM Express namespace on
1013                                   the NVM Express controller.
1014   @param[out] NamespaceId         The NVM Express namespace ID contained in the device path node.
1015
1016   @retval EFI_SUCCESS             DevicePath was successfully translated to NamespaceId.
1017   @retval EFI_INVALID_PARAMETER   If DevicePath or NamespaceId are NULL, then EFI_INVALID_PARAMETER is returned.
1018   @retval EFI_UNSUPPORTED         If DevicePath is not a device path node type that the NVM Express Pass Thru driver
1019                                   supports, then EFI_UNSUPPORTED is returned.
1020   @retval EFI_NOT_FOUND           If DevicePath is a device path node type that the NVM Express Pass Thru driver
1021                                   supports, but there is not a valid translation from DevicePath to a namespace ID,
1022                                   then EFI_NOT_FOUND is returned.
1023 **/
1024 EFI_STATUS
1025 EFIAPI
1026 NvmExpressGetNamespace (
1027   IN     EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL          *This,
1028   IN     EFI_DEVICE_PATH_PROTOCOL                    *DevicePath,
1029      OUT UINT32                                      *NamespaceId
1030   )
1031 {
1032   NVME_NAMESPACE_DEVICE_PATH       *Node;
1033   NVME_CONTROLLER_PRIVATE_DATA     *Private;
1034
1035   if ((This == NULL) || (DevicePath == NULL) || (NamespaceId == NULL)) {
1036     return EFI_INVALID_PARAMETER;
1037   }
1038
1039   if (DevicePath->Type != MESSAGING_DEVICE_PATH) {
1040     return EFI_UNSUPPORTED;
1041   }
1042
1043   Node    = (NVME_NAMESPACE_DEVICE_PATH *)DevicePath;
1044   Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
1045
1046   if (DevicePath->SubType == MSG_NVME_NAMESPACE_DP) {
1047     if (DevicePathNodeLength(DevicePath) != sizeof(NVME_NAMESPACE_DEVICE_PATH)) {
1048       return EFI_NOT_FOUND;
1049     }
1050
1051     //
1052     // Check NamespaceId in the device path node is valid or not.
1053     //
1054     if ((Node->NamespaceId == 0) ||
1055       (Node->NamespaceId > Private->ControllerData->Nn)) {
1056       return EFI_NOT_FOUND;
1057     }
1058
1059     *NamespaceId = Node->NamespaceId;
1060
1061     return EFI_SUCCESS;
1062   } else {
1063     return EFI_UNSUPPORTED;
1064   }
1065 }
1066
1067 /**
1068   Used to allocate and build a device path node for an NVM Express namespace on an NVM Express controller.
1069
1070   The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.BuildDevicePath() function allocates and builds a single device
1071   path node for the NVM Express namespace specified by NamespaceId.
1072
1073   If the NamespaceId is not valid, then EFI_NOT_FOUND is returned.
1074
1075   If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned.
1076
1077   If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES is returned.
1078
1079   Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of DevicePath are
1080   initialized to describe the NVM Express namespace specified by NamespaceId, and EFI_SUCCESS is returned.
1081
1082   @param[in]     This                A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
1083   @param[in]     NamespaceId         The NVM Express namespace ID  for which a device path node is to be
1084                                      allocated and built. Caller must set the NamespaceId to zero if the
1085                                      device path node will contain a valid UUID.
1086   @param[in,out] DevicePath          A pointer to a single device path node that describes the NVM Express
1087                                      namespace specified by NamespaceId. This function is responsible for
1088                                      allocating the buffer DevicePath with the boot service AllocatePool().
1089                                      It is the caller's responsibility to free DevicePath when the caller
1090                                      is finished with DevicePath.
1091   @retval EFI_SUCCESS                The device path node that describes the NVM Express namespace specified
1092                                      by NamespaceId was allocated and returned in DevicePath.
1093   @retval EFI_NOT_FOUND              The NamespaceId is not valid.
1094   @retval EFI_INVALID_PARAMETER      DevicePath is NULL.
1095   @retval EFI_OUT_OF_RESOURCES       There are not enough resources to allocate the DevicePath node.
1096
1097 **/
1098 EFI_STATUS
1099 EFIAPI
1100 NvmExpressBuildDevicePath (
1101   IN     EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL          *This,
1102   IN     UINT32                                      NamespaceId,
1103   IN OUT EFI_DEVICE_PATH_PROTOCOL                    **DevicePath
1104   )
1105 {
1106   NVME_NAMESPACE_DEVICE_PATH     *Node;
1107   NVME_CONTROLLER_PRIVATE_DATA   *Private;
1108   EFI_STATUS                     Status;
1109   NVME_ADMIN_NAMESPACE_DATA      *NamespaceData;
1110
1111   //
1112   // Validate parameters
1113   //
1114   if ((This == NULL) || (DevicePath == NULL)) {
1115     return EFI_INVALID_PARAMETER;
1116   }
1117
1118   Status  = EFI_SUCCESS;
1119   Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
1120
1121   //
1122   // Check NamespaceId is valid or not.
1123   //
1124   if ((NamespaceId == 0) ||
1125     (NamespaceId > Private->ControllerData->Nn)) {
1126     return EFI_NOT_FOUND;
1127   }
1128
1129   Node = (NVME_NAMESPACE_DEVICE_PATH *)AllocateZeroPool (sizeof (NVME_NAMESPACE_DEVICE_PATH));
1130   if (Node == NULL) {
1131     return EFI_OUT_OF_RESOURCES;
1132   }
1133
1134   Node->Header.Type    = MESSAGING_DEVICE_PATH;
1135   Node->Header.SubType = MSG_NVME_NAMESPACE_DP;
1136   SetDevicePathNodeLength (&Node->Header, sizeof (NVME_NAMESPACE_DEVICE_PATH));
1137   Node->NamespaceId    = NamespaceId;
1138
1139   //
1140   // Allocate a buffer for Identify Namespace data.
1141   //
1142   NamespaceData = NULL;
1143   NamespaceData = AllocateZeroPool(sizeof (NVME_ADMIN_NAMESPACE_DATA));
1144   if(NamespaceData == NULL) {
1145     Status = EFI_OUT_OF_RESOURCES;
1146     goto Exit;
1147   }
1148
1149   //
1150   // Get UUID from specified Identify Namespace data.
1151   //
1152   Status = NvmeIdentifyNamespace (
1153              Private,
1154              NamespaceId,
1155              (VOID *)NamespaceData
1156              );
1157
1158   if (EFI_ERROR(Status)) {
1159     goto Exit;
1160   }
1161
1162   Node->NamespaceUuid = NamespaceData->Eui64;
1163
1164   *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)Node;
1165
1166 Exit:
1167   if(NamespaceData != NULL) {
1168     FreePool (NamespaceData);
1169   }
1170
1171   if (EFI_ERROR (Status)) {
1172     FreePool (Node);
1173   }
1174
1175   return Status;
1176 }
1177