MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c

   1 /** @file
   2   NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows
   3   NVM Express specification.
   4
   5   (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
   6   Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
   7   This program and the accompanying materials
   8   are licensed and made available under the terms and conditions of the BSD License
   9   which accompanies this distribution.  The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php.
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 #include "NvmExpress.h"
  18
  19 //
  20 // Page size should be set in the Controller Configuration register
  21 // during controller init, and the controller configuration save in
  22 // the controller's private data.  The Max and Min supported page sizes
  23 // for the controller are specified in the Controller Capabilities register.
  24 //
  25
  26 GLOBAL_REMOVE_IF_UNREFERENCED NVM_EXPRESS_PASS_THRU_MODE gNvmExpressPassThruMode = {
  27   0,
  28   NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL | NVM_EXPRESS_PASS_THRU_ATTRIBUTES_CMD_SET_NVME,
  29   sizeof (UINTN),
  30   0x10000,
  31   0,
  32   0
  33 };
  34
  35
  36 /**
  37   Dump the execution status from a given completion queue entry.
  38
  39   @param[in]     Cq               A pointer to the NVME_CQ item.
  40
  41 **/
  42 VOID
  43 NvmeDumpStatus (
  44   IN NVME_CQ             *Cq
  45   )
  46 {
  47   DEBUG ((EFI_D_VERBOSE, "Dump NVMe Completion Entry Status from [0x%x]:\n", Cq));
  48
  49   DEBUG ((EFI_D_VERBOSE, "  SQ Identifier : [0x%x], Phase Tag : [%d], Cmd Identifier : [0x%x]\n", Cq->Sqid, Cq->Pt, Cq->Cid));
  50
  51   DEBUG ((EFI_D_VERBOSE, "  NVMe Cmd Execution Result - "));
  52
  53   switch (Cq->Sct) {
  54     case 0x0:
  55       switch (Cq->Sc) {
  56         case 0x0:
  57           DEBUG ((EFI_D_VERBOSE, "Successful Completion\n"));
  58           break;
  59         case 0x1:
  60           DEBUG ((EFI_D_VERBOSE, "Invalid Command Opcode\n"));
  61           break;
  62         case 0x2:
  63           DEBUG ((EFI_D_VERBOSE, "Invalid Field in Command\n"));
  64           break;
  65         case 0x3:
  66           DEBUG ((EFI_D_VERBOSE, "Command ID Conflict\n"));
  67           break;
  68         case 0x4:
  69           DEBUG ((EFI_D_VERBOSE, "Data Transfer Error\n"));
  70           break;
  71         case 0x5:
  72           DEBUG ((EFI_D_VERBOSE, "Commands Aborted due to Power Loss Notification\n"));
  73           break;
  74         case 0x6:
  75           DEBUG ((EFI_D_VERBOSE, "Internal Device Error\n"));
  76           break;
  77         case 0x7:
  78           DEBUG ((EFI_D_VERBOSE, "Command Abort Requested\n"));
  79           break;
  80         case 0x8:
  81           DEBUG ((EFI_D_VERBOSE, "Command Aborted due to SQ Deletion\n"));
  82           break;
  83         case 0x9:
  84           DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Failed Fused Command\n"));
  85           break;
  86         case 0xA:
  87           DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Missing Fused Command\n"));
  88           break;
  89         case 0xB:
  90           DEBUG ((EFI_D_VERBOSE, "Invalid Namespace or Format\n"));
  91           break;
  92         case 0xC:
  93           DEBUG ((EFI_D_VERBOSE, "Command Sequence Error\n"));
  94           break;
  95         case 0xD:
  96           DEBUG ((EFI_D_VERBOSE, "Invalid SGL Last Segment Descriptor\n"));
  97           break;
  98         case 0xE:
  99           DEBUG ((EFI_D_VERBOSE, "Invalid Number of SGL Descriptors\n"));
 100           break;
 101         case 0xF:
 102           DEBUG ((EFI_D_VERBOSE, "Data SGL Length Invalid\n"));
 103           break;
 104         case 0x10:
 105           DEBUG ((EFI_D_VERBOSE, "Metadata SGL Length Invalid\n"));
 106           break;
 107         case 0x11:
 108           DEBUG ((EFI_D_VERBOSE, "SGL Descriptor Type Invalid\n"));
 109           break;
 110         case 0x80:
 111           DEBUG ((EFI_D_VERBOSE, "LBA Out of Range\n"));
 112           break;
 113         case 0x81:
 114           DEBUG ((EFI_D_VERBOSE, "Capacity Exceeded\n"));
 115           break;
 116         case 0x82:
 117           DEBUG ((EFI_D_VERBOSE, "Namespace Not Ready\n"));
 118           break;
 119         case 0x83:
 120           DEBUG ((EFI_D_VERBOSE, "Reservation Conflict\n"));
 121           break;
 122       }
 123       break;
 124
 125     case 0x1:
 126       switch (Cq->Sc) {
 127         case 0x0:
 128           DEBUG ((EFI_D_VERBOSE, "Completion Queue Invalid\n"));
 129           break;
 130         case 0x1:
 131           DEBUG ((EFI_D_VERBOSE, "Invalid Queue Identifier\n"));
 132           break;
 133         case 0x2:
 134           DEBUG ((EFI_D_VERBOSE, "Maximum Queue Size Exceeded\n"));
 135           break;
 136         case 0x3:
 137           DEBUG ((EFI_D_VERBOSE, "Abort Command Limit Exceeded\n"));
 138           break;
 139         case 0x5:
 140           DEBUG ((EFI_D_VERBOSE, "Asynchronous Event Request Limit Exceeded\n"));
 141           break;
 142         case 0x6:
 143           DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Slot\n"));
 144           break;
 145         case 0x7:
 146           DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Image\n"));
 147           break;
 148         case 0x8:
 149           DEBUG ((EFI_D_VERBOSE, "Invalid Interrupt Vector\n"));
 150           break;
 151         case 0x9:
 152           DEBUG ((EFI_D_VERBOSE, "Invalid Log Page\n"));
 153           break;
 154         case 0xA:
 155           DEBUG ((EFI_D_VERBOSE, "Invalid Format\n"));
 156           break;
 157         case 0xB:
 158           DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires Conventional Reset\n"));
 159           break;
 160         case 0xC:
 161           DEBUG ((EFI_D_VERBOSE, "Invalid Queue Deletion\n"));
 162           break;
 163         case 0xD:
 164           DEBUG ((EFI_D_VERBOSE, "Feature Identifier Not Saveable\n"));
 165           break;
 166         case 0xE:
 167           DEBUG ((EFI_D_VERBOSE, "Feature Not Changeable\n"));
 168           break;
 169         case 0xF:
 170           DEBUG ((EFI_D_VERBOSE, "Feature Not Namespace Specific\n"));
 171           break;
 172         case 0x10:
 173           DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires NVM Subsystem Reset\n"));
 174           break;
 175         case 0x80:
 176           DEBUG ((EFI_D_VERBOSE, "Conflicting Attributes\n"));
 177           break;
 178         case 0x81:
 179           DEBUG ((EFI_D_VERBOSE, "Invalid Protection Information\n"));
 180           break;
 181         case 0x82:
 182           DEBUG ((EFI_D_VERBOSE, "Attempted Write to Read Only Range\n"));
 183           break;
 184       }
 185       break;
 186
 187     case 0x2:
 188       switch (Cq->Sc) {
 189         case 0x80:
 190           DEBUG ((EFI_D_VERBOSE, "Write Fault\n"));
 191           break;
 192         case 0x81:
 193           DEBUG ((EFI_D_VERBOSE, "Unrecovered Read Error\n"));
 194           break;
 195         case 0x82:
 196           DEBUG ((EFI_D_VERBOSE, "End-to-end Guard Check Error\n"));
 197           break;
 198         case 0x83:
 199           DEBUG ((EFI_D_VERBOSE, "End-to-end Application Tag Check Error\n"));
 200           break;
 201         case 0x84:
 202           DEBUG ((EFI_D_VERBOSE, "End-to-end Reference Tag Check Error\n"));
 203           break;
 204         case 0x85:
 205           DEBUG ((EFI_D_VERBOSE, "Compare Failure\n"));
 206           break;
 207         case 0x86:
 208           DEBUG ((EFI_D_VERBOSE, "Access Denied\n"));
 209           break;
 210       }
 211       break;
 212
 213     default:
 214       break;
 215   }
 216 }
 217
 218 /**
 219   Create PRP lists for data transfer which is larger than 2 memory pages.
 220   Note here we calcuate the number of required PRP lists and allocate them at one time.
 221
 222   @param[in]     PciIo               A pointer to the EFI_PCI_IO_PROTOCOL instance.
 223   @param[in]     PhysicalAddr        The physical base address of data buffer.
 224   @param[in]     Pages               The number of pages to be transfered.
 225   @param[out]    PrpListHost         The host base address of PRP lists.
 226   @param[in,out] PrpListNo           The number of PRP List.
 227   @param[out]    Mapping             The mapping value returned from PciIo.Map().
 228
 229   @retval The pointer to the first PRP List of the PRP lists.
 230
 231 **/
 232 VOID*
 233 NvmeCreatePrpList (
 234   IN     EFI_PCI_IO_PROTOCOL          *PciIo,
 235   IN     EFI_PHYSICAL_ADDRESS         PhysicalAddr,
 236   IN     UINTN                        Pages,
 237      OUT VOID                         **PrpListHost,
 238   IN OUT UINTN                        *PrpListNo,
 239      OUT VOID                         **Mapping
 240   )
 241 {
 242   UINTN                       PrpEntryNo;
 243   UINT64                      PrpListBase;
 244   UINTN                       PrpListIndex;
 245   UINTN                       PrpEntryIndex;
 246   UINT64                      Remainder;
 247   EFI_PHYSICAL_ADDRESS        PrpListPhyAddr;
 248   UINTN                       Bytes;
 249   EFI_STATUS                  Status;
 250
 251   //
 252   // The number of Prp Entry in a memory page.
 253   //
 254   PrpEntryNo = EFI_PAGE_SIZE / sizeof (UINT64);
 255
 256   //
 257   // Calculate total PrpList number.
 258   //
 259   *PrpListNo = (UINTN)DivU64x64Remainder ((UINT64)Pages, (UINT64)PrpEntryNo, &Remainder);
 260   if (Remainder != 0) {
 261     *PrpListNo += 1;
 262   }
 263
 264   Status = PciIo->AllocateBuffer (
 265                     PciIo,
 266                     AllocateAnyPages,
 267                     EfiBootServicesData,
 268                     *PrpListNo,
 269                     PrpListHost,
 270                     0
 271                     );
 272
 273   if (EFI_ERROR (Status)) {
 274     return NULL;
 275   }
 276
 277   Bytes = EFI_PAGES_TO_SIZE (*PrpListNo);
 278   Status = PciIo->Map (
 279                     PciIo,
 280                     EfiPciIoOperationBusMasterCommonBuffer,
 281                     *PrpListHost,
 282                     &Bytes,
 283                     &PrpListPhyAddr,
 284                     Mapping
 285                     );
 286
 287   if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (*PrpListNo))) {
 288     DEBUG ((EFI_D_ERROR, "NvmeCreatePrpList: create PrpList failure!\n"));
 289     goto EXIT;
 290   }
 291   //
 292   // Fill all PRP lists except of last one.
 293   //
 294   ZeroMem (*PrpListHost, Bytes);
 295   for (PrpListIndex = 0; PrpListIndex < *PrpListNo - 1; ++PrpListIndex) {
 296     PrpListBase = *(UINT8*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
 297
 298     for (PrpEntryIndex = 0; PrpEntryIndex < PrpEntryNo; ++PrpEntryIndex) {
 299       if (PrpEntryIndex != PrpEntryNo - 1) {
 300         //
 301         // Fill all PRP entries except of last one.
 302         //
 303         *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;
 304         PhysicalAddr += EFI_PAGE_SIZE;
 305       } else {
 306         //
 307         // Fill last PRP entries with next PRP List pointer.
 308         //
 309         *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PrpListPhyAddr + (PrpListIndex + 1) * EFI_PAGE_SIZE;
 310       }
 311     }
 312   }
 313   //
 314   // Fill last PRP list.
 315   //
 316   PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
 317   for (PrpEntryIndex = 0; PrpEntryIndex < ((Remainder != 0) ? Remainder : PrpEntryNo); ++PrpEntryIndex) {
 318     *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;
 319     PhysicalAddr += EFI_PAGE_SIZE;
 320   }
 321
 322   return (VOID*)(UINTN)PrpListPhyAddr;
 323
 324 EXIT:
 325   PciIo->FreeBuffer (PciIo, *PrpListNo, *PrpListHost);
 326   return NULL;
 327 }
 328
 329
 330 /**
 331   Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports
 332   both blocking I/O and nonblocking I/O. The blocking I/O functionality is required, and the nonblocking
 333   I/O functionality is optional.
 334
 335   @param[in]     This                A pointer to the NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
 336   @param[in]     NamespaceId         Is a 32 bit Namespace ID to which the Express HCI command packet will be sent.
 337                                      A value of 0 denotes the NVM Express controller, a value of all 0FFh in the namespace
 338                                      ID specifies that the command packet should be sent to all valid namespaces.
 339   @param[in]     NamespaceUuid       Is a 64 bit Namespace UUID to which the Express HCI command packet will be sent.
 340                                      A value of 0 denotes the NVM Express controller, a value of all 0FFh in the namespace
 341                                      UUID specifies that the command packet should be sent to all valid namespaces.
 342   @param[in,out] Packet              A pointer to the NVM Express HCI Command Packet to send to the NVMe namespace specified
 343                                      by NamespaceId.
 344   @param[in]     Event               If nonblocking I/O is not supported then Event is ignored, and blocking I/O is performed.
 345                                      If Event is NULL, then blocking I/O is performed. If Event is not NULL and non blocking I/O
 346                                      is supported, then nonblocking I/O is performed, and Event will be signaled when the NVM
 347                                      Express Command Packet completes.
 348
 349   @retval EFI_SUCCESS                The NVM Express Command Packet was sent by the host. TransferLength bytes were transferred
 350                                      to, or from DataBuffer.
 351   @retval EFI_BAD_BUFFER_SIZE        The NVM Express Command Packet was not executed. The number of bytes that could be transferred
 352                                      is returned in TransferLength.
 353   @retval EFI_NOT_READY              The NVM Express Command Packet could not be sent because the controller is not ready. The caller
 354                                      may retry again later.
 355   @retval EFI_DEVICE_ERROR           A device error occurred while attempting to send the NVM Express Command Packet.
 356   @retval EFI_INVALID_PARAMETER      Namespace, or the contents of NVM_EXPRESS_PASS_THRU_COMMAND_PACKET are invalid. The NVM
 357                                      Express Command Packet was not sent, so no additional status information is available.
 358   @retval EFI_UNSUPPORTED            The command described by the NVM Express Command Packet is not supported by the host adapter.
 359                                      The NVM Express Command Packet was not sent, so no additional status information is available.
 360   @retval EFI_TIMEOUT                A timeout occurred while waiting for the NVM Express Command Packet to execute.
 361
 362 **/
 363 EFI_STATUS
 364 EFIAPI
 365 NvmExpressPassThru (
 366   IN     NVM_EXPRESS_PASS_THRU_PROTOCOL              *This,
 367   IN     UINT32                                      NamespaceId,
 368   IN     UINT64                                      NamespaceUuid,
 369   IN OUT NVM_EXPRESS_PASS_THRU_COMMAND_PACKET        *Packet,
 370   IN     EFI_EVENT                                   Event OPTIONAL
 371   )
 372 {
 373   NVME_CONTROLLER_PRIVATE_DATA  *Private;
 374   EFI_STATUS                    Status;
 375   EFI_PCI_IO_PROTOCOL           *PciIo;
 376   NVME_SQ                       *Sq;
 377   NVME_CQ                       *Cq;
 378   UINT8                         Qid;
 379   UINT32                        Bytes;
 380   UINT16                        Offset;
 381   EFI_EVENT                     TimerEvent;
 382   EFI_PCI_IO_PROTOCOL_OPERATION Flag;
 383   EFI_PHYSICAL_ADDRESS          PhyAddr;
 384   VOID                          *MapData;
 385   VOID                          *MapMeta;
 386   VOID                          *MapPrpList;
 387   UINTN                         MapLength;
 388   UINT64                        *Prp;
 389   VOID                          *PrpListHost;
 390   UINTN                         PrpListNo;
 391   UINT32                        Data;
 392
 393   //
 394   // check the data fields in Packet parameter.
 395   //
 396   if ((This == NULL) || (Packet == NULL)) {
 397     return EFI_INVALID_PARAMETER;
 398   }
 399
 400   if ((Packet->NvmeCmd == NULL) || (Packet->NvmeResponse == NULL)) {
 401     return EFI_INVALID_PARAMETER;
 402   }
 403
 404   if (Packet->QueueId != NVME_ADMIN_QUEUE && Packet->QueueId != NVME_IO_QUEUE) {
 405     return EFI_INVALID_PARAMETER;
 406   }
 407
 408   Private     = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
 409   PciIo       = Private->PciIo;
 410   MapData     = NULL;
 411   MapMeta     = NULL;
 412   MapPrpList  = NULL;
 413   PrpListHost = NULL;
 414   PrpListNo   = 0;
 415   Prp         = NULL;
 416   TimerEvent  = NULL;
 417   Status      = EFI_SUCCESS;
 418
 419   Qid = Packet->QueueId;
 420   Sq  = Private->SqBuffer[Qid] + Private->SqTdbl[Qid].Sqt;
 421   Cq  = Private->CqBuffer[Qid] + Private->CqHdbl[Qid].Cqh;
 422
 423   if (Packet->NvmeCmd->Nsid != NamespaceId) {
 424     return EFI_INVALID_PARAMETER;
 425   }
 426
 427   ZeroMem (Sq, sizeof (NVME_SQ));
 428   Sq->Opc  = Packet->NvmeCmd->Cdw0.Opcode;
 429   Sq->Fuse = Packet->NvmeCmd->Cdw0.FusedOperation;
 430   Sq->Cid  = Packet->NvmeCmd->Cdw0.Cid;
 431   Sq->Nsid = Packet->NvmeCmd->Nsid;
 432
 433   //
 434   // Currently we only support PRP for data transfer, SGL is NOT supported.
 435   //
 436   ASSERT (Sq->Psdt == 0);
 437   if (Sq->Psdt != 0) {
 438     DEBUG ((EFI_D_ERROR, "NvmExpressPassThru: doesn't support SGL mechanism\n"));
 439     return EFI_UNSUPPORTED;
 440   }
 441
 442   Sq->Prp[0] = (UINT64)(UINTN)Packet->TransferBuffer;
 443   //
 444   // If the NVMe cmd has data in or out, then mapping the user buffer to the PCI controller specific addresses.
 445   // Note here we don't handle data buffer for CreateIOSubmitionQueue and CreateIOCompletionQueue cmds because
 446   // these two cmds are special which requires their data buffer must support simultaneous access by both the
 447   // processor and a PCI Bus Master. It's caller's responsbility to ensure this.
 448   //
 449   if (((Sq->Opc & (BIT0 | BIT1)) != 0) && (Sq->Opc != NVME_ADMIN_CRIOCQ_OPC) && (Sq->Opc != NVME_ADMIN_CRIOSQ_OPC)) {
 450     if ((Sq->Opc & BIT0) != 0) {
 451       Flag = EfiPciIoOperationBusMasterRead;
 452     } else {
 453       Flag = EfiPciIoOperationBusMasterWrite;
 454     }
 455
 456     MapLength = Packet->TransferLength;
 457     Status = PciIo->Map (
 458                       PciIo,
 459                       Flag,
 460                       Packet->TransferBuffer,
 461                       &MapLength,
 462                       &PhyAddr,
 463                       &MapData
 464                       );
 465     if (EFI_ERROR (Status) || (Packet->TransferLength != MapLength)) {
 466       return EFI_OUT_OF_RESOURCES;
 467     }
 468
 469     Sq->Prp[0] = PhyAddr;
 470     Sq->Prp[1] = 0;
 471
 472     MapLength = Packet->MetadataLength;
 473     if(Packet->MetadataBuffer != NULL) {
 474       MapLength = Packet->MetadataLength;
 475       Status = PciIo->Map (
 476                         PciIo,
 477                         Flag,
 478                         Packet->MetadataBuffer,
 479                         &MapLength,
 480                         &PhyAddr,
 481                         &MapMeta
 482                         );
 483       if (EFI_ERROR (Status) || (Packet->MetadataLength != MapLength)) {
 484         PciIo->Unmap (
 485                  PciIo,
 486                  MapData
 487                  );
 488
 489         return EFI_OUT_OF_RESOURCES;
 490       }
 491       Sq->Mptr = PhyAddr;
 492     }
 493   }
 494   //
 495   // If the buffer size spans more than two memory pages (page size as defined in CC.Mps),
 496   // then build a PRP list in the second PRP submission queue entry.
 497   //
 498   Offset = ((UINT16)Sq->Prp[0]) & (EFI_PAGE_SIZE - 1);
 499   Bytes  = Packet->TransferLength;
 500
 501   if ((Offset + Bytes) > (EFI_PAGE_SIZE * 2)) {
 502     //
 503     // Create PrpList for remaining data buffer.
 504     //
 505     PhyAddr = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);
 506     Prp = NvmeCreatePrpList (PciIo, PhyAddr, EFI_SIZE_TO_PAGES(Offset + Bytes) - 1, &PrpListHost, &PrpListNo, &MapPrpList);
 507     if (Prp == NULL) {
 508       goto EXIT;
 509     }
 510
 511     Sq->Prp[1] = (UINT64)(UINTN)Prp;
 512   } else if ((Offset + Bytes) > EFI_PAGE_SIZE) {
 513     Sq->Prp[1] = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);
 514   }
 515
 516   if(Packet->NvmeCmd->Flags & CDW10_VALID) {
 517     Sq->Payload.Raw.Cdw10 = Packet->NvmeCmd->Cdw10;
 518   }
 519   if(Packet->NvmeCmd->Flags & CDW11_VALID) {
 520     Sq->Payload.Raw.Cdw11 = Packet->NvmeCmd->Cdw11;
 521   }
 522   if(Packet->NvmeCmd->Flags & CDW12_VALID) {
 523     Sq->Payload.Raw.Cdw12 = Packet->NvmeCmd->Cdw12;
 524   }
 525   if(Packet->NvmeCmd->Flags & CDW13_VALID) {
 526     Sq->Payload.Raw.Cdw13 = Packet->NvmeCmd->Cdw13;
 527   }
 528   if(Packet->NvmeCmd->Flags & CDW14_VALID) {
 529     Sq->Payload.Raw.Cdw14 = Packet->NvmeCmd->Cdw14;
 530   }
 531   if(Packet->NvmeCmd->Flags & CDW15_VALID) {
 532     Sq->Payload.Raw.Cdw15 = Packet->NvmeCmd->Cdw15;
 533   }
 534
 535   //
 536   // Ring the submission queue doorbell.
 537   //
 538   Private->SqTdbl[Qid].Sqt ^= 1;
 539   Data = ReadUnaligned32 ((UINT32*)&Private->SqTdbl[Qid]);
 540   PciIo->Mem.Write (
 541                PciIo,
 542                EfiPciIoWidthUint32,
 543                NVME_BAR,
 544                NVME_SQTDBL_OFFSET(Qid, Private->Cap.Dstrd),
 545                1,
 546                &Data
 547                );
 548
 549   Status = gBS->CreateEvent (
 550                   EVT_TIMER,
 551                   TPL_CALLBACK,
 552                   NULL,
 553                   NULL,
 554                   &TimerEvent
 555                   );
 556   if (EFI_ERROR (Status)) {
 557     goto EXIT;
 558   }
 559
 560   Status = gBS->SetTimer(TimerEvent, TimerRelative, Packet->CommandTimeout);
 561
 562   if (EFI_ERROR(Status)) {
 563     Packet->ControllerStatus = NVM_EXPRESS_STATUS_CONTROLLER_DEVICE_ERROR;
 564     goto EXIT;
 565   }
 566
 567   //
 568   // Wait for completion queue to get filled in.
 569   //
 570   Status = EFI_TIMEOUT;
 571   Packet->ControllerStatus = NVM_EXPRESS_STATUS_CONTROLLER_TIMEOUT_COMMAND;
 572   while (EFI_ERROR (gBS->CheckEvent (TimerEvent))) {
 573     if (Cq->Pt != Private->Pt[Qid]) {
 574       Status = EFI_SUCCESS;
 575       Packet->ControllerStatus = NVM_EXPRESS_STATUS_CONTROLLER_READY;
 576       break;
 577     }
 578   }
 579
 580   if ((Private->CqHdbl[Qid].Cqh ^= 1) == 0) {
 581     Private->Pt[Qid] ^= 1;
 582   }
 583
 584   //
 585   // Copy the Respose Queue entry for this command to the callers response buffer
 586   //
 587   CopyMem(Packet->NvmeResponse, Cq, sizeof(NVM_EXPRESS_RESPONSE));
 588
 589   //
 590   // Dump every completion entry status for debugging.
 591   //
 592   DEBUG_CODE_BEGIN();
 593     NvmeDumpStatus(Cq);
 594   DEBUG_CODE_END();
 595
 596   Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[Qid]);
 597   PciIo->Mem.Write (
 598                PciIo,
 599                EfiPciIoWidthUint32,
 600                NVME_BAR,
 601                NVME_CQHDBL_OFFSET(Qid, Private->Cap.Dstrd),
 602                1,
 603                &Data
 604                );
 605
 606 EXIT:
 607   if (MapData != NULL) {
 608     PciIo->Unmap (
 609              PciIo,
 610              MapData
 611              );
 612   }
 613
 614   if (MapMeta != NULL) {
 615     PciIo->Unmap (
 616              PciIo,
 617              MapMeta
 618              );
 619   }
 620
 621   if (MapPrpList != NULL) {
 622     PciIo->Unmap (
 623              PciIo,
 624              MapPrpList
 625              );
 626   }
 627
 628   if (Prp != NULL) {
 629     PciIo->FreeBuffer (PciIo, PrpListNo, PrpListHost);
 630   }
 631
 632   if (TimerEvent != NULL) {
 633     gBS->CloseEvent (TimerEvent);
 634   }
 635   return Status;
 636 }
 637
 638 /**
 639   Used to retrieve the list of namespaces defined on an NVM Express controller.
 640
 641   The NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNextNamespace() function retrieves a list of namespaces
 642   defined on an NVM Express controller. If on input a NamespaceID is specified by all 0xFF in the
 643   namespace buffer, then the first namespace defined on the NVM Express controller is returned in
 644   NamespaceID, and a status of EFI_SUCCESS is returned.
 645
 646   If NamespaceId is a Namespace value that was returned on a previous call to GetNextNamespace(),
 647   then the next valid NamespaceId  for an NVM Express SSD namespace on the NVM Express controller
 648   is returned in NamespaceId, and EFI_SUCCESS is returned.
 649
 650   If Namespace array is not a 0xFFFFFFFF and NamespaceId was not returned on a previous call to
 651   GetNextNamespace(), then EFI_INVALID_PARAMETER is returned.
 652
 653   If NamespaceId is the NamespaceId of the last SSD namespace on the NVM Express controller, then
 654   EFI_NOT_FOUND is returned
 655
 656   @param[in]     This           A pointer to the NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
 657   @param[in,out] NamespaceId    On input, a pointer to a legal NamespaceId for an NVM Express
 658                                 namespace present on the NVM Express controller. On output, a
 659                                 pointer to the next NamespaceId of an NVM Express namespace on
 660                                 an NVM Express controller. An input value of 0xFFFFFFFF retrieves
 661                                 the first NamespaceId for an NVM Express namespace present on an
 662                                 NVM Express controller.
 663   @param[out]    NamespaceUuid  On output, the UUID associated with the next namespace, if a UUID
 664                                 is defined for that NamespaceId, otherwise, zero is returned in
 665                                 this parameter. If the caller does not require a UUID, then a NULL
 666                                 pointer may be passed.
 667
 668   @retval EFI_SUCCESS           The NamespaceId of the next Namespace was returned.
 669   @retval EFI_NOT_FOUND         There are no more namespaces defined on this controller.
 670   @retval EFI_INVALID_PARAMETER Namespace array is not a 0xFFFFFFFF and NamespaceId was not returned
 671                                 on a previous call to GetNextNamespace().
 672
 673 **/
 674 EFI_STATUS
 675 EFIAPI
 676 NvmExpressGetNextNamespace (
 677   IN     NVM_EXPRESS_PASS_THRU_PROTOCOL              *This,
 678   IN OUT UINT32                                      *NamespaceId,
 679      OUT UINT64                                      *NamespaceUuid  OPTIONAL
 680   )
 681 {
 682   NVME_CONTROLLER_PRIVATE_DATA     *Private;
 683   NVME_ADMIN_NAMESPACE_DATA        *NamespaceData;
 684   UINT32                           NextNamespaceId;
 685   EFI_STATUS                       Status;
 686
 687   if ((This == NULL) || (NamespaceId == NULL)) {
 688     return EFI_INVALID_PARAMETER;
 689   }
 690
 691   NamespaceData = NULL;
 692   Status        = EFI_NOT_FOUND;
 693
 694   Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
 695   //
 696   // If the NamespaceId input value is 0xFFFFFFFF, then get the first valid namespace ID
 697   //
 698   if (*NamespaceId == 0xFFFFFFFF) {
 699     //
 700     // Start with the first namespace ID
 701     //
 702     NextNamespaceId = 1;
 703     //
 704     // Allocate buffer for Identify Namespace data.
 705     //
 706     NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));
 707
 708     if (NamespaceData == NULL) {
 709       return EFI_NOT_FOUND;
 710     }
 711
 712     Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);
 713     if (EFI_ERROR(Status)) {
 714       goto Done;
 715     }
 716
 717     *NamespaceId = NextNamespaceId;
 718     if (NamespaceUuid != NULL) {
 719       *NamespaceUuid = NamespaceData->Eui64;
 720     }
 721   } else {
 722     if (*NamespaceId >= Private->ControllerData->Nn) {
 723       return EFI_INVALID_PARAMETER;
 724     }
 725
 726     NextNamespaceId = *NamespaceId + 1;
 727     //
 728     // Allocate buffer for Identify Namespace data.
 729     //
 730     NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));
 731     if (NamespaceData == NULL) {
 732       return EFI_NOT_FOUND;
 733     }
 734
 735     Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);
 736     if (EFI_ERROR(Status)) {
 737       goto Done;
 738     }
 739
 740     *NamespaceId = NextNamespaceId;
 741     if (NamespaceUuid != NULL) {
 742       *NamespaceUuid = NamespaceData->Eui64;
 743     }
 744   }
 745
 746 Done:
 747   if (NamespaceData != NULL) {
 748     FreePool(NamespaceData);
 749   }
 750
 751   return Status;
 752 }
 753
 754 /**
 755   Used to translate a device path node to a Namespace ID and Namespace UUID.
 756
 757   The NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNamwspace() function determines the Namespace ID and Namespace UUID
 758   associated with the NVM Express SSD namespace described by DevicePath. If DevicePath is a device path node type
 759   that the NVM Express Pass Thru driver supports, then the NVM Express Pass Thru driver will attempt to translate
 760   the contents DevicePath into a Namespace ID and UUID. If this translation is successful, then that Namespace ID
 761   and UUID are returned in NamespaceID and NamespaceUUID, and EFI_SUCCESS is returned.
 762
 763   @param[in]  This                A pointer to the NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
 764   @param[in]  DevicePath          A pointer to the device path node that describes an NVM Express namespace on
 765                                   the NVM Express controller.
 766   @param[out] NamespaceId         The NVM Express namespace ID contained in the device path node.
 767   @param[out] NamespaceUuid       The NVM Express namespace contained in the device path node.
 768
 769   @retval EFI_SUCCESS             DevicePath was successfully translated to NamespaceId and NamespaceUuid.
 770   @retval EFI_INVALID_PARAMETER   If DevicePath, NamespaceId, or NamespaceUuid are NULL, then EFI_INVALID_PARAMETER
 771                                   is returned.
 772   @retval EFI_UNSUPPORTED         If DevicePath is not a device path node type that the NVM Express Pass Thru driver
 773                                   supports, then EFI_UNSUPPORTED is returned.
 774   @retval EFI_NOT_FOUND           If DevicePath is a device path node type that the Nvm Express Pass Thru driver
 775                                   supports, but there is not a valid translation from DevicePath to a NamespaceID
 776                                   and NamespaceUuid, then EFI_NOT_FOUND is returned.
 777 **/
 778 EFI_STATUS
 779 EFIAPI
 780 NvmExpressGetNamespace (
 781   IN     NVM_EXPRESS_PASS_THRU_PROTOCOL              *This,
 782   IN     EFI_DEVICE_PATH_PROTOCOL                    *DevicePath,
 783      OUT UINT32                                      *NamespaceId,
 784      OUT UINT64                                      *NamespaceUuid
 785   )
 786 {
 787   NVME_NAMESPACE_DEVICE_PATH       *Node;
 788
 789   if ((This == NULL) || (DevicePath == NULL) || (NamespaceId == NULL) || (NamespaceUuid == NULL)) {
 790     return EFI_INVALID_PARAMETER;
 791   }
 792
 793   if (DevicePath->Type != MESSAGING_DEVICE_PATH) {
 794     return EFI_UNSUPPORTED;
 795   }
 796
 797   Node = (NVME_NAMESPACE_DEVICE_PATH *)DevicePath;
 798
 799   if (DevicePath->SubType == MSG_NVME_NAMESPACE_DP) {
 800     if (DevicePathNodeLength(DevicePath) != sizeof(NVME_NAMESPACE_DEVICE_PATH)) {
 801       return EFI_NOT_FOUND;
 802     }
 803
 804     *NamespaceId   = Node->NamespaceId;
 805     *NamespaceUuid = Node->NamespaceUuid;
 806
 807     return EFI_SUCCESS;
 808   } else {
 809     return EFI_UNSUPPORTED;
 810   }
 811 }
 812
 813 /**
 814   Used to allocate and build a device path node for an NVM Express namespace on an NVM Express controller.
 815
 816   The NVM_EXPRESS_PASS_THRU_PROTOCOL.BuildDevicePath() function allocates and builds a single device
 817   path node for the NVM Express namespace specified by NamespaceId.
 818
 819   If the namespace device specified by NamespaceId is not valid , then EFI_NOT_FOUND is returned.
 820
 821   If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned.
 822
 823   If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES is returned.
 824
 825   Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of DevicePath are
 826   initialized to describe the NVM Express namespace specified by NamespaceId, and EFI_SUCCESS is returned.
 827
 828   @param[in]     This                A pointer to the NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
 829   @param[in]     NamespaceId         The NVM Express namespace ID  for which a device path node is to be
 830                                      allocated and built. Caller must set the NamespaceId to zero if the
 831                                      device path node will contain a valid UUID.
 832   @param[in]     NamespaceUuid       The NVM Express namespace UUID for which a device path node is to be
 833                                      allocated and built. UUID will only be valid of the Namespace ID is zero.
 834   @param[in,out] DevicePath          A pointer to a single device path node that describes the NVM Express
 835                                      namespace specified by NamespaceId. This function is responsible for
 836                                      allocating the buffer DevicePath with the boot service AllocatePool().
 837                                      It is the caller's responsibility to free DevicePath when the caller
 838                                      is finished with DevicePath.
 839   @retval EFI_SUCCESS                The device path node that describes the NVM Express namespace specified
 840                                      by NamespaceId was allocated and returned in DevicePath.
 841   @retval EFI_NOT_FOUND              The NVM Express namespace specified by NamespaceId does not exist on the
 842                                      NVM Express controller.
 843   @retval EFI_INVALID_PARAMETER      DevicePath is NULL.
 844   @retval EFI_OUT_OF_RESOURCES       There are not enough resources to allocate the DevicePath node.
 845
 846 **/
 847 EFI_STATUS
 848 EFIAPI
 849 NvmExpressBuildDevicePath (
 850   IN     NVM_EXPRESS_PASS_THRU_PROTOCOL              *This,
 851   IN     UINT32                                      NamespaceId,
 852   IN     UINT64                                      NamespaceUuid,
 853   IN OUT EFI_DEVICE_PATH_PROTOCOL                    **DevicePath
 854   )
 855 {
 856   NVME_NAMESPACE_DEVICE_PATH     *Node;
 857
 858   //
 859   // Validate parameters
 860   //
 861   if ((This == NULL) || (DevicePath == NULL)) {
 862     return EFI_INVALID_PARAMETER;
 863   }
 864
 865   if (NamespaceId == 0) {
 866     return EFI_NOT_FOUND;
 867   }
 868
 869   Node = (NVME_NAMESPACE_DEVICE_PATH *)AllocateZeroPool (sizeof (NVME_NAMESPACE_DEVICE_PATH));
 870
 871   if (Node == NULL) {
 872     return EFI_OUT_OF_RESOURCES;
 873   }
 874
 875   Node->Header.Type    = MESSAGING_DEVICE_PATH;
 876   Node->Header.SubType = MSG_NVME_NAMESPACE_DP;
 877   SetDevicePathNodeLength (&Node->Header, sizeof (NVME_NAMESPACE_DEVICE_PATH));
 878   Node->NamespaceId    = NamespaceId;
 879   Node->NamespaceUuid  = NamespaceUuid;
 880
 881   *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)Node;
 882   return EFI_SUCCESS;
 883 }
 884