MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c

   1 /** @file
   2   NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows
   3   NVM Express specification.
   4
   5   (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
   6   Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.<BR>
   7   This program and the accompanying materials
   8   are licensed and made available under the terms and conditions of the BSD License
   9   which accompanies this distribution.  The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php.
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 #include "NvmExpress.h"
  18
  19 /**
  20   Dump the execution status from a given completion queue entry.
  21
  22   @param[in]     Cq               A pointer to the NVME_CQ item.
  23
  24 **/
  25 VOID
  26 NvmeDumpStatus (
  27   IN NVME_CQ             *Cq
  28   )
  29 {
  30   DEBUG ((EFI_D_VERBOSE, "Dump NVMe Completion Entry Status from [0x%x]:\n", Cq));
  31
  32   DEBUG ((EFI_D_VERBOSE, "  SQ Identifier : [0x%x], Phase Tag : [%d], Cmd Identifier : [0x%x]\n", Cq->Sqid, Cq->Pt, Cq->Cid));
  33
  34   DEBUG ((EFI_D_VERBOSE, "  NVMe Cmd Execution Result - "));
  35
  36   switch (Cq->Sct) {
  37     case 0x0:
  38       switch (Cq->Sc) {
  39         case 0x0:
  40           DEBUG ((EFI_D_VERBOSE, "Successful Completion\n"));
  41           break;
  42         case 0x1:
  43           DEBUG ((EFI_D_VERBOSE, "Invalid Command Opcode\n"));
  44           break;
  45         case 0x2:
  46           DEBUG ((EFI_D_VERBOSE, "Invalid Field in Command\n"));
  47           break;
  48         case 0x3:
  49           DEBUG ((EFI_D_VERBOSE, "Command ID Conflict\n"));
  50           break;
  51         case 0x4:
  52           DEBUG ((EFI_D_VERBOSE, "Data Transfer Error\n"));
  53           break;
  54         case 0x5:
  55           DEBUG ((EFI_D_VERBOSE, "Commands Aborted due to Power Loss Notification\n"));
  56           break;
  57         case 0x6:
  58           DEBUG ((EFI_D_VERBOSE, "Internal Device Error\n"));
  59           break;
  60         case 0x7:
  61           DEBUG ((EFI_D_VERBOSE, "Command Abort Requested\n"));
  62           break;
  63         case 0x8:
  64           DEBUG ((EFI_D_VERBOSE, "Command Aborted due to SQ Deletion\n"));
  65           break;
  66         case 0x9:
  67           DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Failed Fused Command\n"));
  68           break;
  69         case 0xA:
  70           DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Missing Fused Command\n"));
  71           break;
  72         case 0xB:
  73           DEBUG ((EFI_D_VERBOSE, "Invalid Namespace or Format\n"));
  74           break;
  75         case 0xC:
  76           DEBUG ((EFI_D_VERBOSE, "Command Sequence Error\n"));
  77           break;
  78         case 0xD:
  79           DEBUG ((EFI_D_VERBOSE, "Invalid SGL Last Segment Descriptor\n"));
  80           break;
  81         case 0xE:
  82           DEBUG ((EFI_D_VERBOSE, "Invalid Number of SGL Descriptors\n"));
  83           break;
  84         case 0xF:
  85           DEBUG ((EFI_D_VERBOSE, "Data SGL Length Invalid\n"));
  86           break;
  87         case 0x10:
  88           DEBUG ((EFI_D_VERBOSE, "Metadata SGL Length Invalid\n"));
  89           break;
  90         case 0x11:
  91           DEBUG ((EFI_D_VERBOSE, "SGL Descriptor Type Invalid\n"));
  92           break;
  93         case 0x80:
  94           DEBUG ((EFI_D_VERBOSE, "LBA Out of Range\n"));
  95           break;
  96         case 0x81:
  97           DEBUG ((EFI_D_VERBOSE, "Capacity Exceeded\n"));
  98           break;
  99         case 0x82:
 100           DEBUG ((EFI_D_VERBOSE, "Namespace Not Ready\n"));
 101           break;
 102         case 0x83:
 103           DEBUG ((EFI_D_VERBOSE, "Reservation Conflict\n"));
 104           break;
 105       }
 106       break;
 107
 108     case 0x1:
 109       switch (Cq->Sc) {
 110         case 0x0:
 111           DEBUG ((EFI_D_VERBOSE, "Completion Queue Invalid\n"));
 112           break;
 113         case 0x1:
 114           DEBUG ((EFI_D_VERBOSE, "Invalid Queue Identifier\n"));
 115           break;
 116         case 0x2:
 117           DEBUG ((EFI_D_VERBOSE, "Maximum Queue Size Exceeded\n"));
 118           break;
 119         case 0x3:
 120           DEBUG ((EFI_D_VERBOSE, "Abort Command Limit Exceeded\n"));
 121           break;
 122         case 0x5:
 123           DEBUG ((EFI_D_VERBOSE, "Asynchronous Event Request Limit Exceeded\n"));
 124           break;
 125         case 0x6:
 126           DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Slot\n"));
 127           break;
 128         case 0x7:
 129           DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Image\n"));
 130           break;
 131         case 0x8:
 132           DEBUG ((EFI_D_VERBOSE, "Invalid Interrupt Vector\n"));
 133           break;
 134         case 0x9:
 135           DEBUG ((EFI_D_VERBOSE, "Invalid Log Page\n"));
 136           break;
 137         case 0xA:
 138           DEBUG ((EFI_D_VERBOSE, "Invalid Format\n"));
 139           break;
 140         case 0xB:
 141           DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires Conventional Reset\n"));
 142           break;
 143         case 0xC:
 144           DEBUG ((EFI_D_VERBOSE, "Invalid Queue Deletion\n"));
 145           break;
 146         case 0xD:
 147           DEBUG ((EFI_D_VERBOSE, "Feature Identifier Not Saveable\n"));
 148           break;
 149         case 0xE:
 150           DEBUG ((EFI_D_VERBOSE, "Feature Not Changeable\n"));
 151           break;
 152         case 0xF:
 153           DEBUG ((EFI_D_VERBOSE, "Feature Not Namespace Specific\n"));
 154           break;
 155         case 0x10:
 156           DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires NVM Subsystem Reset\n"));
 157           break;
 158         case 0x80:
 159           DEBUG ((EFI_D_VERBOSE, "Conflicting Attributes\n"));
 160           break;
 161         case 0x81:
 162           DEBUG ((EFI_D_VERBOSE, "Invalid Protection Information\n"));
 163           break;
 164         case 0x82:
 165           DEBUG ((EFI_D_VERBOSE, "Attempted Write to Read Only Range\n"));
 166           break;
 167       }
 168       break;
 169
 170     case 0x2:
 171       switch (Cq->Sc) {
 172         case 0x80:
 173           DEBUG ((EFI_D_VERBOSE, "Write Fault\n"));
 174           break;
 175         case 0x81:
 176           DEBUG ((EFI_D_VERBOSE, "Unrecovered Read Error\n"));
 177           break;
 178         case 0x82:
 179           DEBUG ((EFI_D_VERBOSE, "End-to-end Guard Check Error\n"));
 180           break;
 181         case 0x83:
 182           DEBUG ((EFI_D_VERBOSE, "End-to-end Application Tag Check Error\n"));
 183           break;
 184         case 0x84:
 185           DEBUG ((EFI_D_VERBOSE, "End-to-end Reference Tag Check Error\n"));
 186           break;
 187         case 0x85:
 188           DEBUG ((EFI_D_VERBOSE, "Compare Failure\n"));
 189           break;
 190         case 0x86:
 191           DEBUG ((EFI_D_VERBOSE, "Access Denied\n"));
 192           break;
 193       }
 194       break;
 195
 196     default:
 197       break;
 198   }
 199 }
 200
 201 /**
 202   Create PRP lists for data transfer which is larger than 2 memory pages.
 203   Note here we calcuate the number of required PRP lists and allocate them at one time.
 204
 205   @param[in]     PciIo               A pointer to the EFI_PCI_IO_PROTOCOL instance.
 206   @param[in]     PhysicalAddr        The physical base address of data buffer.
 207   @param[in]     Pages               The number of pages to be transfered.
 208   @param[out]    PrpListHost         The host base address of PRP lists.
 209   @param[in,out] PrpListNo           The number of PRP List.
 210   @param[out]    Mapping             The mapping value returned from PciIo.Map().
 211
 212   @retval The pointer to the first PRP List of the PRP lists.
 213
 214 **/
 215 VOID*
 216 NvmeCreatePrpList (
 217   IN     EFI_PCI_IO_PROTOCOL          *PciIo,
 218   IN     EFI_PHYSICAL_ADDRESS         PhysicalAddr,
 219   IN     UINTN                        Pages,
 220      OUT VOID                         **PrpListHost,
 221   IN OUT UINTN                        *PrpListNo,
 222      OUT VOID                         **Mapping
 223   )
 224 {
 225   UINTN                       PrpEntryNo;
 226   UINT64                      PrpListBase;
 227   UINTN                       PrpListIndex;
 228   UINTN                       PrpEntryIndex;
 229   UINT64                      Remainder;
 230   EFI_PHYSICAL_ADDRESS        PrpListPhyAddr;
 231   UINTN                       Bytes;
 232   EFI_STATUS                  Status;
 233
 234   //
 235   // The number of Prp Entry in a memory page.
 236   //
 237   PrpEntryNo = EFI_PAGE_SIZE / sizeof (UINT64);
 238
 239   //
 240   // Calculate total PrpList number.
 241   //
 242   *PrpListNo = (UINTN)DivU64x64Remainder ((UINT64)Pages, (UINT64)PrpEntryNo - 1, &Remainder);
 243   if (*PrpListNo == 0) {
 244     *PrpListNo = 1;
 245   } else if ((Remainder != 0) && (Remainder != 1)) {
 246     *PrpListNo += 1;
 247   } else if (Remainder == 1) {
 248     Remainder = PrpEntryNo;
 249   } else if (Remainder == 0) {
 250     Remainder = PrpEntryNo - 1;
 251   }
 252
 253   Status = PciIo->AllocateBuffer (
 254                     PciIo,
 255                     AllocateAnyPages,
 256                     EfiBootServicesData,
 257                     *PrpListNo,
 258                     PrpListHost,
 259                     0
 260                     );
 261
 262   if (EFI_ERROR (Status)) {
 263     return NULL;
 264   }
 265
 266   Bytes = EFI_PAGES_TO_SIZE (*PrpListNo);
 267   Status = PciIo->Map (
 268                     PciIo,
 269                     EfiPciIoOperationBusMasterCommonBuffer,
 270                     *PrpListHost,
 271                     &Bytes,
 272                     &PrpListPhyAddr,
 273                     Mapping
 274                     );
 275
 276   if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (*PrpListNo))) {
 277     DEBUG ((EFI_D_ERROR, "NvmeCreatePrpList: create PrpList failure!\n"));
 278     goto EXIT;
 279   }
 280   //
 281   // Fill all PRP lists except of last one.
 282   //
 283   ZeroMem (*PrpListHost, Bytes);
 284   for (PrpListIndex = 0; PrpListIndex < *PrpListNo - 1; ++PrpListIndex) {
 285     PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
 286
 287     for (PrpEntryIndex = 0; PrpEntryIndex < PrpEntryNo; ++PrpEntryIndex) {
 288       if (PrpEntryIndex != PrpEntryNo - 1) {
 289         //
 290         // Fill all PRP entries except of last one.
 291         //
 292         *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;
 293         PhysicalAddr += EFI_PAGE_SIZE;
 294       } else {
 295         //
 296         // Fill last PRP entries with next PRP List pointer.
 297         //
 298         *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PrpListPhyAddr + (PrpListIndex + 1) * EFI_PAGE_SIZE;
 299       }
 300     }
 301   }
 302   //
 303   // Fill last PRP list.
 304   //
 305   PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
 306   for (PrpEntryIndex = 0; PrpEntryIndex < Remainder; ++PrpEntryIndex) {
 307     *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;
 308     PhysicalAddr += EFI_PAGE_SIZE;
 309   }
 310
 311   return (VOID*)(UINTN)PrpListPhyAddr;
 312
 313 EXIT:
 314   PciIo->FreeBuffer (PciIo, *PrpListNo, *PrpListHost);
 315   return NULL;
 316 }
 317
 318
 319 /**
 320   Aborts the asynchronous PassThru requests.
 321
 322   @param[in] Private        The pointer to the NVME_CONTROLLER_PRIVATE_DATA
 323                             data structure.
 324
 325   @retval EFI_SUCCESS       The asynchronous PassThru requests have been aborted.
 326   @return EFI_DEVICE_ERROR  Fail to abort all the asynchronous PassThru requests.
 327
 328 **/
 329 EFI_STATUS
 330 AbortAsyncPassThruTasks (
 331   IN NVME_CONTROLLER_PRIVATE_DATA    *Private
 332   )
 333 {
 334   EFI_PCI_IO_PROTOCOL                *PciIo;
 335   LIST_ENTRY                         *Link;
 336   LIST_ENTRY                         *NextLink;
 337   NVME_BLKIO2_SUBTASK                *Subtask;
 338   NVME_BLKIO2_REQUEST                *BlkIo2Request;
 339   NVME_PASS_THRU_ASYNC_REQ           *AsyncRequest;
 340   EFI_BLOCK_IO2_TOKEN                *Token;
 341   EFI_TPL                            OldTpl;
 342   EFI_STATUS                         Status;
 343
 344   PciIo  = Private->PciIo;
 345   OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
 346
 347   //
 348   // Cancel the unsubmitted subtasks.
 349   //
 350   for (Link = GetFirstNode (&Private->UnsubmittedSubtasks);
 351        !IsNull (&Private->UnsubmittedSubtasks, Link);
 352        Link = NextLink) {
 353     NextLink      = GetNextNode (&Private->UnsubmittedSubtasks, Link);
 354     Subtask       = NVME_BLKIO2_SUBTASK_FROM_LINK (Link);
 355     BlkIo2Request = Subtask->BlockIo2Request;
 356     Token         = BlkIo2Request->Token;
 357
 358     BlkIo2Request->UnsubmittedSubtaskNum--;
 359     if (Subtask->IsLast) {
 360       BlkIo2Request->LastSubtaskSubmitted = TRUE;
 361     }
 362     Token->TransactionStatus = EFI_ABORTED;
 363
 364     RemoveEntryList (Link);
 365     InsertTailList (&BlkIo2Request->SubtasksQueue, Link);
 366     gBS->SignalEvent (Subtask->Event);
 367   }
 368
 369   //
 370   // Cleanup the resources for the asynchronous PassThru requests.
 371   //
 372   for (Link = GetFirstNode (&Private->AsyncPassThruQueue);
 373        !IsNull (&Private->AsyncPassThruQueue, Link);
 374        Link = NextLink) {
 375     NextLink = GetNextNode (&Private->AsyncPassThruQueue, Link);
 376     AsyncRequest = NVME_PASS_THRU_ASYNC_REQ_FROM_THIS (Link);
 377
 378     if (AsyncRequest->MapData != NULL) {
 379       PciIo->Unmap (PciIo, AsyncRequest->MapData);
 380     }
 381     if (AsyncRequest->MapMeta != NULL) {
 382       PciIo->Unmap (PciIo, AsyncRequest->MapMeta);
 383     }
 384     if (AsyncRequest->MapPrpList != NULL) {
 385       PciIo->Unmap (PciIo, AsyncRequest->MapPrpList);
 386     }
 387     if (AsyncRequest->PrpListHost != NULL) {
 388       PciIo->FreeBuffer (
 389                PciIo,
 390                AsyncRequest->PrpListNo,
 391                AsyncRequest->PrpListHost
 392                );
 393     }
 394
 395     RemoveEntryList (Link);
 396     gBS->SignalEvent (AsyncRequest->CallerEvent);
 397     FreePool (AsyncRequest);
 398   }
 399
 400   if (IsListEmpty (&Private->AsyncPassThruQueue) &&
 401       IsListEmpty (&Private->UnsubmittedSubtasks)) {
 402     Status = EFI_SUCCESS;
 403   } else {
 404     Status = EFI_DEVICE_ERROR;
 405   }
 406
 407   gBS->RestoreTPL (OldTpl);
 408
 409   return Status;
 410 }
 411
 412
 413 /**
 414   Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports
 415   both blocking I/O and non-blocking I/O. The blocking I/O functionality is required, and the non-blocking
 416   I/O functionality is optional.
 417
 418
 419   @param[in]     This                A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
 420   @param[in]     NamespaceId         A 32 bit namespace ID as defined in the NVMe specification to which the NVM Express Command
 421                                      Packet will be sent.  A value of 0 denotes the NVM Express controller, a value of all 0xFF's
 422                                      (all bytes are 0xFF) in the namespace ID specifies that the command packet should be sent to
 423                                      all valid namespaces.
 424   @param[in,out] Packet              A pointer to the NVM Express Command Packet.
 425   @param[in]     Event               If non-blocking I/O is not supported then Event is ignored, and blocking I/O is performed.
 426                                      If Event is NULL, then blocking I/O is performed. If Event is not NULL and non-blocking I/O
 427                                      is supported, then non-blocking I/O is performed, and Event will be signaled when the NVM
 428                                      Express Command Packet completes.
 429
 430   @retval EFI_SUCCESS                The NVM Express Command Packet was sent by the host. TransferLength bytes were transferred
 431                                      to, or from DataBuffer.
 432   @retval EFI_BAD_BUFFER_SIZE        The NVM Express Command Packet was not executed. The number of bytes that could be transferred
 433                                      is returned in TransferLength.
 434   @retval EFI_NOT_READY              The NVM Express Command Packet could not be sent because the controller is not ready. The caller
 435                                      may retry again later.
 436   @retval EFI_DEVICE_ERROR           A device error occurred while attempting to send the NVM Express Command Packet.
 437   @retval EFI_INVALID_PARAMETER      NamespaceId or the contents of EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET are invalid. The NVM
 438                                      Express Command Packet was not sent, so no additional status information is available.
 439   @retval EFI_UNSUPPORTED            The command described by the NVM Express Command Packet is not supported by the NVM Express
 440                                      controller. The NVM Express Command Packet was not sent so no additional status information
 441                                      is available.
 442   @retval EFI_TIMEOUT                A timeout occurred while waiting for the NVM Express Command Packet to execute.
 443
 444 **/
 445 EFI_STATUS
 446 EFIAPI
 447 NvmExpressPassThru (
 448   IN     EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL          *This,
 449   IN     UINT32                                      NamespaceId,
 450   IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET    *Packet,
 451   IN     EFI_EVENT                                   Event OPTIONAL
 452   )
 453 {
 454   NVME_CONTROLLER_PRIVATE_DATA   *Private;
 455   EFI_STATUS                     Status;
 456   EFI_PCI_IO_PROTOCOL            *PciIo;
 457   NVME_SQ                        *Sq;
 458   NVME_CQ                        *Cq;
 459   UINT16                         QueueId;
 460   UINT32                         Bytes;
 461   UINT16                         Offset;
 462   EFI_EVENT                      TimerEvent;
 463   EFI_PCI_IO_PROTOCOL_OPERATION  Flag;
 464   EFI_PHYSICAL_ADDRESS           PhyAddr;
 465   VOID                           *MapData;
 466   VOID                           *MapMeta;
 467   VOID                           *MapPrpList;
 468   UINTN                          MapLength;
 469   UINT64                         *Prp;
 470   VOID                           *PrpListHost;
 471   UINTN                          PrpListNo;
 472   UINT32                         Attributes;
 473   UINT32                         IoAlign;
 474   UINT32                         MaxTransLen;
 475   UINT32                         Data;
 476   NVME_PASS_THRU_ASYNC_REQ       *AsyncRequest;
 477   EFI_TPL                        OldTpl;
 478
 479   //
 480   // check the data fields in Packet parameter.
 481   //
 482   if ((This == NULL) || (Packet == NULL)) {
 483     return EFI_INVALID_PARAMETER;
 484   }
 485
 486   if ((Packet->NvmeCmd == NULL) || (Packet->NvmeCompletion == NULL)) {
 487     return EFI_INVALID_PARAMETER;
 488   }
 489
 490   if (Packet->QueueType != NVME_ADMIN_QUEUE && Packet->QueueType != NVME_IO_QUEUE) {
 491     return EFI_INVALID_PARAMETER;
 492   }
 493
 494   //
 495   // 'Attributes' with neither EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL nor
 496   // EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL set is an illegal
 497   // configuration.
 498   //
 499   Attributes  = This->Mode->Attributes;
 500   if ((Attributes & (EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL |
 501     EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL)) == 0) {
 502     return EFI_INVALID_PARAMETER;
 503   }
 504
 505   //
 506   // Buffer alignment check for TransferBuffer & MetadataBuffer.
 507   //
 508   IoAlign     = This->Mode->IoAlign;
 509   if (IoAlign > 0 && (((UINTN) Packet->TransferBuffer & (IoAlign - 1)) != 0)) {
 510     return EFI_INVALID_PARAMETER;
 511   }
 512
 513   if (IoAlign > 0 && (((UINTN) Packet->MetadataBuffer & (IoAlign - 1)) != 0)) {
 514     return EFI_INVALID_PARAMETER;
 515   }
 516
 517   Private     = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
 518
 519   //
 520   // Check NamespaceId is valid or not.
 521   //
 522   if ((NamespaceId > Private->ControllerData->Nn) &&
 523       (NamespaceId != (UINT32) -1)) {
 524     return EFI_INVALID_PARAMETER;
 525   }
 526
 527   //
 528   // Check whether TransferLength exceeds the maximum data transfer size.
 529   //
 530   if (Private->ControllerData->Mdts != 0) {
 531     MaxTransLen = (1 << (Private->ControllerData->Mdts)) *
 532                   (1 << (Private->Cap.Mpsmin + 12));
 533     if (Packet->TransferLength > MaxTransLen) {
 534       Packet->TransferLength = MaxTransLen;
 535       return EFI_BAD_BUFFER_SIZE;
 536     }
 537   }
 538
 539   PciIo       = Private->PciIo;
 540   MapData     = NULL;
 541   MapMeta     = NULL;
 542   MapPrpList  = NULL;
 543   PrpListHost = NULL;
 544   PrpListNo   = 0;
 545   Prp         = NULL;
 546   TimerEvent  = NULL;
 547   Status      = EFI_SUCCESS;
 548
 549   if (Packet->QueueType == NVME_ADMIN_QUEUE) {
 550     QueueId = 0;
 551   } else {
 552     if (Event == NULL) {
 553       QueueId = 1;
 554     } else {
 555       QueueId = 2;
 556
 557       //
 558       // Submission queue full check.
 559       //
 560       if ((Private->SqTdbl[QueueId].Sqt + 1) % (NVME_ASYNC_CSQ_SIZE + 1) ==
 561           Private->AsyncSqHead) {
 562         return EFI_NOT_READY;
 563       }
 564     }
 565   }
 566   Sq  = Private->SqBuffer[QueueId] + Private->SqTdbl[QueueId].Sqt;
 567   Cq  = Private->CqBuffer[QueueId] + Private->CqHdbl[QueueId].Cqh;
 568
 569   if (Packet->NvmeCmd->Nsid != NamespaceId) {
 570     return EFI_INVALID_PARAMETER;
 571   }
 572
 573   ZeroMem (Sq, sizeof (NVME_SQ));
 574   Sq->Opc  = (UINT8)Packet->NvmeCmd->Cdw0.Opcode;
 575   Sq->Fuse = (UINT8)Packet->NvmeCmd->Cdw0.FusedOperation;
 576   Sq->Cid  = Private->Cid[QueueId]++;
 577   Sq->Nsid = Packet->NvmeCmd->Nsid;
 578
 579   //
 580   // Currently we only support PRP for data transfer, SGL is NOT supported.
 581   //
 582   ASSERT (Sq->Psdt == 0);
 583   if (Sq->Psdt != 0) {
 584     DEBUG ((EFI_D_ERROR, "NvmExpressPassThru: doesn't support SGL mechanism\n"));
 585     return EFI_UNSUPPORTED;
 586   }
 587
 588   Sq->Prp[0] = (UINT64)(UINTN)Packet->TransferBuffer;
 589   //
 590   // If the NVMe cmd has data in or out, then mapping the user buffer to the PCI controller specific addresses.
 591   // Note here we don't handle data buffer for CreateIOSubmitionQueue and CreateIOCompletionQueue cmds because
 592   // these two cmds are special which requires their data buffer must support simultaneous access by both the
 593   // processor and a PCI Bus Master. It's caller's responsbility to ensure this.
 594   //
 595   if (((Sq->Opc & (BIT0 | BIT1)) != 0) && (Sq->Opc != NVME_ADMIN_CRIOCQ_CMD) && (Sq->Opc != NVME_ADMIN_CRIOSQ_CMD)) {
 596     if ((Packet->TransferLength == 0) || (Packet->TransferBuffer == NULL)) {
 597       return EFI_INVALID_PARAMETER;
 598     }
 599
 600     if ((Sq->Opc & BIT0) != 0) {
 601       Flag = EfiPciIoOperationBusMasterRead;
 602     } else {
 603       Flag = EfiPciIoOperationBusMasterWrite;
 604     }
 605
 606     MapLength = Packet->TransferLength;
 607     Status = PciIo->Map (
 608                       PciIo,
 609                       Flag,
 610                       Packet->TransferBuffer,
 611                       &MapLength,
 612                       &PhyAddr,
 613                       &MapData
 614                       );
 615     if (EFI_ERROR (Status) || (Packet->TransferLength != MapLength)) {
 616       return EFI_OUT_OF_RESOURCES;
 617     }
 618
 619     Sq->Prp[0] = PhyAddr;
 620     Sq->Prp[1] = 0;
 621
 622     if((Packet->MetadataLength != 0) && (Packet->MetadataBuffer != NULL)) {
 623       MapLength = Packet->MetadataLength;
 624       Status = PciIo->Map (
 625                         PciIo,
 626                         Flag,
 627                         Packet->MetadataBuffer,
 628                         &MapLength,
 629                         &PhyAddr,
 630                         &MapMeta
 631                         );
 632       if (EFI_ERROR (Status) || (Packet->MetadataLength != MapLength)) {
 633         PciIo->Unmap (
 634                  PciIo,
 635                  MapData
 636                  );
 637
 638         return EFI_OUT_OF_RESOURCES;
 639       }
 640       Sq->Mptr = PhyAddr;
 641     }
 642   }
 643   //
 644   // If the buffer size spans more than two memory pages (page size as defined in CC.Mps),
 645   // then build a PRP list in the second PRP submission queue entry.
 646   //
 647   Offset = ((UINT16)Sq->Prp[0]) & (EFI_PAGE_SIZE - 1);
 648   Bytes  = Packet->TransferLength;
 649
 650   if ((Offset + Bytes) > (EFI_PAGE_SIZE * 2)) {
 651     //
 652     // Create PrpList for remaining data buffer.
 653     //
 654     PhyAddr = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);
 655     Prp = NvmeCreatePrpList (PciIo, PhyAddr, EFI_SIZE_TO_PAGES(Offset + Bytes) - 1, &PrpListHost, &PrpListNo, &MapPrpList);
 656     if (Prp == NULL) {
 657       goto EXIT;
 658     }
 659
 660     Sq->Prp[1] = (UINT64)(UINTN)Prp;
 661   } else if ((Offset + Bytes) > EFI_PAGE_SIZE) {
 662     Sq->Prp[1] = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);
 663   }
 664
 665   if(Packet->NvmeCmd->Flags & CDW2_VALID) {
 666     Sq->Rsvd2 = (UINT64)Packet->NvmeCmd->Cdw2;
 667   }
 668   if(Packet->NvmeCmd->Flags & CDW3_VALID) {
 669     Sq->Rsvd2 |= LShiftU64 ((UINT64)Packet->NvmeCmd->Cdw3, 32);
 670   }
 671   if(Packet->NvmeCmd->Flags & CDW10_VALID) {
 672     Sq->Payload.Raw.Cdw10 = Packet->NvmeCmd->Cdw10;
 673   }
 674   if(Packet->NvmeCmd->Flags & CDW11_VALID) {
 675     Sq->Payload.Raw.Cdw11 = Packet->NvmeCmd->Cdw11;
 676   }
 677   if(Packet->NvmeCmd->Flags & CDW12_VALID) {
 678     Sq->Payload.Raw.Cdw12 = Packet->NvmeCmd->Cdw12;
 679   }
 680   if(Packet->NvmeCmd->Flags & CDW13_VALID) {
 681     Sq->Payload.Raw.Cdw13 = Packet->NvmeCmd->Cdw13;
 682   }
 683   if(Packet->NvmeCmd->Flags & CDW14_VALID) {
 684     Sq->Payload.Raw.Cdw14 = Packet->NvmeCmd->Cdw14;
 685   }
 686   if(Packet->NvmeCmd->Flags & CDW15_VALID) {
 687     Sq->Payload.Raw.Cdw15 = Packet->NvmeCmd->Cdw15;
 688   }
 689
 690   //
 691   // Ring the submission queue doorbell.
 692   //
 693   if ((Event != NULL) && (QueueId != 0)) {
 694     Private->SqTdbl[QueueId].Sqt =
 695       (Private->SqTdbl[QueueId].Sqt + 1) % (NVME_ASYNC_CSQ_SIZE + 1);
 696   } else {
 697     Private->SqTdbl[QueueId].Sqt ^= 1;
 698   }
 699   Data = ReadUnaligned32 ((UINT32*)&Private->SqTdbl[QueueId]);
 700   Status = PciIo->Mem.Write (
 701                PciIo,
 702                EfiPciIoWidthUint32,
 703                NVME_BAR,
 704                NVME_SQTDBL_OFFSET(QueueId, Private->Cap.Dstrd),
 705                1,
 706                &Data
 707                );
 708
 709   if (EFI_ERROR (Status)) {
 710     goto EXIT;
 711   }
 712
 713   //
 714   // For non-blocking requests, return directly if the command is placed
 715   // in the submission queue.
 716   //
 717   if ((Event != NULL) && (QueueId != 0)) {
 718     AsyncRequest = AllocateZeroPool (sizeof (NVME_PASS_THRU_ASYNC_REQ));
 719     if (AsyncRequest == NULL) {
 720       Status = EFI_DEVICE_ERROR;
 721       goto EXIT;
 722     }
 723
 724     AsyncRequest->Signature     = NVME_PASS_THRU_ASYNC_REQ_SIG;
 725     AsyncRequest->Packet        = Packet;
 726     AsyncRequest->CommandId     = Sq->Cid;
 727     AsyncRequest->CallerEvent   = Event;
 728     AsyncRequest->MapData       = MapData;
 729     AsyncRequest->MapMeta       = MapMeta;
 730     AsyncRequest->MapPrpList    = MapPrpList;
 731     AsyncRequest->PrpListNo     = PrpListNo;
 732     AsyncRequest->PrpListHost   = PrpListHost;
 733
 734     OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
 735     InsertTailList (&Private->AsyncPassThruQueue, &AsyncRequest->Link);
 736     gBS->RestoreTPL (OldTpl);
 737
 738     return EFI_SUCCESS;
 739   }
 740
 741   Status = gBS->CreateEvent (
 742                   EVT_TIMER,
 743                   TPL_CALLBACK,
 744                   NULL,
 745                   NULL,
 746                   &TimerEvent
 747                   );
 748   if (EFI_ERROR (Status)) {
 749     goto EXIT;
 750   }
 751
 752   Status = gBS->SetTimer(TimerEvent, TimerRelative, Packet->CommandTimeout);
 753
 754   if (EFI_ERROR(Status)) {
 755     goto EXIT;
 756   }
 757
 758   //
 759   // Wait for completion queue to get filled in.
 760   //
 761   Status = EFI_TIMEOUT;
 762   while (EFI_ERROR (gBS->CheckEvent (TimerEvent))) {
 763     if (Cq->Pt != Private->Pt[QueueId]) {
 764       Status = EFI_SUCCESS;
 765       break;
 766     }
 767   }
 768
 769   //
 770   // Check the NVMe cmd execution result
 771   //
 772   if (Status != EFI_TIMEOUT) {
 773     if ((Cq->Sct == 0) && (Cq->Sc == 0)) {
 774       Status = EFI_SUCCESS;
 775     } else {
 776       Status = EFI_DEVICE_ERROR;
 777       //
 778       // Copy the Respose Queue entry for this command to the callers response buffer
 779       //
 780       CopyMem(Packet->NvmeCompletion, Cq, sizeof(EFI_NVM_EXPRESS_COMPLETION));
 781
 782       //
 783       // Dump every completion entry status for debugging.
 784       //
 785       DEBUG_CODE_BEGIN();
 786         NvmeDumpStatus(Cq);
 787       DEBUG_CODE_END();
 788     }
 789   } else {
 790     //
 791     // Timeout occurs for an NVMe command. Reset the controller to abort the
 792     // outstanding commands.
 793     //
 794     DEBUG ((DEBUG_ERROR, "NvmExpressPassThru: Timeout occurs for an NVMe command.\n"));
 795
 796     //
 797     // Disable the timer to trigger the process of async transfers temporarily.
 798     //
 799     Status = gBS->SetTimer (Private->TimerEvent, TimerCancel, 0);
 800     if (EFI_ERROR (Status)) {
 801       goto EXIT;
 802     }
 803
 804     //
 805     // Reset the NVMe controller.
 806     //
 807     Status = NvmeControllerInit (Private);
 808     if (!EFI_ERROR (Status)) {
 809       Status = AbortAsyncPassThruTasks (Private);
 810       if (!EFI_ERROR (Status)) {
 811         //
 812         // Re-enable the timer to trigger the process of async transfers.
 813         //
 814         Status = gBS->SetTimer (Private->TimerEvent, TimerPeriodic, NVME_HC_ASYNC_TIMER);
 815         if (!EFI_ERROR (Status)) {
 816           //
 817           // Return EFI_TIMEOUT to indicate a timeout occurs for NVMe PassThru command.
 818           //
 819           Status = EFI_TIMEOUT;
 820         }
 821       }
 822     } else {
 823       Status = EFI_DEVICE_ERROR;
 824     }
 825
 826     goto EXIT;
 827   }
 828
 829   if ((Private->CqHdbl[QueueId].Cqh ^= 1) == 0) {
 830     Private->Pt[QueueId] ^= 1;
 831   }
 832
 833   Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[QueueId]);
 834   Status = PciIo->Mem.Write (
 835                PciIo,
 836                EfiPciIoWidthUint32,
 837                NVME_BAR,
 838                NVME_CQHDBL_OFFSET(QueueId, Private->Cap.Dstrd),
 839                1,
 840                &Data
 841                );
 842
 843   //
 844   // For now, the code does not support the non-blocking feature for admin queue.
 845   // If Event is not NULL for admin queue, signal the caller's event here.
 846   //
 847   if (Event != NULL) {
 848     ASSERT (QueueId == 0);
 849     gBS->SignalEvent (Event);
 850   }
 851
 852 EXIT:
 853   if (MapData != NULL) {
 854     PciIo->Unmap (
 855              PciIo,
 856              MapData
 857              );
 858   }
 859
 860   if (MapMeta != NULL) {
 861     PciIo->Unmap (
 862              PciIo,
 863              MapMeta
 864              );
 865   }
 866
 867   if (MapPrpList != NULL) {
 868     PciIo->Unmap (
 869              PciIo,
 870              MapPrpList
 871              );
 872   }
 873
 874   if (Prp != NULL) {
 875     PciIo->FreeBuffer (PciIo, PrpListNo, PrpListHost);
 876   }
 877
 878   if (TimerEvent != NULL) {
 879     gBS->CloseEvent (TimerEvent);
 880   }
 881   return Status;
 882 }
 883
 884 /**
 885   Used to retrieve the next namespace ID for this NVM Express controller.
 886
 887   The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNextNamespace() function retrieves the next valid
 888   namespace ID on this NVM Express controller.
 889
 890   If on input the value pointed to by NamespaceId is 0xFFFFFFFF, then the first valid namespace
 891   ID defined on the NVM Express controller is returned in the location pointed to by NamespaceId
 892   and a status of EFI_SUCCESS is returned.
 893
 894   If on input the value pointed to by NamespaceId is an invalid namespace ID other than 0xFFFFFFFF,
 895   then EFI_INVALID_PARAMETER is returned.
 896
 897   If on input the value pointed to by NamespaceId is a valid namespace ID, then the next valid
 898   namespace ID on the NVM Express controller is returned in the location pointed to by NamespaceId,
 899   and EFI_SUCCESS is returned.
 900
 901   If the value pointed to by NamespaceId is the namespace ID of the last namespace on the NVM
 902   Express controller, then EFI_NOT_FOUND is returned.
 903
 904   @param[in]     This           A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
 905   @param[in,out] NamespaceId    On input, a pointer to a legal NamespaceId for an NVM Express
 906                                 namespace present on the NVM Express controller. On output, a
 907                                 pointer to the next NamespaceId of an NVM Express namespace on
 908                                 an NVM Express controller. An input value of 0xFFFFFFFF retrieves
 909                                 the first NamespaceId for an NVM Express namespace present on an
 910                                 NVM Express controller.
 911
 912   @retval EFI_SUCCESS           The Namespace ID of the next Namespace was returned.
 913   @retval EFI_NOT_FOUND         There are no more namespaces defined on this controller.
 914   @retval EFI_INVALID_PARAMETER NamespaceId is an invalid value other than 0xFFFFFFFF.
 915
 916 **/
 917 EFI_STATUS
 918 EFIAPI
 919 NvmExpressGetNextNamespace (
 920   IN     EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL          *This,
 921   IN OUT UINT32                                      *NamespaceId
 922   )
 923 {
 924   NVME_CONTROLLER_PRIVATE_DATA     *Private;
 925   NVME_ADMIN_NAMESPACE_DATA        *NamespaceData;
 926   UINT32                           NextNamespaceId;
 927   EFI_STATUS                       Status;
 928
 929   if ((This == NULL) || (NamespaceId == NULL)) {
 930     return EFI_INVALID_PARAMETER;
 931   }
 932
 933   NamespaceData = NULL;
 934   Status        = EFI_NOT_FOUND;
 935
 936   Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
 937   //
 938   // If the NamespaceId input value is 0xFFFFFFFF, then get the first valid namespace ID
 939   //
 940   if (*NamespaceId == 0xFFFFFFFF) {
 941     //
 942     // Start with the first namespace ID
 943     //
 944     NextNamespaceId = 1;
 945     //
 946     // Allocate buffer for Identify Namespace data.
 947     //
 948     NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));
 949
 950     if (NamespaceData == NULL) {
 951       return EFI_NOT_FOUND;
 952     }
 953
 954     Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);
 955     if (EFI_ERROR(Status)) {
 956       goto Done;
 957     }
 958
 959     *NamespaceId = NextNamespaceId;
 960   } else {
 961     if (*NamespaceId > Private->ControllerData->Nn) {
 962       return EFI_INVALID_PARAMETER;
 963     }
 964
 965     NextNamespaceId = *NamespaceId + 1;
 966     if (NextNamespaceId > Private->ControllerData->Nn) {
 967       return EFI_NOT_FOUND;
 968     }
 969
 970     //
 971     // Allocate buffer for Identify Namespace data.
 972     //
 973     NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));
 974     if (NamespaceData == NULL) {
 975       return EFI_NOT_FOUND;
 976     }
 977
 978     Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);
 979     if (EFI_ERROR(Status)) {
 980       goto Done;
 981     }
 982
 983     *NamespaceId = NextNamespaceId;
 984   }
 985
 986 Done:
 987   if (NamespaceData != NULL) {
 988     FreePool(NamespaceData);
 989   }
 990
 991   return Status;
 992 }
 993
 994 /**
 995   Used to translate a device path node to a namespace ID.
 996
 997   The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNamespace() function determines the namespace ID associated with the
 998   namespace described by DevicePath.
 999
1000   If DevicePath is a device path node type that the NVM Express Pass Thru driver supports, then the NVM Express
1001   Pass Thru driver will attempt to translate the contents DevicePath into a namespace ID.
1002
1003   If this translation is successful, then that namespace ID is returned in NamespaceId, and EFI_SUCCESS is returned
1004
1005   @param[in]  This                A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
1006   @param[in]  DevicePath          A pointer to the device path node that describes an NVM Express namespace on
1007                                   the NVM Express controller.
1008   @param[out] NamespaceId         The NVM Express namespace ID contained in the device path node.
1009
1010   @retval EFI_SUCCESS             DevicePath was successfully translated to NamespaceId.
1011   @retval EFI_INVALID_PARAMETER   If DevicePath or NamespaceId are NULL, then EFI_INVALID_PARAMETER is returned.
1012   @retval EFI_UNSUPPORTED         If DevicePath is not a device path node type that the NVM Express Pass Thru driver
1013                                   supports, then EFI_UNSUPPORTED is returned.
1014   @retval EFI_NOT_FOUND           If DevicePath is a device path node type that the NVM Express Pass Thru driver
1015                                   supports, but there is not a valid translation from DevicePath to a namespace ID,
1016                                   then EFI_NOT_FOUND is returned.
1017 **/
1018 EFI_STATUS
1019 EFIAPI
1020 NvmExpressGetNamespace (
1021   IN     EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL          *This,
1022   IN     EFI_DEVICE_PATH_PROTOCOL                    *DevicePath,
1023      OUT UINT32                                      *NamespaceId
1024   )
1025 {
1026   NVME_NAMESPACE_DEVICE_PATH       *Node;
1027   NVME_CONTROLLER_PRIVATE_DATA     *Private;
1028
1029   if ((This == NULL) || (DevicePath == NULL) || (NamespaceId == NULL)) {
1030     return EFI_INVALID_PARAMETER;
1031   }
1032
1033   if (DevicePath->Type != MESSAGING_DEVICE_PATH) {
1034     return EFI_UNSUPPORTED;
1035   }
1036
1037   Node    = (NVME_NAMESPACE_DEVICE_PATH *)DevicePath;
1038   Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
1039
1040   if (DevicePath->SubType == MSG_NVME_NAMESPACE_DP) {
1041     if (DevicePathNodeLength(DevicePath) != sizeof(NVME_NAMESPACE_DEVICE_PATH)) {
1042       return EFI_NOT_FOUND;
1043     }
1044
1045     //
1046     // Check NamespaceId in the device path node is valid or not.
1047     //
1048     if ((Node->NamespaceId == 0) ||
1049       (Node->NamespaceId > Private->ControllerData->Nn)) {
1050       return EFI_NOT_FOUND;
1051     }
1052
1053     *NamespaceId = Node->NamespaceId;
1054
1055     return EFI_SUCCESS;
1056   } else {
1057     return EFI_UNSUPPORTED;
1058   }
1059 }
1060
1061 /**
1062   Used to allocate and build a device path node for an NVM Express namespace on an NVM Express controller.
1063
1064   The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.BuildDevicePath() function allocates and builds a single device
1065   path node for the NVM Express namespace specified by NamespaceId.
1066
1067   If the NamespaceId is not valid, then EFI_NOT_FOUND is returned.
1068
1069   If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned.
1070
1071   If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES is returned.
1072
1073   Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of DevicePath are
1074   initialized to describe the NVM Express namespace specified by NamespaceId, and EFI_SUCCESS is returned.
1075
1076   @param[in]     This                A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
1077   @param[in]     NamespaceId         The NVM Express namespace ID  for which a device path node is to be
1078                                      allocated and built. Caller must set the NamespaceId to zero if the
1079                                      device path node will contain a valid UUID.
1080   @param[in,out] DevicePath          A pointer to a single device path node that describes the NVM Express
1081                                      namespace specified by NamespaceId. This function is responsible for
1082                                      allocating the buffer DevicePath with the boot service AllocatePool().
1083                                      It is the caller's responsibility to free DevicePath when the caller
1084                                      is finished with DevicePath.
1085   @retval EFI_SUCCESS                The device path node that describes the NVM Express namespace specified
1086                                      by NamespaceId was allocated and returned in DevicePath.
1087   @retval EFI_NOT_FOUND              The NamespaceId is not valid.
1088   @retval EFI_INVALID_PARAMETER      DevicePath is NULL.
1089   @retval EFI_OUT_OF_RESOURCES       There are not enough resources to allocate the DevicePath node.
1090
1091 **/
1092 EFI_STATUS
1093 EFIAPI
1094 NvmExpressBuildDevicePath (
1095   IN     EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL          *This,
1096   IN     UINT32                                      NamespaceId,
1097   IN OUT EFI_DEVICE_PATH_PROTOCOL                    **DevicePath
1098   )
1099 {
1100   NVME_NAMESPACE_DEVICE_PATH     *Node;
1101   NVME_CONTROLLER_PRIVATE_DATA   *Private;
1102   EFI_STATUS                     Status;
1103   NVME_ADMIN_NAMESPACE_DATA      *NamespaceData;
1104
1105   //
1106   // Validate parameters
1107   //
1108   if ((This == NULL) || (DevicePath == NULL)) {
1109     return EFI_INVALID_PARAMETER;
1110   }
1111
1112   Status  = EFI_SUCCESS;
1113   Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
1114
1115   //
1116   // Check NamespaceId is valid or not.
1117   //
1118   if ((NamespaceId == 0) ||
1119     (NamespaceId > Private->ControllerData->Nn)) {
1120     return EFI_NOT_FOUND;
1121   }
1122
1123   Node = (NVME_NAMESPACE_DEVICE_PATH *)AllocateZeroPool (sizeof (NVME_NAMESPACE_DEVICE_PATH));
1124   if (Node == NULL) {
1125     return EFI_OUT_OF_RESOURCES;
1126   }
1127
1128   Node->Header.Type    = MESSAGING_DEVICE_PATH;
1129   Node->Header.SubType = MSG_NVME_NAMESPACE_DP;
1130   SetDevicePathNodeLength (&Node->Header, sizeof (NVME_NAMESPACE_DEVICE_PATH));
1131   Node->NamespaceId    = NamespaceId;
1132
1133   //
1134   // Allocate a buffer for Identify Namespace data.
1135   //
1136   NamespaceData = NULL;
1137   NamespaceData = AllocateZeroPool(sizeof (NVME_ADMIN_NAMESPACE_DATA));
1138   if(NamespaceData == NULL) {
1139     Status = EFI_OUT_OF_RESOURCES;
1140     goto Exit;
1141   }
1142
1143   //
1144   // Get UUID from specified Identify Namespace data.
1145   //
1146   Status = NvmeIdentifyNamespace (
1147              Private,
1148              NamespaceId,
1149              (VOID *)NamespaceData
1150              );
1151
1152   if (EFI_ERROR(Status)) {
1153     goto Exit;
1154   }
1155
1156   Node->NamespaceUuid = NamespaceData->Eui64;
1157
1158   *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)Node;
1159
1160 Exit:
1161   if(NamespaceData != NULL) {
1162     FreePool (NamespaceData);
1163   }
1164
1165   if (EFI_ERROR (Status)) {
1166     FreePool (Node);
1167   }
1168
1169   return Status;
1170 }
1171