MdeModulePkg NvmExpressDxe: return error code in error path
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / NvmExpressDxe / NvmExpressPassthru.c
1 /** @file
2 NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows
3 NVM Express specification.
4
5 (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
6 Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php.
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #include "NvmExpress.h"
18
19 /**
20 Dump the execution status from a given completion queue entry.
21
22 @param[in] Cq A pointer to the NVME_CQ item.
23
24 **/
25 VOID
26 NvmeDumpStatus (
27 IN NVME_CQ *Cq
28 )
29 {
30 DEBUG ((EFI_D_VERBOSE, "Dump NVMe Completion Entry Status from [0x%x]:\n", Cq));
31
32 DEBUG ((EFI_D_VERBOSE, " SQ Identifier : [0x%x], Phase Tag : [%d], Cmd Identifier : [0x%x]\n", Cq->Sqid, Cq->Pt, Cq->Cid));
33
34 DEBUG ((EFI_D_VERBOSE, " NVMe Cmd Execution Result - "));
35
36 switch (Cq->Sct) {
37 case 0x0:
38 switch (Cq->Sc) {
39 case 0x0:
40 DEBUG ((EFI_D_VERBOSE, "Successful Completion\n"));
41 break;
42 case 0x1:
43 DEBUG ((EFI_D_VERBOSE, "Invalid Command Opcode\n"));
44 break;
45 case 0x2:
46 DEBUG ((EFI_D_VERBOSE, "Invalid Field in Command\n"));
47 break;
48 case 0x3:
49 DEBUG ((EFI_D_VERBOSE, "Command ID Conflict\n"));
50 break;
51 case 0x4:
52 DEBUG ((EFI_D_VERBOSE, "Data Transfer Error\n"));
53 break;
54 case 0x5:
55 DEBUG ((EFI_D_VERBOSE, "Commands Aborted due to Power Loss Notification\n"));
56 break;
57 case 0x6:
58 DEBUG ((EFI_D_VERBOSE, "Internal Device Error\n"));
59 break;
60 case 0x7:
61 DEBUG ((EFI_D_VERBOSE, "Command Abort Requested\n"));
62 break;
63 case 0x8:
64 DEBUG ((EFI_D_VERBOSE, "Command Aborted due to SQ Deletion\n"));
65 break;
66 case 0x9:
67 DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Failed Fused Command\n"));
68 break;
69 case 0xA:
70 DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Missing Fused Command\n"));
71 break;
72 case 0xB:
73 DEBUG ((EFI_D_VERBOSE, "Invalid Namespace or Format\n"));
74 break;
75 case 0xC:
76 DEBUG ((EFI_D_VERBOSE, "Command Sequence Error\n"));
77 break;
78 case 0xD:
79 DEBUG ((EFI_D_VERBOSE, "Invalid SGL Last Segment Descriptor\n"));
80 break;
81 case 0xE:
82 DEBUG ((EFI_D_VERBOSE, "Invalid Number of SGL Descriptors\n"));
83 break;
84 case 0xF:
85 DEBUG ((EFI_D_VERBOSE, "Data SGL Length Invalid\n"));
86 break;
87 case 0x10:
88 DEBUG ((EFI_D_VERBOSE, "Metadata SGL Length Invalid\n"));
89 break;
90 case 0x11:
91 DEBUG ((EFI_D_VERBOSE, "SGL Descriptor Type Invalid\n"));
92 break;
93 case 0x80:
94 DEBUG ((EFI_D_VERBOSE, "LBA Out of Range\n"));
95 break;
96 case 0x81:
97 DEBUG ((EFI_D_VERBOSE, "Capacity Exceeded\n"));
98 break;
99 case 0x82:
100 DEBUG ((EFI_D_VERBOSE, "Namespace Not Ready\n"));
101 break;
102 case 0x83:
103 DEBUG ((EFI_D_VERBOSE, "Reservation Conflict\n"));
104 break;
105 }
106 break;
107
108 case 0x1:
109 switch (Cq->Sc) {
110 case 0x0:
111 DEBUG ((EFI_D_VERBOSE, "Completion Queue Invalid\n"));
112 break;
113 case 0x1:
114 DEBUG ((EFI_D_VERBOSE, "Invalid Queue Identifier\n"));
115 break;
116 case 0x2:
117 DEBUG ((EFI_D_VERBOSE, "Maximum Queue Size Exceeded\n"));
118 break;
119 case 0x3:
120 DEBUG ((EFI_D_VERBOSE, "Abort Command Limit Exceeded\n"));
121 break;
122 case 0x5:
123 DEBUG ((EFI_D_VERBOSE, "Asynchronous Event Request Limit Exceeded\n"));
124 break;
125 case 0x6:
126 DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Slot\n"));
127 break;
128 case 0x7:
129 DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Image\n"));
130 break;
131 case 0x8:
132 DEBUG ((EFI_D_VERBOSE, "Invalid Interrupt Vector\n"));
133 break;
134 case 0x9:
135 DEBUG ((EFI_D_VERBOSE, "Invalid Log Page\n"));
136 break;
137 case 0xA:
138 DEBUG ((EFI_D_VERBOSE, "Invalid Format\n"));
139 break;
140 case 0xB:
141 DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires Conventional Reset\n"));
142 break;
143 case 0xC:
144 DEBUG ((EFI_D_VERBOSE, "Invalid Queue Deletion\n"));
145 break;
146 case 0xD:
147 DEBUG ((EFI_D_VERBOSE, "Feature Identifier Not Saveable\n"));
148 break;
149 case 0xE:
150 DEBUG ((EFI_D_VERBOSE, "Feature Not Changeable\n"));
151 break;
152 case 0xF:
153 DEBUG ((EFI_D_VERBOSE, "Feature Not Namespace Specific\n"));
154 break;
155 case 0x10:
156 DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires NVM Subsystem Reset\n"));
157 break;
158 case 0x80:
159 DEBUG ((EFI_D_VERBOSE, "Conflicting Attributes\n"));
160 break;
161 case 0x81:
162 DEBUG ((EFI_D_VERBOSE, "Invalid Protection Information\n"));
163 break;
164 case 0x82:
165 DEBUG ((EFI_D_VERBOSE, "Attempted Write to Read Only Range\n"));
166 break;
167 }
168 break;
169
170 case 0x2:
171 switch (Cq->Sc) {
172 case 0x80:
173 DEBUG ((EFI_D_VERBOSE, "Write Fault\n"));
174 break;
175 case 0x81:
176 DEBUG ((EFI_D_VERBOSE, "Unrecovered Read Error\n"));
177 break;
178 case 0x82:
179 DEBUG ((EFI_D_VERBOSE, "End-to-end Guard Check Error\n"));
180 break;
181 case 0x83:
182 DEBUG ((EFI_D_VERBOSE, "End-to-end Application Tag Check Error\n"));
183 break;
184 case 0x84:
185 DEBUG ((EFI_D_VERBOSE, "End-to-end Reference Tag Check Error\n"));
186 break;
187 case 0x85:
188 DEBUG ((EFI_D_VERBOSE, "Compare Failure\n"));
189 break;
190 case 0x86:
191 DEBUG ((EFI_D_VERBOSE, "Access Denied\n"));
192 break;
193 }
194 break;
195
196 default:
197 break;
198 }
199 }
200
201 /**
202 Create PRP lists for data transfer which is larger than 2 memory pages.
203 Note here we calcuate the number of required PRP lists and allocate them at one time.
204
205 @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.
206 @param[in] PhysicalAddr The physical base address of data buffer.
207 @param[in] Pages The number of pages to be transfered.
208 @param[out] PrpListHost The host base address of PRP lists.
209 @param[in,out] PrpListNo The number of PRP List.
210 @param[out] Mapping The mapping value returned from PciIo.Map().
211
212 @retval The pointer to the first PRP List of the PRP lists.
213
214 **/
215 VOID*
216 NvmeCreatePrpList (
217 IN EFI_PCI_IO_PROTOCOL *PciIo,
218 IN EFI_PHYSICAL_ADDRESS PhysicalAddr,
219 IN UINTN Pages,
220 OUT VOID **PrpListHost,
221 IN OUT UINTN *PrpListNo,
222 OUT VOID **Mapping
223 )
224 {
225 UINTN PrpEntryNo;
226 UINT64 PrpListBase;
227 UINTN PrpListIndex;
228 UINTN PrpEntryIndex;
229 UINT64 Remainder;
230 EFI_PHYSICAL_ADDRESS PrpListPhyAddr;
231 UINTN Bytes;
232 EFI_STATUS Status;
233
234 //
235 // The number of Prp Entry in a memory page.
236 //
237 PrpEntryNo = EFI_PAGE_SIZE / sizeof (UINT64);
238
239 //
240 // Calculate total PrpList number.
241 //
242 *PrpListNo = (UINTN)DivU64x64Remainder ((UINT64)Pages, (UINT64)PrpEntryNo - 1, &Remainder);
243 if (*PrpListNo == 0) {
244 *PrpListNo = 1;
245 } else if ((Remainder != 0) && (Remainder != 1)) {
246 *PrpListNo += 1;
247 } else if (Remainder == 1) {
248 Remainder = PrpEntryNo;
249 } else if (Remainder == 0) {
250 Remainder = PrpEntryNo - 1;
251 }
252
253 Status = PciIo->AllocateBuffer (
254 PciIo,
255 AllocateAnyPages,
256 EfiBootServicesData,
257 *PrpListNo,
258 PrpListHost,
259 0
260 );
261
262 if (EFI_ERROR (Status)) {
263 return NULL;
264 }
265
266 Bytes = EFI_PAGES_TO_SIZE (*PrpListNo);
267 Status = PciIo->Map (
268 PciIo,
269 EfiPciIoOperationBusMasterCommonBuffer,
270 *PrpListHost,
271 &Bytes,
272 &PrpListPhyAddr,
273 Mapping
274 );
275
276 if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (*PrpListNo))) {
277 DEBUG ((EFI_D_ERROR, "NvmeCreatePrpList: create PrpList failure!\n"));
278 goto EXIT;
279 }
280 //
281 // Fill all PRP lists except of last one.
282 //
283 ZeroMem (*PrpListHost, Bytes);
284 for (PrpListIndex = 0; PrpListIndex < *PrpListNo - 1; ++PrpListIndex) {
285 PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
286
287 for (PrpEntryIndex = 0; PrpEntryIndex < PrpEntryNo; ++PrpEntryIndex) {
288 if (PrpEntryIndex != PrpEntryNo - 1) {
289 //
290 // Fill all PRP entries except of last one.
291 //
292 *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;
293 PhysicalAddr += EFI_PAGE_SIZE;
294 } else {
295 //
296 // Fill last PRP entries with next PRP List pointer.
297 //
298 *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PrpListPhyAddr + (PrpListIndex + 1) * EFI_PAGE_SIZE;
299 }
300 }
301 }
302 //
303 // Fill last PRP list.
304 //
305 PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;
306 for (PrpEntryIndex = 0; PrpEntryIndex < Remainder; ++PrpEntryIndex) {
307 *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;
308 PhysicalAddr += EFI_PAGE_SIZE;
309 }
310
311 return (VOID*)(UINTN)PrpListPhyAddr;
312
313 EXIT:
314 PciIo->FreeBuffer (PciIo, *PrpListNo, *PrpListHost);
315 return NULL;
316 }
317
318
319 /**
320 Aborts the asynchronous PassThru requests.
321
322 @param[in] Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA
323 data structure.
324
325 @retval EFI_SUCCESS The asynchronous PassThru requests have been aborted.
326 @return EFI_DEVICE_ERROR Fail to abort all the asynchronous PassThru requests.
327
328 **/
329 EFI_STATUS
330 AbortAsyncPassThruTasks (
331 IN NVME_CONTROLLER_PRIVATE_DATA *Private
332 )
333 {
334 EFI_PCI_IO_PROTOCOL *PciIo;
335 LIST_ENTRY *Link;
336 LIST_ENTRY *NextLink;
337 NVME_BLKIO2_SUBTASK *Subtask;
338 NVME_BLKIO2_REQUEST *BlkIo2Request;
339 NVME_PASS_THRU_ASYNC_REQ *AsyncRequest;
340 EFI_BLOCK_IO2_TOKEN *Token;
341 EFI_TPL OldTpl;
342 EFI_STATUS Status;
343
344 PciIo = Private->PciIo;
345 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
346
347 //
348 // Cancel the unsubmitted subtasks.
349 //
350 for (Link = GetFirstNode (&Private->UnsubmittedSubtasks);
351 !IsNull (&Private->UnsubmittedSubtasks, Link);
352 Link = NextLink) {
353 NextLink = GetNextNode (&Private->UnsubmittedSubtasks, Link);
354 Subtask = NVME_BLKIO2_SUBTASK_FROM_LINK (Link);
355 BlkIo2Request = Subtask->BlockIo2Request;
356 Token = BlkIo2Request->Token;
357
358 BlkIo2Request->UnsubmittedSubtaskNum--;
359 if (Subtask->IsLast) {
360 BlkIo2Request->LastSubtaskSubmitted = TRUE;
361 }
362 Token->TransactionStatus = EFI_ABORTED;
363
364 RemoveEntryList (Link);
365 InsertTailList (&BlkIo2Request->SubtasksQueue, Link);
366 gBS->SignalEvent (Subtask->Event);
367 }
368
369 //
370 // Cleanup the resources for the asynchronous PassThru requests.
371 //
372 for (Link = GetFirstNode (&Private->AsyncPassThruQueue);
373 !IsNull (&Private->AsyncPassThruQueue, Link);
374 Link = NextLink) {
375 NextLink = GetNextNode (&Private->AsyncPassThruQueue, Link);
376 AsyncRequest = NVME_PASS_THRU_ASYNC_REQ_FROM_THIS (Link);
377
378 if (AsyncRequest->MapData != NULL) {
379 PciIo->Unmap (PciIo, AsyncRequest->MapData);
380 }
381 if (AsyncRequest->MapMeta != NULL) {
382 PciIo->Unmap (PciIo, AsyncRequest->MapMeta);
383 }
384 if (AsyncRequest->MapPrpList != NULL) {
385 PciIo->Unmap (PciIo, AsyncRequest->MapPrpList);
386 }
387 if (AsyncRequest->PrpListHost != NULL) {
388 PciIo->FreeBuffer (
389 PciIo,
390 AsyncRequest->PrpListNo,
391 AsyncRequest->PrpListHost
392 );
393 }
394
395 RemoveEntryList (Link);
396 gBS->SignalEvent (AsyncRequest->CallerEvent);
397 FreePool (AsyncRequest);
398 }
399
400 if (IsListEmpty (&Private->AsyncPassThruQueue) &&
401 IsListEmpty (&Private->UnsubmittedSubtasks)) {
402 Status = EFI_SUCCESS;
403 } else {
404 Status = EFI_DEVICE_ERROR;
405 }
406
407 gBS->RestoreTPL (OldTpl);
408
409 return Status;
410 }
411
412
413 /**
414 Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports
415 both blocking I/O and non-blocking I/O. The blocking I/O functionality is required, and the non-blocking
416 I/O functionality is optional.
417
418
419 @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
420 @param[in] NamespaceId A 32 bit namespace ID as defined in the NVMe specification to which the NVM Express Command
421 Packet will be sent. A value of 0 denotes the NVM Express controller, a value of all 0xFF's
422 (all bytes are 0xFF) in the namespace ID specifies that the command packet should be sent to
423 all valid namespaces.
424 @param[in,out] Packet A pointer to the NVM Express Command Packet.
425 @param[in] Event If non-blocking I/O is not supported then Event is ignored, and blocking I/O is performed.
426 If Event is NULL, then blocking I/O is performed. If Event is not NULL and non-blocking I/O
427 is supported, then non-blocking I/O is performed, and Event will be signaled when the NVM
428 Express Command Packet completes.
429
430 @retval EFI_SUCCESS The NVM Express Command Packet was sent by the host. TransferLength bytes were transferred
431 to, or from DataBuffer.
432 @retval EFI_BAD_BUFFER_SIZE The NVM Express Command Packet was not executed. The number of bytes that could be transferred
433 is returned in TransferLength.
434 @retval EFI_NOT_READY The NVM Express Command Packet could not be sent because the controller is not ready. The caller
435 may retry again later.
436 @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the NVM Express Command Packet.
437 @retval EFI_INVALID_PARAMETER NamespaceId or the contents of EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET are invalid. The NVM
438 Express Command Packet was not sent, so no additional status information is available.
439 @retval EFI_UNSUPPORTED The command described by the NVM Express Command Packet is not supported by the NVM Express
440 controller. The NVM Express Command Packet was not sent so no additional status information
441 is available.
442 @retval EFI_TIMEOUT A timeout occurred while waiting for the NVM Express Command Packet to execute.
443
444 **/
445 EFI_STATUS
446 EFIAPI
447 NvmExpressPassThru (
448 IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
449 IN UINT32 NamespaceId,
450 IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet,
451 IN EFI_EVENT Event OPTIONAL
452 )
453 {
454 NVME_CONTROLLER_PRIVATE_DATA *Private;
455 EFI_STATUS Status;
456 EFI_STATUS PreviousStatus;
457 EFI_PCI_IO_PROTOCOL *PciIo;
458 NVME_SQ *Sq;
459 NVME_CQ *Cq;
460 UINT16 QueueId;
461 UINT32 Bytes;
462 UINT16 Offset;
463 EFI_EVENT TimerEvent;
464 EFI_PCI_IO_PROTOCOL_OPERATION Flag;
465 EFI_PHYSICAL_ADDRESS PhyAddr;
466 VOID *MapData;
467 VOID *MapMeta;
468 VOID *MapPrpList;
469 UINTN MapLength;
470 UINT64 *Prp;
471 VOID *PrpListHost;
472 UINTN PrpListNo;
473 UINT32 Attributes;
474 UINT32 IoAlign;
475 UINT32 MaxTransLen;
476 UINT32 Data;
477 NVME_PASS_THRU_ASYNC_REQ *AsyncRequest;
478 EFI_TPL OldTpl;
479
480 //
481 // check the data fields in Packet parameter.
482 //
483 if ((This == NULL) || (Packet == NULL)) {
484 return EFI_INVALID_PARAMETER;
485 }
486
487 if ((Packet->NvmeCmd == NULL) || (Packet->NvmeCompletion == NULL)) {
488 return EFI_INVALID_PARAMETER;
489 }
490
491 if (Packet->QueueType != NVME_ADMIN_QUEUE && Packet->QueueType != NVME_IO_QUEUE) {
492 return EFI_INVALID_PARAMETER;
493 }
494
495 //
496 // 'Attributes' with neither EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL nor
497 // EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL set is an illegal
498 // configuration.
499 //
500 Attributes = This->Mode->Attributes;
501 if ((Attributes & (EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL |
502 EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL)) == 0) {
503 return EFI_INVALID_PARAMETER;
504 }
505
506 //
507 // Buffer alignment check for TransferBuffer & MetadataBuffer.
508 //
509 IoAlign = This->Mode->IoAlign;
510 if (IoAlign > 0 && (((UINTN) Packet->TransferBuffer & (IoAlign - 1)) != 0)) {
511 return EFI_INVALID_PARAMETER;
512 }
513
514 if (IoAlign > 0 && (((UINTN) Packet->MetadataBuffer & (IoAlign - 1)) != 0)) {
515 return EFI_INVALID_PARAMETER;
516 }
517
518 Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
519
520 //
521 // Check NamespaceId is valid or not.
522 //
523 if ((NamespaceId > Private->ControllerData->Nn) &&
524 (NamespaceId != (UINT32) -1)) {
525 return EFI_INVALID_PARAMETER;
526 }
527
528 //
529 // Check whether TransferLength exceeds the maximum data transfer size.
530 //
531 if (Private->ControllerData->Mdts != 0) {
532 MaxTransLen = (1 << (Private->ControllerData->Mdts)) *
533 (1 << (Private->Cap.Mpsmin + 12));
534 if (Packet->TransferLength > MaxTransLen) {
535 Packet->TransferLength = MaxTransLen;
536 return EFI_BAD_BUFFER_SIZE;
537 }
538 }
539
540 PciIo = Private->PciIo;
541 MapData = NULL;
542 MapMeta = NULL;
543 MapPrpList = NULL;
544 PrpListHost = NULL;
545 PrpListNo = 0;
546 Prp = NULL;
547 TimerEvent = NULL;
548 Status = EFI_SUCCESS;
549
550 if (Packet->QueueType == NVME_ADMIN_QUEUE) {
551 QueueId = 0;
552 } else {
553 if (Event == NULL) {
554 QueueId = 1;
555 } else {
556 QueueId = 2;
557
558 //
559 // Submission queue full check.
560 //
561 if ((Private->SqTdbl[QueueId].Sqt + 1) % (NVME_ASYNC_CSQ_SIZE + 1) ==
562 Private->AsyncSqHead) {
563 return EFI_NOT_READY;
564 }
565 }
566 }
567 Sq = Private->SqBuffer[QueueId] + Private->SqTdbl[QueueId].Sqt;
568 Cq = Private->CqBuffer[QueueId] + Private->CqHdbl[QueueId].Cqh;
569
570 if (Packet->NvmeCmd->Nsid != NamespaceId) {
571 return EFI_INVALID_PARAMETER;
572 }
573
574 ZeroMem (Sq, sizeof (NVME_SQ));
575 Sq->Opc = (UINT8)Packet->NvmeCmd->Cdw0.Opcode;
576 Sq->Fuse = (UINT8)Packet->NvmeCmd->Cdw0.FusedOperation;
577 Sq->Cid = Private->Cid[QueueId]++;
578 Sq->Nsid = Packet->NvmeCmd->Nsid;
579
580 //
581 // Currently we only support PRP for data transfer, SGL is NOT supported.
582 //
583 ASSERT (Sq->Psdt == 0);
584 if (Sq->Psdt != 0) {
585 DEBUG ((EFI_D_ERROR, "NvmExpressPassThru: doesn't support SGL mechanism\n"));
586 return EFI_UNSUPPORTED;
587 }
588
589 Sq->Prp[0] = (UINT64)(UINTN)Packet->TransferBuffer;
590 //
591 // If the NVMe cmd has data in or out, then mapping the user buffer to the PCI controller specific addresses.
592 // Note here we don't handle data buffer for CreateIOSubmitionQueue and CreateIOCompletionQueue cmds because
593 // these two cmds are special which requires their data buffer must support simultaneous access by both the
594 // processor and a PCI Bus Master. It's caller's responsbility to ensure this.
595 //
596 if (((Sq->Opc & (BIT0 | BIT1)) != 0) &&
597 !((Packet->QueueType == NVME_ADMIN_QUEUE) && ((Sq->Opc == NVME_ADMIN_CRIOCQ_CMD) || (Sq->Opc == NVME_ADMIN_CRIOSQ_CMD)))) {
598 if ((Packet->TransferLength == 0) || (Packet->TransferBuffer == NULL)) {
599 return EFI_INVALID_PARAMETER;
600 }
601
602 if ((Sq->Opc & BIT0) != 0) {
603 Flag = EfiPciIoOperationBusMasterRead;
604 } else {
605 Flag = EfiPciIoOperationBusMasterWrite;
606 }
607
608 MapLength = Packet->TransferLength;
609 Status = PciIo->Map (
610 PciIo,
611 Flag,
612 Packet->TransferBuffer,
613 &MapLength,
614 &PhyAddr,
615 &MapData
616 );
617 if (EFI_ERROR (Status) || (Packet->TransferLength != MapLength)) {
618 return EFI_OUT_OF_RESOURCES;
619 }
620
621 Sq->Prp[0] = PhyAddr;
622 Sq->Prp[1] = 0;
623
624 if((Packet->MetadataLength != 0) && (Packet->MetadataBuffer != NULL)) {
625 MapLength = Packet->MetadataLength;
626 Status = PciIo->Map (
627 PciIo,
628 Flag,
629 Packet->MetadataBuffer,
630 &MapLength,
631 &PhyAddr,
632 &MapMeta
633 );
634 if (EFI_ERROR (Status) || (Packet->MetadataLength != MapLength)) {
635 PciIo->Unmap (
636 PciIo,
637 MapData
638 );
639
640 return EFI_OUT_OF_RESOURCES;
641 }
642 Sq->Mptr = PhyAddr;
643 }
644 }
645 //
646 // If the buffer size spans more than two memory pages (page size as defined in CC.Mps),
647 // then build a PRP list in the second PRP submission queue entry.
648 //
649 Offset = ((UINT16)Sq->Prp[0]) & (EFI_PAGE_SIZE - 1);
650 Bytes = Packet->TransferLength;
651
652 if ((Offset + Bytes) > (EFI_PAGE_SIZE * 2)) {
653 //
654 // Create PrpList for remaining data buffer.
655 //
656 PhyAddr = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);
657 Prp = NvmeCreatePrpList (PciIo, PhyAddr, EFI_SIZE_TO_PAGES(Offset + Bytes) - 1, &PrpListHost, &PrpListNo, &MapPrpList);
658 if (Prp == NULL) {
659 Status = EFI_OUT_OF_RESOURCES;
660 goto EXIT;
661 }
662
663 Sq->Prp[1] = (UINT64)(UINTN)Prp;
664 } else if ((Offset + Bytes) > EFI_PAGE_SIZE) {
665 Sq->Prp[1] = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);
666 }
667
668 if(Packet->NvmeCmd->Flags & CDW2_VALID) {
669 Sq->Rsvd2 = (UINT64)Packet->NvmeCmd->Cdw2;
670 }
671 if(Packet->NvmeCmd->Flags & CDW3_VALID) {
672 Sq->Rsvd2 |= LShiftU64 ((UINT64)Packet->NvmeCmd->Cdw3, 32);
673 }
674 if(Packet->NvmeCmd->Flags & CDW10_VALID) {
675 Sq->Payload.Raw.Cdw10 = Packet->NvmeCmd->Cdw10;
676 }
677 if(Packet->NvmeCmd->Flags & CDW11_VALID) {
678 Sq->Payload.Raw.Cdw11 = Packet->NvmeCmd->Cdw11;
679 }
680 if(Packet->NvmeCmd->Flags & CDW12_VALID) {
681 Sq->Payload.Raw.Cdw12 = Packet->NvmeCmd->Cdw12;
682 }
683 if(Packet->NvmeCmd->Flags & CDW13_VALID) {
684 Sq->Payload.Raw.Cdw13 = Packet->NvmeCmd->Cdw13;
685 }
686 if(Packet->NvmeCmd->Flags & CDW14_VALID) {
687 Sq->Payload.Raw.Cdw14 = Packet->NvmeCmd->Cdw14;
688 }
689 if(Packet->NvmeCmd->Flags & CDW15_VALID) {
690 Sq->Payload.Raw.Cdw15 = Packet->NvmeCmd->Cdw15;
691 }
692
693 //
694 // Ring the submission queue doorbell.
695 //
696 if ((Event != NULL) && (QueueId != 0)) {
697 Private->SqTdbl[QueueId].Sqt =
698 (Private->SqTdbl[QueueId].Sqt + 1) % (NVME_ASYNC_CSQ_SIZE + 1);
699 } else {
700 Private->SqTdbl[QueueId].Sqt ^= 1;
701 }
702 Data = ReadUnaligned32 ((UINT32*)&Private->SqTdbl[QueueId]);
703 Status = PciIo->Mem.Write (
704 PciIo,
705 EfiPciIoWidthUint32,
706 NVME_BAR,
707 NVME_SQTDBL_OFFSET(QueueId, Private->Cap.Dstrd),
708 1,
709 &Data
710 );
711
712 if (EFI_ERROR (Status)) {
713 goto EXIT;
714 }
715
716 //
717 // For non-blocking requests, return directly if the command is placed
718 // in the submission queue.
719 //
720 if ((Event != NULL) && (QueueId != 0)) {
721 AsyncRequest = AllocateZeroPool (sizeof (NVME_PASS_THRU_ASYNC_REQ));
722 if (AsyncRequest == NULL) {
723 Status = EFI_DEVICE_ERROR;
724 goto EXIT;
725 }
726
727 AsyncRequest->Signature = NVME_PASS_THRU_ASYNC_REQ_SIG;
728 AsyncRequest->Packet = Packet;
729 AsyncRequest->CommandId = Sq->Cid;
730 AsyncRequest->CallerEvent = Event;
731 AsyncRequest->MapData = MapData;
732 AsyncRequest->MapMeta = MapMeta;
733 AsyncRequest->MapPrpList = MapPrpList;
734 AsyncRequest->PrpListNo = PrpListNo;
735 AsyncRequest->PrpListHost = PrpListHost;
736
737 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
738 InsertTailList (&Private->AsyncPassThruQueue, &AsyncRequest->Link);
739 gBS->RestoreTPL (OldTpl);
740
741 return EFI_SUCCESS;
742 }
743
744 Status = gBS->CreateEvent (
745 EVT_TIMER,
746 TPL_CALLBACK,
747 NULL,
748 NULL,
749 &TimerEvent
750 );
751 if (EFI_ERROR (Status)) {
752 goto EXIT;
753 }
754
755 Status = gBS->SetTimer(TimerEvent, TimerRelative, Packet->CommandTimeout);
756
757 if (EFI_ERROR(Status)) {
758 goto EXIT;
759 }
760
761 //
762 // Wait for completion queue to get filled in.
763 //
764 Status = EFI_TIMEOUT;
765 while (EFI_ERROR (gBS->CheckEvent (TimerEvent))) {
766 if (Cq->Pt != Private->Pt[QueueId]) {
767 Status = EFI_SUCCESS;
768 break;
769 }
770 }
771
772 //
773 // Check the NVMe cmd execution result
774 //
775 if (Status != EFI_TIMEOUT) {
776 if ((Cq->Sct == 0) && (Cq->Sc == 0)) {
777 Status = EFI_SUCCESS;
778 } else {
779 Status = EFI_DEVICE_ERROR;
780 //
781 // Copy the Respose Queue entry for this command to the callers response buffer
782 //
783 CopyMem(Packet->NvmeCompletion, Cq, sizeof(EFI_NVM_EXPRESS_COMPLETION));
784
785 //
786 // Dump every completion entry status for debugging.
787 //
788 DEBUG_CODE_BEGIN();
789 NvmeDumpStatus(Cq);
790 DEBUG_CODE_END();
791 }
792 } else {
793 //
794 // Timeout occurs for an NVMe command. Reset the controller to abort the
795 // outstanding commands.
796 //
797 DEBUG ((DEBUG_ERROR, "NvmExpressPassThru: Timeout occurs for an NVMe command.\n"));
798
799 //
800 // Disable the timer to trigger the process of async transfers temporarily.
801 //
802 Status = gBS->SetTimer (Private->TimerEvent, TimerCancel, 0);
803 if (EFI_ERROR (Status)) {
804 goto EXIT;
805 }
806
807 //
808 // Reset the NVMe controller.
809 //
810 Status = NvmeControllerInit (Private);
811 if (!EFI_ERROR (Status)) {
812 Status = AbortAsyncPassThruTasks (Private);
813 if (!EFI_ERROR (Status)) {
814 //
815 // Re-enable the timer to trigger the process of async transfers.
816 //
817 Status = gBS->SetTimer (Private->TimerEvent, TimerPeriodic, NVME_HC_ASYNC_TIMER);
818 if (!EFI_ERROR (Status)) {
819 //
820 // Return EFI_TIMEOUT to indicate a timeout occurs for NVMe PassThru command.
821 //
822 Status = EFI_TIMEOUT;
823 }
824 }
825 } else {
826 Status = EFI_DEVICE_ERROR;
827 }
828
829 goto EXIT;
830 }
831
832 if ((Private->CqHdbl[QueueId].Cqh ^= 1) == 0) {
833 Private->Pt[QueueId] ^= 1;
834 }
835
836 Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[QueueId]);
837 PreviousStatus = Status;
838 Status = PciIo->Mem.Write (
839 PciIo,
840 EfiPciIoWidthUint32,
841 NVME_BAR,
842 NVME_CQHDBL_OFFSET(QueueId, Private->Cap.Dstrd),
843 1,
844 &Data
845 );
846 // The return status of PciIo->Mem.Write should not override
847 // previous status if previous status contains error.
848 Status = EFI_ERROR (PreviousStatus) ? PreviousStatus : Status;
849
850 //
851 // For now, the code does not support the non-blocking feature for admin queue.
852 // If Event is not NULL for admin queue, signal the caller's event here.
853 //
854 if (Event != NULL) {
855 ASSERT (QueueId == 0);
856 gBS->SignalEvent (Event);
857 }
858
859 EXIT:
860 if (MapData != NULL) {
861 PciIo->Unmap (
862 PciIo,
863 MapData
864 );
865 }
866
867 if (MapMeta != NULL) {
868 PciIo->Unmap (
869 PciIo,
870 MapMeta
871 );
872 }
873
874 if (MapPrpList != NULL) {
875 PciIo->Unmap (
876 PciIo,
877 MapPrpList
878 );
879 }
880
881 if (Prp != NULL) {
882 PciIo->FreeBuffer (PciIo, PrpListNo, PrpListHost);
883 }
884
885 if (TimerEvent != NULL) {
886 gBS->CloseEvent (TimerEvent);
887 }
888 return Status;
889 }
890
891 /**
892 Used to retrieve the next namespace ID for this NVM Express controller.
893
894 The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNextNamespace() function retrieves the next valid
895 namespace ID on this NVM Express controller.
896
897 If on input the value pointed to by NamespaceId is 0xFFFFFFFF, then the first valid namespace
898 ID defined on the NVM Express controller is returned in the location pointed to by NamespaceId
899 and a status of EFI_SUCCESS is returned.
900
901 If on input the value pointed to by NamespaceId is an invalid namespace ID other than 0xFFFFFFFF,
902 then EFI_INVALID_PARAMETER is returned.
903
904 If on input the value pointed to by NamespaceId is a valid namespace ID, then the next valid
905 namespace ID on the NVM Express controller is returned in the location pointed to by NamespaceId,
906 and EFI_SUCCESS is returned.
907
908 If the value pointed to by NamespaceId is the namespace ID of the last namespace on the NVM
909 Express controller, then EFI_NOT_FOUND is returned.
910
911 @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
912 @param[in,out] NamespaceId On input, a pointer to a legal NamespaceId for an NVM Express
913 namespace present on the NVM Express controller. On output, a
914 pointer to the next NamespaceId of an NVM Express namespace on
915 an NVM Express controller. An input value of 0xFFFFFFFF retrieves
916 the first NamespaceId for an NVM Express namespace present on an
917 NVM Express controller.
918
919 @retval EFI_SUCCESS The Namespace ID of the next Namespace was returned.
920 @retval EFI_NOT_FOUND There are no more namespaces defined on this controller.
921 @retval EFI_INVALID_PARAMETER NamespaceId is an invalid value other than 0xFFFFFFFF.
922
923 **/
924 EFI_STATUS
925 EFIAPI
926 NvmExpressGetNextNamespace (
927 IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
928 IN OUT UINT32 *NamespaceId
929 )
930 {
931 NVME_CONTROLLER_PRIVATE_DATA *Private;
932 NVME_ADMIN_NAMESPACE_DATA *NamespaceData;
933 UINT32 NextNamespaceId;
934 EFI_STATUS Status;
935
936 if ((This == NULL) || (NamespaceId == NULL)) {
937 return EFI_INVALID_PARAMETER;
938 }
939
940 NamespaceData = NULL;
941 Status = EFI_NOT_FOUND;
942
943 Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
944 //
945 // If the NamespaceId input value is 0xFFFFFFFF, then get the first valid namespace ID
946 //
947 if (*NamespaceId == 0xFFFFFFFF) {
948 //
949 // Start with the first namespace ID
950 //
951 NextNamespaceId = 1;
952 //
953 // Allocate buffer for Identify Namespace data.
954 //
955 NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));
956
957 if (NamespaceData == NULL) {
958 return EFI_NOT_FOUND;
959 }
960
961 Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);
962 if (EFI_ERROR(Status)) {
963 goto Done;
964 }
965
966 *NamespaceId = NextNamespaceId;
967 } else {
968 if (*NamespaceId > Private->ControllerData->Nn) {
969 return EFI_INVALID_PARAMETER;
970 }
971
972 NextNamespaceId = *NamespaceId + 1;
973 if (NextNamespaceId > Private->ControllerData->Nn) {
974 return EFI_NOT_FOUND;
975 }
976
977 //
978 // Allocate buffer for Identify Namespace data.
979 //
980 NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));
981 if (NamespaceData == NULL) {
982 return EFI_NOT_FOUND;
983 }
984
985 Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);
986 if (EFI_ERROR(Status)) {
987 goto Done;
988 }
989
990 *NamespaceId = NextNamespaceId;
991 }
992
993 Done:
994 if (NamespaceData != NULL) {
995 FreePool(NamespaceData);
996 }
997
998 return Status;
999 }
1000
1001 /**
1002 Used to translate a device path node to a namespace ID.
1003
1004 The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNamespace() function determines the namespace ID associated with the
1005 namespace described by DevicePath.
1006
1007 If DevicePath is a device path node type that the NVM Express Pass Thru driver supports, then the NVM Express
1008 Pass Thru driver will attempt to translate the contents DevicePath into a namespace ID.
1009
1010 If this translation is successful, then that namespace ID is returned in NamespaceId, and EFI_SUCCESS is returned
1011
1012 @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
1013 @param[in] DevicePath A pointer to the device path node that describes an NVM Express namespace on
1014 the NVM Express controller.
1015 @param[out] NamespaceId The NVM Express namespace ID contained in the device path node.
1016
1017 @retval EFI_SUCCESS DevicePath was successfully translated to NamespaceId.
1018 @retval EFI_INVALID_PARAMETER If DevicePath or NamespaceId are NULL, then EFI_INVALID_PARAMETER is returned.
1019 @retval EFI_UNSUPPORTED If DevicePath is not a device path node type that the NVM Express Pass Thru driver
1020 supports, then EFI_UNSUPPORTED is returned.
1021 @retval EFI_NOT_FOUND If DevicePath is a device path node type that the NVM Express Pass Thru driver
1022 supports, but there is not a valid translation from DevicePath to a namespace ID,
1023 then EFI_NOT_FOUND is returned.
1024 **/
1025 EFI_STATUS
1026 EFIAPI
1027 NvmExpressGetNamespace (
1028 IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
1029 IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
1030 OUT UINT32 *NamespaceId
1031 )
1032 {
1033 NVME_NAMESPACE_DEVICE_PATH *Node;
1034 NVME_CONTROLLER_PRIVATE_DATA *Private;
1035
1036 if ((This == NULL) || (DevicePath == NULL) || (NamespaceId == NULL)) {
1037 return EFI_INVALID_PARAMETER;
1038 }
1039
1040 if (DevicePath->Type != MESSAGING_DEVICE_PATH) {
1041 return EFI_UNSUPPORTED;
1042 }
1043
1044 Node = (NVME_NAMESPACE_DEVICE_PATH *)DevicePath;
1045 Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
1046
1047 if (DevicePath->SubType == MSG_NVME_NAMESPACE_DP) {
1048 if (DevicePathNodeLength(DevicePath) != sizeof(NVME_NAMESPACE_DEVICE_PATH)) {
1049 return EFI_NOT_FOUND;
1050 }
1051
1052 //
1053 // Check NamespaceId in the device path node is valid or not.
1054 //
1055 if ((Node->NamespaceId == 0) ||
1056 (Node->NamespaceId > Private->ControllerData->Nn)) {
1057 return EFI_NOT_FOUND;
1058 }
1059
1060 *NamespaceId = Node->NamespaceId;
1061
1062 return EFI_SUCCESS;
1063 } else {
1064 return EFI_UNSUPPORTED;
1065 }
1066 }
1067
1068 /**
1069 Used to allocate and build a device path node for an NVM Express namespace on an NVM Express controller.
1070
1071 The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.BuildDevicePath() function allocates and builds a single device
1072 path node for the NVM Express namespace specified by NamespaceId.
1073
1074 If the NamespaceId is not valid, then EFI_NOT_FOUND is returned.
1075
1076 If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned.
1077
1078 If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES is returned.
1079
1080 Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of DevicePath are
1081 initialized to describe the NVM Express namespace specified by NamespaceId, and EFI_SUCCESS is returned.
1082
1083 @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.
1084 @param[in] NamespaceId The NVM Express namespace ID for which a device path node is to be
1085 allocated and built. Caller must set the NamespaceId to zero if the
1086 device path node will contain a valid UUID.
1087 @param[in,out] DevicePath A pointer to a single device path node that describes the NVM Express
1088 namespace specified by NamespaceId. This function is responsible for
1089 allocating the buffer DevicePath with the boot service AllocatePool().
1090 It is the caller's responsibility to free DevicePath when the caller
1091 is finished with DevicePath.
1092 @retval EFI_SUCCESS The device path node that describes the NVM Express namespace specified
1093 by NamespaceId was allocated and returned in DevicePath.
1094 @retval EFI_NOT_FOUND The NamespaceId is not valid.
1095 @retval EFI_INVALID_PARAMETER DevicePath is NULL.
1096 @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate the DevicePath node.
1097
1098 **/
1099 EFI_STATUS
1100 EFIAPI
1101 NvmExpressBuildDevicePath (
1102 IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,
1103 IN UINT32 NamespaceId,
1104 IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
1105 )
1106 {
1107 NVME_NAMESPACE_DEVICE_PATH *Node;
1108 NVME_CONTROLLER_PRIVATE_DATA *Private;
1109 EFI_STATUS Status;
1110 NVME_ADMIN_NAMESPACE_DATA *NamespaceData;
1111
1112 //
1113 // Validate parameters
1114 //
1115 if ((This == NULL) || (DevicePath == NULL)) {
1116 return EFI_INVALID_PARAMETER;
1117 }
1118
1119 Status = EFI_SUCCESS;
1120 Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);
1121
1122 //
1123 // Check NamespaceId is valid or not.
1124 //
1125 if ((NamespaceId == 0) ||
1126 (NamespaceId > Private->ControllerData->Nn)) {
1127 return EFI_NOT_FOUND;
1128 }
1129
1130 Node = (NVME_NAMESPACE_DEVICE_PATH *)AllocateZeroPool (sizeof (NVME_NAMESPACE_DEVICE_PATH));
1131 if (Node == NULL) {
1132 return EFI_OUT_OF_RESOURCES;
1133 }
1134
1135 Node->Header.Type = MESSAGING_DEVICE_PATH;
1136 Node->Header.SubType = MSG_NVME_NAMESPACE_DP;
1137 SetDevicePathNodeLength (&Node->Header, sizeof (NVME_NAMESPACE_DEVICE_PATH));
1138 Node->NamespaceId = NamespaceId;
1139
1140 //
1141 // Allocate a buffer for Identify Namespace data.
1142 //
1143 NamespaceData = NULL;
1144 NamespaceData = AllocateZeroPool(sizeof (NVME_ADMIN_NAMESPACE_DATA));
1145 if(NamespaceData == NULL) {
1146 Status = EFI_OUT_OF_RESOURCES;
1147 goto Exit;
1148 }
1149
1150 //
1151 // Get UUID from specified Identify Namespace data.
1152 //
1153 Status = NvmeIdentifyNamespace (
1154 Private,
1155 NamespaceId,
1156 (VOID *)NamespaceData
1157 );
1158
1159 if (EFI_ERROR(Status)) {
1160 goto Exit;
1161 }
1162
1163 Node->NamespaceUuid = NamespaceData->Eui64;
1164
1165 *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)Node;
1166
1167 Exit:
1168 if(NamespaceData != NULL) {
1169 FreePool (NamespaceData);
1170 }
1171
1172 if (EFI_ERROR (Status)) {
1173 FreePool (Node);
1174 }
1175
1176 return Status;
1177 }
1178