MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.h

   1 /** @file
   2   The NvmExpressPei driver is used to manage non-volatile memory subsystem
   3   which follows NVM Express specification at PEI phase.
   4
   5   Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
   6
   7   SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 **/
  10
  11 #ifndef _NVM_EXPRESS_PEI_HCI_H_
  12 #define _NVM_EXPRESS_PEI_HCI_H_
  13
  14 //
  15 // NVME host controller registers operation definitions
  16 //
  17 #define NVME_GET_CAP(Private, Cap)             NvmeMmioRead  (Cap, Private->MmioBase + NVME_CAP_OFFSET, sizeof (NVME_CAP))
  18 #define NVME_GET_CC(Private, Cc)               NvmeMmioRead  (Cc, Private->MmioBase + NVME_CC_OFFSET, sizeof (NVME_CC))
  19 #define NVME_SET_CC(Private, Cc)               NvmeMmioWrite (Private->MmioBase + NVME_CC_OFFSET, Cc, sizeof (NVME_CC))
  20 #define NVME_GET_CSTS(Private, Csts)           NvmeMmioRead  (Csts, Private->MmioBase + NVME_CSTS_OFFSET, sizeof (NVME_CSTS))
  21 #define NVME_GET_AQA(Private, Aqa)             NvmeMmioRead  (Aqa, Private->MmioBase + NVME_AQA_OFFSET, sizeof (NVME_AQA))
  22 #define NVME_SET_AQA(Private, Aqa)             NvmeMmioWrite (Private->MmioBase + NVME_AQA_OFFSET, Aqa, sizeof (NVME_AQA))
  23 #define NVME_GET_ASQ(Private, Asq)             NvmeMmioRead  (Asq, Private->MmioBase + NVME_ASQ_OFFSET, sizeof (NVME_ASQ))
  24 #define NVME_SET_ASQ(Private, Asq)             NvmeMmioWrite (Private->MmioBase + NVME_ASQ_OFFSET, Asq, sizeof (NVME_ASQ))
  25 #define NVME_GET_ACQ(Private, Acq)             NvmeMmioRead  (Acq, Private->MmioBase + NVME_ACQ_OFFSET, sizeof (NVME_ACQ))
  26 #define NVME_SET_ACQ(Private, Acq)             NvmeMmioWrite (Private->MmioBase + NVME_ACQ_OFFSET, Acq, sizeof (NVME_ACQ))
  27 #define NVME_GET_VER(Private, Ver)             NvmeMmioRead  (Ver, Private->MmioBase + NVME_VER_OFFSET, sizeof (NVME_VER))
  28 #define NVME_SET_SQTDBL(Private, Qid, Sqtdbl)  NvmeMmioWrite (Private->MmioBase + NVME_SQTDBL_OFFSET(Qid, Private->Cap.Dstrd), Sqtdbl, sizeof (NVME_SQTDBL))
  29 #define NVME_SET_CQHDBL(Private, Qid, Cqhdbl)  NvmeMmioWrite (Private->MmioBase + NVME_CQHDBL_OFFSET(Qid, Private->Cap.Dstrd), Cqhdbl, sizeof (NVME_CQHDBL))
  30
  31 //
  32 // Base memory address enum types
  33 //
  34 enum {
  35   BASEMEM_ASQ,
  36   BASEMEM_ACQ,
  37   BASEMEM_SQ,
  38   BASEMEM_CQ,
  39   BASEMEM_PRP,
  40   MAX_BASEMEM_COUNT
  41 };
  42
  43 //
  44 // All of base memories are 4K(0x1000) alignment
  45 //
  46 #define ALIGN(v, a)                          (UINTN)((((v) - 1) | ((a) - 1)) + 1)
  47 #define NVME_MEM_BASE(Private)               ((UINTN)(Private->Buffer))
  48 #define NVME_ASQ_BASE(Private)               (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ASQ))                                * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
  49 #define NVME_ACQ_BASE(Private)               (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ACQ))                                * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
  50 #define NVME_SQ_BASE(Private, Index)         (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_SQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
  51 #define NVME_CQ_BASE(Private, Index)         (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_CQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
  52 #define NVME_PRP_BASE(Private)               (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_PRP))                                * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
  53
  54
  55 /**
  56   Transfer MMIO Data to memory.
  57
  58   @param[in,out] MemBuffer    Destination: Memory address.
  59   @param[in] MmioAddr         Source: MMIO address.
  60   @param[in] Size             Size for read.
  61
  62   @retval EFI_SUCCESS         MMIO read sucessfully.
  63
  64 **/
  65 EFI_STATUS
  66 NvmeMmioRead (
  67   IN OUT VOID *MemBuffer,
  68   IN     UINTN MmioAddr,
  69   IN     UINTN Size
  70   );
  71
  72 /**
  73   Transfer memory data to MMIO.
  74
  75   @param[in,out] MmioAddr    Destination: MMIO address.
  76   @param[in] MemBuffer       Source: Memory address.
  77   @param[in] Size            Size for write.
  78
  79   @retval EFI_SUCCESS        MMIO write sucessfully.
  80
  81 **/
  82 EFI_STATUS
  83 NvmeMmioWrite (
  84   IN OUT UINTN MmioAddr,
  85   IN     VOID *MemBuffer,
  86   IN     UINTN Size
  87   );
  88
  89 /**
  90   Get the page offset for specific NVME based memory.
  91
  92   @param[in] BaseMemIndex    The Index of BaseMem (0-based).
  93
  94   @retval - The page count for specific BaseMem Index
  95
  96 **/
  97 UINT32
  98 NvmeBaseMemPageOffset (
  99   IN UINTN              BaseMemIndex
 100   );
 101
 102 /**
 103   Initialize the Nvm Express controller.
 104
 105   @param[in] Private     The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.
 106
 107   @retval EFI_SUCCESS    The NVM Express Controller is initialized successfully.
 108   @retval Others         A device error occurred while initializing the controller.
 109
 110 **/
 111 EFI_STATUS
 112 NvmeControllerInit (
 113   IN PEI_NVME_CONTROLLER_PRIVATE_DATA    *Private
 114   );
 115
 116 /**
 117   Get specified identify namespace data.
 118
 119   @param[in] Private        The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.
 120   @param[in] NamespaceId    The specified namespace identifier.
 121   @param[in] Buffer         The buffer used to store the identify namespace data.
 122
 123   @return EFI_SUCCESS         Successfully get the identify namespace data.
 124   @return EFI_DEVICE_ERROR    Fail to get the identify namespace data.
 125
 126 **/
 127 EFI_STATUS
 128 NvmeIdentifyNamespace (
 129   IN PEI_NVME_CONTROLLER_PRIVATE_DATA    *Private,
 130   IN UINT32                              NamespaceId,
 131   IN VOID                                *Buffer
 132   );
 133
 134 /**
 135   Free the DMA resources allocated by an NVME controller.
 136
 137   @param[in] Private     The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.
 138
 139 **/
 140 VOID
 141 NvmeFreeDmaResource (
 142   IN PEI_NVME_CONTROLLER_PRIVATE_DATA    *Private
 143   );
 144
 145 #endif