MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h

   1 /** @file
   2   Header files and data structures needed by PCI Bus module.
   3
   4 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
   5 This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15
  16 #ifndef _EFI_PCI_BUS_H_
  17 #define _EFI_PCI_BUS_H_
  18
  19 #include <PiDxe.h>
  20
  21 #include <Protocol/LoadedImage.h>
  22 #include <Protocol/PciHostBridgeResourceAllocation.h>
  23 #include <Protocol/PciIo.h>
  24 #include <Protocol/LoadFile2.h>
  25 #include <Protocol/PciRootBridgeIo.h>
  26 #include <Protocol/PciHotPlugRequest.h>
  27 #include <Protocol/DevicePath.h>
  28 #include <Protocol/PciPlatform.h>
  29 #include <Protocol/PciHotPlugInit.h>
  30 #include <Protocol/Decompress.h>
  31 #include <Protocol/BusSpecificDriverOverride.h>
  32 #include <Protocol/IncompatiblePciDeviceSupport.h>
  33 #include <Protocol/PciOverride.h>
  34 #include <Protocol/PciEnumerationComplete.h>
  35 #include <Protocol/DevicePathToText.h>
  36
  37 #include <Library/DebugLib.h>
  38 #include <Library/UefiDriverEntryPoint.h>
  39 #include <Library/BaseLib.h>
  40 #include <Library/UefiLib.h>
  41 #include <Library/BaseMemoryLib.h>
  42 #include <Library/ReportStatusCodeLib.h>
  43 #include <Library/MemoryAllocationLib.h>
  44 #include <Library/UefiBootServicesTableLib.h>
  45 #include <Library/DevicePathLib.h>
  46 #include <Library/PcdLib.h>
  47 #include <Library/PeCoffLib.h>
  48
  49 #include <IndustryStandard/Pci.h>
  50 #include <IndustryStandard/PeImage.h>
  51 #include <IndustryStandard/Acpi.h>
  52
  53 typedef struct _PCI_IO_DEVICE              PCI_IO_DEVICE;
  54 typedef struct _PCI_BAR                    PCI_BAR;
  55
  56 #define EFI_PCI_RID(Bus, Device, Function)  (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)
  57 #define EFI_PCI_BUS_OF_RID(RID)             ((UINT32)RID >> 8)
  58
  59 #define     EFI_PCI_IOV_POLICY_ARI           0x0001
  60 #define     EFI_PCI_IOV_POLICY_SRIOV         0x0002
  61 #define     EFI_PCI_IOV_POLICY_MRIOV         0x0004
  62
  63 typedef enum {
  64   PciBarTypeUnknown = 0,
  65   PciBarTypeIo16,
  66   PciBarTypeIo32,
  67   PciBarTypeMem32,
  68   PciBarTypePMem32,
  69   PciBarTypeMem64,
  70   PciBarTypePMem64,
  71   PciBarTypeIo,
  72   PciBarTypeMem,
  73   PciBarTypeMaxType
  74 } PCI_BAR_TYPE;
  75
  76 #include "ComponentName.h"
  77 #include "PciIo.h"
  78 #include "PciCommand.h"
  79 #include "PciDeviceSupport.h"
  80 #include "PciEnumerator.h"
  81 #include "PciEnumeratorSupport.h"
  82 #include "PciDriverOverride.h"
  83 #include "PciRomTable.h"
  84 #include "PciOptionRomSupport.h"
  85 #include "PciPowerManagement.h"
  86 #include "PciHotPlugSupport.h"
  87 #include "PciLib.h"
  88
  89 #define VGABASE1  0x3B0
  90 #define VGALIMIT1 0x3BB
  91
  92 #define VGABASE2  0x3C0
  93 #define VGALIMIT2 0x3DF
  94
  95 #define ISABASE   0x100
  96 #define ISALIMIT  0x3FF
  97
  98 //
  99 // PCI BAR parameters
 100 //
 101 struct _PCI_BAR {
 102   UINT64        BaseAddress;
 103   UINT64        Length;
 104   UINT64        Alignment;
 105   PCI_BAR_TYPE  BarType;
 106   BOOLEAN       Prefetchable;
 107   UINT8         MemType;
 108   UINT16        Offset;
 109 };
 110
 111 //
 112 // defined in PCI Card Specification, 8.0
 113 //
 114 #define PCI_CARD_MEMORY_BASE_0                0x1C
 115 #define PCI_CARD_MEMORY_LIMIT_0               0x20
 116 #define PCI_CARD_MEMORY_BASE_1                0x24
 117 #define PCI_CARD_MEMORY_LIMIT_1               0x28
 118 #define PCI_CARD_IO_BASE_0_LOWER              0x2C
 119 #define PCI_CARD_IO_BASE_0_UPPER              0x2E
 120 #define PCI_CARD_IO_LIMIT_0_LOWER             0x30
 121 #define PCI_CARD_IO_LIMIT_0_UPPER             0x32
 122 #define PCI_CARD_IO_BASE_1_LOWER              0x34
 123 #define PCI_CARD_IO_BASE_1_UPPER              0x36
 124 #define PCI_CARD_IO_LIMIT_1_LOWER             0x38
 125 #define PCI_CARD_IO_LIMIT_1_UPPER             0x3A
 126 #define PCI_CARD_BRIDGE_CONTROL               0x3E
 127
 128 #define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
 129 #define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
 130
 131 #define RB_IO_RANGE                           1
 132 #define RB_MEM32_RANGE                        2
 133 #define RB_PMEM32_RANGE                       3
 134 #define RB_MEM64_RANGE                        4
 135 #define RB_PMEM64_RANGE                       5
 136
 137 #define PPB_BAR_0                             0
 138 #define PPB_BAR_1                             1
 139 #define PPB_IO_RANGE                          2
 140 #define PPB_MEM32_RANGE                       3
 141 #define PPB_PMEM32_RANGE                      4
 142 #define PPB_PMEM64_RANGE                      5
 143 #define PPB_MEM64_RANGE                       0xFF
 144
 145 #define P2C_BAR_0                             0
 146 #define P2C_MEM_1                             1
 147 #define P2C_MEM_2                             2
 148 #define P2C_IO_1                              3
 149 #define P2C_IO_2                              4
 150
 151 #define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001
 152 #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002
 153 #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004
 154 #define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008
 155 #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
 156 #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020
 157 #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040
 158
 159 #define PCI_MAX_HOST_BRIDGE_NUM               0x0010
 160
 161 //
 162 // Define option for attribute
 163 //
 164 #define EFI_SET_SUPPORTS    0
 165 #define EFI_SET_ATTRIBUTES  1
 166
 167 #define PCI_IO_DEVICE_SIGNATURE               SIGNATURE_32 ('p', 'c', 'i', 'o')
 168
 169 struct _PCI_IO_DEVICE {
 170   UINT32                                    Signature;
 171   EFI_HANDLE                                Handle;
 172   EFI_PCI_IO_PROTOCOL                       PciIo;
 173   LIST_ENTRY                                Link;
 174
 175   EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
 176   EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;
 177   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;
 178   EFI_LOAD_FILE2_PROTOCOL                   LoadFile2;
 179
 180   //
 181   // PCI configuration space header type
 182   //
 183   PCI_TYPE00                                Pci;
 184
 185   //
 186   // Bus number, Device number, Function number
 187   //
 188   UINT8                                     BusNumber;
 189   UINT8                                     DeviceNumber;
 190   UINT8                                     FunctionNumber;
 191
 192   //
 193   // BAR for this PCI Device
 194   //
 195   PCI_BAR                                   PciBar[PCI_MAX_BAR];
 196
 197   //
 198   // The bridge device this pci device is subject to
 199   //
 200   PCI_IO_DEVICE                             *Parent;
 201
 202   //
 203   // A linked list for children Pci Device if it is bridge device
 204   //
 205   LIST_ENTRY                                ChildList;
 206
 207   //
 208   // TURE if the PCI bus driver creates the handle for this PCI device
 209   //
 210   BOOLEAN                                   Registered;
 211
 212   //
 213   // TRUE if the PCI bus driver successfully allocates the resource required by
 214   // this PCI device
 215   //
 216   BOOLEAN                                   Allocated;
 217
 218   //
 219   // The attribute this PCI device currently set
 220   //
 221   UINT64                                    Attributes;
 222
 223   //
 224   // The attributes this PCI device actually supports
 225   //
 226   UINT64                                    Supports;
 227
 228   //
 229   // The resource decode the bridge supports
 230   //
 231   UINT32                                    Decodes;
 232
 233   //
 234   // TRUE if the ROM image is from the PCI Option ROM BAR
 235   //
 236   BOOLEAN                                   EmbeddedRom;
 237
 238   //
 239   // The OptionRom Size
 240   //
 241   UINT64                                    RomSize;
 242
 243   //
 244   // The OptionRom Size
 245   //
 246   UINT64                                    RomBase;
 247
 248   //
 249   // TRUE if all OpROM (in device or in platform specific position) have been processed
 250   //
 251   BOOLEAN                                   AllOpRomProcessed;
 252
 253   //
 254   // TRUE if the ROM image contains EFI OpROM
 255   //
 256   BOOLEAN                                   HasEfiOpRom;
 257
 258   //
 259   // TRUE if there is any EFI driver in the OptionRom
 260   //
 261   BOOLEAN                                   BusOverride;
 262
 263   //
 264   // A list tracking reserved resource on a bridge device
 265   //
 266   LIST_ENTRY                                ReservedResourceList;
 267
 268   //
 269   // A list tracking image handle of platform specific overriding driver
 270   //
 271   LIST_ENTRY                                OptionRomDriverList;
 272
 273   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;
 274   EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;
 275
 276   //
 277   // Bus number ranges for a PCI Root Bridge device
 278   //
 279   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *BusNumberRanges;
 280
 281   BOOLEAN                                   IsPciExp;
 282   //
 283   // For SR-IOV
 284   //
 285   UINT8                                     PciExpressCapabilityOffset;
 286   UINT32                                    AriCapabilityOffset;
 287   UINT32                                    SrIovCapabilityOffset;
 288   UINT32                                    MrIovCapabilityOffset;
 289   PCI_BAR                                   VfPciBar[PCI_MAX_BAR];
 290   UINT32                                    SystemPageSize;
 291   UINT16                                    InitialVFs;
 292   UINT16                                    ReservedBusNum;
 293   //
 294   // Per PCI to PCI Bridge spec, I/O window is 4K aligned,
 295   // but some chipsets support non-stardard I/O window aligments less than 4K.
 296   // This field is used to support this case.
 297   //
 298   UINT16                                    BridgeIoAlignment;
 299 };
 300
 301 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
 302   CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
 303
 304 #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
 305   CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
 306
 307 #define PCI_IO_DEVICE_FROM_LINK(a) \
 308   CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
 309
 310 #define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
 311   CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
 312
 313
 314
 315 //
 316 // Global Variables
 317 //
 318 extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;
 319 extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;
 320 extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;
 321 extern EFI_COMPONENT_NAME2_PROTOCOL                 gPciBusComponentName2;
 322 extern BOOLEAN                                      gFullEnumeration;
 323 extern UINTN                                        gPciHostBridgeNumber;
 324 extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
 325 extern UINT64                                       gAllOne;
 326 extern UINT64                                       gAllZero;
 327 extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;
 328 extern EFI_PCI_OVERRIDE_PROTOCOL                    *gPciOverrideProtocol;
 329 extern BOOLEAN                                      mReserveIsaAliases;
 330 extern BOOLEAN                                      mReserveVgaAliases;
 331
 332 /**
 333   Macro that checks whether device is a GFX device.
 334
 335   @param  _p      Specified device.
 336
 337   @retval TRUE    Device is a a GFX device.
 338   @retval FALSE   Device is not a a GFX device.
 339
 340 **/
 341 #define IS_PCI_GFX(_p)     IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
 342
 343 /**
 344   Test to see if this driver supports ControllerHandle. Any ControllerHandle
 345   than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.
 346
 347   @param  This                Protocol instance pointer.
 348   @param  Controller          Handle of device to test.
 349   @param  RemainingDevicePath Optional parameter use to pick a specific child.
 350                               device to start.
 351
 352   @retval EFI_SUCCESS         This driver supports this device.
 353   @retval EFI_ALREADY_STARTED This driver is already running on this device.
 354   @retval other               This driver does not support this device.
 355
 356 **/
 357 EFI_STATUS
 358 EFIAPI
 359 PciBusDriverBindingSupported (
 360   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 361   IN EFI_HANDLE                     Controller,
 362   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 363   );
 364
 365 /**
 366   Start this driver on ControllerHandle and enumerate Pci bus and start
 367   all device under PCI bus.
 368
 369   @param  This                 Protocol instance pointer.
 370   @param  Controller           Handle of device to bind driver to.
 371   @param  RemainingDevicePath  Optional parameter use to pick a specific child.
 372                                device to start.
 373
 374   @retval EFI_SUCCESS          This driver is added to ControllerHandle.
 375   @retval EFI_ALREADY_STARTED  This driver is already running on ControllerHandle.
 376   @retval other                This driver does not support this device.
 377
 378 **/
 379 EFI_STATUS
 380 EFIAPI
 381 PciBusDriverBindingStart (
 382   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 383   IN EFI_HANDLE                     Controller,
 384   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 385   );
 386
 387 /**
 388   Stop this driver on ControllerHandle. Support stoping any child handles
 389   created by this driver.
 390
 391   @param  This              Protocol instance pointer.
 392   @param  Controller        Handle of device to stop driver on.
 393   @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of
 394                             children is zero stop the entire bus driver.
 395   @param  ChildHandleBuffer List of Child Handles to Stop.
 396
 397   @retval EFI_SUCCESS       This driver is removed ControllerHandle.
 398   @retval other             This driver was not removed from this device.
 399
 400 **/
 401 EFI_STATUS
 402 EFIAPI
 403 PciBusDriverBindingStop (
 404   IN  EFI_DRIVER_BINDING_PROTOCOL   *This,
 405   IN  EFI_HANDLE                    Controller,
 406   IN  UINTN                         NumberOfChildren,
 407   IN  EFI_HANDLE                    *ChildHandleBuffer
 408   );
 409
 410 #endif