MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h

   1 /** @file
   2   Header files and data structures needed by PCI Bus module.
   3
   4 Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
   5 This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15
  16 #ifndef _EFI_PCI_BUS_H_
  17 #define _EFI_PCI_BUS_H_
  18
  19 #include <PiDxe.h>
  20
  21 #include <Guid/EventGroup.h>
  22
  23 #include <Protocol/LoadedImage.h>
  24 #include <Protocol/PciHostBridgeResourceAllocation.h>
  25 #include <Protocol/PciIo.h>
  26 #include <Protocol/LoadFile2.h>
  27 #include <Protocol/PciRootBridgeIo.h>
  28 #include <Protocol/PciHotPlugRequest.h>
  29 #include <Protocol/DevicePath.h>
  30 #include <Protocol/PciPlatform.h>
  31 #include <Protocol/PciHotPlugInit.h>
  32 #include <Protocol/Decompress.h>
  33 #include <Protocol/BusSpecificDriverOverride.h>
  34 #include <Protocol/IncompatiblePciDeviceSupport.h>
  35 #include <Protocol/PciOverride.h>
  36 #include <Protocol/PciEnumerationComplete.h>
  37 #include <Protocol/IoMmu.h>
  38
  39 #include <Library/DebugLib.h>
  40 #include <Library/UefiDriverEntryPoint.h>
  41 #include <Library/BaseLib.h>
  42 #include <Library/UefiLib.h>
  43 #include <Library/BaseMemoryLib.h>
  44 #include <Library/ReportStatusCodeLib.h>
  45 #include <Library/MemoryAllocationLib.h>
  46 #include <Library/UefiBootServicesTableLib.h>
  47 #include <Library/DevicePathLib.h>
  48 #include <Library/PcdLib.h>
  49 #include <Library/PeCoffLib.h>
  50
  51 #include <IndustryStandard/Pci.h>
  52 #include <IndustryStandard/PeImage.h>
  53 #include <IndustryStandard/Acpi.h>
  54
  55 typedef struct _PCI_IO_DEVICE              PCI_IO_DEVICE;
  56 typedef struct _PCI_BAR                    PCI_BAR;
  57
  58 #define EFI_PCI_RID(Bus, Device, Function)  (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)
  59 #define EFI_PCI_BUS_OF_RID(RID)             ((UINT32)RID >> 8)
  60
  61 #define     EFI_PCI_IOV_POLICY_ARI           0x0001
  62 #define     EFI_PCI_IOV_POLICY_SRIOV         0x0002
  63 #define     EFI_PCI_IOV_POLICY_MRIOV         0x0004
  64
  65 typedef enum {
  66   PciBarTypeUnknown = 0,
  67   PciBarTypeIo16,
  68   PciBarTypeIo32,
  69   PciBarTypeMem32,
  70   PciBarTypePMem32,
  71   PciBarTypeMem64,
  72   PciBarTypePMem64,
  73   PciBarTypeIo,
  74   PciBarTypeMem,
  75   PciBarTypeMaxType
  76 } PCI_BAR_TYPE;
  77
  78 #include "ComponentName.h"
  79 #include "PciIo.h"
  80 #include "PciCommand.h"
  81 #include "PciDeviceSupport.h"
  82 #include "PciEnumerator.h"
  83 #include "PciEnumeratorSupport.h"
  84 #include "PciDriverOverride.h"
  85 #include "PciRomTable.h"
  86 #include "PciOptionRomSupport.h"
  87 #include "PciPowerManagement.h"
  88 #include "PciHotPlugSupport.h"
  89 #include "PciLib.h"
  90
  91 #define VGABASE1  0x3B0
  92 #define VGALIMIT1 0x3BB
  93
  94 #define VGABASE2  0x3C0
  95 #define VGALIMIT2 0x3DF
  96
  97 #define ISABASE   0x100
  98 #define ISALIMIT  0x3FF
  99
 100 //
 101 // PCI BAR parameters
 102 //
 103 struct _PCI_BAR {
 104   UINT64        BaseAddress;
 105   UINT64        Length;
 106   UINT64        Alignment;
 107   PCI_BAR_TYPE  BarType;
 108   BOOLEAN       BarTypeFixed;
 109   UINT16        Offset;
 110 };
 111
 112 //
 113 // defined in PCI Card Specification, 8.0
 114 //
 115 #define PCI_CARD_MEMORY_BASE_0                0x1C
 116 #define PCI_CARD_MEMORY_LIMIT_0               0x20
 117 #define PCI_CARD_MEMORY_BASE_1                0x24
 118 #define PCI_CARD_MEMORY_LIMIT_1               0x28
 119 #define PCI_CARD_IO_BASE_0_LOWER              0x2C
 120 #define PCI_CARD_IO_BASE_0_UPPER              0x2E
 121 #define PCI_CARD_IO_LIMIT_0_LOWER             0x30
 122 #define PCI_CARD_IO_LIMIT_0_UPPER             0x32
 123 #define PCI_CARD_IO_BASE_1_LOWER              0x34
 124 #define PCI_CARD_IO_BASE_1_UPPER              0x36
 125 #define PCI_CARD_IO_LIMIT_1_LOWER             0x38
 126 #define PCI_CARD_IO_LIMIT_1_UPPER             0x3A
 127 #define PCI_CARD_BRIDGE_CONTROL               0x3E
 128
 129 #define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
 130 #define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
 131
 132 #define RB_IO_RANGE                           1
 133 #define RB_MEM32_RANGE                        2
 134 #define RB_PMEM32_RANGE                       3
 135 #define RB_MEM64_RANGE                        4
 136 #define RB_PMEM64_RANGE                       5
 137
 138 #define PPB_BAR_0                             0
 139 #define PPB_BAR_1                             1
 140 #define PPB_IO_RANGE                          2
 141 #define PPB_MEM32_RANGE                       3
 142 #define PPB_PMEM32_RANGE                      4
 143 #define PPB_PMEM64_RANGE                      5
 144 #define PPB_MEM64_RANGE                       0xFF
 145
 146 #define P2C_BAR_0                             0
 147 #define P2C_MEM_1                             1
 148 #define P2C_MEM_2                             2
 149 #define P2C_IO_1                              3
 150 #define P2C_IO_2                              4
 151
 152 #define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001
 153 #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002
 154 #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004
 155 #define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008
 156 #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
 157 #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020
 158 #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040
 159
 160 #define PCI_MAX_HOST_BRIDGE_NUM               0x0010
 161
 162 //
 163 // Define option for attribute
 164 //
 165 #define EFI_SET_SUPPORTS    0
 166 #define EFI_SET_ATTRIBUTES  1
 167
 168 #define PCI_IO_DEVICE_SIGNATURE               SIGNATURE_32 ('p', 'c', 'i', 'o')
 169
 170 struct _PCI_IO_DEVICE {
 171   UINT32                                    Signature;
 172   EFI_HANDLE                                Handle;
 173   EFI_PCI_IO_PROTOCOL                       PciIo;
 174   LIST_ENTRY                                Link;
 175
 176   EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
 177   EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;
 178   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;
 179   EFI_LOAD_FILE2_PROTOCOL                   LoadFile2;
 180
 181   //
 182   // PCI configuration space header type
 183   //
 184   PCI_TYPE00                                Pci;
 185
 186   //
 187   // Bus number, Device number, Function number
 188   //
 189   UINT8                                     BusNumber;
 190   UINT8                                     DeviceNumber;
 191   UINT8                                     FunctionNumber;
 192
 193   //
 194   // BAR for this PCI Device
 195   //
 196   PCI_BAR                                   PciBar[PCI_MAX_BAR];
 197
 198   //
 199   // The bridge device this pci device is subject to
 200   //
 201   PCI_IO_DEVICE                             *Parent;
 202
 203   //
 204   // A linked list for children Pci Device if it is bridge device
 205   //
 206   LIST_ENTRY                                ChildList;
 207
 208   //
 209   // TRUE if the PCI bus driver creates the handle for this PCI device
 210   //
 211   BOOLEAN                                   Registered;
 212
 213   //
 214   // TRUE if the PCI bus driver successfully allocates the resource required by
 215   // this PCI device
 216   //
 217   BOOLEAN                                   Allocated;
 218
 219   //
 220   // The attribute this PCI device currently set
 221   //
 222   UINT64                                    Attributes;
 223
 224   //
 225   // The attributes this PCI device actually supports
 226   //
 227   UINT64                                    Supports;
 228
 229   //
 230   // The resource decode the bridge supports
 231   //
 232   UINT32                                    Decodes;
 233
 234   //
 235   // TRUE if the ROM image is from the PCI Option ROM BAR
 236   //
 237   BOOLEAN                                   EmbeddedRom;
 238
 239   //
 240   // The OptionRom Size
 241   //
 242   UINT64                                    RomSize;
 243
 244   //
 245   // TRUE if all OpROM (in device or in platform specific position) have been processed
 246   //
 247   BOOLEAN                                   AllOpRomProcessed;
 248
 249   //
 250   // TRUE if there is any EFI driver in the OptionRom
 251   //
 252   BOOLEAN                                   BusOverride;
 253
 254   //
 255   // A list tracking reserved resource on a bridge device
 256   //
 257   LIST_ENTRY                                ReservedResourceList;
 258
 259   //
 260   // A list tracking image handle of platform specific overriding driver
 261   //
 262   LIST_ENTRY                                OptionRomDriverList;
 263
 264   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;
 265   EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;
 266
 267   //
 268   // Bus number ranges for a PCI Root Bridge device
 269   //
 270   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *BusNumberRanges;
 271
 272   BOOLEAN                                   IsPciExp;
 273   //
 274   // For SR-IOV
 275   //
 276   UINT8                                     PciExpressCapabilityOffset;
 277   UINT32                                    AriCapabilityOffset;
 278   UINT32                                    SrIovCapabilityOffset;
 279   UINT32                                    MrIovCapabilityOffset;
 280   PCI_BAR                                   VfPciBar[PCI_MAX_BAR];
 281   UINT32                                    SystemPageSize;
 282   UINT16                                    InitialVFs;
 283   UINT16                                    ReservedBusNum;
 284   //
 285   // Per PCI to PCI Bridge spec, I/O window is 4K aligned,
 286   // but some chipsets support non-standard I/O window alignments less than 4K.
 287   // This field is used to support this case.
 288   //
 289   UINT16                                    BridgeIoAlignment;
 290 };
 291
 292 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
 293   CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
 294
 295 #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
 296   CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
 297
 298 #define PCI_IO_DEVICE_FROM_LINK(a) \
 299   CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
 300
 301 #define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
 302   CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
 303
 304
 305
 306 //
 307 // Global Variables
 308 //
 309 extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport;
 310 extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;
 311 extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;
 312 extern EFI_COMPONENT_NAME2_PROTOCOL                 gPciBusComponentName2;
 313 extern BOOLEAN                                      gFullEnumeration;
 314 extern UINTN                                        gPciHostBridgeNumber;
 315 extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
 316 extern UINT64                                       gAllOne;
 317 extern UINT64                                       gAllZero;
 318 extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;
 319 extern EFI_PCI_OVERRIDE_PROTOCOL                    *gPciOverrideProtocol;
 320 extern BOOLEAN                                      mReserveIsaAliases;
 321 extern BOOLEAN                                      mReserveVgaAliases;
 322
 323 /**
 324   Macro that checks whether device is a GFX device.
 325
 326   @param  _p      Specified device.
 327
 328   @retval TRUE    Device is a GFX device.
 329   @retval FALSE   Device is not a GFX device.
 330
 331 **/
 332 #define IS_PCI_GFX(_p)     IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
 333
 334 /**
 335   Test to see if this driver supports ControllerHandle. Any ControllerHandle
 336   than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.
 337
 338   @param  This                Protocol instance pointer.
 339   @param  Controller          Handle of device to test.
 340   @param  RemainingDevicePath Optional parameter use to pick a specific child
 341                               device to start.
 342
 343   @retval EFI_SUCCESS         This driver supports this device.
 344   @retval EFI_ALREADY_STARTED This driver is already running on this device.
 345   @retval other               This driver does not support this device.
 346
 347 **/
 348 EFI_STATUS
 349 EFIAPI
 350 PciBusDriverBindingSupported (
 351   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 352   IN EFI_HANDLE                     Controller,
 353   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 354   );
 355
 356 /**
 357   Start this driver on ControllerHandle and enumerate Pci bus and start
 358   all device under PCI bus.
 359
 360   @param  This                 Protocol instance pointer.
 361   @param  Controller           Handle of device to bind driver to.
 362   @param  RemainingDevicePath  Optional parameter use to pick a specific child
 363                                device to start.
 364
 365   @retval EFI_SUCCESS          This driver is added to ControllerHandle.
 366   @retval EFI_ALREADY_STARTED  This driver is already running on ControllerHandle.
 367   @retval other                This driver does not support this device.
 368
 369 **/
 370 EFI_STATUS
 371 EFIAPI
 372 PciBusDriverBindingStart (
 373   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 374   IN EFI_HANDLE                     Controller,
 375   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 376   );
 377
 378 /**
 379   Stop this driver on ControllerHandle. Support stopping any child handles
 380   created by this driver.
 381
 382   @param  This              Protocol instance pointer.
 383   @param  Controller        Handle of device to stop driver on.
 384   @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of
 385                             children is zero stop the entire bus driver.
 386   @param  ChildHandleBuffer List of Child Handles to Stop.
 387
 388   @retval EFI_SUCCESS       This driver is removed ControllerHandle.
 389   @retval other             This driver was not removed from this device.
 390
 391 **/
 392 EFI_STATUS
 393 EFIAPI
 394 PciBusDriverBindingStop (
 395   IN  EFI_DRIVER_BINDING_PROTOCOL   *This,
 396   IN  EFI_HANDLE                    Controller,
 397   IN  UINTN                         NumberOfChildren,
 398   IN  EFI_HANDLE                    *ChildHandleBuffer
 399   );
 400
 401 #endif