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Fix the bug that the device claiming too much resource cannot be rejected by the...
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciEnumerator.c
1 /** @file
2 PCI eunmeration implementation on entire PCI bus system for PCI Bus module.
3
4 Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include "PciBus.h"
16
17 /**
18 This routine is used to enumerate entire pci bus system
19 in a given platform.
20
21 @param Controller Parent controller handle.
22
23 @retval EFI_SUCCESS PCI enumeration finished successfully.
24 @retval other Some error occurred when enumerating the pci bus system.
25
26 **/
27 EFI_STATUS
28 PciEnumerator (
29 IN EFI_HANDLE Controller
30 )
31 {
32 EFI_HANDLE Handle;
33 EFI_HANDLE HostBridgeHandle;
34 EFI_STATUS Status;
35 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc;
36 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
37
38 //
39 // If PCI bus has already done the full enumeration, never do it again
40 //
41 if (!gFullEnumeration) {
42 return PciEnumeratorLight (Controller);
43 }
44
45 //
46 // Get the rootbridge Io protocol to find the host bridge handle
47 //
48 Status = gBS->OpenProtocol (
49 Controller,
50 &gEfiPciRootBridgeIoProtocolGuid,
51 (VOID **) &PciRootBridgeIo,
52 gPciBusDriverBinding.DriverBindingHandle,
53 Controller,
54 EFI_OPEN_PROTOCOL_GET_PROTOCOL
55 );
56
57 if (EFI_ERROR (Status)) {
58 return Status;
59 }
60
61 //
62 // Get the host bridge handle
63 //
64 HostBridgeHandle = PciRootBridgeIo->ParentHandle;
65
66 //
67 // Get the pci host bridge resource allocation protocol
68 //
69 Status = gBS->OpenProtocol (
70 HostBridgeHandle,
71 &gEfiPciHostBridgeResourceAllocationProtocolGuid,
72 (VOID **) &PciResAlloc,
73 gPciBusDriverBinding.DriverBindingHandle,
74 Controller,
75 EFI_OPEN_PROTOCOL_GET_PROTOCOL
76 );
77
78 if (EFI_ERROR (Status)) {
79 return Status;
80 }
81
82 //
83 // Notify the pci bus enumeration is about to begin
84 //
85 NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginEnumeration);
86
87 //
88 // Start the bus allocation phase
89 //
90 Status = PciHostBridgeEnumerator (PciResAlloc);
91
92 if (EFI_ERROR (Status)) {
93 return Status;
94 }
95
96 //
97 // Submit the resource request
98 //
99 Status = PciHostBridgeResourceAllocator (PciResAlloc);
100
101 if (EFI_ERROR (Status)) {
102 return Status;
103 }
104
105 //
106 // Notify the pci bus enumeration is about to complete
107 //
108 NotifyPhase (PciResAlloc, EfiPciHostBridgeEndEnumeration);
109
110 //
111 // Process P2C
112 //
113 Status = PciHostBridgeP2CProcess (PciResAlloc);
114
115 if (EFI_ERROR (Status)) {
116 return Status;
117 }
118
119 //
120 // Process attributes for devices on this host bridge
121 //
122 Status = PciHostBridgeDeviceAttribute (PciResAlloc);
123 if (EFI_ERROR (Status)) {
124 return Status;
125 }
126
127 gFullEnumeration = FALSE;
128
129 Handle = NULL;
130 Status = gBS->InstallProtocolInterface (
131 &Handle,
132 &gEfiPciEnumerationCompleteProtocolGuid,
133 EFI_NATIVE_INTERFACE,
134 NULL
135 );
136 if (EFI_ERROR (Status)) {
137 return Status;
138 }
139
140 return EFI_SUCCESS;
141 }
142
143 /**
144 Enumerate PCI root bridge.
145
146 @param PciResAlloc Pointer to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
147 @param RootBridgeDev Instance of root bridge device.
148
149 @retval EFI_SUCCESS Successfully enumerated root bridge.
150 @retval other Failed to enumerate root bridge.
151
152 **/
153 EFI_STATUS
154 PciRootBridgeEnumerator (
155 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
156 IN PCI_IO_DEVICE *RootBridgeDev
157 )
158 {
159 EFI_STATUS Status;
160 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;
161 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration1;
162 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration2;
163 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration3;
164 UINT8 SubBusNumber;
165 UINT8 StartBusNumber;
166 UINT8 PaddedBusRange;
167 EFI_HANDLE RootBridgeHandle;
168 UINT8 Desc;
169 UINT64 AddrLen;
170 UINT64 AddrRangeMin;
171
172 SubBusNumber = 0;
173 StartBusNumber = 0;
174 PaddedBusRange = 0;
175
176 //
177 // Get the root bridge handle
178 //
179 RootBridgeHandle = RootBridgeDev->Handle;
180
181 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
182 EFI_PROGRESS_CODE,
183 EFI_IO_BUS_PCI | EFI_IOB_PCI_BUS_ENUM,
184 RootBridgeDev->DevicePath
185 );
186
187 //
188 // Get the Bus information
189 //
190 Status = PciResAlloc->StartBusEnumeration (
191 PciResAlloc,
192 RootBridgeHandle,
193 (VOID **) &Configuration
194 );
195
196 if (EFI_ERROR (Status)) {
197 return Status;
198 }
199
200 if (Configuration == NULL || Configuration->Desc == ACPI_END_TAG_DESCRIPTOR) {
201 return EFI_INVALID_PARAMETER;
202 }
203 RootBridgeDev->BusNumberRanges = Configuration;
204
205 //
206 // Sort the descriptors in ascending order
207 //
208 for (Configuration1 = Configuration; Configuration1->Desc != ACPI_END_TAG_DESCRIPTOR; Configuration1++) {
209 Configuration2 = Configuration1;
210 for (Configuration3 = Configuration1 + 1; Configuration3->Desc != ACPI_END_TAG_DESCRIPTOR; Configuration3++) {
211 if (Configuration2->AddrRangeMin > Configuration3->AddrRangeMin) {
212 Configuration2 = Configuration3;
213 }
214 }
215 //
216 // All other fields other than AddrRangeMin and AddrLen are ignored in a descriptor,
217 // so only need to swap these two fields.
218 //
219 if (Configuration2 != Configuration1) {
220 AddrRangeMin = Configuration1->AddrRangeMin;
221 Configuration1->AddrRangeMin = Configuration2->AddrRangeMin;
222 Configuration2->AddrRangeMin = AddrRangeMin;
223
224 AddrLen = Configuration1->AddrLen;
225 Configuration1->AddrLen = Configuration2->AddrLen;
226 Configuration2->AddrLen = AddrLen;
227 }
228 }
229
230 //
231 // Get the bus number to start with
232 //
233 StartBusNumber = (UINT8) (Configuration->AddrRangeMin);
234
235 //
236 // Initialize the subordinate bus number
237 //
238 SubBusNumber = StartBusNumber;
239
240 //
241 // Reset all assigned PCI bus number
242 //
243 ResetAllPpbBusNumber (
244 RootBridgeDev,
245 StartBusNumber
246 );
247
248 //
249 // Assign bus number
250 //
251 Status = PciScanBus (
252 RootBridgeDev,
253 StartBusNumber,
254 &SubBusNumber,
255 &PaddedBusRange
256 );
257
258 if (EFI_ERROR (Status)) {
259 return Status;
260 }
261
262
263 //
264 // Assign max bus number scanned
265 //
266
267 Status = PciAllocateBusNumber (RootBridgeDev, SubBusNumber, PaddedBusRange, &SubBusNumber);
268 if (EFI_ERROR (Status)) {
269 return Status;
270 }
271
272 //
273 // Find the bus range which contains the higest bus number, then returns the number of buses
274 // that should be decoded.
275 //
276 while (Configuration->AddrRangeMin + Configuration->AddrLen - 1 < SubBusNumber) {
277 Configuration++;
278 }
279 AddrLen = Configuration->AddrLen;
280 Configuration->AddrLen = SubBusNumber - Configuration->AddrRangeMin + 1;
281
282 //
283 // Save the Desc field of the next descriptor. Mark the next descriptor as an END descriptor.
284 //
285 Configuration++;
286 Desc = Configuration->Desc;
287 Configuration->Desc = ACPI_END_TAG_DESCRIPTOR;
288
289 //
290 // Set bus number
291 //
292 Status = PciResAlloc->SetBusNumbers (
293 PciResAlloc,
294 RootBridgeHandle,
295 RootBridgeDev->BusNumberRanges
296 );
297
298 //
299 // Restore changed fields
300 //
301 Configuration->Desc = Desc;
302 (Configuration - 1)->AddrLen = AddrLen;
303
304 return Status;
305 }
306
307 /**
308 This routine is used to process all PCI devices' Option Rom
309 on a certain root bridge.
310
311 @param Bridge Given parent's root bridge.
312 @param RomBase Base address of ROM driver loaded from.
313 @param MaxLength Maximum rom size.
314
315 **/
316 VOID
317 ProcessOptionRom (
318 IN PCI_IO_DEVICE *Bridge,
319 IN UINT64 RomBase,
320 IN UINT64 MaxLength
321 )
322 {
323 LIST_ENTRY *CurrentLink;
324 PCI_IO_DEVICE *Temp;
325
326 //
327 // Go through bridges to reach all devices
328 //
329 CurrentLink = Bridge->ChildList.ForwardLink;
330 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
331 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
332 if (!IsListEmpty (&Temp->ChildList)) {
333
334 //
335 // Go further to process the option rom under this bridge
336 //
337 ProcessOptionRom (Temp, RomBase, MaxLength);
338 }
339
340 if (Temp->RomSize != 0 && Temp->RomSize <= MaxLength) {
341
342 //
343 // Load and process the option rom
344 //
345 LoadOpRomImage (Temp, RomBase);
346 }
347
348 CurrentLink = CurrentLink->ForwardLink;
349 }
350 }
351
352 /**
353 This routine is used to assign bus number to the given PCI bus system
354
355 @param Bridge Parent root bridge instance.
356 @param StartBusNumber Number of beginning.
357 @param SubBusNumber The number of sub bus.
358
359 @retval EFI_SUCCESS Successfully assigned bus number.
360 @retval EFI_DEVICE_ERROR Failed to assign bus number.
361
362 **/
363 EFI_STATUS
364 PciAssignBusNumber (
365 IN PCI_IO_DEVICE *Bridge,
366 IN UINT8 StartBusNumber,
367 OUT UINT8 *SubBusNumber
368 )
369 {
370 EFI_STATUS Status;
371 PCI_TYPE00 Pci;
372 UINT8 Device;
373 UINT8 Func;
374 UINT64 Address;
375 UINTN SecondBus;
376 UINT16 Register;
377 UINT8 Register8;
378 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
379
380 PciRootBridgeIo = Bridge->PciRootBridgeIo;
381
382 SecondBus = 0;
383 Register = 0;
384
385 *SubBusNumber = StartBusNumber;
386
387 //
388 // First check to see whether the parent is ppb
389 //
390 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
391 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
392
393 //
394 // Check to see whether a pci device is present
395 //
396 Status = PciDevicePresent (
397 PciRootBridgeIo,
398 &Pci,
399 StartBusNumber,
400 Device,
401 Func
402 );
403
404 if (!EFI_ERROR (Status) &&
405 (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci))) {
406
407 //
408 // Reserved one bus for cardbus bridge
409 //
410 Status = PciAllocateBusNumber (Bridge, *SubBusNumber, 1, SubBusNumber);
411 if (EFI_ERROR (Status)) {
412 return Status;
413 }
414 SecondBus = *SubBusNumber;
415
416 Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);
417
418 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);
419
420 Status = PciRootBridgeIo->Pci.Write (
421 PciRootBridgeIo,
422 EfiPciWidthUint16,
423 Address,
424 1,
425 &Register
426 );
427
428 //
429 // Initialize SubBusNumber to SecondBus
430 //
431 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);
432 Status = PciRootBridgeIo->Pci.Write (
433 PciRootBridgeIo,
434 EfiPciWidthUint8,
435 Address,
436 1,
437 SubBusNumber
438 );
439 //
440 // If it is PPB, resursively search down this bridge
441 //
442 if (IS_PCI_BRIDGE (&Pci)) {
443
444 Register8 = 0xFF;
445 Status = PciRootBridgeIo->Pci.Write (
446 PciRootBridgeIo,
447 EfiPciWidthUint8,
448 Address,
449 1,
450 &Register8
451 );
452
453 Status = PciAssignBusNumber (
454 Bridge,
455 (UINT8) (SecondBus),
456 SubBusNumber
457 );
458
459 if (EFI_ERROR (Status)) {
460 return EFI_DEVICE_ERROR;
461 }
462 }
463
464 //
465 // Set the current maximum bus number under the PPB
466 //
467 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);
468
469 Status = PciRootBridgeIo->Pci.Write (
470 PciRootBridgeIo,
471 EfiPciWidthUint8,
472 Address,
473 1,
474 SubBusNumber
475 );
476
477 }
478
479 if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
480
481 //
482 // Skip sub functions, this is not a multi function device
483 //
484 Func = PCI_MAX_FUNC;
485 }
486 }
487 }
488
489 return EFI_SUCCESS;
490 }
491
492 /**
493 This routine is used to determine the root bridge attribute by interfacing
494 the host bridge resource allocation protocol.
495
496 @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
497 @param RootBridgeDev Root bridge instance
498
499 @retval EFI_SUCCESS Successfully got root bridge's attribute.
500 @retval other Failed to get attribute.
501
502 **/
503 EFI_STATUS
504 DetermineRootBridgeAttributes (
505 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
506 IN PCI_IO_DEVICE *RootBridgeDev
507 )
508 {
509 UINT64 Attributes;
510 EFI_STATUS Status;
511 EFI_HANDLE RootBridgeHandle;
512
513 Attributes = 0;
514 RootBridgeHandle = RootBridgeDev->Handle;
515
516 //
517 // Get root bridge attribute by calling into pci host bridge resource allocation protocol
518 //
519 Status = PciResAlloc->GetAllocAttributes (
520 PciResAlloc,
521 RootBridgeHandle,
522 &Attributes
523 );
524
525 if (EFI_ERROR (Status)) {
526 return Status;
527 }
528
529 //
530 // Here is the point where PCI bus driver calls HOST bridge allocation protocol
531 // Currently we hardcoded for ea815
532 //
533 if ((Attributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) {
534 RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED;
535 }
536
537 if ((Attributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0) {
538 RootBridgeDev->Decodes |= EFI_BRIDGE_MEM64_DECODE_SUPPORTED;
539 RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED;
540 }
541
542 RootBridgeDev->Decodes |= EFI_BRIDGE_MEM32_DECODE_SUPPORTED;
543 RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED;
544 RootBridgeDev->Decodes |= EFI_BRIDGE_IO16_DECODE_SUPPORTED;
545
546 return EFI_SUCCESS;
547 }
548
549 /**
550 Get Max Option Rom size on specified bridge.
551
552 @param Bridge Given bridge device instance.
553
554 @return Max size of option rom needed.
555
556 **/
557 UINT64
558 GetMaxOptionRomSize (
559 IN PCI_IO_DEVICE *Bridge
560 )
561 {
562 LIST_ENTRY *CurrentLink;
563 PCI_IO_DEVICE *Temp;
564 UINT64 MaxOptionRomSize;
565 UINT64 TempOptionRomSize;
566
567 MaxOptionRomSize = 0;
568
569 //
570 // Go through bridges to reach all devices
571 //
572 CurrentLink = Bridge->ChildList.ForwardLink;
573 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
574 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
575 if (!IsListEmpty (&Temp->ChildList)) {
576
577 //
578 // Get max option rom size under this bridge
579 //
580 TempOptionRomSize = GetMaxOptionRomSize (Temp);
581
582 //
583 // Compare with the option rom size of the bridge
584 // Get the larger one
585 //
586 if (Temp->RomSize > TempOptionRomSize) {
587 TempOptionRomSize = Temp->RomSize;
588 }
589
590 } else {
591
592 //
593 // For devices get the rom size directly
594 //
595 TempOptionRomSize = Temp->RomSize;
596 }
597
598 //
599 // Get the largest rom size on this bridge
600 //
601 if (TempOptionRomSize > MaxOptionRomSize) {
602 MaxOptionRomSize = TempOptionRomSize;
603 }
604
605 CurrentLink = CurrentLink->ForwardLink;
606 }
607
608 return MaxOptionRomSize;
609 }
610
611 /**
612 Process attributes of devices on this host bridge
613
614 @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
615
616 @retval EFI_SUCCESS Successfully process attribute.
617 @retval EFI_NOT_FOUND Can not find the specific root bridge device.
618 @retval other Failed to determine the root bridge device's attribute.
619
620 **/
621 EFI_STATUS
622 PciHostBridgeDeviceAttribute (
623 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
624 )
625 {
626 EFI_HANDLE RootBridgeHandle;
627 PCI_IO_DEVICE *RootBridgeDev;
628 EFI_STATUS Status;
629
630 RootBridgeHandle = NULL;
631
632 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
633
634 //
635 // Get RootBridg Device by handle
636 //
637 RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);
638
639 if (RootBridgeDev == NULL) {
640 return EFI_NOT_FOUND;
641 }
642
643 //
644 // Set the attributes for devcies behind the Root Bridge
645 //
646 Status = DetermineDeviceAttribute (RootBridgeDev);
647 if (EFI_ERROR (Status)) {
648 return Status;
649 }
650
651 }
652
653 return EFI_SUCCESS;
654 }
655
656 /**
657 Get resource allocation status from the ACPI resource descriptor.
658
659 @param AcpiConfig Point to Acpi configuration table.
660 @param IoResStatus Return the status of I/O resource.
661 @param Mem32ResStatus Return the status of 32-bit Memory resource.
662 @param PMem32ResStatus Return the status of 32-bit Prefetchable Memory resource.
663 @param Mem64ResStatus Return the status of 64-bit Memory resource.
664 @param PMem64ResStatus Return the status of 64-bit Prefetchable Memory resource.
665
666 **/
667 VOID
668 GetResourceAllocationStatus (
669 VOID *AcpiConfig,
670 OUT UINT64 *IoResStatus,
671 OUT UINT64 *Mem32ResStatus,
672 OUT UINT64 *PMem32ResStatus,
673 OUT UINT64 *Mem64ResStatus,
674 OUT UINT64 *PMem64ResStatus
675 )
676 {
677 UINT8 *Temp;
678 UINT64 ResStatus;
679 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ACPIAddressDesc;
680
681 Temp = (UINT8 *) AcpiConfig;
682
683 while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
684
685 ACPIAddressDesc = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;
686 ResStatus = ACPIAddressDesc->AddrTranslationOffset;
687
688 switch (ACPIAddressDesc->ResType) {
689 case 0:
690 if (ACPIAddressDesc->AddrSpaceGranularity == 32) {
691 if (ACPIAddressDesc->SpecificFlag == 0x06) {
692 //
693 // Pmem32
694 //
695 *PMem32ResStatus = ResStatus;
696 } else {
697 //
698 // Mem32
699 //
700 *Mem32ResStatus = ResStatus;
701 }
702 }
703
704 if (ACPIAddressDesc->AddrSpaceGranularity == 64) {
705 if (ACPIAddressDesc->SpecificFlag == 0x06) {
706 //
707 // PMem64
708 //
709 *PMem64ResStatus = ResStatus;
710 } else {
711 //
712 // Mem64
713 //
714 *Mem64ResStatus = ResStatus;
715 }
716 }
717
718 break;
719
720 case 1:
721 //
722 // Io
723 //
724 *IoResStatus = ResStatus;
725 break;
726
727 default:
728 break;
729 }
730
731 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
732 }
733 }
734
735 /**
736 Remove a PCI device from device pool and mark its bar.
737
738 @param PciDevice Instance of Pci device.
739
740 @retval EFI_SUCCESS Successfully remove the PCI device.
741 @retval EFI_ABORTED Pci device is a root bridge or a PCI-PCI bridge.
742
743 **/
744 EFI_STATUS
745 RejectPciDevice (
746 IN PCI_IO_DEVICE *PciDevice
747 )
748 {
749 PCI_IO_DEVICE *Bridge;
750 PCI_IO_DEVICE *Temp;
751 LIST_ENTRY *CurrentLink;
752
753 //
754 // Remove the padding resource from a bridge
755 //
756 if ( IS_PCI_BRIDGE(&PciDevice->Pci) &&
757 PciDevice->ResourcePaddingDescriptors != NULL ) {
758 FreePool (PciDevice->ResourcePaddingDescriptors);
759 PciDevice->ResourcePaddingDescriptors = NULL;
760 return EFI_SUCCESS;
761 }
762
763 //
764 // Skip RB and PPB
765 //
766 if (IS_PCI_BRIDGE (&PciDevice->Pci) || (PciDevice->Parent == NULL)) {
767 return EFI_ABORTED;
768 }
769
770 if (IS_CARDBUS_BRIDGE (&PciDevice->Pci)) {
771 //
772 // Get the root bridge device
773 //
774 Bridge = PciDevice;
775 while (Bridge->Parent != NULL) {
776 Bridge = Bridge->Parent;
777 }
778
779 RemoveAllPciDeviceOnBridge (Bridge->Handle, PciDevice);
780
781 //
782 // Mark its bar
783 //
784 InitializeP2C (PciDevice);
785 }
786
787 //
788 // Remove the device
789 //
790 Bridge = PciDevice->Parent;
791 CurrentLink = Bridge->ChildList.ForwardLink;
792 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
793 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
794 if (Temp == PciDevice) {
795 InitializePciDevice (Temp);
796 RemoveEntryList (CurrentLink);
797 FreePciDevice (Temp);
798 return EFI_SUCCESS;
799 }
800
801 CurrentLink = CurrentLink->ForwardLink;
802 }
803
804 return EFI_ABORTED;
805 }
806
807 /**
808 Determine whethter a PCI device can be rejected.
809
810 @param PciResNode Pointer to Pci resource node instance.
811
812 @retval TRUE The PCI device can be rejected.
813 @retval TRUE The PCI device cannot be rejected.
814
815 **/
816 BOOLEAN
817 IsRejectiveDevice (
818 IN PCI_RESOURCE_NODE *PciResNode
819 )
820 {
821 PCI_IO_DEVICE *Temp;
822
823 Temp = PciResNode->PciDev;
824
825 //
826 // Ensure the device is present
827 //
828 if (Temp == NULL) {
829 return FALSE;
830 }
831
832 //
833 // PPB and RB should go ahead
834 //
835 if (IS_PCI_BRIDGE (&Temp->Pci) || (Temp->Parent == NULL)) {
836 return TRUE;
837 }
838
839 //
840 // Skip device on Bus0
841 //
842 if ((Temp->Parent != NULL) && (Temp->BusNumber == 0)) {
843 return FALSE;
844 }
845
846 //
847 // Skip VGA
848 //
849 if (IS_PCI_VGA (&Temp->Pci)) {
850 return FALSE;
851 }
852
853 return TRUE;
854 }
855
856 /**
857 Compare two resource nodes and get the larger resource consumer.
858
859 @param PciResNode1 resource node 1 want to be compared
860 @param PciResNode2 resource node 2 want to be compared
861
862 @return Larger resource node.
863
864 **/
865 PCI_RESOURCE_NODE *
866 GetLargerConsumerDevice (
867 IN PCI_RESOURCE_NODE *PciResNode1,
868 IN PCI_RESOURCE_NODE *PciResNode2
869 )
870 {
871 if (PciResNode2 == NULL) {
872 return PciResNode1;
873 }
874
875 if ((IS_PCI_BRIDGE(&(PciResNode2->PciDev->Pci)) || (PciResNode2->PciDev->Parent == NULL)) \
876 && (PciResNode2->ResourceUsage != PciResUsagePadding) )
877 {
878 return PciResNode1;
879 }
880
881 if (PciResNode1 == NULL) {
882 return PciResNode2;
883 }
884
885 if ((PciResNode1->Length) > (PciResNode2->Length)) {
886 return PciResNode1;
887 }
888
889 return PciResNode2;
890 }
891
892
893 /**
894 Get the max resource consumer in the host resource pool.
895
896 @param ResPool Pointer to resource pool node.
897
898 @return The max resource consumer in the host resource pool.
899
900 **/
901 PCI_RESOURCE_NODE *
902 GetMaxResourceConsumerDevice (
903 IN PCI_RESOURCE_NODE *ResPool
904 )
905 {
906 PCI_RESOURCE_NODE *Temp;
907 LIST_ENTRY *CurrentLink;
908 PCI_RESOURCE_NODE *PciResNode;
909 PCI_RESOURCE_NODE *PPBResNode;
910
911 PciResNode = NULL;
912
913 CurrentLink = ResPool->ChildList.ForwardLink;
914 while (CurrentLink != NULL && CurrentLink != &ResPool->ChildList) {
915
916 Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
917
918 if (!IsRejectiveDevice (Temp)) {
919 CurrentLink = CurrentLink->ForwardLink;
920 continue;
921 }
922
923 if ((IS_PCI_BRIDGE (&(Temp->PciDev->Pci)) || (Temp->PciDev->Parent == NULL)) \
924 && (Temp->ResourceUsage != PciResUsagePadding))
925 {
926 PPBResNode = GetMaxResourceConsumerDevice (Temp);
927 PciResNode = GetLargerConsumerDevice (PciResNode, PPBResNode);
928 } else {
929 PciResNode = GetLargerConsumerDevice (PciResNode, Temp);
930 }
931
932 CurrentLink = CurrentLink->ForwardLink;
933 }
934
935 return PciResNode;
936 }
937
938 /**
939 Adjust host bridge allocation so as to reduce resource requirement
940
941 @param IoPool Pointer to instance of I/O resource Node.
942 @param Mem32Pool Pointer to instance of 32-bit memory resource Node.
943 @param PMem32Pool Pointer to instance of 32-bit Prefetchable memory resource node.
944 @param Mem64Pool Pointer to instance of 64-bit memory resource node.
945 @param PMem64Pool Pointer to instance of 64-bit Prefetchable memory resource node.
946 @param IoResStatus Status of I/O resource Node.
947 @param Mem32ResStatus Status of 32-bit memory resource Node.
948 @param PMem32ResStatus Status of 32-bit Prefetchable memory resource node.
949 @param Mem64ResStatus Status of 64-bit memory resource node.
950 @param PMem64ResStatus Status of 64-bit Prefetchable memory resource node.
951
952 @retval EFI_SUCCESS Successfully adjusted resoruce on host bridge.
953 @retval EFI_ABORTED Host bridge hasn't this resource type or no resource be adjusted.
954
955 **/
956 EFI_STATUS
957 PciHostBridgeAdjustAllocation (
958 IN PCI_RESOURCE_NODE *IoPool,
959 IN PCI_RESOURCE_NODE *Mem32Pool,
960 IN PCI_RESOURCE_NODE *PMem32Pool,
961 IN PCI_RESOURCE_NODE *Mem64Pool,
962 IN PCI_RESOURCE_NODE *PMem64Pool,
963 IN UINT64 IoResStatus,
964 IN UINT64 Mem32ResStatus,
965 IN UINT64 PMem32ResStatus,
966 IN UINT64 Mem64ResStatus,
967 IN UINT64 PMem64ResStatus
968 )
969 {
970 BOOLEAN AllocationAjusted;
971 PCI_RESOURCE_NODE *PciResNode;
972 PCI_RESOURCE_NODE *ResPool[5];
973 PCI_IO_DEVICE *RemovedPciDev[5];
974 UINT64 ResStatus[5];
975 UINTN RemovedPciDevNum;
976 UINTN DevIndex;
977 UINTN ResType;
978 EFI_STATUS Status;
979 EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData;
980
981 PciResNode = NULL;
982 ZeroMem (RemovedPciDev, 5 * sizeof (PCI_IO_DEVICE *));
983 RemovedPciDevNum = 0;
984
985 ResPool[0] = IoPool;
986 ResPool[1] = Mem32Pool;
987 ResPool[2] = PMem32Pool;
988 ResPool[3] = Mem64Pool;
989 ResPool[4] = PMem64Pool;
990
991 ResStatus[0] = IoResStatus;
992 ResStatus[1] = Mem32ResStatus;
993 ResStatus[2] = PMem32ResStatus;
994 ResStatus[3] = Mem64ResStatus;
995 ResStatus[4] = PMem64ResStatus;
996
997 AllocationAjusted = FALSE;
998
999 for (ResType = 0; ResType < 5; ResType++) {
1000
1001 if (ResStatus[ResType] == EFI_RESOURCE_SATISFIED) {
1002 continue;
1003 }
1004
1005 if (ResStatus[ResType] == EFI_RESOURCE_NOT_SATISFIED) {
1006 //
1007 // Host bridge hasn't this resource type
1008 //
1009 return EFI_ABORTED;
1010 }
1011
1012 //
1013 // Hostbridge hasn't enough resource
1014 //
1015 PciResNode = GetMaxResourceConsumerDevice (ResPool[ResType]);
1016 if (PciResNode == NULL) {
1017 continue;
1018 }
1019
1020 //
1021 // Check if the device has been removed before
1022 //
1023 for (DevIndex = 0; DevIndex < RemovedPciDevNum; DevIndex++) {
1024 if (PciResNode->PciDev == RemovedPciDev[DevIndex]) {
1025 break;
1026 }
1027 }
1028
1029 if (DevIndex != RemovedPciDevNum) {
1030 continue;
1031 }
1032
1033 //
1034 // Remove the device if it isn't in the array
1035 //
1036 Status = RejectPciDevice (PciResNode->PciDev);
1037 if (Status == EFI_SUCCESS) {
1038 DEBUG ((
1039 EFI_D_ERROR,
1040 "PciBus: [%02x|%02x|%02x] was rejected due to resource confliction.\n",
1041 PciResNode->PciDev->BusNumber, PciResNode->PciDev->DeviceNumber, PciResNode->PciDev->FunctionNumber
1042 ));
1043
1044 //
1045 // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code
1046 //
1047 //
1048 // Have no way to get ReqRes, AllocRes & Bar here
1049 //
1050 ZeroMem (&AllocFailExtendedData, sizeof (AllocFailExtendedData));
1051 AllocFailExtendedData.DevicePathSize = (UINT16) sizeof (EFI_DEVICE_PATH_PROTOCOL);
1052 AllocFailExtendedData.DevicePath = (UINT8 *) PciResNode->PciDev->DevicePath;
1053 AllocFailExtendedData.Bar = PciResNode->Bar;
1054
1055 REPORT_STATUS_CODE_WITH_EXTENDED_DATA (
1056 EFI_PROGRESS_CODE,
1057 EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT,
1058 (VOID *) &AllocFailExtendedData,
1059 sizeof (AllocFailExtendedData)
1060 );
1061
1062 //
1063 // Add it to the array and indicate at least a device has been rejected
1064 //
1065 RemovedPciDev[RemovedPciDevNum++] = PciResNode->PciDev;
1066 AllocationAjusted = TRUE;
1067 }
1068 }
1069 //
1070 // End for
1071 //
1072
1073 if (AllocationAjusted) {
1074 return EFI_SUCCESS;
1075 } else {
1076 return EFI_ABORTED;
1077 }
1078 }
1079
1080 /**
1081 Summary requests for all resource type, and contruct ACPI resource
1082 requestor instance.
1083
1084 @param Bridge detecting bridge
1085 @param IoNode Pointer to instance of I/O resource Node
1086 @param Mem32Node Pointer to instance of 32-bit memory resource Node
1087 @param PMem32Node Pointer to instance of 32-bit Pmemory resource node
1088 @param Mem64Node Pointer to instance of 64-bit memory resource node
1089 @param PMem64Node Pointer to instance of 64-bit Pmemory resource node
1090 @param Config Output buffer holding new constructed APCI resource requestor
1091
1092 @retval EFI_SUCCESS Successfully constructed ACPI resource.
1093 @retval EFI_OUT_OF_RESOURCES No memory availabe.
1094
1095 **/
1096 EFI_STATUS
1097 ConstructAcpiResourceRequestor (
1098 IN PCI_IO_DEVICE *Bridge,
1099 IN PCI_RESOURCE_NODE *IoNode,
1100 IN PCI_RESOURCE_NODE *Mem32Node,
1101 IN PCI_RESOURCE_NODE *PMem32Node,
1102 IN PCI_RESOURCE_NODE *Mem64Node,
1103 IN PCI_RESOURCE_NODE *PMem64Node,
1104 OUT VOID **Config
1105 )
1106 {
1107 UINT8 NumConfig;
1108 UINT8 Aperture;
1109 UINT8 *Configuration;
1110 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
1111 EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;
1112
1113 NumConfig = 0;
1114 Aperture = 0;
1115
1116 *Config = NULL;
1117
1118 //
1119 // if there is io request, add to the io aperture
1120 //
1121 if (ResourceRequestExisted (IoNode)) {
1122 NumConfig++;
1123 Aperture |= 0x01;
1124 }
1125
1126 //
1127 // if there is mem32 request, add to the mem32 aperture
1128 //
1129 if (ResourceRequestExisted (Mem32Node)) {
1130 NumConfig++;
1131 Aperture |= 0x02;
1132 }
1133
1134 //
1135 // if there is pmem32 request, add to the pmem32 aperture
1136 //
1137 if (ResourceRequestExisted (PMem32Node)) {
1138 NumConfig++;
1139 Aperture |= 0x04;
1140 }
1141
1142 //
1143 // if there is mem64 request, add to the mem64 aperture
1144 //
1145 if (ResourceRequestExisted (Mem64Node)) {
1146 NumConfig++;
1147 Aperture |= 0x08;
1148 }
1149
1150 //
1151 // if there is pmem64 request, add to the pmem64 aperture
1152 //
1153 if (ResourceRequestExisted (PMem64Node)) {
1154 NumConfig++;
1155 Aperture |= 0x10;
1156 }
1157
1158 if (NumConfig != 0) {
1159
1160 //
1161 // If there is at least one type of resource request,
1162 // allocate a acpi resource node
1163 //
1164 Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
1165 if (Configuration == NULL) {
1166 return EFI_OUT_OF_RESOURCES;
1167 }
1168
1169 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
1170
1171 //
1172 // Deal with io aperture
1173 //
1174 if ((Aperture & 0x01) != 0) {
1175 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1176 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
1177 //
1178 // Io
1179 //
1180 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
1181 //
1182 // non ISA range
1183 //
1184 Ptr->SpecificFlag = 1;
1185 Ptr->AddrLen = IoNode->Length;
1186 Ptr->AddrRangeMax = IoNode->Alignment;
1187
1188 Ptr++;
1189 }
1190 //
1191 // Deal with mem32 aperture
1192 //
1193 if ((Aperture & 0x02) != 0) {
1194 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1195 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
1196 //
1197 // Mem
1198 //
1199 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1200 //
1201 // Nonprefechable
1202 //
1203 Ptr->SpecificFlag = 0;
1204 //
1205 // 32 bit
1206 //
1207 Ptr->AddrSpaceGranularity = 32;
1208 Ptr->AddrLen = Mem32Node->Length;
1209 Ptr->AddrRangeMax = Mem32Node->Alignment;
1210
1211 Ptr++;
1212 }
1213
1214 //
1215 // Deal with Pmem32 aperture
1216 //
1217 if ((Aperture & 0x04) != 0) {
1218 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1219 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
1220 //
1221 // Mem
1222 //
1223 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1224 //
1225 // prefechable
1226 //
1227 Ptr->SpecificFlag = 0x6;
1228 //
1229 // 32 bit
1230 //
1231 Ptr->AddrSpaceGranularity = 32;
1232 Ptr->AddrLen = PMem32Node->Length;
1233 Ptr->AddrRangeMax = PMem32Node->Alignment;
1234
1235 Ptr++;
1236 }
1237 //
1238 // Deal with mem64 aperture
1239 //
1240 if ((Aperture & 0x08) != 0) {
1241 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1242 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
1243 //
1244 // Mem
1245 //
1246 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1247 //
1248 // nonprefechable
1249 //
1250 Ptr->SpecificFlag = 0;
1251 //
1252 // 64 bit
1253 //
1254 Ptr->AddrSpaceGranularity = 64;
1255 Ptr->AddrLen = Mem64Node->Length;
1256 Ptr->AddrRangeMax = Mem64Node->Alignment;
1257
1258 Ptr++;
1259 }
1260 //
1261 // Deal with Pmem64 aperture
1262 //
1263 if ((Aperture & 0x10) != 0) {
1264 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1265 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
1266 //
1267 // Mem
1268 //
1269 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1270 //
1271 // prefechable
1272 //
1273 Ptr->SpecificFlag = 0x06;
1274 //
1275 // 64 bit
1276 //
1277 Ptr->AddrSpaceGranularity = 64;
1278 Ptr->AddrLen = PMem64Node->Length;
1279 Ptr->AddrRangeMax = PMem64Node->Alignment;
1280
1281 Ptr++;
1282 }
1283
1284 //
1285 // put the checksum
1286 //
1287 PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) Ptr;
1288
1289 PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;
1290 PtrEnd->Checksum = 0;
1291
1292 } else {
1293
1294 //
1295 // If there is no resource request
1296 //
1297 Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
1298 if (Configuration == NULL) {
1299 return EFI_OUT_OF_RESOURCES;
1300 }
1301
1302 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (Configuration);
1303 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1304
1305 PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Ptr + 1);
1306 PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;
1307 PtrEnd->Checksum = 0;
1308 }
1309
1310 *Config = Configuration;
1311
1312 return EFI_SUCCESS;
1313 }
1314
1315 /**
1316 Get resource base from an acpi configuration descriptor.
1317
1318 @param Config An acpi configuration descriptor.
1319 @param IoBase Output of I/O resource base address.
1320 @param Mem32Base Output of 32-bit memory base address.
1321 @param PMem32Base Output of 32-bit prefetchable memory base address.
1322 @param Mem64Base Output of 64-bit memory base address.
1323 @param PMem64Base Output of 64-bit prefetchable memory base address.
1324
1325 **/
1326 VOID
1327 GetResourceBase (
1328 IN VOID *Config,
1329 OUT UINT64 *IoBase,
1330 OUT UINT64 *Mem32Base,
1331 OUT UINT64 *PMem32Base,
1332 OUT UINT64 *Mem64Base,
1333 OUT UINT64 *PMem64Base
1334 )
1335 {
1336 UINT8 *Temp;
1337 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
1338 UINT64 ResStatus;
1339
1340 ASSERT (Config != NULL);
1341
1342 *IoBase = 0xFFFFFFFFFFFFFFFFULL;
1343 *Mem32Base = 0xFFFFFFFFFFFFFFFFULL;
1344 *PMem32Base = 0xFFFFFFFFFFFFFFFFULL;
1345 *Mem64Base = 0xFFFFFFFFFFFFFFFFULL;
1346 *PMem64Base = 0xFFFFFFFFFFFFFFFFULL;
1347
1348 Temp = (UINT8 *) Config;
1349
1350 while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
1351
1352 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;
1353 ResStatus = Ptr->AddrTranslationOffset;
1354
1355 if (ResStatus == EFI_RESOURCE_SATISFIED) {
1356
1357 switch (Ptr->ResType) {
1358
1359 //
1360 // Memory type aperture
1361 //
1362 case 0:
1363
1364 //
1365 // Check to see the granularity
1366 //
1367 if (Ptr->AddrSpaceGranularity == 32) {
1368 if ((Ptr->SpecificFlag & 0x06) != 0) {
1369 *PMem32Base = Ptr->AddrRangeMin;
1370 } else {
1371 *Mem32Base = Ptr->AddrRangeMin;
1372 }
1373 }
1374
1375 if (Ptr->AddrSpaceGranularity == 64) {
1376 if ((Ptr->SpecificFlag & 0x06) != 0) {
1377 *PMem64Base = Ptr->AddrRangeMin;
1378 } else {
1379 *Mem64Base = Ptr->AddrRangeMin;
1380 }
1381 }
1382 break;
1383
1384 case 1:
1385
1386 //
1387 // Io type aperture
1388 //
1389 *IoBase = Ptr->AddrRangeMin;
1390 break;
1391
1392 default:
1393 break;
1394
1395 }
1396 //
1397 // End switch
1398 //
1399 }
1400 //
1401 // End for
1402 //
1403 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
1404 }
1405 }
1406
1407 /**
1408 Enumerate pci bridge, allocate resource and determine attribute
1409 for devices on this bridge.
1410
1411 @param BridgeDev Pointer to instance of bridge device.
1412
1413 @retval EFI_SUCCESS Successfully enumerated PCI bridge.
1414 @retval other Failed to enumerate.
1415
1416 **/
1417 EFI_STATUS
1418 PciBridgeEnumerator (
1419 IN PCI_IO_DEVICE *BridgeDev
1420 )
1421 {
1422 UINT8 SubBusNumber;
1423 UINT8 StartBusNumber;
1424 EFI_PCI_IO_PROTOCOL *PciIo;
1425 EFI_STATUS Status;
1426
1427 SubBusNumber = 0;
1428 StartBusNumber = 0;
1429 PciIo = &(BridgeDev->PciIo);
1430 Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);
1431
1432 if (EFI_ERROR (Status)) {
1433 return Status;
1434 }
1435
1436 Status = PciAssignBusNumber (
1437 BridgeDev,
1438 StartBusNumber,
1439 &SubBusNumber
1440 );
1441
1442 if (EFI_ERROR (Status)) {
1443 return Status;
1444 }
1445
1446 Status = PciPciDeviceInfoCollector (BridgeDev, StartBusNumber);
1447
1448 if (EFI_ERROR (Status)) {
1449 return Status;
1450 }
1451
1452 Status = PciBridgeResourceAllocator (BridgeDev);
1453
1454 if (EFI_ERROR (Status)) {
1455 return Status;
1456 }
1457
1458 Status = DetermineDeviceAttribute (BridgeDev);
1459
1460 if (EFI_ERROR (Status)) {
1461 return Status;
1462 }
1463
1464 return EFI_SUCCESS;
1465
1466 }
1467
1468 /**
1469 Allocate all kinds of resource for PCI bridge.
1470
1471 @param Bridge Pointer to bridge instance.
1472
1473 @retval EFI_SUCCESS Successfully allocated resource for PCI bridge.
1474 @retval other Failed to allocate resource for bridge.
1475
1476 **/
1477 EFI_STATUS
1478 PciBridgeResourceAllocator (
1479 IN PCI_IO_DEVICE *Bridge
1480 )
1481 {
1482 PCI_RESOURCE_NODE *IoBridge;
1483 PCI_RESOURCE_NODE *Mem32Bridge;
1484 PCI_RESOURCE_NODE *PMem32Bridge;
1485 PCI_RESOURCE_NODE *Mem64Bridge;
1486 PCI_RESOURCE_NODE *PMem64Bridge;
1487 UINT64 IoBase;
1488 UINT64 Mem32Base;
1489 UINT64 PMem32Base;
1490 UINT64 Mem64Base;
1491 UINT64 PMem64Base;
1492 EFI_STATUS Status;
1493
1494 IoBridge = CreateResourceNode (
1495 Bridge,
1496 0,
1497 Bridge->BridgeIoAlignment,
1498 0,
1499 PciBarTypeIo16,
1500 PciResUsageTypical
1501 );
1502
1503 Mem32Bridge = CreateResourceNode (
1504 Bridge,
1505 0,
1506 0xFFFFF,
1507 0,
1508 PciBarTypeMem32,
1509 PciResUsageTypical
1510 );
1511
1512 PMem32Bridge = CreateResourceNode (
1513 Bridge,
1514 0,
1515 0xFFFFF,
1516 0,
1517 PciBarTypePMem32,
1518 PciResUsageTypical
1519 );
1520
1521 Mem64Bridge = CreateResourceNode (
1522 Bridge,
1523 0,
1524 0xFFFFF,
1525 0,
1526 PciBarTypeMem64,
1527 PciResUsageTypical
1528 );
1529
1530 PMem64Bridge = CreateResourceNode (
1531 Bridge,
1532 0,
1533 0xFFFFF,
1534 0,
1535 PciBarTypePMem64,
1536 PciResUsageTypical
1537 );
1538
1539 //
1540 // Create resourcemap by going through all the devices subject to this root bridge
1541 //
1542 CreateResourceMap (
1543 Bridge,
1544 IoBridge,
1545 Mem32Bridge,
1546 PMem32Bridge,
1547 Mem64Bridge,
1548 PMem64Bridge
1549 );
1550
1551 Status = GetResourceBaseFromBridge (
1552 Bridge,
1553 &IoBase,
1554 &Mem32Base,
1555 &PMem32Base,
1556 &Mem64Base,
1557 &PMem64Base
1558 );
1559
1560 if (EFI_ERROR (Status)) {
1561 return Status;
1562 }
1563
1564 //
1565 // Program IO resources
1566 //
1567 ProgramResource (
1568 IoBase,
1569 IoBridge
1570 );
1571
1572 //
1573 // Program Mem32 resources
1574 //
1575 ProgramResource (
1576 Mem32Base,
1577 Mem32Bridge
1578 );
1579
1580 //
1581 // Program PMem32 resources
1582 //
1583 ProgramResource (
1584 PMem32Base,
1585 PMem32Bridge
1586 );
1587
1588 //
1589 // Program Mem64 resources
1590 //
1591 ProgramResource (
1592 Mem64Base,
1593 Mem64Bridge
1594 );
1595
1596 //
1597 // Program PMem64 resources
1598 //
1599 ProgramResource (
1600 PMem64Base,
1601 PMem64Bridge
1602 );
1603
1604 DestroyResourceTree (IoBridge);
1605 DestroyResourceTree (Mem32Bridge);
1606 DestroyResourceTree (PMem32Bridge);
1607 DestroyResourceTree (PMem64Bridge);
1608 DestroyResourceTree (Mem64Bridge);
1609
1610 gBS->FreePool (IoBridge);
1611 gBS->FreePool (Mem32Bridge);
1612 gBS->FreePool (PMem32Bridge);
1613 gBS->FreePool (PMem64Bridge);
1614 gBS->FreePool (Mem64Bridge);
1615
1616 return EFI_SUCCESS;
1617 }
1618
1619 /**
1620 Get resource base address for a pci bridge device.
1621
1622 @param Bridge Given Pci driver instance.
1623 @param IoBase Output for base address of I/O type resource.
1624 @param Mem32Base Output for base address of 32-bit memory type resource.
1625 @param PMem32Base Ooutput for base address of 32-bit Pmemory type resource.
1626 @param Mem64Base Output for base address of 64-bit memory type resource.
1627 @param PMem64Base Output for base address of 64-bit Pmemory type resource.
1628
1629 @retval EFI_SUCCESS Successfully got resource base address.
1630 @retval EFI_OUT_OF_RESOURCES PCI bridge is not available.
1631
1632 **/
1633 EFI_STATUS
1634 GetResourceBaseFromBridge (
1635 IN PCI_IO_DEVICE *Bridge,
1636 OUT UINT64 *IoBase,
1637 OUT UINT64 *Mem32Base,
1638 OUT UINT64 *PMem32Base,
1639 OUT UINT64 *Mem64Base,
1640 OUT UINT64 *PMem64Base
1641 )
1642 {
1643 if (!Bridge->Allocated) {
1644 return EFI_OUT_OF_RESOURCES;
1645 }
1646
1647 *IoBase = gAllOne;
1648 *Mem32Base = gAllOne;
1649 *PMem32Base = gAllOne;
1650 *Mem64Base = gAllOne;
1651 *PMem64Base = gAllOne;
1652
1653 if (IS_PCI_BRIDGE (&Bridge->Pci)) {
1654
1655 if (Bridge->PciBar[PPB_IO_RANGE].Length > 0) {
1656 *IoBase = Bridge->PciBar[PPB_IO_RANGE].BaseAddress;
1657 }
1658
1659 if (Bridge->PciBar[PPB_MEM32_RANGE].Length > 0) {
1660 *Mem32Base = Bridge->PciBar[PPB_MEM32_RANGE].BaseAddress;
1661 }
1662
1663 if (Bridge->PciBar[PPB_PMEM32_RANGE].Length > 0) {
1664 *PMem32Base = Bridge->PciBar[PPB_PMEM32_RANGE].BaseAddress;
1665 }
1666
1667 if (Bridge->PciBar[PPB_PMEM64_RANGE].Length > 0) {
1668 *PMem64Base = Bridge->PciBar[PPB_PMEM64_RANGE].BaseAddress;
1669 } else {
1670 *PMem64Base = gAllOne;
1671 }
1672
1673 }
1674
1675 if (IS_CARDBUS_BRIDGE (&Bridge->Pci)) {
1676 if (Bridge->PciBar[P2C_IO_1].Length > 0) {
1677 *IoBase = Bridge->PciBar[P2C_IO_1].BaseAddress;
1678 } else {
1679 if (Bridge->PciBar[P2C_IO_2].Length > 0) {
1680 *IoBase = Bridge->PciBar[P2C_IO_2].BaseAddress;
1681 }
1682 }
1683
1684 if (Bridge->PciBar[P2C_MEM_1].Length > 0) {
1685 if (Bridge->PciBar[P2C_MEM_1].BarType == PciBarTypePMem32) {
1686 *PMem32Base = Bridge->PciBar[P2C_MEM_1].BaseAddress;
1687 }
1688
1689 if (Bridge->PciBar[P2C_MEM_1].BarType == PciBarTypeMem32) {
1690 *Mem32Base = Bridge->PciBar[P2C_MEM_1].BaseAddress;
1691 }
1692 }
1693
1694 if (Bridge->PciBar[P2C_MEM_2].Length > 0) {
1695 if (Bridge->PciBar[P2C_MEM_2].BarType == PciBarTypePMem32) {
1696 *PMem32Base = Bridge->PciBar[P2C_MEM_2].BaseAddress;
1697 }
1698
1699 if (Bridge->PciBar[P2C_MEM_2].BarType == PciBarTypeMem32) {
1700 *Mem32Base = Bridge->PciBar[P2C_MEM_2].BaseAddress;
1701 }
1702 }
1703 }
1704
1705 return EFI_SUCCESS;
1706 }
1707
1708 /**
1709 These are the notifications from the PCI bus driver that it is about to enter a certain
1710 phase of the PCI enumeration process.
1711
1712 This member function can be used to notify the host bridge driver to perform specific actions,
1713 including any chipset-specific initialization, so that the chipset is ready to enter the next phase.
1714 Eight notification points are defined at this time. See belows:
1715 EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data
1716 structures. The PCI enumerator should issue this notification
1717 before starting a fresh enumeration process. Enumeration cannot
1718 be restarted after sending any other notification such as
1719 EfiPciHostBridgeBeginBusAllocation.
1720 EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is
1721 required here. This notification can be used to perform any
1722 chipset-specific programming.
1723 EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No
1724 specific action is required here. This notification can be used to
1725 perform any chipset-specific programming.
1726 EfiPciHostBridgeBeginResourceAllocation
1727 The resource allocation phase is about to begin. No specific
1728 action is required here. This notification can be used to perform
1729 any chipset-specific programming.
1730 EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI
1731 root bridges. These resource settings are returned on the next call to
1732 GetProposedResources(). Before calling NotifyPhase() with a Phase of
1733 EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible
1734 for gathering I/O and memory requests for
1735 all the PCI root bridges and submitting these requests using
1736 SubmitResources(). This function pads the resource amount
1737 to suit the root bridge hardware, takes care of dependencies between
1738 the PCI root bridges, and calls the Global Coherency Domain (GCD)
1739 with the allocation request. In the case of padding, the allocated range
1740 could be bigger than what was requested.
1741 EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated
1742 resources (proposed resources) for all the PCI root bridges. After the
1743 hardware is programmed, reassigning resources will not be supported.
1744 The bus settings are not affected.
1745 EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI
1746 root bridges and resets the I/O and memory apertures to their initial
1747 state. The bus settings are not affected. If the request to allocate
1748 resources fails, the PCI enumerator can use this notification to
1749 deallocate previous resources, adjust the requests, and retry
1750 allocation.
1751 EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is
1752 required here. This notification can be used to perform any chipsetspecific
1753 programming.
1754
1755 @param[in] PciResAlloc The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
1756 @param[in] Phase The phase during enumeration
1757
1758 @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error
1759 is valid for a Phase of EfiPciHostBridgeAllocateResources if
1760 SubmitResources() has not been called for one or more
1761 PCI root bridges before this call
1762 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid
1763 for a Phase of EfiPciHostBridgeSetResources.
1764 @retval EFI_INVALID_PARAMETER Invalid phase parameter
1765 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1766 This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the
1767 previously submitted resource requests cannot be fulfilled or
1768 were only partially fulfilled.
1769 @retval EFI_SUCCESS The notification was accepted without any errors.
1770
1771 **/
1772 EFI_STATUS
1773 NotifyPhase (
1774 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
1775 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
1776 )
1777 {
1778 EFI_HANDLE HostBridgeHandle;
1779 EFI_HANDLE RootBridgeHandle;
1780 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
1781 EFI_STATUS Status;
1782
1783 HostBridgeHandle = NULL;
1784 RootBridgeHandle = NULL;
1785 if (gPciPlatformProtocol != NULL) {
1786 //
1787 // Get Host Bridge Handle.
1788 //
1789 PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle);
1790
1791 //
1792 // Get the rootbridge Io protocol to find the host bridge handle
1793 //
1794 Status = gBS->HandleProtocol (
1795 RootBridgeHandle,
1796 &gEfiPciRootBridgeIoProtocolGuid,
1797 (VOID **) &PciRootBridgeIo
1798 );
1799
1800 if (EFI_ERROR (Status)) {
1801 return EFI_NOT_FOUND;
1802 }
1803
1804 HostBridgeHandle = PciRootBridgeIo->ParentHandle;
1805
1806 //
1807 // Call PlatformPci::PlatformNotify() if the protocol is present.
1808 //
1809 gPciPlatformProtocol->PlatformNotify (
1810 gPciPlatformProtocol,
1811 HostBridgeHandle,
1812 Phase,
1813 ChipsetEntry
1814 );
1815 } else if (gPciOverrideProtocol != NULL){
1816 //
1817 // Get Host Bridge Handle.
1818 //
1819 PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle);
1820
1821 //
1822 // Get the rootbridge Io protocol to find the host bridge handle
1823 //
1824 Status = gBS->HandleProtocol (
1825 RootBridgeHandle,
1826 &gEfiPciRootBridgeIoProtocolGuid,
1827 (VOID **) &PciRootBridgeIo
1828 );
1829
1830 if (EFI_ERROR (Status)) {
1831 return EFI_NOT_FOUND;
1832 }
1833
1834 HostBridgeHandle = PciRootBridgeIo->ParentHandle;
1835
1836 //
1837 // Call PlatformPci::PhaseNotify() if the protocol is present.
1838 //
1839 gPciOverrideProtocol->PlatformNotify (
1840 gPciOverrideProtocol,
1841 HostBridgeHandle,
1842 Phase,
1843 ChipsetEntry
1844 );
1845 }
1846
1847 Status = PciResAlloc->NotifyPhase (
1848 PciResAlloc,
1849 Phase
1850 );
1851
1852 if (gPciPlatformProtocol != NULL) {
1853 //
1854 // Call PlatformPci::PlatformNotify() if the protocol is present.
1855 //
1856 gPciPlatformProtocol->PlatformNotify (
1857 gPciPlatformProtocol,
1858 HostBridgeHandle,
1859 Phase,
1860 ChipsetExit
1861 );
1862
1863 } else if (gPciOverrideProtocol != NULL) {
1864 //
1865 // Call PlatformPci::PhaseNotify() if the protocol is present.
1866 //
1867 gPciOverrideProtocol->PlatformNotify (
1868 gPciOverrideProtocol,
1869 HostBridgeHandle,
1870 Phase,
1871 ChipsetExit
1872 );
1873 }
1874
1875 return Status;
1876 }
1877
1878 /**
1879 Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various
1880 stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual
1881 PCI controllers before enumeration.
1882
1883 This function is called during the PCI enumeration process. No specific action is expected from this
1884 member function. It allows the host bridge driver to preinitialize individual PCI controllers before
1885 enumeration.
1886
1887 @param Bridge Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
1888 @param Bus The bus number of the pci device.
1889 @param Device The device number of the pci device.
1890 @param Func The function number of the pci device.
1891 @param Phase The phase of the PCI device enumeration.
1892
1893 @retval EFI_SUCCESS The requested parameters were returned.
1894 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
1895 @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in
1896 EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
1897 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should
1898 not enumerate this device, including its child devices if it is a PCI-to-PCI
1899 bridge.
1900
1901 **/
1902 EFI_STATUS
1903 PreprocessController (
1904 IN PCI_IO_DEVICE *Bridge,
1905 IN UINT8 Bus,
1906 IN UINT8 Device,
1907 IN UINT8 Func,
1908 IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
1909 )
1910 {
1911 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS RootBridgePciAddress;
1912 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc;
1913 EFI_HANDLE RootBridgeHandle;
1914 EFI_HANDLE HostBridgeHandle;
1915 EFI_STATUS Status;
1916
1917 //
1918 // Get the host bridge handle
1919 //
1920 HostBridgeHandle = Bridge->PciRootBridgeIo->ParentHandle;
1921
1922 //
1923 // Get the pci host bridge resource allocation protocol
1924 //
1925 Status = gBS->OpenProtocol (
1926 HostBridgeHandle,
1927 &gEfiPciHostBridgeResourceAllocationProtocolGuid,
1928 (VOID **) &PciResAlloc,
1929 NULL,
1930 NULL,
1931 EFI_OPEN_PROTOCOL_GET_PROTOCOL
1932 );
1933
1934 if (EFI_ERROR (Status)) {
1935 return EFI_UNSUPPORTED;
1936 }
1937
1938 //
1939 // Get Root Brige Handle
1940 //
1941 while (Bridge->Parent != NULL) {
1942 Bridge = Bridge->Parent;
1943 }
1944
1945 RootBridgeHandle = Bridge->Handle;
1946
1947 RootBridgePciAddress.Register = 0;
1948 RootBridgePciAddress.Function = Func;
1949 RootBridgePciAddress.Device = Device;
1950 RootBridgePciAddress.Bus = Bus;
1951 RootBridgePciAddress.ExtendedRegister = 0;
1952
1953 if (gPciPlatformProtocol != NULL) {
1954 //
1955 // Call PlatformPci::PrepController() if the protocol is present.
1956 //
1957 gPciPlatformProtocol->PlatformPrepController (
1958 gPciPlatformProtocol,
1959 HostBridgeHandle,
1960 RootBridgeHandle,
1961 RootBridgePciAddress,
1962 Phase,
1963 ChipsetEntry
1964 );
1965 } else if (gPciOverrideProtocol != NULL) {
1966 //
1967 // Call PlatformPci::PrepController() if the protocol is present.
1968 //
1969 gPciOverrideProtocol->PlatformPrepController (
1970 gPciOverrideProtocol,
1971 HostBridgeHandle,
1972 RootBridgeHandle,
1973 RootBridgePciAddress,
1974 Phase,
1975 ChipsetEntry
1976 );
1977 }
1978
1979 Status = PciResAlloc->PreprocessController (
1980 PciResAlloc,
1981 RootBridgeHandle,
1982 RootBridgePciAddress,
1983 Phase
1984 );
1985
1986 if (gPciPlatformProtocol != NULL) {
1987 //
1988 // Call PlatformPci::PrepController() if the protocol is present.
1989 //
1990 gPciPlatformProtocol->PlatformPrepController (
1991 gPciPlatformProtocol,
1992 HostBridgeHandle,
1993 RootBridgeHandle,
1994 RootBridgePciAddress,
1995 Phase,
1996 ChipsetExit
1997 );
1998 } else if (gPciOverrideProtocol != NULL) {
1999 //
2000 // Call PlatformPci::PrepController() if the protocol is present.
2001 //
2002 gPciOverrideProtocol->PlatformPrepController (
2003 gPciOverrideProtocol,
2004 HostBridgeHandle,
2005 RootBridgeHandle,
2006 RootBridgePciAddress,
2007 Phase,
2008 ChipsetExit
2009 );
2010 }
2011
2012 return EFI_SUCCESS;
2013 }
2014
2015 /**
2016 This function allows the PCI bus driver to be notified to act as requested when a hot-plug event has
2017 happened on the hot-plug controller. Currently, the operations include add operation and remove operation..
2018
2019 @param This A pointer to the hot plug request protocol.
2020 @param Operation The operation the PCI bus driver is requested to make.
2021 @param Controller The handle of the hot-plug controller.
2022 @param RemainingDevicePath The remaining device path for the PCI-like hot-plug device.
2023 @param NumberOfChildren The number of child handles.
2024 For a add operation, it is an output parameter.
2025 For a remove operation, it's an input parameter.
2026 @param ChildHandleBuffer The buffer which contains the child handles.
2027
2028 @retval EFI_INVALID_PARAMETER Operation is not a legal value.
2029 Controller is NULL or not a valid handle.
2030 NumberOfChildren is NULL.
2031 ChildHandleBuffer is NULL while Operation is add.
2032 @retval EFI_OUT_OF_RESOURCES There are no enough resources to start the devices.
2033 @retval EFI_NOT_FOUND Can not find bridge according to controller handle.
2034 @retval EFI_SUCCESS The handles for the specified device have been created or destroyed
2035 as requested, and for an add operation, the new handles are
2036 returned in ChildHandleBuffer.
2037 **/
2038 EFI_STATUS
2039 EFIAPI
2040 PciHotPlugRequestNotify (
2041 IN EFI_PCI_HOTPLUG_REQUEST_PROTOCOL * This,
2042 IN EFI_PCI_HOTPLUG_OPERATION Operation,
2043 IN EFI_HANDLE Controller,
2044 IN EFI_DEVICE_PATH_PROTOCOL * RemainingDevicePath OPTIONAL,
2045 IN OUT UINT8 *NumberOfChildren,
2046 IN OUT EFI_HANDLE * ChildHandleBuffer
2047 )
2048 {
2049 PCI_IO_DEVICE *Bridge;
2050 PCI_IO_DEVICE *Temp;
2051 EFI_PCI_IO_PROTOCOL *PciIo;
2052 UINTN Index;
2053 EFI_HANDLE RootBridgeHandle;
2054 EFI_STATUS Status;
2055
2056 //
2057 // Check input parameter validity
2058 //
2059 if ((Controller == NULL) || (NumberOfChildren == NULL)){
2060 return EFI_INVALID_PARAMETER;
2061 }
2062
2063 if ((Operation != EfiPciHotPlugRequestAdd) && (Operation != EfiPciHotplugRequestRemove)) {
2064 return EFI_INVALID_PARAMETER;
2065 }
2066
2067 if (Operation == EfiPciHotPlugRequestAdd){
2068 if (ChildHandleBuffer == NULL) {
2069 return EFI_INVALID_PARAMETER;
2070 }
2071 } else if ((Operation == EfiPciHotplugRequestRemove) && (*NumberOfChildren != 0)) {
2072 if (ChildHandleBuffer == NULL) {
2073 return EFI_INVALID_PARAMETER;
2074 }
2075 }
2076
2077 Status = gBS->OpenProtocol (
2078 Controller,
2079 &gEfiPciIoProtocolGuid,
2080 (VOID **) &PciIo,
2081 gPciBusDriverBinding.DriverBindingHandle,
2082 Controller,
2083 EFI_OPEN_PROTOCOL_GET_PROTOCOL
2084 );
2085
2086 if (EFI_ERROR (Status)) {
2087 return EFI_NOT_FOUND;
2088 }
2089
2090 Bridge = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);
2091
2092 //
2093 // Get root bridge handle
2094 //
2095 Temp = Bridge;
2096 while (Temp->Parent != NULL) {
2097 Temp = Temp->Parent;
2098 }
2099
2100 RootBridgeHandle = Temp->Handle;
2101
2102 if (Operation == EfiPciHotPlugRequestAdd) {
2103 //
2104 // Report Status Code to indicate hot plug happens
2105 //
2106 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
2107 EFI_PROGRESS_CODE,
2108 (EFI_IO_BUS_PCI | EFI_IOB_PC_HOTPLUG),
2109 Temp->DevicePath
2110 );
2111
2112 if (NumberOfChildren != NULL) {
2113 *NumberOfChildren = 0;
2114 }
2115
2116 if (IsListEmpty (&Bridge->ChildList)) {
2117
2118 Status = PciBridgeEnumerator (Bridge);
2119
2120 if (EFI_ERROR (Status)) {
2121 return Status;
2122 }
2123 }
2124
2125 Status = StartPciDevicesOnBridge (
2126 RootBridgeHandle,
2127 Bridge,
2128 RemainingDevicePath,
2129 NumberOfChildren,
2130 ChildHandleBuffer
2131 );
2132
2133 return Status;
2134 }
2135
2136 if (Operation == EfiPciHotplugRequestRemove) {
2137
2138 if (*NumberOfChildren == 0) {
2139 //
2140 // Remove all devices on the bridge
2141 //
2142 RemoveAllPciDeviceOnBridge (RootBridgeHandle, Bridge);
2143 return EFI_SUCCESS;
2144
2145 }
2146
2147 for (Index = 0; Index < *NumberOfChildren; Index++) {
2148 //
2149 // De register all the pci device
2150 //
2151 Status = DeRegisterPciDevice (RootBridgeHandle, ChildHandleBuffer[Index]);
2152
2153 if (EFI_ERROR (Status)) {
2154 return Status;
2155 }
2156
2157 }
2158 //
2159 // End for
2160 //
2161 return EFI_SUCCESS;
2162 }
2163
2164 return EFI_SUCCESS;
2165 }
2166
2167 /**
2168 Search hostbridge according to given handle
2169
2170 @param RootBridgeHandle Host bridge handle.
2171
2172 @retval TRUE Found host bridge handle.
2173 @retval FALSE Not found hot bridge handle.
2174
2175 **/
2176 BOOLEAN
2177 SearchHostBridgeHandle (
2178 IN EFI_HANDLE RootBridgeHandle
2179 )
2180 {
2181 EFI_HANDLE HostBridgeHandle;
2182 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
2183 UINTN Index;
2184 EFI_STATUS Status;
2185
2186 //
2187 // Get the rootbridge Io protocol to find the host bridge handle
2188 //
2189 Status = gBS->OpenProtocol (
2190 RootBridgeHandle,
2191 &gEfiPciRootBridgeIoProtocolGuid,
2192 (VOID **) &PciRootBridgeIo,
2193 gPciBusDriverBinding.DriverBindingHandle,
2194 RootBridgeHandle,
2195 EFI_OPEN_PROTOCOL_GET_PROTOCOL
2196 );
2197
2198 if (EFI_ERROR (Status)) {
2199 return FALSE;
2200 }
2201
2202 HostBridgeHandle = PciRootBridgeIo->ParentHandle;
2203 for (Index = 0; Index < gPciHostBridgeNumber; Index++) {
2204 if (HostBridgeHandle == gPciHostBrigeHandles[Index]) {
2205 return TRUE;
2206 }
2207 }
2208
2209 return FALSE;
2210 }
2211
2212 /**
2213 Add host bridge handle to global variable for enumerating.
2214
2215 @param HostBridgeHandle Host bridge handle.
2216
2217 @retval EFI_SUCCESS Successfully added host bridge.
2218 @retval EFI_ABORTED Host bridge is NULL, or given host bridge
2219 has been in host bridge list.
2220
2221 **/
2222 EFI_STATUS
2223 AddHostBridgeEnumerator (
2224 IN EFI_HANDLE HostBridgeHandle
2225 )
2226 {
2227 UINTN Index;
2228
2229 if (HostBridgeHandle == NULL) {
2230 return EFI_ABORTED;
2231 }
2232
2233 for (Index = 0; Index < gPciHostBridgeNumber; Index++) {
2234 if (HostBridgeHandle == gPciHostBrigeHandles[Index]) {
2235 return EFI_ABORTED;
2236 }
2237 }
2238
2239 if (Index < PCI_MAX_HOST_BRIDGE_NUM) {
2240 gPciHostBrigeHandles[Index] = HostBridgeHandle;
2241 gPciHostBridgeNumber++;
2242 }
2243
2244 return EFI_SUCCESS;
2245 }
2246
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