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MdeModulePkg/PciBus: Add IOMMU support.
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciIo.c
1 /** @file
2 EFI PCI IO protocol functions implementation for PCI Bus module.
3
4 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include "PciBus.h"
16
17 extern EDKII_IOMMU_PROTOCOL *mIoMmuProtocol;
18
19 //
20 // Pci Io Protocol Interface
21 //
22 EFI_PCI_IO_PROTOCOL mPciIoInterface = {
23 PciIoPollMem,
24 PciIoPollIo,
25 {
26 PciIoMemRead,
27 PciIoMemWrite
28 },
29 {
30 PciIoIoRead,
31 PciIoIoWrite
32 },
33 {
34 PciIoConfigRead,
35 PciIoConfigWrite
36 },
37 PciIoCopyMem,
38 PciIoMap,
39 PciIoUnmap,
40 PciIoAllocateBuffer,
41 PciIoFreeBuffer,
42 PciIoFlush,
43 PciIoGetLocation,
44 PciIoAttributes,
45 PciIoGetBarAttributes,
46 PciIoSetBarAttributes,
47 0,
48 NULL
49 };
50
51 /**
52 Initializes a PCI I/O Instance.
53
54 @param PciIoDevice Pci device instance.
55
56 **/
57 VOID
58 InitializePciIoInstance (
59 IN PCI_IO_DEVICE *PciIoDevice
60 )
61 {
62 CopyMem (&PciIoDevice->PciIo, &mPciIoInterface, sizeof (EFI_PCI_IO_PROTOCOL));
63 }
64
65 /**
66 Verifies access to a PCI Base Address Register (BAR).
67
68 @param PciIoDevice Pci device instance.
69 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
70 base address for the memory or I/O operation to perform.
71 @param Type Operation type could be memory or I/O.
72 @param Width Signifies the width of the memory or I/O operations.
73 @param Count The number of memory or I/O operations to perform.
74 @param Offset The offset within the PCI configuration space for the PCI controller.
75
76 @retval EFI_INVALID_PARAMETER Invalid Width/BarIndex or Bar type.
77 @retval EFI_SUCCESS Successfully verified.
78
79 **/
80 EFI_STATUS
81 PciIoVerifyBarAccess (
82 IN PCI_IO_DEVICE *PciIoDevice,
83 IN UINT8 BarIndex,
84 IN PCI_BAR_TYPE Type,
85 IN IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
86 IN IN UINTN Count,
87 IN UINT64 *Offset
88 )
89 {
90 if ((UINT32)Width >= EfiPciIoWidthMaximum) {
91 return EFI_INVALID_PARAMETER;
92 }
93
94 if (BarIndex == EFI_PCI_IO_PASS_THROUGH_BAR) {
95 return EFI_SUCCESS;
96 }
97
98 //
99 // BarIndex 0-5 is legal
100 //
101 if (BarIndex >= PCI_MAX_BAR) {
102 return EFI_INVALID_PARAMETER;
103 }
104
105 if (!CheckBarType (PciIoDevice, BarIndex, Type)) {
106 return EFI_INVALID_PARAMETER;
107 }
108
109 //
110 // If Width is EfiPciIoWidthFifoUintX then convert to EfiPciIoWidthUintX
111 // If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX
112 //
113 if (Width >= EfiPciIoWidthFifoUint8 && Width <= EfiPciIoWidthFifoUint64) {
114 Count = 1;
115 }
116
117 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & 0x03);
118
119 if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PciIoDevice->PciBar[BarIndex].Length) {
120 return EFI_INVALID_PARAMETER;
121 }
122
123 *Offset = *Offset + PciIoDevice->PciBar[BarIndex].BaseAddress;
124
125 return EFI_SUCCESS;
126 }
127
128 /**
129 Verifies access to a PCI Configuration Header.
130
131 @param PciIoDevice Pci device instance.
132 @param Width Signifies the width of the memory or I/O operations.
133 @param Count The number of memory or I/O operations to perform.
134 @param Offset The offset within the PCI configuration space for the PCI controller.
135
136 @retval EFI_INVALID_PARAMETER Invalid Width
137 @retval EFI_UNSUPPORTED Offset overflowed.
138 @retval EFI_SUCCESS Successfully verified.
139
140 **/
141 EFI_STATUS
142 PciIoVerifyConfigAccess (
143 IN PCI_IO_DEVICE *PciIoDevice,
144 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
145 IN UINTN Count,
146 IN UINT64 *Offset
147 )
148 {
149 UINT64 ExtendOffset;
150
151 if ((UINT32)Width >= EfiPciIoWidthMaximum) {
152 return EFI_INVALID_PARAMETER;
153 }
154
155 //
156 // If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX
157 //
158 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & 0x03);
159
160 if (PciIoDevice->IsPciExp) {
161 if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PCI_EXP_MAX_CONFIG_OFFSET) {
162 return EFI_UNSUPPORTED;
163 }
164
165 ExtendOffset = LShiftU64 (*Offset, 32);
166 *Offset = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, 0);
167 *Offset = (*Offset) | ExtendOffset;
168
169 } else {
170 if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PCI_MAX_CONFIG_OFFSET) {
171 return EFI_UNSUPPORTED;
172 }
173
174 *Offset = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, *Offset);
175 }
176
177 return EFI_SUCCESS;
178 }
179
180 /**
181 Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is
182 satisfied or after a defined duration.
183
184 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
185 @param Width Signifies the width of the memory or I/O operations.
186 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
187 base address for the memory operation to perform.
188 @param Offset The offset within the selected BAR to start the memory operation.
189 @param Mask Mask used for the polling criteria.
190 @param Value The comparison value used for the polling exit criteria.
191 @param Delay The number of 100 ns units to poll.
192 @param Result Pointer to the last value read from the memory location.
193
194 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
195 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
196 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.
197 @retval EFI_TIMEOUT Delay expired before a match occurred.
198 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
199 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
200
201 **/
202 EFI_STATUS
203 EFIAPI
204 PciIoPollMem (
205 IN EFI_PCI_IO_PROTOCOL *This,
206 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
207 IN UINT8 BarIndex,
208 IN UINT64 Offset,
209 IN UINT64 Mask,
210 IN UINT64 Value,
211 IN UINT64 Delay,
212 OUT UINT64 *Result
213 )
214 {
215 EFI_STATUS Status;
216 PCI_IO_DEVICE *PciIoDevice;
217
218 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
219
220 if ((UINT32)Width >= EfiPciIoWidthMaximum) {
221 return EFI_INVALID_PARAMETER;
222 }
223
224 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, 1, &Offset);
225 if (EFI_ERROR (Status)) {
226 return EFI_UNSUPPORTED;
227 }
228
229 if (Width > EfiPciIoWidthUint64) {
230 return EFI_INVALID_PARAMETER;
231 }
232
233 //
234 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
235 //
236 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
237 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
238 Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);
239 if (EFI_ERROR (Status)) {
240 return Status;
241 }
242 if ((*Result & Mask) == Value || Delay == 0) {
243 return EFI_SUCCESS;
244 }
245 do {
246 //
247 // Stall 10 us = 100 * 100ns
248 //
249 gBS->Stall (10);
250
251 Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);
252 if (EFI_ERROR (Status)) {
253 return Status;
254 }
255 if ((*Result & Mask) == Value) {
256 return EFI_SUCCESS;
257 }
258 if (Delay <= 100) {
259 return EFI_TIMEOUT;
260 }
261 Delay -= 100;
262 } while (TRUE);
263 }
264 }
265
266 Status = PciIoDevice->PciRootBridgeIo->PollMem (
267 PciIoDevice->PciRootBridgeIo,
268 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
269 Offset,
270 Mask,
271 Value,
272 Delay,
273 Result
274 );
275
276 if (EFI_ERROR (Status)) {
277 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
278 EFI_ERROR_CODE | EFI_ERROR_MINOR,
279 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,
280 PciIoDevice->DevicePath
281 );
282 }
283
284 return Status;
285 }
286
287 /**
288 Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is
289 satisfied or after a defined duration.
290
291 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
292 @param Width Signifies the width of the memory or I/O operations.
293 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
294 base address for the memory operation to perform.
295 @param Offset The offset within the selected BAR to start the memory operation.
296 @param Mask Mask used for the polling criteria.
297 @param Value The comparison value used for the polling exit criteria.
298 @param Delay The number of 100 ns units to poll.
299 @param Result Pointer to the last value read from the memory location.
300
301 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
302 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
303 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.
304 @retval EFI_TIMEOUT Delay expired before a match occurred.
305 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
306 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
307
308 **/
309 EFI_STATUS
310 EFIAPI
311 PciIoPollIo (
312 IN EFI_PCI_IO_PROTOCOL *This,
313 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
314 IN UINT8 BarIndex,
315 IN UINT64 Offset,
316 IN UINT64 Mask,
317 IN UINT64 Value,
318 IN UINT64 Delay,
319 OUT UINT64 *Result
320 )
321 {
322 EFI_STATUS Status;
323 PCI_IO_DEVICE *PciIoDevice;
324
325 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
326
327 if ((UINT32)Width > EfiPciIoWidthUint64) {
328 return EFI_INVALID_PARAMETER;
329 }
330
331 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, 1, &Offset);
332 if (EFI_ERROR (Status)) {
333 return EFI_UNSUPPORTED;
334 }
335
336 //
337 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
338 //
339 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
340 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
341 Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);
342 if (EFI_ERROR (Status)) {
343 return Status;
344 }
345 if ((*Result & Mask) == Value || Delay == 0) {
346 return EFI_SUCCESS;
347 }
348 do {
349 //
350 // Stall 10 us = 100 * 100ns
351 //
352 gBS->Stall (10);
353
354 Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);
355 if (EFI_ERROR (Status)) {
356 return Status;
357 }
358 if ((*Result & Mask) == Value) {
359 return EFI_SUCCESS;
360 }
361 if (Delay <= 100) {
362 return EFI_TIMEOUT;
363 }
364 Delay -= 100;
365 } while (TRUE);
366 }
367 }
368
369 Status = PciIoDevice->PciRootBridgeIo->PollIo (
370 PciIoDevice->PciRootBridgeIo,
371 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
372 Offset,
373 Mask,
374 Value,
375 Delay,
376 Result
377 );
378
379 if (EFI_ERROR (Status)) {
380 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
381 EFI_ERROR_CODE | EFI_ERROR_MINOR,
382 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,
383 PciIoDevice->DevicePath
384 );
385 }
386
387 return Status;
388 }
389
390 /**
391 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
392
393 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
394 @param Width Signifies the width of the memory or I/O operations.
395 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
396 base address for the memory or I/O operation to perform.
397 @param Offset The offset within the selected BAR to start the memory or I/O operation.
398 @param Count The number of memory or I/O operations to perform.
399 @param Buffer For read operations, the destination buffer to store the results. For write
400 operations, the source buffer to write data from.
401
402 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
403 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
404 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
405 valid for the PCI BAR specified by BarIndex.
406 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
407 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
408
409 **/
410 EFI_STATUS
411 EFIAPI
412 PciIoMemRead (
413 IN EFI_PCI_IO_PROTOCOL *This,
414 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
415 IN UINT8 BarIndex,
416 IN UINT64 Offset,
417 IN UINTN Count,
418 IN OUT VOID *Buffer
419 )
420 {
421 EFI_STATUS Status;
422 PCI_IO_DEVICE *PciIoDevice;
423
424 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
425
426 if ((UINT32)Width >= EfiPciIoWidthMaximum) {
427 return EFI_INVALID_PARAMETER;
428 }
429
430 if (Buffer == NULL) {
431 return EFI_INVALID_PARAMETER;
432 }
433
434 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, Count, &Offset);
435 if (EFI_ERROR (Status)) {
436 return EFI_UNSUPPORTED;
437 }
438
439 //
440 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
441 //
442 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
443 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
444 Count *= (UINTN)(1 << (Width & 0x03));
445 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
446 }
447 }
448
449
450 Status = PciIoDevice->PciRootBridgeIo->Mem.Read (
451 PciIoDevice->PciRootBridgeIo,
452 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
453 Offset,
454 Count,
455 Buffer
456 );
457
458 if (EFI_ERROR (Status)) {
459 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
460 EFI_ERROR_CODE | EFI_ERROR_MINOR,
461 EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR,
462 PciIoDevice->DevicePath
463 );
464 }
465
466 return Status;
467 }
468
469 /**
470 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
471
472 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
473 @param Width Signifies the width of the memory or I/O operations.
474 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
475 base address for the memory or I/O operation to perform.
476 @param Offset The offset within the selected BAR to start the memory or I/O operation.
477 @param Count The number of memory or I/O operations to perform.
478 @param Buffer For read operations, the destination buffer to store the results. For write
479 operations, the source buffer to write data from.
480
481 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
482 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
483 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
484 valid for the PCI BAR specified by BarIndex.
485 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
486 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
487
488 **/
489 EFI_STATUS
490 EFIAPI
491 PciIoMemWrite (
492 IN EFI_PCI_IO_PROTOCOL *This,
493 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
494 IN UINT8 BarIndex,
495 IN UINT64 Offset,
496 IN UINTN Count,
497 IN OUT VOID *Buffer
498 )
499 {
500 EFI_STATUS Status;
501 PCI_IO_DEVICE *PciIoDevice;
502
503 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
504
505 if ((UINT32)Width >= EfiPciIoWidthMaximum) {
506 return EFI_INVALID_PARAMETER;
507 }
508
509 if (Buffer == NULL) {
510 return EFI_INVALID_PARAMETER;
511 }
512
513 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, Count, &Offset);
514 if (EFI_ERROR (Status)) {
515 return EFI_UNSUPPORTED;
516 }
517
518 //
519 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
520 //
521 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
522 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
523 Count *= (UINTN)(1 << (Width & 0x03));
524 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
525 }
526 }
527
528 Status = PciIoDevice->PciRootBridgeIo->Mem.Write (
529 PciIoDevice->PciRootBridgeIo,
530 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
531 Offset,
532 Count,
533 Buffer
534 );
535
536 if (EFI_ERROR (Status)) {
537 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
538 EFI_ERROR_CODE | EFI_ERROR_MINOR,
539 EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR,
540 PciIoDevice->DevicePath
541 );
542 }
543
544 return Status;
545 }
546
547 /**
548 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
549
550 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
551 @param Width Signifies the width of the memory or I/O operations.
552 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
553 base address for the memory or I/O operation to perform.
554 @param Offset The offset within the selected BAR to start the memory or I/O operation.
555 @param Count The number of memory or I/O operations to perform.
556 @param Buffer For read operations, the destination buffer to store the results. For write
557 operations, the source buffer to write data from.
558
559 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
560 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
561 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
562 valid for the PCI BAR specified by BarIndex.
563 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
564 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
565
566 **/
567 EFI_STATUS
568 EFIAPI
569 PciIoIoRead (
570 IN EFI_PCI_IO_PROTOCOL *This,
571 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
572 IN UINT8 BarIndex,
573 IN UINT64 Offset,
574 IN UINTN Count,
575 IN OUT VOID *Buffer
576 )
577 {
578 EFI_STATUS Status;
579 PCI_IO_DEVICE *PciIoDevice;
580
581 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
582
583 if ((UINT32)Width >= EfiPciIoWidthMaximum) {
584 return EFI_INVALID_PARAMETER;
585 }
586
587 if (Buffer == NULL) {
588 return EFI_INVALID_PARAMETER;
589 }
590
591 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, Count, &Offset);
592 if (EFI_ERROR (Status)) {
593 return EFI_UNSUPPORTED;
594 }
595
596 //
597 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
598 //
599 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
600 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
601 Count *= (UINTN)(1 << (Width & 0x03));
602 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
603 }
604 }
605
606 Status = PciIoDevice->PciRootBridgeIo->Io.Read (
607 PciIoDevice->PciRootBridgeIo,
608 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
609 Offset,
610 Count,
611 Buffer
612 );
613
614 if (EFI_ERROR (Status)) {
615 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
616 EFI_ERROR_CODE | EFI_ERROR_MINOR,
617 EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR,
618 PciIoDevice->DevicePath
619 );
620 }
621
622 return Status;
623 }
624
625 /**
626 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
627
628 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
629 @param Width Signifies the width of the memory or I/O operations.
630 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
631 base address for the memory or I/O operation to perform.
632 @param Offset The offset within the selected BAR to start the memory or I/O operation.
633 @param Count The number of memory or I/O operations to perform.
634 @param Buffer For read operations, the destination buffer to store the results. For write
635 operations, the source buffer to write data from.
636
637 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
638 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
639 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
640 valid for the PCI BAR specified by BarIndex.
641 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
642 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
643
644 **/
645 EFI_STATUS
646 EFIAPI
647 PciIoIoWrite (
648 IN EFI_PCI_IO_PROTOCOL *This,
649 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
650 IN UINT8 BarIndex,
651 IN UINT64 Offset,
652 IN UINTN Count,
653 IN OUT VOID *Buffer
654 )
655 {
656 EFI_STATUS Status;
657 PCI_IO_DEVICE *PciIoDevice;
658
659 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
660
661 if ((UINT32)Width >= EfiPciIoWidthMaximum) {
662 return EFI_INVALID_PARAMETER;
663 }
664
665 if (Buffer == NULL) {
666 return EFI_INVALID_PARAMETER;
667 }
668
669 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, Count, &Offset);
670 if (EFI_ERROR (Status)) {
671 return EFI_UNSUPPORTED;
672 }
673
674 //
675 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
676 //
677 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
678 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
679 Count *= (UINTN)(1 << (Width & 0x03));
680 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
681 }
682 }
683
684 Status = PciIoDevice->PciRootBridgeIo->Io.Write (
685 PciIoDevice->PciRootBridgeIo,
686 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
687 Offset,
688 Count,
689 Buffer
690 );
691
692 if (EFI_ERROR (Status)) {
693 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
694 EFI_ERROR_CODE | EFI_ERROR_MINOR,
695 EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR,
696 PciIoDevice->DevicePath
697 );
698 }
699
700 return Status;
701 }
702
703 /**
704 Enable a PCI driver to access PCI controller registers in PCI configuration space.
705
706 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
707 @param Width Signifies the width of the memory operations.
708 @param Offset The offset within the PCI configuration space for the PCI controller.
709 @param Count The number of PCI configuration operations to perform.
710 @param Buffer For read operations, the destination buffer to store the results. For write
711 operations, the source buffer to write data from.
712
713
714 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
715 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
716 valid for the PCI configuration header of the PCI controller.
717 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
718 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
719
720 **/
721 EFI_STATUS
722 EFIAPI
723 PciIoConfigRead (
724 IN EFI_PCI_IO_PROTOCOL *This,
725 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
726 IN UINT32 Offset,
727 IN UINTN Count,
728 IN OUT VOID *Buffer
729 )
730 {
731 EFI_STATUS Status;
732 PCI_IO_DEVICE *PciIoDevice;
733 UINT64 Address;
734
735 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
736
737 Address = Offset;
738 Status = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);
739 if (EFI_ERROR (Status)) {
740 return Status;
741 }
742
743 //
744 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
745 //
746 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
747 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
748 Count *= (UINTN)(1 << (Width & 0x03));
749 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
750 }
751 }
752
753 Status = PciIoDevice->PciRootBridgeIo->Pci.Read (
754 PciIoDevice->PciRootBridgeIo,
755 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
756 Address,
757 Count,
758 Buffer
759 );
760
761 if (EFI_ERROR (Status)) {
762 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
763 EFI_ERROR_CODE | EFI_ERROR_MINOR,
764 EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR,
765 PciIoDevice->DevicePath
766 );
767 }
768
769 return Status;
770 }
771
772 /**
773 Enable a PCI driver to access PCI controller registers in PCI configuration space.
774
775 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
776 @param Width Signifies the width of the memory operations.
777 @param Offset The offset within the PCI configuration space for the PCI controller.
778 @param Count The number of PCI configuration operations to perform.
779 @param Buffer For read operations, the destination buffer to store the results. For write
780 operations, the source buffer to write data from.
781
782
783 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
784 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
785 valid for the PCI configuration header of the PCI controller.
786 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
787 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
788
789 **/
790 EFI_STATUS
791 EFIAPI
792 PciIoConfigWrite (
793 IN EFI_PCI_IO_PROTOCOL *This,
794 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
795 IN UINT32 Offset,
796 IN UINTN Count,
797 IN OUT VOID *Buffer
798 )
799 {
800 EFI_STATUS Status;
801 PCI_IO_DEVICE *PciIoDevice;
802 UINT64 Address;
803
804 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
805
806 Address = Offset;
807 Status = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);
808 if (EFI_ERROR (Status)) {
809 return Status;
810 }
811
812 //
813 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
814 //
815 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
816 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
817 Count *= (UINTN)(1 << (Width & 0x03));
818 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
819 }
820 }
821
822 Status = PciIoDevice->PciRootBridgeIo->Pci.Write (
823 PciIoDevice->PciRootBridgeIo,
824 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
825 Address,
826 Count,
827 Buffer
828 );
829
830 if (EFI_ERROR (Status)) {
831 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
832 EFI_ERROR_CODE | EFI_ERROR_MINOR,
833 EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR,
834 PciIoDevice->DevicePath
835 );
836 }
837
838 return Status;
839 }
840
841 /**
842 Enables a PCI driver to copy one region of PCI memory space to another region of PCI
843 memory space.
844
845 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
846 @param Width Signifies the width of the memory operations.
847 @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the
848 base address for the memory operation to perform.
849 @param DestOffset The destination offset within the BAR specified by DestBarIndex to
850 start the memory writes for the copy operation.
851 @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the
852 base address for the memory operation to perform.
853 @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start
854 the memory reads for the copy operation.
855 @param Count The number of memory operations to perform. Bytes moved is Width
856 size * Count, starting at DestOffset and SrcOffset.
857
858 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.
859 @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.
860 @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.
861 @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count
862 is not valid for the PCI BAR specified by DestBarIndex.
863 @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is
864 not valid for the PCI BAR specified by SrcBarIndex.
865 @retval EFI_INVALID_PARAMETER Width is invalid.
866 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
867
868 **/
869 EFI_STATUS
870 EFIAPI
871 PciIoCopyMem (
872 IN EFI_PCI_IO_PROTOCOL *This,
873 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
874 IN UINT8 DestBarIndex,
875 IN UINT64 DestOffset,
876 IN UINT8 SrcBarIndex,
877 IN UINT64 SrcOffset,
878 IN UINTN Count
879 )
880 {
881 EFI_STATUS Status;
882 PCI_IO_DEVICE *PciIoDevice;
883
884 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
885
886 if ((UINT32)Width >= EfiPciIoWidthMaximum) {
887 return EFI_INVALID_PARAMETER;
888 }
889
890 if (Width == EfiPciIoWidthFifoUint8 ||
891 Width == EfiPciIoWidthFifoUint16 ||
892 Width == EfiPciIoWidthFifoUint32 ||
893 Width == EfiPciIoWidthFifoUint64 ||
894 Width == EfiPciIoWidthFillUint8 ||
895 Width == EfiPciIoWidthFillUint16 ||
896 Width == EfiPciIoWidthFillUint32 ||
897 Width == EfiPciIoWidthFillUint64) {
898 return EFI_INVALID_PARAMETER;
899 }
900
901 Status = PciIoVerifyBarAccess (PciIoDevice, DestBarIndex, PciBarTypeMem, Width, Count, &DestOffset);
902 if (EFI_ERROR (Status)) {
903 return EFI_UNSUPPORTED;
904 }
905
906 Status = PciIoVerifyBarAccess (PciIoDevice, SrcBarIndex, PciBarTypeMem, Width, Count, &SrcOffset);
907 if (EFI_ERROR (Status)) {
908 return EFI_UNSUPPORTED;
909 }
910
911 //
912 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
913 //
914 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
915 if ((SrcOffset & ((1 << (Width & 0x03)) - 1)) != 0 || (DestOffset & ((1 << (Width & 0x03)) - 1)) != 0) {
916 Count *= (UINTN)(1 << (Width & 0x03));
917 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
918 }
919 }
920
921 Status = PciIoDevice->PciRootBridgeIo->CopyMem (
922 PciIoDevice->PciRootBridgeIo,
923 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
924 DestOffset,
925 SrcOffset,
926 Count
927 );
928
929 if (EFI_ERROR (Status)) {
930 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
931 EFI_ERROR_CODE | EFI_ERROR_MINOR,
932 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,
933 PciIoDevice->DevicePath
934 );
935 }
936
937 return Status;
938 }
939
940 /**
941 Provides the PCI controller-specific addresses needed to access system memory.
942
943 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
944 @param Operation Indicates if the bus master is going to read or write to system memory.
945 @param HostAddress The system memory address to map to the PCI controller.
946 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes
947 that were mapped.
948 @param DeviceAddress The resulting map address for the bus master PCI controller to use to
949 access the hosts HostAddress.
950 @param Mapping A resulting value to pass to Unmap().
951
952 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
953 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
954 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
955 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
956 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
957
958 **/
959 EFI_STATUS
960 EFIAPI
961 PciIoMap (
962 IN EFI_PCI_IO_PROTOCOL *This,
963 IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,
964 IN VOID *HostAddress,
965 IN OUT UINTN *NumberOfBytes,
966 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
967 OUT VOID **Mapping
968 )
969 {
970 EFI_STATUS Status;
971 PCI_IO_DEVICE *PciIoDevice;
972 UINT64 IoMmuAttribute;
973 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION RootBridgeIoOperation;
974
975 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
976
977 if ((UINT32)Operation >= EfiPciIoOperationMaximum) {
978 return EFI_INVALID_PARAMETER;
979 }
980
981 if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL) {
982 return EFI_INVALID_PARAMETER;
983 }
984
985 RootBridgeIoOperation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION)Operation;
986 if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) != 0) {
987 RootBridgeIoOperation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION)(Operation + EfiPciOperationBusMasterRead64);
988 }
989
990 Status = PciIoDevice->PciRootBridgeIo->Map (
991 PciIoDevice->PciRootBridgeIo,
992 RootBridgeIoOperation,
993 HostAddress,
994 NumberOfBytes,
995 DeviceAddress,
996 Mapping
997 );
998
999 if (EFI_ERROR (Status)) {
1000 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
1001 EFI_ERROR_CODE | EFI_ERROR_MINOR,
1002 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,
1003 PciIoDevice->DevicePath
1004 );
1005 }
1006
1007 if (mIoMmuProtocol != NULL) {
1008 if (!EFI_ERROR (Status)) {
1009 switch (Operation) {
1010 case EfiPciIoOperationBusMasterRead:
1011 IoMmuAttribute = EDKII_IOMMU_ACCESS_READ;
1012 break;
1013 case EfiPciIoOperationBusMasterWrite:
1014 IoMmuAttribute = EDKII_IOMMU_ACCESS_WRITE;
1015 break;
1016 case EfiPciIoOperationBusMasterCommonBuffer:
1017 IoMmuAttribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
1018 break;
1019 default:
1020 ASSERT(FALSE);
1021 return EFI_INVALID_PARAMETER;
1022 }
1023 mIoMmuProtocol->SetAttribute (
1024 mIoMmuProtocol,
1025 PciIoDevice->Handle,
1026 *Mapping,
1027 IoMmuAttribute
1028 );
1029 }
1030 }
1031
1032 return Status;
1033 }
1034
1035 /**
1036 Completes the Map() operation and releases any corresponding resources.
1037
1038 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1039 @param Mapping The mapping value returned from Map().
1040
1041 @retval EFI_SUCCESS The range was unmapped.
1042 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
1043
1044 **/
1045 EFI_STATUS
1046 EFIAPI
1047 PciIoUnmap (
1048 IN EFI_PCI_IO_PROTOCOL *This,
1049 IN VOID *Mapping
1050 )
1051 {
1052 EFI_STATUS Status;
1053 PCI_IO_DEVICE *PciIoDevice;
1054
1055 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1056
1057 if (mIoMmuProtocol != NULL) {
1058 mIoMmuProtocol->SetAttribute (
1059 mIoMmuProtocol,
1060 PciIoDevice->Handle,
1061 Mapping,
1062 0
1063 );
1064 }
1065
1066 Status = PciIoDevice->PciRootBridgeIo->Unmap (
1067 PciIoDevice->PciRootBridgeIo,
1068 Mapping
1069 );
1070
1071 if (EFI_ERROR (Status)) {
1072 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
1073 EFI_ERROR_CODE | EFI_ERROR_MINOR,
1074 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,
1075 PciIoDevice->DevicePath
1076 );
1077 }
1078
1079 return Status;
1080 }
1081
1082 /**
1083 Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer
1084 mapping.
1085
1086 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1087 @param Type This parameter is not used and must be ignored.
1088 @param MemoryType The type of memory to allocate, EfiBootServicesData or
1089 EfiRuntimeServicesData.
1090 @param Pages The number of pages to allocate.
1091 @param HostAddress A pointer to store the base system memory address of the
1092 allocated range.
1093 @param Attributes The requested bit mask of attributes for the allocated range.
1094
1095 @retval EFI_SUCCESS The requested memory pages were allocated.
1096 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
1097 MEMORY_WRITE_COMBINE and MEMORY_CACHED.
1098 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1099 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
1100
1101 **/
1102 EFI_STATUS
1103 EFIAPI
1104 PciIoAllocateBuffer (
1105 IN EFI_PCI_IO_PROTOCOL *This,
1106 IN EFI_ALLOCATE_TYPE Type,
1107 IN EFI_MEMORY_TYPE MemoryType,
1108 IN UINTN Pages,
1109 OUT VOID **HostAddress,
1110 IN UINT64 Attributes
1111 )
1112 {
1113 EFI_STATUS Status;
1114 PCI_IO_DEVICE *PciIoDevice;
1115
1116 if ((Attributes &
1117 (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | EFI_PCI_ATTRIBUTE_MEMORY_CACHED))) != 0){
1118 return EFI_UNSUPPORTED;
1119 }
1120
1121 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1122
1123 if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) != 0) {
1124 Attributes |= EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE;
1125 }
1126
1127 Status = PciIoDevice->PciRootBridgeIo->AllocateBuffer (
1128 PciIoDevice->PciRootBridgeIo,
1129 Type,
1130 MemoryType,
1131 Pages,
1132 HostAddress,
1133 Attributes
1134 );
1135
1136 if (EFI_ERROR (Status)) {
1137 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
1138 EFI_ERROR_CODE | EFI_ERROR_MINOR,
1139 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,
1140 PciIoDevice->DevicePath
1141 );
1142 }
1143
1144 return Status;
1145 }
1146
1147 /**
1148 Frees memory that was allocated with AllocateBuffer().
1149
1150 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1151 @param Pages The number of pages to free.
1152 @param HostAddress The base system memory address of the allocated range.
1153
1154 @retval EFI_SUCCESS The requested memory pages were freed.
1155 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
1156 was not allocated with AllocateBuffer().
1157
1158 **/
1159 EFI_STATUS
1160 EFIAPI
1161 PciIoFreeBuffer (
1162 IN EFI_PCI_IO_PROTOCOL *This,
1163 IN UINTN Pages,
1164 IN VOID *HostAddress
1165 )
1166 {
1167 EFI_STATUS Status;
1168 PCI_IO_DEVICE *PciIoDevice;
1169
1170 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1171
1172 Status = PciIoDevice->PciRootBridgeIo->FreeBuffer (
1173 PciIoDevice->PciRootBridgeIo,
1174 Pages,
1175 HostAddress
1176 );
1177
1178 if (EFI_ERROR (Status)) {
1179 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
1180 EFI_ERROR_CODE | EFI_ERROR_MINOR,
1181 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,
1182 PciIoDevice->DevicePath
1183 );
1184 }
1185
1186 return Status;
1187 }
1188
1189 /**
1190 Flushes all PCI posted write transactions from a PCI host bridge to system memory.
1191
1192 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1193
1194 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host
1195 bridge to system memory.
1196 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI
1197 host bridge due to a hardware error.
1198
1199 **/
1200 EFI_STATUS
1201 EFIAPI
1202 PciIoFlush (
1203 IN EFI_PCI_IO_PROTOCOL *This
1204 )
1205 {
1206 EFI_STATUS Status;
1207 PCI_IO_DEVICE *PciIoDevice;
1208
1209 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1210
1211 Status = PciIoDevice->PciRootBridgeIo->Flush (
1212 PciIoDevice->PciRootBridgeIo
1213 );
1214 if (EFI_ERROR (Status)) {
1215 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
1216 EFI_ERROR_CODE | EFI_ERROR_MINOR,
1217 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,
1218 PciIoDevice->DevicePath
1219 );
1220 }
1221
1222 return Status;
1223 }
1224
1225 /**
1226 Retrieves this PCI controller's current PCI bus number, device number, and function number.
1227
1228 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1229 @param SegmentNumber The PCI controller's current PCI segment number.
1230 @param BusNumber The PCI controller's current PCI bus number.
1231 @param DeviceNumber The PCI controller's current PCI device number.
1232 @param FunctionNumber The PCI controller's current PCI function number.
1233
1234 @retval EFI_SUCCESS The PCI controller location was returned.
1235 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1236
1237 **/
1238 EFI_STATUS
1239 EFIAPI
1240 PciIoGetLocation (
1241 IN EFI_PCI_IO_PROTOCOL *This,
1242 OUT UINTN *Segment,
1243 OUT UINTN *Bus,
1244 OUT UINTN *Device,
1245 OUT UINTN *Function
1246 )
1247 {
1248 PCI_IO_DEVICE *PciIoDevice;
1249
1250 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1251
1252 if (Segment == NULL || Bus == NULL || Device == NULL || Function == NULL) {
1253 return EFI_INVALID_PARAMETER;
1254 }
1255
1256 *Segment = PciIoDevice->PciRootBridgeIo->SegmentNumber;
1257 *Bus = PciIoDevice->BusNumber;
1258 *Device = PciIoDevice->DeviceNumber;
1259 *Function = PciIoDevice->FunctionNumber;
1260
1261 return EFI_SUCCESS;
1262 }
1263
1264 /**
1265 Check BAR type for PCI resource.
1266
1267 @param PciIoDevice PCI device instance.
1268 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
1269 base address for the memory or I/O operation to perform.
1270 @param BarType Memory or I/O.
1271
1272 @retval TRUE Pci device's bar type is same with input BarType.
1273 @retval TRUE Pci device's bar type is not same with input BarType.
1274
1275 **/
1276 BOOLEAN
1277 CheckBarType (
1278 IN PCI_IO_DEVICE *PciIoDevice,
1279 IN UINT8 BarIndex,
1280 IN PCI_BAR_TYPE BarType
1281 )
1282 {
1283 switch (BarType) {
1284
1285 case PciBarTypeMem:
1286
1287 if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem32 &&
1288 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem32 &&
1289 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem64 &&
1290 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem64 ) {
1291 return FALSE;
1292 }
1293
1294 return TRUE;
1295
1296 case PciBarTypeIo:
1297 if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo32 &&
1298 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo16){
1299 return FALSE;
1300 }
1301
1302 return TRUE;
1303
1304 default:
1305 break;
1306 }
1307
1308 return FALSE;
1309 }
1310
1311 /**
1312 Set/Disable new attributes to a Root Bridge.
1313
1314 @param PciIoDevice Pci device instance.
1315 @param Attributes New attribute want to be set.
1316 @param Operation Set or Disable.
1317
1318 @retval EFI_UNSUPPORTED If root bridge does not support change attribute.
1319 @retval EFI_SUCCESS Successfully set new attributs.
1320
1321 **/
1322 EFI_STATUS
1323 ModifyRootBridgeAttributes (
1324 IN PCI_IO_DEVICE *PciIoDevice,
1325 IN UINT64 Attributes,
1326 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation
1327 )
1328 {
1329 UINT64 PciRootBridgeSupports;
1330 UINT64 PciRootBridgeAttributes;
1331 UINT64 NewPciRootBridgeAttributes;
1332 EFI_STATUS Status;
1333
1334 //
1335 // Get the current attributes of this PCI device's PCI Root Bridge
1336 //
1337 Status = PciIoDevice->PciRootBridgeIo->GetAttributes (
1338 PciIoDevice->PciRootBridgeIo,
1339 &PciRootBridgeSupports,
1340 &PciRootBridgeAttributes
1341 );
1342 if (EFI_ERROR (Status)) {
1343 return EFI_UNSUPPORTED;
1344 }
1345
1346 //
1347 // Mask off attributes not supported by PCI root bridge.
1348 //
1349 Attributes &= ~(UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |
1350 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |
1351 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
1352
1353 //
1354 // Record the new attribute of the Root Bridge
1355 //
1356 if (Operation == EfiPciIoAttributeOperationEnable) {
1357 NewPciRootBridgeAttributes = PciRootBridgeAttributes | Attributes;
1358 } else {
1359 NewPciRootBridgeAttributes = PciRootBridgeAttributes & (~Attributes);
1360 }
1361
1362 //
1363 // Call the PCI Root Bridge to attempt to modify the attributes
1364 //
1365 if ((NewPciRootBridgeAttributes ^ PciRootBridgeAttributes) != 0) {
1366
1367 Status = PciIoDevice->PciRootBridgeIo->SetAttributes (
1368 PciIoDevice->PciRootBridgeIo,
1369 NewPciRootBridgeAttributes,
1370 NULL,
1371 NULL
1372 );
1373 if (EFI_ERROR (Status)) {
1374 //
1375 // The PCI Root Bridge could not modify the attributes, so return the error.
1376 //
1377 return EFI_UNSUPPORTED;
1378 }
1379 }
1380
1381 //
1382 // Also update the attributes for this Root Bridge structure
1383 //
1384 PciIoDevice->Attributes = NewPciRootBridgeAttributes;
1385
1386 return EFI_SUCCESS;
1387 }
1388
1389 /**
1390 Check whether this device can be enable/disable to snoop.
1391
1392 @param PciIoDevice Pci device instance.
1393 @param Operation Enable/Disable.
1394
1395 @retval EFI_UNSUPPORTED Pci device is not GFX device or not support snoop.
1396 @retval EFI_SUCCESS Snoop can be supported.
1397
1398 **/
1399 EFI_STATUS
1400 SupportPaletteSnoopAttributes (
1401 IN PCI_IO_DEVICE *PciIoDevice,
1402 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation
1403 )
1404 {
1405 PCI_IO_DEVICE *Temp;
1406 UINT16 VGACommand;
1407
1408 //
1409 // Snoop attribute can be only modified by GFX
1410 //
1411 if (!IS_PCI_GFX (&PciIoDevice->Pci)) {
1412 return EFI_UNSUPPORTED;
1413 }
1414
1415 //
1416 // Get the boot VGA on the same segement
1417 //
1418 Temp = ActiveVGADeviceOnTheSameSegment (PciIoDevice);
1419
1420 if (Temp == NULL) {
1421 //
1422 // If there is no VGA device on the segement, set
1423 // this graphics card to decode the palette range
1424 //
1425 return EFI_SUCCESS;
1426 }
1427
1428 //
1429 // Check these two agents are on the same path
1430 //
1431 if (!PciDevicesOnTheSamePath (Temp, PciIoDevice)) {
1432 //
1433 // they are not on the same path, so snoop can be enabled or disabled
1434 //
1435 return EFI_SUCCESS;
1436 }
1437 //
1438 // Check if they are on the same bus
1439 //
1440 if (Temp->Parent == PciIoDevice->Parent) {
1441
1442 PCI_READ_COMMAND_REGISTER (Temp, &VGACommand);
1443
1444 //
1445 // If they are on the same bus, either one can
1446 // be set to snoop, the other set to decode
1447 //
1448 if ((VGACommand & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {
1449 //
1450 // VGA has set to snoop, so GFX can be only set to disable snoop
1451 //
1452 if (Operation == EfiPciIoAttributeOperationEnable) {
1453 return EFI_UNSUPPORTED;
1454 }
1455 } else {
1456 //
1457 // VGA has disabled to snoop, so GFX can be only enabled
1458 //
1459 if (Operation == EfiPciIoAttributeOperationDisable) {
1460 return EFI_UNSUPPORTED;
1461 }
1462 }
1463
1464 return EFI_SUCCESS;
1465 }
1466
1467 //
1468 // If they are on the same path but on the different bus
1469 // The first agent is set to snoop, the second one set to
1470 // decode
1471 //
1472
1473 if (Temp->BusNumber < PciIoDevice->BusNumber) {
1474 //
1475 // GFX should be set to decode
1476 //
1477 if (Operation == EfiPciIoAttributeOperationDisable) {
1478 PCI_ENABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);
1479 Temp->Attributes |= EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;
1480 } else {
1481 return EFI_UNSUPPORTED;
1482 }
1483
1484 } else {
1485 //
1486 // GFX should be set to snoop
1487 //
1488 if (Operation == EfiPciIoAttributeOperationEnable) {
1489 PCI_DISABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);
1490 Temp->Attributes &= (~(UINT64)EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);
1491 } else {
1492 return EFI_UNSUPPORTED;
1493 }
1494
1495 }
1496
1497 return EFI_SUCCESS;
1498 }
1499
1500 /**
1501 Performs an operation on the attributes that this PCI controller supports. The operations include
1502 getting the set of supported attributes, retrieving the current attributes, setting the current
1503 attributes, enabling attributes, and disabling attributes.
1504
1505 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1506 @param Operation The operation to perform on the attributes for this PCI controller.
1507 @param Attributes The mask of attributes that are used for Set, Enable, and Disable
1508 operations.
1509 @param Result A pointer to the result mask of attributes that are returned for the Get
1510 and Supported operations.
1511
1512 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.
1513 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1514 @retval EFI_UNSUPPORTED one or more of the bits set in
1515 Attributes are not supported by this PCI controller or one of
1516 its parent bridges when Operation is Set, Enable or Disable.
1517
1518 **/
1519 EFI_STATUS
1520 EFIAPI
1521 PciIoAttributes (
1522 IN EFI_PCI_IO_PROTOCOL * This,
1523 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
1524 IN UINT64 Attributes,
1525 OUT UINT64 *Result OPTIONAL
1526 )
1527 {
1528 EFI_STATUS Status;
1529
1530 PCI_IO_DEVICE *PciIoDevice;
1531 PCI_IO_DEVICE *UpStreamBridge;
1532 PCI_IO_DEVICE *Temp;
1533
1534 UINT64 Supports;
1535 UINT64 UpStreamAttributes;
1536 UINT16 BridgeControl;
1537 UINT16 Command;
1538
1539 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1540
1541 switch (Operation) {
1542 case EfiPciIoAttributeOperationGet:
1543 if (Result == NULL) {
1544 return EFI_INVALID_PARAMETER;
1545 }
1546
1547 *Result = PciIoDevice->Attributes;
1548 return EFI_SUCCESS;
1549
1550 case EfiPciIoAttributeOperationSupported:
1551 if (Result == NULL) {
1552 return EFI_INVALID_PARAMETER;
1553 }
1554
1555 *Result = PciIoDevice->Supports;
1556 return EFI_SUCCESS;
1557
1558 case EfiPciIoAttributeOperationSet:
1559 Status = PciIoDevice->PciIo.Attributes (
1560 &(PciIoDevice->PciIo),
1561 EfiPciIoAttributeOperationEnable,
1562 Attributes,
1563 NULL
1564 );
1565 if (EFI_ERROR (Status)) {
1566 return EFI_UNSUPPORTED;
1567 }
1568
1569 Status = PciIoDevice->PciIo.Attributes (
1570 &(PciIoDevice->PciIo),
1571 EfiPciIoAttributeOperationDisable,
1572 (~Attributes) & (PciIoDevice->Supports),
1573 NULL
1574 );
1575 if (EFI_ERROR (Status)) {
1576 return EFI_UNSUPPORTED;
1577 }
1578
1579 return EFI_SUCCESS;
1580
1581 case EfiPciIoAttributeOperationEnable:
1582 case EfiPciIoAttributeOperationDisable:
1583 break;
1584
1585 default:
1586 return EFI_INVALID_PARAMETER;
1587 }
1588 //
1589 // Just a trick for ENABLE attribute
1590 // EFI_PCI_DEVICE_ENABLE is not defined in UEFI spec, which is the internal usage.
1591 // So, this logic doesn't confrom to UEFI spec, which should be removed.
1592 // But this trick logic is still kept for some binary drivers that depend on it.
1593 //
1594 if ((Attributes & EFI_PCI_DEVICE_ENABLE) == EFI_PCI_DEVICE_ENABLE) {
1595 Attributes &= (PciIoDevice->Supports);
1596
1597 //
1598 // Raise the EFI_P_PC_ENABLE Status code
1599 //
1600 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
1601 EFI_PROGRESS_CODE,
1602 EFI_IO_BUS_PCI | EFI_P_PC_ENABLE,
1603 PciIoDevice->DevicePath
1604 );
1605 }
1606
1607 //
1608 // Check VGA and VGA16, they can not be set at the same time
1609 //
1610 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO)) != 0) {
1611 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {
1612 return EFI_UNSUPPORTED;
1613 }
1614 }
1615
1616 //
1617 // If no attributes can be supported, then return.
1618 // Otherwise, set the attributes that it can support.
1619 //
1620 Supports = (PciIoDevice->Supports) & Attributes;
1621 if (Supports != Attributes) {
1622 return EFI_UNSUPPORTED;
1623 }
1624
1625 //
1626 // For Root Bridge, just call RootBridgeIo to set attributes;
1627 //
1628 if (PciIoDevice->Parent == NULL) {
1629 Status = ModifyRootBridgeAttributes (PciIoDevice, Attributes, Operation);
1630 return Status;
1631 }
1632
1633 Command = 0;
1634 BridgeControl = 0;
1635
1636 //
1637 // For PPB & P2C, set relevant attribute bits
1638 //
1639 if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
1640
1641 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {
1642 BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA;
1643 }
1644
1645 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_ISA_IO) != 0) {
1646 BridgeControl |= EFI_PCI_BRIDGE_CONTROL_ISA;
1647 }
1648
1649 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {
1650 Command |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;
1651 }
1652
1653 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {
1654 BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA_16;
1655 }
1656
1657 } else {
1658 //
1659 // Do with the attributes on VGA
1660 // Only for VGA's legacy resource, we just can enable once.
1661 //
1662 if ((Attributes &
1663 (EFI_PCI_IO_ATTRIBUTE_VGA_IO |
1664 EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 |
1665 EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY)) != 0) {
1666 //
1667 // Check if a VGA has been enabled before enabling a new one
1668 //
1669 if (Operation == EfiPciIoAttributeOperationEnable) {
1670 //
1671 // Check if there have been an active VGA device on the same segment
1672 //
1673 Temp = ActiveVGADeviceOnTheSameSegment (PciIoDevice);
1674 if (Temp != NULL && Temp != PciIoDevice) {
1675 //
1676 // An active VGA has been detected, so can not enable another
1677 //
1678 return EFI_UNSUPPORTED;
1679 }
1680 }
1681 }
1682
1683 //
1684 // Do with the attributes on GFX
1685 //
1686 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {
1687
1688 if (Operation == EfiPciIoAttributeOperationEnable) {
1689 //
1690 // Check if snoop can be enabled in current configuration
1691 //
1692 Status = SupportPaletteSnoopAttributes (PciIoDevice, Operation);
1693
1694 if (EFI_ERROR (Status)) {
1695
1696 //
1697 // Enable operation is forbidden, so mask the bit in attributes
1698 // so as to keep consistent with the actual Status
1699 //
1700 // Attributes &= (~EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO);
1701 //
1702 //
1703 //
1704 return EFI_UNSUPPORTED;
1705
1706 }
1707 }
1708
1709 //
1710 // It can be supported, so get ready to set the bit
1711 //
1712 Command |= EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;
1713 }
1714 }
1715
1716 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_IO) != 0) {
1717 Command |= EFI_PCI_COMMAND_IO_SPACE;
1718 }
1719
1720 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_MEMORY) != 0) {
1721 Command |= EFI_PCI_COMMAND_MEMORY_SPACE;
1722 }
1723
1724 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_BUS_MASTER) != 0) {
1725 Command |= EFI_PCI_COMMAND_BUS_MASTER;
1726 }
1727 //
1728 // The upstream bridge should be also set to revelant attribute
1729 // expect for IO, Mem and BusMaster
1730 //
1731 UpStreamAttributes = Attributes &
1732 (~(EFI_PCI_IO_ATTRIBUTE_IO |
1733 EFI_PCI_IO_ATTRIBUTE_MEMORY |
1734 EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
1735 )
1736 );
1737 UpStreamBridge = PciIoDevice->Parent;
1738
1739 if (Operation == EfiPciIoAttributeOperationEnable) {
1740 //
1741 // Enable relevant attributes to command register and bridge control register
1742 //
1743 Status = PCI_ENABLE_COMMAND_REGISTER (PciIoDevice, Command);
1744 if (BridgeControl != 0) {
1745 Status = PCI_ENABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);
1746 }
1747
1748 PciIoDevice->Attributes |= Attributes;
1749
1750 //
1751 // Enable attributes of the upstream bridge
1752 //
1753 Status = UpStreamBridge->PciIo.Attributes (
1754 &(UpStreamBridge->PciIo),
1755 EfiPciIoAttributeOperationEnable,
1756 UpStreamAttributes,
1757 NULL
1758 );
1759 } else {
1760
1761 //
1762 // Disable relevant attributes to command register and bridge control register
1763 //
1764 Status = PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, Command);
1765 if (BridgeControl != 0) {
1766 Status = PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);
1767 }
1768
1769 PciIoDevice->Attributes &= (~Attributes);
1770 Status = EFI_SUCCESS;
1771
1772 }
1773
1774 if (EFI_ERROR (Status)) {
1775 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
1776 EFI_ERROR_CODE | EFI_ERROR_MINOR,
1777 EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,
1778 PciIoDevice->DevicePath
1779 );
1780 }
1781
1782 return Status;
1783 }
1784
1785 /**
1786 Retrieve the AddrTranslationOffset from RootBridgeIo for the
1787 specified range.
1788
1789 @param RootBridgeIo Root Bridge IO instance.
1790 @param AddrRangeMin The base address of the MMIO.
1791 @param AddrLen The length of the MMIO.
1792
1793 @retval The AddrTranslationOffset from RootBridgeIo for the
1794 specified range, or (UINT64) -1 if the range is not
1795 found in RootBridgeIo.
1796 **/
1797 UINT64
1798 GetMmioAddressTranslationOffset (
1799 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *RootBridgeIo,
1800 UINT64 AddrRangeMin,
1801 UINT64 AddrLen
1802 )
1803 {
1804 EFI_STATUS Status;
1805 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;
1806
1807 Status = RootBridgeIo->Configuration (
1808 RootBridgeIo,
1809 (VOID **) &Configuration
1810 );
1811 if (EFI_ERROR (Status)) {
1812 return (UINT64) -1;
1813 }
1814
1815 while (Configuration->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
1816 if ((Configuration->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) &&
1817 (Configuration->AddrRangeMin <= AddrRangeMin) &&
1818 (Configuration->AddrRangeMin + Configuration->AddrLen >= AddrRangeMin + AddrLen)
1819 ) {
1820 return Configuration->AddrTranslationOffset;
1821 }
1822 Configuration++;
1823 }
1824
1825 //
1826 // The resource occupied by BAR should be in the range reported by RootBridge.
1827 //
1828 ASSERT (FALSE);
1829 return (UINT64) -1;
1830 }
1831
1832 /**
1833 Gets the attributes that this PCI controller supports setting on a BAR using
1834 SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.
1835
1836 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1837 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
1838 base address for resource range. The legal range for this field is 0..5.
1839 @param Supports A pointer to the mask of attributes that this PCI controller supports
1840 setting for this BAR with SetBarAttributes().
1841 @param Resources A pointer to the ACPI 2.0 resource descriptors that describe the current
1842 configuration of this BAR of the PCI controller.
1843
1844 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI
1845 controller supports are returned in Supports. If Resources
1846 is not NULL, then the ACPI 2.0 resource descriptors that the PCI
1847 controller is currently using are returned in Resources.
1848 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
1849 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
1850 @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate
1851 Resources.
1852
1853 **/
1854 EFI_STATUS
1855 EFIAPI
1856 PciIoGetBarAttributes (
1857 IN EFI_PCI_IO_PROTOCOL * This,
1858 IN UINT8 BarIndex,
1859 OUT UINT64 *Supports, OPTIONAL
1860 OUT VOID **Resources OPTIONAL
1861 )
1862 {
1863 PCI_IO_DEVICE *PciIoDevice;
1864 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
1865 EFI_ACPI_END_TAG_DESCRIPTOR *End;
1866
1867 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1868
1869 if (Supports == NULL && Resources == NULL) {
1870 return EFI_INVALID_PARAMETER;
1871 }
1872
1873 if ((BarIndex >= PCI_MAX_BAR) || (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeUnknown)) {
1874 return EFI_UNSUPPORTED;
1875 }
1876
1877 //
1878 // This driver does not support modifications to the WRITE_COMBINE or
1879 // CACHED attributes for BAR ranges.
1880 //
1881 if (Supports != NULL) {
1882 *Supports = PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED & EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE;
1883 }
1884
1885 if (Resources != NULL) {
1886 Descriptor = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
1887 if (Descriptor == NULL) {
1888 return EFI_OUT_OF_RESOURCES;
1889 }
1890
1891 *Resources = Descriptor;
1892
1893 Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1894 Descriptor->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
1895 Descriptor->AddrRangeMin = PciIoDevice->PciBar[BarIndex].BaseAddress;
1896 Descriptor->AddrLen = PciIoDevice->PciBar[BarIndex].Length;
1897 Descriptor->AddrRangeMax = PciIoDevice->PciBar[BarIndex].Alignment;
1898
1899 switch (PciIoDevice->PciBar[BarIndex].BarType) {
1900 case PciBarTypeIo16:
1901 case PciBarTypeIo32:
1902 //
1903 // Io
1904 //
1905 Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
1906 break;
1907
1908 case PciBarTypePMem32:
1909 //
1910 // prefechable
1911 //
1912 Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
1913 //
1914 // Fall through
1915 //
1916 case PciBarTypeMem32:
1917 //
1918 // Mem
1919 //
1920 Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1921 //
1922 // 32 bit
1923 //
1924 Descriptor->AddrSpaceGranularity = 32;
1925 break;
1926
1927 case PciBarTypePMem64:
1928 //
1929 // prefechable
1930 //
1931 Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
1932 //
1933 // Fall through
1934 //
1935 case PciBarTypeMem64:
1936 //
1937 // Mem
1938 //
1939 Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1940 //
1941 // 64 bit
1942 //
1943 Descriptor->AddrSpaceGranularity = 64;
1944 break;
1945
1946 default:
1947 break;
1948 }
1949
1950 //
1951 // put the checksum
1952 //
1953 End = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Descriptor + 1);
1954 End->Desc = ACPI_END_TAG_DESCRIPTOR;
1955 End->Checksum = 0;
1956
1957 //
1958 // Get the Address Translation Offset
1959 //
1960 if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
1961 Descriptor->AddrTranslationOffset = GetMmioAddressTranslationOffset (
1962 PciIoDevice->PciRootBridgeIo,
1963 Descriptor->AddrRangeMin,
1964 Descriptor->AddrLen
1965 );
1966 if (Descriptor->AddrTranslationOffset == (UINT64) -1) {
1967 FreePool (Descriptor);
1968 return EFI_UNSUPPORTED;
1969 }
1970 }
1971 }
1972
1973 return EFI_SUCCESS;
1974 }
1975
1976 /**
1977 Sets the attributes for a range of a BAR on a PCI controller.
1978
1979 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1980 @param Attributes The mask of attributes to set for the resource range specified by
1981 BarIndex, Offset, and Length.
1982 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
1983 base address for resource range. The legal range for this field is 0..5.
1984 @param Offset A pointer to the BAR relative base address of the resource range to be
1985 modified by the attributes specified by Attributes.
1986 @param Length A pointer to the length of the resource range to be modified by the
1987 attributes specified by Attributes.
1988
1989 @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource
1990 range specified by BarIndex, Offset, and Length were
1991 set on the PCI controller, and the actual resource range is returned
1992 in Offset and Length.
1993 @retval EFI_INVALID_PARAMETER Offset or Length is NULL.
1994 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
1995 @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the
1996 resource range specified by BarIndex, Offset, and
1997 Length.
1998
1999 **/
2000 EFI_STATUS
2001 EFIAPI
2002 PciIoSetBarAttributes (
2003 IN EFI_PCI_IO_PROTOCOL *This,
2004 IN UINT64 Attributes,
2005 IN UINT8 BarIndex,
2006 IN OUT UINT64 *Offset,
2007 IN OUT UINT64 *Length
2008 )
2009 {
2010 EFI_STATUS Status;
2011 PCI_IO_DEVICE *PciIoDevice;
2012 UINT64 NonRelativeOffset;
2013 UINT64 Supports;
2014
2015 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
2016
2017 //
2018 // Make sure Offset and Length are not NULL
2019 //
2020 if (Offset == NULL || Length == NULL) {
2021 return EFI_INVALID_PARAMETER;
2022 }
2023
2024 if (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeUnknown) {
2025 return EFI_UNSUPPORTED;
2026 }
2027 //
2028 // This driver does not support setting the WRITE_COMBINE or the CACHED attributes.
2029 // If Attributes is not 0, then return EFI_UNSUPPORTED.
2030 //
2031 Supports = PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED & EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE;
2032
2033 if (Attributes != (Attributes & Supports)) {
2034 return EFI_UNSUPPORTED;
2035 }
2036 //
2037 // Attributes must be supported. Make sure the BAR range describd by BarIndex, Offset, and
2038 // Length are valid for this PCI device.
2039 //
2040 NonRelativeOffset = *Offset;
2041 Status = PciIoVerifyBarAccess (
2042 PciIoDevice,
2043 BarIndex,
2044 PciBarTypeMem,
2045 EfiPciIoWidthUint8,
2046 (UINT32) *Length,
2047 &NonRelativeOffset
2048 );
2049 if (EFI_ERROR (Status)) {
2050 return EFI_UNSUPPORTED;
2051 }
2052
2053 return EFI_SUCCESS;
2054 }
2055
2056 /**
2057 Program parent bridge's attribute recurrently.
2058
2059 @param PciIoDevice Child Pci device instance
2060 @param Operation The operation to perform on the attributes for this PCI controller.
2061 @param Attributes The mask of attributes that are used for Set, Enable, and Disable
2062 operations.
2063
2064 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.
2065 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
2066 @retval EFI_UNSUPPORTED one or more of the bits set in
2067 Attributes are not supported by this PCI controller or one of
2068 its parent bridges when Operation is Set, Enable or Disable.
2069
2070 **/
2071 EFI_STATUS
2072 UpStreamBridgesAttributes (
2073 IN PCI_IO_DEVICE *PciIoDevice,
2074 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
2075 IN UINT64 Attributes
2076 )
2077 {
2078 PCI_IO_DEVICE *Parent;
2079 EFI_PCI_IO_PROTOCOL *PciIo;
2080
2081 Parent = PciIoDevice->Parent;
2082
2083 while (Parent != NULL && IS_PCI_BRIDGE (&Parent->Pci)) {
2084
2085 //
2086 // Get the PciIo Protocol
2087 //
2088 PciIo = &Parent->PciIo;
2089
2090 PciIo->Attributes (PciIo, Operation, Attributes, NULL);
2091
2092 Parent = Parent->Parent;
2093 }
2094
2095 return EFI_SUCCESS;
2096 }
2097
2098 /**
2099 Test whether two Pci devices has same parent bridge.
2100
2101 @param PciDevice1 The first pci device for testing.
2102 @param PciDevice2 The second pci device for testing.
2103
2104 @retval TRUE Two Pci device has the same parent bridge.
2105 @retval FALSE Two Pci device has not the same parent bridge.
2106
2107 **/
2108 BOOLEAN
2109 PciDevicesOnTheSamePath (
2110 IN PCI_IO_DEVICE *PciDevice1,
2111 IN PCI_IO_DEVICE *PciDevice2
2112 )
2113 {
2114 BOOLEAN Existed1;
2115 BOOLEAN Existed2;
2116
2117 if (PciDevice1->Parent == PciDevice2->Parent) {
2118 return TRUE;
2119 }
2120
2121 Existed1 = PciDeviceExisted (PciDevice1->Parent, PciDevice2);
2122 Existed2 = PciDeviceExisted (PciDevice2->Parent, PciDevice1);
2123
2124 return (BOOLEAN) (Existed1 || Existed2);
2125 }
2126
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