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1 /** @file
2 EFI PCI IO protocol functions implementation for PCI Bus module.
3
4 Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include "PciBus.h"
16
17 //
18 // Pci Io Protocol Interface
19 //
20 EFI_PCI_IO_PROTOCOL mPciIoInterface = {
21 PciIoPollMem,
22 PciIoPollIo,
23 {
24 PciIoMemRead,
25 PciIoMemWrite
26 },
27 {
28 PciIoIoRead,
29 PciIoIoWrite
30 },
31 {
32 PciIoConfigRead,
33 PciIoConfigWrite
34 },
35 PciIoCopyMem,
36 PciIoMap,
37 PciIoUnmap,
38 PciIoAllocateBuffer,
39 PciIoFreeBuffer,
40 PciIoFlush,
41 PciIoGetLocation,
42 PciIoAttributes,
43 PciIoGetBarAttributes,
44 PciIoSetBarAttributes,
45 0,
46 NULL
47 };
48
49 /**
50 Report a error Status code of PCI bus driver controller.
51
52 @param PciIoDevice Pci device instance.
53 @param Code Status code value.
54
55 **/
56 EFI_STATUS
57 ReportErrorStatusCode (
58 IN PCI_IO_DEVICE *PciIoDevice,
59 IN EFI_STATUS_CODE_VALUE Code
60 )
61 {
62 return REPORT_STATUS_CODE_WITH_DEVICE_PATH (
63 EFI_ERROR_CODE | EFI_ERROR_MINOR,
64 Code,
65 PciIoDevice->DevicePath
66 );
67 }
68
69 /**
70 Initializes a PCI I/O Instance.
71
72 @param PciIoDevice Pci device instance.
73
74 **/
75 VOID
76 InitializePciIoInstance (
77 IN PCI_IO_DEVICE *PciIoDevice
78 )
79 {
80 CopyMem (&PciIoDevice->PciIo, &mPciIoInterface, sizeof (EFI_PCI_IO_PROTOCOL));
81 }
82
83 /**
84 Verifies access to a PCI Base Address Register (BAR).
85
86 @param PciIoDevice Pci device instance.
87 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
88 base address for the memory or I/O operation to perform.
89 @param Type Operation type could be memory or I/O.
90 @param Width Signifies the width of the memory or I/O operations.
91 @param Count The number of memory or I/O operations to perform.
92 @param Offset The offset within the PCI configuration space for the PCI controller.
93
94 @retval EFI_INVALID_PARAMETER Invalid Width/BarIndex or Bar type.
95 @retval EFI_SUCCESS Successfully verified.
96
97 **/
98 EFI_STATUS
99 PciIoVerifyBarAccess (
100 IN PCI_IO_DEVICE *PciIoDevice,
101 IN UINT8 BarIndex,
102 IN PCI_BAR_TYPE Type,
103 IN IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
104 IN IN UINTN Count,
105 IN UINT64 *Offset
106 )
107 {
108 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
109 return EFI_INVALID_PARAMETER;
110 }
111
112 if (BarIndex == EFI_PCI_IO_PASS_THROUGH_BAR) {
113 return EFI_SUCCESS;
114 }
115
116 //
117 // BarIndex 0-5 is legal
118 //
119 if (BarIndex >= PCI_MAX_BAR) {
120 return EFI_INVALID_PARAMETER;
121 }
122
123 if (!CheckBarType (PciIoDevice, BarIndex, Type)) {
124 return EFI_INVALID_PARAMETER;
125 }
126
127 //
128 // If Width is EfiPciIoWidthFifoUintX then convert to EfiPciIoWidthUintX
129 // If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX
130 //
131 if (Width >= EfiPciIoWidthFifoUint8 && Width <= EfiPciIoWidthFifoUint64) {
132 Count = 1;
133 }
134
135 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & 0x03);
136
137 if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PciIoDevice->PciBar[BarIndex].Length) {
138 return EFI_INVALID_PARAMETER;
139 }
140
141 *Offset = *Offset + PciIoDevice->PciBar[BarIndex].BaseAddress;
142
143 return EFI_SUCCESS;
144 }
145
146 /**
147 Verifies access to a PCI Configuration Header.
148
149 @param PciIoDevice Pci device instance.
150 @param Width Signifies the width of the memory or I/O operations.
151 @param Count The number of memory or I/O operations to perform.
152 @param Offset The offset within the PCI configuration space for the PCI controller.
153
154 @retval EFI_INVALID_PARAMETER Invalid Width
155 @retval EFI_UNSUPPORTED Offset overflowed.
156 @retval EFI_SUCCESS Successfully verified.
157
158 **/
159 EFI_STATUS
160 PciIoVerifyConfigAccess (
161 IN PCI_IO_DEVICE *PciIoDevice,
162 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
163 IN UINTN Count,
164 IN UINT64 *Offset
165 )
166 {
167 UINT64 ExtendOffset;
168
169 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
170 return EFI_INVALID_PARAMETER;
171 }
172
173 //
174 // If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX
175 //
176 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & 0x03);
177
178 if (PciIoDevice->IsPciExp) {
179 if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PCI_EXP_MAX_CONFIG_OFFSET) {
180 return EFI_UNSUPPORTED;
181 }
182
183 ExtendOffset = LShiftU64 (*Offset, 32);
184 *Offset = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, 0);
185 *Offset = (*Offset) | ExtendOffset;
186
187 } else {
188 if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PCI_MAX_CONFIG_OFFSET) {
189 return EFI_UNSUPPORTED;
190 }
191
192 *Offset = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, *Offset);
193 }
194
195 return EFI_SUCCESS;
196 }
197
198 /**
199 Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is
200 satisfied or after a defined duration.
201
202 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
203 @param Width Signifies the width of the memory or I/O operations.
204 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
205 base address for the memory operation to perform.
206 @param Offset The offset within the selected BAR to start the memory operation.
207 @param Mask Mask used for the polling criteria.
208 @param Value The comparison value used for the polling exit criteria.
209 @param Delay The number of 100 ns units to poll.
210 @param Result Pointer to the last value read from the memory location.
211
212 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
213 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
214 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.
215 @retval EFI_TIMEOUT Delay expired before a match occurred.
216 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
217 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
218
219 **/
220 EFI_STATUS
221 EFIAPI
222 PciIoPollMem (
223 IN EFI_PCI_IO_PROTOCOL *This,
224 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
225 IN UINT8 BarIndex,
226 IN UINT64 Offset,
227 IN UINT64 Mask,
228 IN UINT64 Value,
229 IN UINT64 Delay,
230 OUT UINT64 *Result
231 )
232 {
233 EFI_STATUS Status;
234 PCI_IO_DEVICE *PciIoDevice;
235
236 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
237
238 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
239 return EFI_INVALID_PARAMETER;
240 }
241
242 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, 1, &Offset);
243 if (EFI_ERROR (Status)) {
244 return EFI_UNSUPPORTED;
245 }
246
247 if (Width > EfiPciIoWidthUint64) {
248 return EFI_INVALID_PARAMETER;
249 }
250
251 //
252 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
253 //
254 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
255 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
256 Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);
257 if (EFI_ERROR (Status)) {
258 return Status;
259 }
260 if ((*Result & Mask) == Value || Delay == 0) {
261 return EFI_SUCCESS;
262 }
263 do {
264 //
265 // Stall 10 us = 100 * 100ns
266 //
267 gBS->Stall (10);
268
269 Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);
270 if (EFI_ERROR (Status)) {
271 return Status;
272 }
273 if ((*Result & Mask) == Value) {
274 return EFI_SUCCESS;
275 }
276 if (Delay <= 100) {
277 return EFI_TIMEOUT;
278 }
279 Delay -= 100;
280 } while (TRUE);
281 }
282 }
283
284 Status = PciIoDevice->PciRootBridgeIo->PollMem (
285 PciIoDevice->PciRootBridgeIo,
286 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
287 Offset,
288 Mask,
289 Value,
290 Delay,
291 Result
292 );
293
294 if (EFI_ERROR (Status)) {
295 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
296 }
297
298 return Status;
299 }
300
301 /**
302 Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is
303 satisfied or after a defined duration.
304
305 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
306 @param Width Signifies the width of the memory or I/O operations.
307 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
308 base address for the memory operation to perform.
309 @param Offset The offset within the selected BAR to start the memory operation.
310 @param Mask Mask used for the polling criteria.
311 @param Value The comparison value used for the polling exit criteria.
312 @param Delay The number of 100 ns units to poll.
313 @param Result Pointer to the last value read from the memory location.
314
315 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
316 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
317 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.
318 @retval EFI_TIMEOUT Delay expired before a match occurred.
319 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
320 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
321
322 **/
323 EFI_STATUS
324 EFIAPI
325 PciIoPollIo (
326 IN EFI_PCI_IO_PROTOCOL *This,
327 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
328 IN UINT8 BarIndex,
329 IN UINT64 Offset,
330 IN UINT64 Mask,
331 IN UINT64 Value,
332 IN UINT64 Delay,
333 OUT UINT64 *Result
334 )
335 {
336 EFI_STATUS Status;
337 PCI_IO_DEVICE *PciIoDevice;
338
339 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
340
341 if (Width < 0 || Width > EfiPciIoWidthUint64) {
342 return EFI_INVALID_PARAMETER;
343 }
344
345 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, 1, &Offset);
346 if (EFI_ERROR (Status)) {
347 return EFI_UNSUPPORTED;
348 }
349
350 //
351 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
352 //
353 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
354 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
355 Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);
356 if (EFI_ERROR (Status)) {
357 return Status;
358 }
359 if ((*Result & Mask) == Value || Delay == 0) {
360 return EFI_SUCCESS;
361 }
362 do {
363 //
364 // Stall 10 us = 100 * 100ns
365 //
366 gBS->Stall (10);
367
368 Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);
369 if (EFI_ERROR (Status)) {
370 return Status;
371 }
372 if ((*Result & Mask) == Value) {
373 return EFI_SUCCESS;
374 }
375 if (Delay <= 100) {
376 return EFI_TIMEOUT;
377 }
378 Delay -= 100;
379 } while (TRUE);
380 }
381 }
382
383 Status = PciIoDevice->PciRootBridgeIo->PollIo (
384 PciIoDevice->PciRootBridgeIo,
385 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
386 Offset,
387 Mask,
388 Value,
389 Delay,
390 Result
391 );
392
393 if (EFI_ERROR (Status)) {
394 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
395 }
396
397 return Status;
398 }
399
400 /**
401 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
402
403 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
404 @param Width Signifies the width of the memory or I/O operations.
405 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
406 base address for the memory or I/O operation to perform.
407 @param Offset The offset within the selected BAR to start the memory or I/O operation.
408 @param Count The number of memory or I/O operations to perform.
409 @param Buffer For read operations, the destination buffer to store the results. For write
410 operations, the source buffer to write data from.
411
412 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
413 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
414 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
415 valid for the PCI BAR specified by BarIndex.
416 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
417 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
418
419 **/
420 EFI_STATUS
421 EFIAPI
422 PciIoMemRead (
423 IN EFI_PCI_IO_PROTOCOL *This,
424 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
425 IN UINT8 BarIndex,
426 IN UINT64 Offset,
427 IN UINTN Count,
428 IN OUT VOID *Buffer
429 )
430 {
431 EFI_STATUS Status;
432 PCI_IO_DEVICE *PciIoDevice;
433
434 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
435
436 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
437 return EFI_INVALID_PARAMETER;
438 }
439
440 if (Buffer == NULL) {
441 return EFI_INVALID_PARAMETER;
442 }
443
444 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, Count, &Offset);
445 if (EFI_ERROR (Status)) {
446 return EFI_UNSUPPORTED;
447 }
448
449 //
450 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
451 //
452 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
453 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
454 Count *= (UINTN)(1 << (Width & 0x03));
455 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
456 }
457 }
458
459
460 Status = PciIoDevice->PciRootBridgeIo->Mem.Read (
461 PciIoDevice->PciRootBridgeIo,
462 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
463 Offset,
464 Count,
465 Buffer
466 );
467
468 if (EFI_ERROR (Status)) {
469 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR);
470 }
471
472 return Status;
473 }
474
475 /**
476 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
477
478 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
479 @param Width Signifies the width of the memory or I/O operations.
480 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
481 base address for the memory or I/O operation to perform.
482 @param Offset The offset within the selected BAR to start the memory or I/O operation.
483 @param Count The number of memory or I/O operations to perform.
484 @param Buffer For read operations, the destination buffer to store the results. For write
485 operations, the source buffer to write data from.
486
487 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
488 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
489 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
490 valid for the PCI BAR specified by BarIndex.
491 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
492 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
493
494 **/
495 EFI_STATUS
496 EFIAPI
497 PciIoMemWrite (
498 IN EFI_PCI_IO_PROTOCOL *This,
499 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
500 IN UINT8 BarIndex,
501 IN UINT64 Offset,
502 IN UINTN Count,
503 IN OUT VOID *Buffer
504 )
505 {
506 EFI_STATUS Status;
507 PCI_IO_DEVICE *PciIoDevice;
508
509 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
510
511 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
512 return EFI_INVALID_PARAMETER;
513 }
514
515 if (Buffer == NULL) {
516 return EFI_INVALID_PARAMETER;
517 }
518
519 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, Count, &Offset);
520 if (EFI_ERROR (Status)) {
521 return EFI_UNSUPPORTED;
522 }
523
524 //
525 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
526 //
527 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
528 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
529 Count *= (UINTN)(1 << (Width & 0x03));
530 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
531 }
532 }
533
534 Status = PciIoDevice->PciRootBridgeIo->Mem.Write (
535 PciIoDevice->PciRootBridgeIo,
536 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
537 Offset,
538 Count,
539 Buffer
540 );
541
542 if (EFI_ERROR (Status)) {
543 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR);
544 }
545
546 return Status;
547 }
548
549 /**
550 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
551
552 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
553 @param Width Signifies the width of the memory or I/O operations.
554 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
555 base address for the memory or I/O operation to perform.
556 @param Offset The offset within the selected BAR to start the memory or I/O operation.
557 @param Count The number of memory or I/O operations to perform.
558 @param Buffer For read operations, the destination buffer to store the results. For write
559 operations, the source buffer to write data from.
560
561 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
562 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
563 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
564 valid for the PCI BAR specified by BarIndex.
565 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
566 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
567
568 **/
569 EFI_STATUS
570 EFIAPI
571 PciIoIoRead (
572 IN EFI_PCI_IO_PROTOCOL *This,
573 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
574 IN UINT8 BarIndex,
575 IN UINT64 Offset,
576 IN UINTN Count,
577 IN OUT VOID *Buffer
578 )
579 {
580 EFI_STATUS Status;
581 PCI_IO_DEVICE *PciIoDevice;
582
583 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
584
585 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
586 return EFI_INVALID_PARAMETER;
587 }
588
589 if (Buffer == NULL) {
590 return EFI_INVALID_PARAMETER;
591 }
592
593 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, Count, &Offset);
594 if (EFI_ERROR (Status)) {
595 return EFI_UNSUPPORTED;
596 }
597
598 //
599 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
600 //
601 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
602 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
603 Count *= (UINTN)(1 << (Width & 0x03));
604 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
605 }
606 }
607
608 Status = PciIoDevice->PciRootBridgeIo->Io.Read (
609 PciIoDevice->PciRootBridgeIo,
610 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
611 Offset,
612 Count,
613 Buffer
614 );
615
616 if (EFI_ERROR (Status)) {
617 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR);
618 }
619
620 return Status;
621 }
622
623 /**
624 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
625
626 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
627 @param Width Signifies the width of the memory or I/O operations.
628 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
629 base address for the memory or I/O operation to perform.
630 @param Offset The offset within the selected BAR to start the memory or I/O operation.
631 @param Count The number of memory or I/O operations to perform.
632 @param Buffer For read operations, the destination buffer to store the results. For write
633 operations, the source buffer to write data from.
634
635 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
636 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
637 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
638 valid for the PCI BAR specified by BarIndex.
639 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
640 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
641
642 **/
643 EFI_STATUS
644 EFIAPI
645 PciIoIoWrite (
646 IN EFI_PCI_IO_PROTOCOL *This,
647 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
648 IN UINT8 BarIndex,
649 IN UINT64 Offset,
650 IN UINTN Count,
651 IN OUT VOID *Buffer
652 )
653 {
654 EFI_STATUS Status;
655 PCI_IO_DEVICE *PciIoDevice;
656
657 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
658
659 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
660 return EFI_INVALID_PARAMETER;
661 }
662
663 if (Buffer == NULL) {
664 return EFI_INVALID_PARAMETER;
665 }
666
667 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, Count, &Offset);
668 if (EFI_ERROR (Status)) {
669 return EFI_UNSUPPORTED;
670 }
671
672 //
673 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
674 //
675 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
676 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
677 Count *= (UINTN)(1 << (Width & 0x03));
678 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
679 }
680 }
681
682 Status = PciIoDevice->PciRootBridgeIo->Io.Write (
683 PciIoDevice->PciRootBridgeIo,
684 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
685 Offset,
686 Count,
687 Buffer
688 );
689
690 if (EFI_ERROR (Status)) {
691 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR);
692 }
693
694 return Status;
695 }
696
697 /**
698 Enable a PCI driver to access PCI controller registers in PCI configuration space.
699
700 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
701 @param Width Signifies the width of the memory operations.
702 @param Offset The offset within the PCI configuration space for the PCI controller.
703 @param Count The number of PCI configuration operations to perform.
704 @param Buffer For read operations, the destination buffer to store the results. For write
705 operations, the source buffer to write data from.
706
707
708 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
709 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
710 valid for the PCI configuration header of the PCI controller.
711 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
712 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
713
714 **/
715 EFI_STATUS
716 EFIAPI
717 PciIoConfigRead (
718 IN EFI_PCI_IO_PROTOCOL *This,
719 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
720 IN UINT32 Offset,
721 IN UINTN Count,
722 IN OUT VOID *Buffer
723 )
724 {
725 EFI_STATUS Status;
726 PCI_IO_DEVICE *PciIoDevice;
727 UINT64 Address;
728
729 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
730
731 Address = Offset;
732 Status = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);
733 if (EFI_ERROR (Status)) {
734 return Status;
735 }
736
737 //
738 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
739 //
740 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
741 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
742 Count *= (UINTN)(1 << (Width & 0x03));
743 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
744 }
745 }
746
747 Status = PciIoDevice->PciRootBridgeIo->Pci.Read (
748 PciIoDevice->PciRootBridgeIo,
749 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
750 Address,
751 Count,
752 Buffer
753 );
754
755 if (EFI_ERROR (Status)) {
756 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR);
757 }
758
759 return Status;
760 }
761
762 /**
763 Enable a PCI driver to access PCI controller registers in PCI configuration space.
764
765 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
766 @param Width Signifies the width of the memory operations.
767 @param Offset The offset within the PCI configuration space for the PCI controller.
768 @param Count The number of PCI configuration operations to perform.
769 @param Buffer For read operations, the destination buffer to store the results. For write
770 operations, the source buffer to write data from.
771
772
773 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
774 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
775 valid for the PCI configuration header of the PCI controller.
776 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
777 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
778
779 **/
780 EFI_STATUS
781 EFIAPI
782 PciIoConfigWrite (
783 IN EFI_PCI_IO_PROTOCOL *This,
784 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
785 IN UINT32 Offset,
786 IN UINTN Count,
787 IN OUT VOID *Buffer
788 )
789 {
790 EFI_STATUS Status;
791 PCI_IO_DEVICE *PciIoDevice;
792 UINT64 Address;
793
794 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
795
796 Address = Offset;
797 Status = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);
798 if (EFI_ERROR (Status)) {
799 return Status;
800 }
801
802 //
803 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
804 //
805 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
806 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
807 Count *= (UINTN)(1 << (Width & 0x03));
808 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
809 }
810 }
811
812 Status = PciIoDevice->PciRootBridgeIo->Pci.Write (
813 PciIoDevice->PciRootBridgeIo,
814 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
815 Address,
816 Count,
817 Buffer
818 );
819
820 if (EFI_ERROR (Status)) {
821 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR);
822 }
823
824 return Status;
825 }
826
827 /**
828 Enables a PCI driver to copy one region of PCI memory space to another region of PCI
829 memory space.
830
831 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
832 @param Width Signifies the width of the memory operations.
833 @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the
834 base address for the memory operation to perform.
835 @param DestOffset The destination offset within the BAR specified by DestBarIndex to
836 start the memory writes for the copy operation.
837 @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the
838 base address for the memory operation to perform.
839 @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start
840 the memory reads for the copy operation.
841 @param Count The number of memory operations to perform. Bytes moved is Width
842 size * Count, starting at DestOffset and SrcOffset.
843
844 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.
845 @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.
846 @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.
847 @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count
848 is not valid for the PCI BAR specified by DestBarIndex.
849 @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is
850 not valid for the PCI BAR specified by SrcBarIndex.
851 @retval EFI_INVALID_PARAMETER Width is invalid.
852 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
853
854 **/
855 EFI_STATUS
856 EFIAPI
857 PciIoCopyMem (
858 IN EFI_PCI_IO_PROTOCOL *This,
859 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
860 IN UINT8 DestBarIndex,
861 IN UINT64 DestOffset,
862 IN UINT8 SrcBarIndex,
863 IN UINT64 SrcOffset,
864 IN UINTN Count
865 )
866 {
867 EFI_STATUS Status;
868 PCI_IO_DEVICE *PciIoDevice;
869
870 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
871
872 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
873 return EFI_INVALID_PARAMETER;
874 }
875
876 if (Width == EfiPciIoWidthFifoUint8 ||
877 Width == EfiPciIoWidthFifoUint16 ||
878 Width == EfiPciIoWidthFifoUint32 ||
879 Width == EfiPciIoWidthFifoUint64 ||
880 Width == EfiPciIoWidthFillUint8 ||
881 Width == EfiPciIoWidthFillUint16 ||
882 Width == EfiPciIoWidthFillUint32 ||
883 Width == EfiPciIoWidthFillUint64) {
884 return EFI_INVALID_PARAMETER;
885 }
886
887 Status = PciIoVerifyBarAccess (PciIoDevice, DestBarIndex, PciBarTypeMem, Width, Count, &DestOffset);
888 if (EFI_ERROR (Status)) {
889 return EFI_UNSUPPORTED;
890 }
891
892 Status = PciIoVerifyBarAccess (PciIoDevice, SrcBarIndex, PciBarTypeMem, Width, Count, &SrcOffset);
893 if (EFI_ERROR (Status)) {
894 return EFI_UNSUPPORTED;
895 }
896
897 //
898 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
899 //
900 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
901 if ((SrcOffset & ((1 << (Width & 0x03)) - 1)) != 0 || (DestOffset & ((1 << (Width & 0x03)) - 1)) != 0) {
902 Count *= (UINTN)(1 << (Width & 0x03));
903 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
904 }
905 }
906
907 Status = PciIoDevice->PciRootBridgeIo->CopyMem (
908 PciIoDevice->PciRootBridgeIo,
909 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
910 DestOffset,
911 SrcOffset,
912 Count
913 );
914
915 if (EFI_ERROR (Status)) {
916 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
917 }
918
919 return Status;
920 }
921
922 /**
923 Provides the PCI controller-specific addresses needed to access system memory.
924
925 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
926 @param Operation Indicates if the bus master is going to read or write to system memory.
927 @param HostAddress The system memory address to map to the PCI controller.
928 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes
929 that were mapped.
930 @param DeviceAddress The resulting map address for the bus master PCI controller to use to
931 access the hosts HostAddress.
932 @param Mapping A resulting value to pass to Unmap().
933
934 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
935 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
936 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
937 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
938 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
939
940 **/
941 EFI_STATUS
942 EFIAPI
943 PciIoMap (
944 IN EFI_PCI_IO_PROTOCOL *This,
945 IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,
946 IN VOID *HostAddress,
947 IN OUT UINTN *NumberOfBytes,
948 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
949 OUT VOID **Mapping
950 )
951 {
952 EFI_STATUS Status;
953 PCI_IO_DEVICE *PciIoDevice;
954
955 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
956
957 if (Operation < 0 || Operation >= EfiPciIoOperationMaximum) {
958 return EFI_INVALID_PARAMETER;
959 }
960
961 if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL) {
962 return EFI_INVALID_PARAMETER;
963 }
964
965 if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) != 0) {
966 Operation = (EFI_PCI_IO_PROTOCOL_OPERATION) (Operation + EfiPciOperationBusMasterRead64);
967 }
968
969 Status = PciIoDevice->PciRootBridgeIo->Map (
970 PciIoDevice->PciRootBridgeIo,
971 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) Operation,
972 HostAddress,
973 NumberOfBytes,
974 DeviceAddress,
975 Mapping
976 );
977
978 if (EFI_ERROR (Status)) {
979 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
980 }
981
982 return Status;
983 }
984
985 /**
986 Completes the Map() operation and releases any corresponding resources.
987
988 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
989 @param Mapping The mapping value returned from Map().
990
991 @retval EFI_SUCCESS The range was unmapped.
992 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
993
994 **/
995 EFI_STATUS
996 EFIAPI
997 PciIoUnmap (
998 IN EFI_PCI_IO_PROTOCOL *This,
999 IN VOID *Mapping
1000 )
1001 {
1002 EFI_STATUS Status;
1003 PCI_IO_DEVICE *PciIoDevice;
1004
1005 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1006
1007 Status = PciIoDevice->PciRootBridgeIo->Unmap (
1008 PciIoDevice->PciRootBridgeIo,
1009 Mapping
1010 );
1011
1012 if (EFI_ERROR (Status)) {
1013 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
1014 }
1015
1016 return Status;
1017 }
1018
1019 /**
1020 Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer
1021 mapping.
1022
1023 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1024 @param Type This parameter is not used and must be ignored.
1025 @param MemoryType The type of memory to allocate, EfiBootServicesData or
1026 EfiRuntimeServicesData.
1027 @param Pages The number of pages to allocate.
1028 @param HostAddress A pointer to store the base system memory address of the
1029 allocated range.
1030 @param Attributes The requested bit mask of attributes for the allocated range.
1031
1032 @retval EFI_SUCCESS The requested memory pages were allocated.
1033 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
1034 MEMORY_WRITE_COMBINE and MEMORY_CACHED.
1035 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1036 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
1037
1038 **/
1039 EFI_STATUS
1040 EFIAPI
1041 PciIoAllocateBuffer (
1042 IN EFI_PCI_IO_PROTOCOL *This,
1043 IN EFI_ALLOCATE_TYPE Type,
1044 IN EFI_MEMORY_TYPE MemoryType,
1045 IN UINTN Pages,
1046 OUT VOID **HostAddress,
1047 IN UINT64 Attributes
1048 )
1049 {
1050 EFI_STATUS Status;
1051 PCI_IO_DEVICE *PciIoDevice;
1052
1053 if ((Attributes &
1054 (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | EFI_PCI_ATTRIBUTE_MEMORY_CACHED))) != 0){
1055 return EFI_UNSUPPORTED;
1056 }
1057
1058 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1059
1060 if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) != 0) {
1061 Attributes |= EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE;
1062 }
1063
1064 Status = PciIoDevice->PciRootBridgeIo->AllocateBuffer (
1065 PciIoDevice->PciRootBridgeIo,
1066 Type,
1067 MemoryType,
1068 Pages,
1069 HostAddress,
1070 Attributes
1071 );
1072
1073 if (EFI_ERROR (Status)) {
1074 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
1075 }
1076
1077 return Status;
1078 }
1079
1080 /**
1081 Frees memory that was allocated with AllocateBuffer().
1082
1083 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1084 @param Pages The number of pages to free.
1085 @param HostAddress The base system memory address of the allocated range.
1086
1087 @retval EFI_SUCCESS The requested memory pages were freed.
1088 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
1089 was not allocated with AllocateBuffer().
1090
1091 **/
1092 EFI_STATUS
1093 EFIAPI
1094 PciIoFreeBuffer (
1095 IN EFI_PCI_IO_PROTOCOL *This,
1096 IN UINTN Pages,
1097 IN VOID *HostAddress
1098 )
1099 {
1100 EFI_STATUS Status;
1101 PCI_IO_DEVICE *PciIoDevice;
1102
1103 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1104
1105 Status = PciIoDevice->PciRootBridgeIo->FreeBuffer (
1106 PciIoDevice->PciRootBridgeIo,
1107 Pages,
1108 HostAddress
1109 );
1110
1111 if (EFI_ERROR (Status)) {
1112 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
1113 }
1114
1115 return Status;
1116 }
1117
1118 /**
1119 Flushes all PCI posted write transactions from a PCI host bridge to system memory.
1120
1121 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1122
1123 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host
1124 bridge to system memory.
1125 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI
1126 host bridge due to a hardware error.
1127
1128 **/
1129 EFI_STATUS
1130 EFIAPI
1131 PciIoFlush (
1132 IN EFI_PCI_IO_PROTOCOL *This
1133 )
1134 {
1135 EFI_STATUS Status;
1136 PCI_IO_DEVICE *PciIoDevice;
1137
1138 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1139
1140 Status = PciIoDevice->PciRootBridgeIo->Flush (
1141 PciIoDevice->PciRootBridgeIo
1142 );
1143 if (EFI_ERROR (Status)) {
1144 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
1145 }
1146
1147 return Status;
1148 }
1149
1150 /**
1151 Retrieves this PCI controller's current PCI bus number, device number, and function number.
1152
1153 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1154 @param SegmentNumber The PCI controller's current PCI segment number.
1155 @param BusNumber The PCI controller's current PCI bus number.
1156 @param DeviceNumber The PCI controller's current PCI device number.
1157 @param FunctionNumber The PCI controller's current PCI function number.
1158
1159 @retval EFI_SUCCESS The PCI controller location was returned.
1160 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1161
1162 **/
1163 EFI_STATUS
1164 EFIAPI
1165 PciIoGetLocation (
1166 IN EFI_PCI_IO_PROTOCOL *This,
1167 OUT UINTN *Segment,
1168 OUT UINTN *Bus,
1169 OUT UINTN *Device,
1170 OUT UINTN *Function
1171 )
1172 {
1173 PCI_IO_DEVICE *PciIoDevice;
1174
1175 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1176
1177 if (Segment == NULL || Bus == NULL || Device == NULL || Function == NULL) {
1178 return EFI_INVALID_PARAMETER;
1179 }
1180
1181 *Segment = PciIoDevice->PciRootBridgeIo->SegmentNumber;
1182 *Bus = PciIoDevice->BusNumber;
1183 *Device = PciIoDevice->DeviceNumber;
1184 *Function = PciIoDevice->FunctionNumber;
1185
1186 return EFI_SUCCESS;
1187 }
1188
1189 /**
1190 Check BAR type for PCI resource.
1191
1192 @param PciIoDevice PCI device instance.
1193 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
1194 base address for the memory or I/O operation to perform.
1195 @param BarType Memory or I/O.
1196
1197 @retval TRUE Pci device's bar type is same with input BarType.
1198 @retval TRUE Pci device's bar type is not same with input BarType.
1199
1200 **/
1201 BOOLEAN
1202 CheckBarType (
1203 IN PCI_IO_DEVICE *PciIoDevice,
1204 IN UINT8 BarIndex,
1205 IN PCI_BAR_TYPE BarType
1206 )
1207 {
1208 switch (BarType) {
1209
1210 case PciBarTypeMem:
1211
1212 if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem32 &&
1213 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem32 &&
1214 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem64 &&
1215 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem64 ) {
1216 return FALSE;
1217 }
1218
1219 return TRUE;
1220
1221 case PciBarTypeIo:
1222 if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo32 &&
1223 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo16){
1224 return FALSE;
1225 }
1226
1227 return TRUE;
1228
1229 default:
1230 break;
1231 }
1232
1233 return FALSE;
1234 }
1235
1236 /**
1237 Set/Disable new attributes to a Root Bridge.
1238
1239 @param PciIoDevice Pci device instance.
1240 @param Attributes New attribute want to be set.
1241 @param Operation Set or Disable.
1242
1243 @retval EFI_UNSUPPORTED If root bridge does not support change attribute.
1244 @retval EFI_SUCCESS Successfully set new attributs.
1245
1246 **/
1247 EFI_STATUS
1248 ModifyRootBridgeAttributes (
1249 IN PCI_IO_DEVICE *PciIoDevice,
1250 IN UINT64 Attributes,
1251 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation
1252 )
1253 {
1254 UINT64 PciRootBridgeSupports;
1255 UINT64 PciRootBridgeAttributes;
1256 UINT64 NewPciRootBridgeAttributes;
1257 EFI_STATUS Status;
1258
1259 //
1260 // Get the current attributes of this PCI device's PCI Root Bridge
1261 //
1262 Status = PciIoDevice->PciRootBridgeIo->GetAttributes (
1263 PciIoDevice->PciRootBridgeIo,
1264 &PciRootBridgeSupports,
1265 &PciRootBridgeAttributes
1266 );
1267 if (EFI_ERROR (Status)) {
1268 return EFI_UNSUPPORTED;
1269 }
1270
1271 //
1272 // Mask off EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE &
1273 // EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM, which are not supported by PCI root bridge.
1274 //
1275 Attributes &= ~(UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |
1276 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM);
1277
1278 //
1279 // Record the new attribute of the Root Bridge
1280 //
1281 if (Operation == EfiPciIoAttributeOperationEnable) {
1282 NewPciRootBridgeAttributes = PciRootBridgeAttributes | Attributes;
1283 } else {
1284 NewPciRootBridgeAttributes = PciRootBridgeAttributes & (~Attributes);
1285 }
1286
1287 //
1288 // Call the PCI Root Bridge to attempt to modify the attributes
1289 //
1290 if ((NewPciRootBridgeAttributes ^ PciRootBridgeAttributes) != 0) {
1291
1292 Status = PciIoDevice->PciRootBridgeIo->SetAttributes (
1293 PciIoDevice->PciRootBridgeIo,
1294 NewPciRootBridgeAttributes,
1295 NULL,
1296 NULL
1297 );
1298 if (EFI_ERROR (Status)) {
1299 //
1300 // The PCI Root Bridge could not modify the attributes, so return the error.
1301 //
1302 return EFI_UNSUPPORTED;
1303 }
1304 }
1305
1306 //
1307 // Also update the attributes for this Root Bridge structure
1308 //
1309 PciIoDevice->Attributes = NewPciRootBridgeAttributes;
1310
1311 return EFI_SUCCESS;
1312 }
1313
1314 /**
1315 Check whether this device can be enable/disable to snoop.
1316
1317 @param PciIoDevice Pci device instance.
1318 @param Operation Enable/Disable.
1319
1320 @retval EFI_UNSUPPORTED Pci device is not GFX device or not support snoop.
1321 @retval EFI_SUCCESS Snoop can be supported.
1322
1323 **/
1324 EFI_STATUS
1325 SupportPaletteSnoopAttributes (
1326 IN PCI_IO_DEVICE *PciIoDevice,
1327 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation
1328 )
1329 {
1330 PCI_IO_DEVICE *Temp;
1331 UINT16 VGACommand;
1332
1333 //
1334 // Snoop attribute can be only modified by GFX
1335 //
1336 if (!IS_PCI_GFX (&PciIoDevice->Pci)) {
1337 return EFI_UNSUPPORTED;
1338 }
1339
1340 //
1341 // Get the boot VGA on the same segement
1342 //
1343 Temp = ActiveVGADeviceOnTheSameSegment (PciIoDevice);
1344
1345 if (Temp == NULL) {
1346 //
1347 // If there is no VGA device on the segement, set
1348 // this graphics card to decode the palette range
1349 //
1350 return EFI_SUCCESS;
1351 }
1352
1353 //
1354 // Check these two agents are on the same path
1355 //
1356 if (!PciDevicesOnTheSamePath (Temp, PciIoDevice)) {
1357 //
1358 // they are not on the same path, so snoop can be enabled or disabled
1359 //
1360 return EFI_SUCCESS;
1361 }
1362 //
1363 // Check if they are on the same bus
1364 //
1365 if (Temp->Parent == PciIoDevice->Parent) {
1366
1367 PCI_READ_COMMAND_REGISTER (Temp, &VGACommand);
1368
1369 //
1370 // If they are on the same bus, either one can
1371 // be set to snoop, the other set to decode
1372 //
1373 if ((VGACommand & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {
1374 //
1375 // VGA has set to snoop, so GFX can be only set to disable snoop
1376 //
1377 if (Operation == EfiPciIoAttributeOperationEnable) {
1378 return EFI_UNSUPPORTED;
1379 }
1380 } else {
1381 //
1382 // VGA has disabled to snoop, so GFX can be only enabled
1383 //
1384 if (Operation == EfiPciIoAttributeOperationDisable) {
1385 return EFI_UNSUPPORTED;
1386 }
1387 }
1388
1389 return EFI_SUCCESS;
1390 }
1391
1392 //
1393 // If they are on the same path but on the different bus
1394 // The first agent is set to snoop, the second one set to
1395 // decode
1396 //
1397
1398 if (Temp->BusNumber < PciIoDevice->BusNumber) {
1399 //
1400 // GFX should be set to decode
1401 //
1402 if (Operation == EfiPciIoAttributeOperationDisable) {
1403 PCI_ENABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);
1404 Temp->Attributes |= EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;
1405 } else {
1406 return EFI_UNSUPPORTED;
1407 }
1408
1409 } else {
1410 //
1411 // GFX should be set to snoop
1412 //
1413 if (Operation == EfiPciIoAttributeOperationEnable) {
1414 PCI_DISABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);
1415 Temp->Attributes &= (~EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);
1416 } else {
1417 return EFI_UNSUPPORTED;
1418 }
1419
1420 }
1421
1422 return EFI_SUCCESS;
1423 }
1424
1425 /**
1426 Performs an operation on the attributes that this PCI controller supports. The operations include
1427 getting the set of supported attributes, retrieving the current attributes, setting the current
1428 attributes, enabling attributes, and disabling attributes.
1429
1430 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1431 @param Operation The operation to perform on the attributes for this PCI controller.
1432 @param Attributes The mask of attributes that are used for Set, Enable, and Disable
1433 operations.
1434 @param Result A pointer to the result mask of attributes that are returned for the Get
1435 and Supported operations.
1436
1437 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.
1438 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1439 @retval EFI_UNSUPPORTED one or more of the bits set in
1440 Attributes are not supported by this PCI controller or one of
1441 its parent bridges when Operation is Set, Enable or Disable.
1442
1443 **/
1444 EFI_STATUS
1445 EFIAPI
1446 PciIoAttributes (
1447 IN EFI_PCI_IO_PROTOCOL * This,
1448 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
1449 IN UINT64 Attributes,
1450 OUT UINT64 *Result OPTIONAL
1451 )
1452 {
1453 EFI_STATUS Status;
1454
1455 PCI_IO_DEVICE *PciIoDevice;
1456 PCI_IO_DEVICE *UpStreamBridge;
1457 PCI_IO_DEVICE *Temp;
1458
1459 UINT64 Supports;
1460 UINT64 UpStreamAttributes;
1461 UINT16 BridgeControl;
1462 UINT16 Command;
1463
1464 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1465
1466 switch (Operation) {
1467 case EfiPciIoAttributeOperationGet:
1468 if (Result == NULL) {
1469 return EFI_INVALID_PARAMETER;
1470 }
1471
1472 *Result = PciIoDevice->Attributes;
1473 return EFI_SUCCESS;
1474
1475 case EfiPciIoAttributeOperationSupported:
1476 if (Result == NULL) {
1477 return EFI_INVALID_PARAMETER;
1478 }
1479
1480 *Result = PciIoDevice->Supports;
1481 return EFI_SUCCESS;
1482
1483 case EfiPciIoAttributeOperationSet:
1484 Status = PciIoDevice->PciIo.Attributes (
1485 &(PciIoDevice->PciIo),
1486 EfiPciIoAttributeOperationEnable,
1487 Attributes,
1488 NULL
1489 );
1490 if (EFI_ERROR (Status)) {
1491 return EFI_UNSUPPORTED;
1492 }
1493
1494 Status = PciIoDevice->PciIo.Attributes (
1495 &(PciIoDevice->PciIo),
1496 EfiPciIoAttributeOperationDisable,
1497 (~Attributes) & (PciIoDevice->Supports),
1498 NULL
1499 );
1500 if (EFI_ERROR (Status)) {
1501 return EFI_UNSUPPORTED;
1502 }
1503
1504 return EFI_SUCCESS;
1505
1506 case EfiPciIoAttributeOperationEnable:
1507 case EfiPciIoAttributeOperationDisable:
1508 break;
1509
1510 default:
1511 return EFI_INVALID_PARAMETER;
1512 }
1513 //
1514 // Just a trick for ENABLE attribute
1515 // EFI_PCI_DEVICE_ENABLE is not defined in UEFI spec, which is the internal usage.
1516 // So, this logic doesn't confrom to UEFI spec, which should be removed.
1517 // But this trick logic is still kept for some binary drivers that depend on it.
1518 //
1519 if ((Attributes & EFI_PCI_DEVICE_ENABLE) == EFI_PCI_DEVICE_ENABLE) {
1520 Attributes &= (PciIoDevice->Supports);
1521
1522 //
1523 // Raise the EFI_P_PC_ENABLE Status code
1524 //
1525 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
1526 EFI_PROGRESS_CODE,
1527 EFI_IO_BUS_PCI | EFI_P_PC_ENABLE,
1528 PciIoDevice->DevicePath
1529 );
1530 }
1531
1532 //
1533 // Check VGA and VGA16, they can not be set at the same time
1534 //
1535 if (((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0 &&
1536 (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16) != 0) ||
1537 ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0 &&
1538 (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16) != 0) ||
1539 ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0 &&
1540 (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16) != 0) ||
1541 ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0 &&
1542 (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16) != 0) ) {
1543 return EFI_UNSUPPORTED;
1544 }
1545
1546 //
1547 // workaround for PCI drivers which always set ISA_IO or VGA_IO attribute without detecting support of
1548 // ISA_IO/ISA_IO_16 or VGA_IO/VGA_IO_16 to maintain backward-compatibility.
1549 //
1550 if (((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0) &&
1551 ((PciIoDevice->Supports & (EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) \
1552 == EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) {
1553 Attributes &= ~(UINT64)EFI_PCI_IO_ATTRIBUTE_VGA_IO;
1554 Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_IO_16;
1555 }
1556
1557 if (((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0) &&
1558 ((PciIoDevice->Supports & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) \
1559 == EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) {
1560 Attributes &= ~(UINT64)EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;
1561 Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16;
1562 }
1563
1564 //
1565 // If no attributes can be supported, then return.
1566 // Otherwise, set the attributes that it can support.
1567 //
1568 Supports = (PciIoDevice->Supports) & Attributes;
1569 if (Supports != Attributes) {
1570 return EFI_UNSUPPORTED;
1571 }
1572
1573 //
1574 // For Root Bridge, just call RootBridgeIo to set attributes;
1575 //
1576 if (PciIoDevice->Parent == NULL) {
1577 Status = ModifyRootBridgeAttributes (PciIoDevice, Attributes, Operation);
1578 return Status;
1579 }
1580
1581 Command = 0;
1582 BridgeControl = 0;
1583
1584 //
1585 // For PPB & P2C, set relevant attribute bits
1586 //
1587 if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
1588
1589 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {
1590 BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA;
1591 }
1592
1593 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_ISA_IO) != 0) {
1594 BridgeControl |= EFI_PCI_BRIDGE_CONTROL_ISA;
1595 }
1596
1597 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {
1598 Command |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;
1599 }
1600
1601 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {
1602 BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA_16;
1603 }
1604
1605 } else {
1606 //
1607 // Do with the attributes on VGA
1608 // Only for VGA's legacy resource, we just can enable once.
1609 //
1610 if ((Attributes &
1611 (EFI_PCI_IO_ATTRIBUTE_VGA_IO |
1612 EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 |
1613 EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY)) != 0) {
1614 //
1615 // Check if a VGA has been enabled before enabling a new one
1616 //
1617 if (Operation == EfiPciIoAttributeOperationEnable) {
1618 //
1619 // Check if there have been an active VGA device on the same segment
1620 //
1621 Temp = ActiveVGADeviceOnTheSameSegment (PciIoDevice);
1622 if (Temp != NULL && Temp != PciIoDevice) {
1623 //
1624 // An active VGA has been detected, so can not enable another
1625 //
1626 return EFI_UNSUPPORTED;
1627 }
1628 }
1629 }
1630
1631 //
1632 // Do with the attributes on GFX
1633 //
1634 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {
1635
1636 if (Operation == EfiPciIoAttributeOperationEnable) {
1637 //
1638 // Check if snoop can be enabled in current configuration
1639 //
1640 Status = SupportPaletteSnoopAttributes (PciIoDevice, Operation);
1641
1642 if (EFI_ERROR (Status)) {
1643
1644 //
1645 // Enable operation is forbidden, so mask the bit in attributes
1646 // so as to keep consistent with the actual Status
1647 //
1648 // Attributes &= (~EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO);
1649 //
1650 //
1651 //
1652 return EFI_UNSUPPORTED;
1653
1654 }
1655 }
1656
1657 //
1658 // It can be supported, so get ready to set the bit
1659 //
1660 Command |= EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;
1661 }
1662 }
1663
1664 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_IO) != 0) {
1665 Command |= EFI_PCI_COMMAND_IO_SPACE;
1666 }
1667
1668 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_MEMORY) != 0) {
1669 Command |= EFI_PCI_COMMAND_MEMORY_SPACE;
1670 }
1671
1672 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_BUS_MASTER) != 0) {
1673 Command |= EFI_PCI_COMMAND_BUS_MASTER;
1674 }
1675 //
1676 // The upstream bridge should be also set to revelant attribute
1677 // expect for IO, Mem and BusMaster
1678 //
1679 UpStreamAttributes = Attributes &
1680 (~(EFI_PCI_IO_ATTRIBUTE_IO |
1681 EFI_PCI_IO_ATTRIBUTE_MEMORY |
1682 EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
1683 )
1684 );
1685 UpStreamBridge = PciIoDevice->Parent;
1686
1687 if (Operation == EfiPciIoAttributeOperationEnable) {
1688 //
1689 // Enable relevant attributes to command register and bridge control register
1690 //
1691 Status = PCI_ENABLE_COMMAND_REGISTER (PciIoDevice, Command);
1692 if (BridgeControl != 0) {
1693 Status = PCI_ENABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);
1694 }
1695
1696 PciIoDevice->Attributes |= Attributes;
1697
1698 //
1699 // Enable attributes of the upstream bridge
1700 //
1701 Status = UpStreamBridge->PciIo.Attributes (
1702 &(UpStreamBridge->PciIo),
1703 EfiPciIoAttributeOperationEnable,
1704 UpStreamAttributes,
1705 NULL
1706 );
1707 } else {
1708
1709 //
1710 // Disable relevant attributes to command register and bridge control register
1711 //
1712 Status = PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, Command);
1713 if (BridgeControl != 0) {
1714 Status = PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);
1715 }
1716
1717 PciIoDevice->Attributes &= (~Attributes);
1718 Status = EFI_SUCCESS;
1719
1720 }
1721
1722 if (EFI_ERROR (Status)) {
1723 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
1724 }
1725
1726 return Status;
1727 }
1728
1729 /**
1730 Gets the attributes that this PCI controller supports setting on a BAR using
1731 SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.
1732
1733 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1734 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
1735 base address for resource range. The legal range for this field is 0..5.
1736 @param Supports A pointer to the mask of attributes that this PCI controller supports
1737 setting for this BAR with SetBarAttributes().
1738 @param Resources A pointer to the ACPI 2.0 resource descriptors that describe the current
1739 configuration of this BAR of the PCI controller.
1740
1741 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI
1742 controller supports are returned in Supports. If Resources
1743 is not NULL, then the ACPI 2.0 resource descriptors that the PCI
1744 controller is currently using are returned in Resources.
1745 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
1746 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
1747 @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate
1748 Resources.
1749
1750 **/
1751 EFI_STATUS
1752 EFIAPI
1753 PciIoGetBarAttributes (
1754 IN EFI_PCI_IO_PROTOCOL * This,
1755 IN UINT8 BarIndex,
1756 OUT UINT64 *Supports, OPTIONAL
1757 OUT VOID **Resources OPTIONAL
1758 )
1759 {
1760
1761 UINT8 *Configuration;
1762 UINT8 NumConfig;
1763 PCI_IO_DEVICE *PciIoDevice;
1764 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
1765 EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;
1766
1767 NumConfig = 0;
1768
1769 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1770
1771 if (Supports == NULL && Resources == NULL) {
1772 return EFI_INVALID_PARAMETER;
1773 }
1774
1775 if (BarIndex >= PCI_MAX_BAR) {
1776 return EFI_UNSUPPORTED;
1777 }
1778
1779 //
1780 // This driver does not support modifications to the WRITE_COMBINE or
1781 // CACHED attributes for BAR ranges.
1782 //
1783 if (Supports != NULL) {
1784 *Supports = PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED & EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE;
1785 }
1786
1787 if (Resources != NULL) {
1788
1789 if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeUnknown) {
1790 NumConfig = 1;
1791 }
1792
1793 Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
1794 if (Configuration == NULL) {
1795 return EFI_OUT_OF_RESOURCES;
1796 }
1797
1798 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
1799
1800 if (NumConfig == 1) {
1801 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1802 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
1803
1804 Ptr->AddrRangeMin = PciIoDevice->PciBar[BarIndex].BaseAddress;
1805 Ptr->AddrLen = PciIoDevice->PciBar[BarIndex].Length;
1806 Ptr->AddrRangeMax = PciIoDevice->PciBar[BarIndex].Alignment;
1807
1808 switch (PciIoDevice->PciBar[BarIndex].BarType) {
1809 case PciBarTypeIo16:
1810 case PciBarTypeIo32:
1811 //
1812 // Io
1813 //
1814 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
1815 break;
1816
1817 case PciBarTypeMem32:
1818 //
1819 // Mem
1820 //
1821 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1822 //
1823 // 32 bit
1824 //
1825 Ptr->AddrSpaceGranularity = 32;
1826 break;
1827
1828 case PciBarTypePMem32:
1829 //
1830 // Mem
1831 //
1832 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1833 //
1834 // prefechable
1835 //
1836 Ptr->SpecificFlag = 0x6;
1837 //
1838 // 32 bit
1839 //
1840 Ptr->AddrSpaceGranularity = 32;
1841 break;
1842
1843 case PciBarTypeMem64:
1844 //
1845 // Mem
1846 //
1847 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1848 //
1849 // 64 bit
1850 //
1851 Ptr->AddrSpaceGranularity = 64;
1852 break;
1853
1854 case PciBarTypePMem64:
1855 //
1856 // Mem
1857 //
1858 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1859 //
1860 // prefechable
1861 //
1862 Ptr->SpecificFlag = 0x6;
1863 //
1864 // 64 bit
1865 //
1866 Ptr->AddrSpaceGranularity = 64;
1867 break;
1868
1869 default:
1870 break;
1871 }
1872
1873 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ((UINT8 *) Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR));
1874 }
1875
1876 //
1877 // put the checksum
1878 //
1879 PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) ((UINT8 *) Ptr);
1880 PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;
1881 PtrEnd->Checksum = 0;
1882
1883 *Resources = Configuration;
1884 }
1885
1886 return EFI_SUCCESS;
1887 }
1888
1889 /**
1890 Sets the attributes for a range of a BAR on a PCI controller.
1891
1892 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1893 @param Attributes The mask of attributes to set for the resource range specified by
1894 BarIndex, Offset, and Length.
1895 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
1896 base address for resource range. The legal range for this field is 0..5.
1897 @param Offset A pointer to the BAR relative base address of the resource range to be
1898 modified by the attributes specified by Attributes.
1899 @param Length A pointer to the length of the resource range to be modified by the
1900 attributes specified by Attributes.
1901
1902 @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource
1903 range specified by BarIndex, Offset, and Length were
1904 set on the PCI controller, and the actual resource range is returned
1905 in Offset and Length.
1906 @retval EFI_INVALID_PARAMETER Offset or Length is NULL.
1907 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
1908 @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the
1909 resource range specified by BarIndex, Offset, and
1910 Length.
1911
1912 **/
1913 EFI_STATUS
1914 EFIAPI
1915 PciIoSetBarAttributes (
1916 IN EFI_PCI_IO_PROTOCOL *This,
1917 IN UINT64 Attributes,
1918 IN UINT8 BarIndex,
1919 IN OUT UINT64 *Offset,
1920 IN OUT UINT64 *Length
1921 )
1922 {
1923 EFI_STATUS Status;
1924 PCI_IO_DEVICE *PciIoDevice;
1925 UINT64 NonRelativeOffset;
1926 UINT64 Supports;
1927
1928 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1929
1930 //
1931 // Make sure Offset and Length are not NULL
1932 //
1933 if (Offset == NULL || Length == NULL) {
1934 return EFI_INVALID_PARAMETER;
1935 }
1936
1937 if (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeUnknown) {
1938 return EFI_UNSUPPORTED;
1939 }
1940 //
1941 // This driver does not support setting the WRITE_COMBINE or the CACHED attributes.
1942 // If Attributes is not 0, then return EFI_UNSUPPORTED.
1943 //
1944 Supports = PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED & EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE;
1945
1946 if (Attributes != (Attributes & Supports)) {
1947 return EFI_UNSUPPORTED;
1948 }
1949 //
1950 // Attributes must be supported. Make sure the BAR range describd by BarIndex, Offset, and
1951 // Length are valid for this PCI device.
1952 //
1953 NonRelativeOffset = *Offset;
1954 Status = PciIoVerifyBarAccess (
1955 PciIoDevice,
1956 BarIndex,
1957 PciBarTypeMem,
1958 EfiPciIoWidthUint8,
1959 (UINT32) *Length,
1960 &NonRelativeOffset
1961 );
1962 if (EFI_ERROR (Status)) {
1963 return EFI_UNSUPPORTED;
1964 }
1965
1966 return EFI_SUCCESS;
1967 }
1968
1969 /**
1970 Program parent bridge's attribute recurrently.
1971
1972 @param PciIoDevice Child Pci device instance
1973 @param Operation The operation to perform on the attributes for this PCI controller.
1974 @param Attributes The mask of attributes that are used for Set, Enable, and Disable
1975 operations.
1976
1977 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.
1978 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1979 @retval EFI_UNSUPPORTED one or more of the bits set in
1980 Attributes are not supported by this PCI controller or one of
1981 its parent bridges when Operation is Set, Enable or Disable.
1982
1983 **/
1984 EFI_STATUS
1985 UpStreamBridgesAttributes (
1986 IN PCI_IO_DEVICE *PciIoDevice,
1987 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
1988 IN UINT64 Attributes
1989 )
1990 {
1991 PCI_IO_DEVICE *Parent;
1992 EFI_PCI_IO_PROTOCOL *PciIo;
1993
1994 Parent = PciIoDevice->Parent;
1995
1996 while (Parent != NULL && IS_PCI_BRIDGE (&Parent->Pci)) {
1997
1998 //
1999 // Get the PciIo Protocol
2000 //
2001 PciIo = &Parent->PciIo;
2002
2003 PciIo->Attributes (PciIo, Operation, Attributes, NULL);
2004
2005 Parent = Parent->Parent;
2006 }
2007
2008 return EFI_SUCCESS;
2009 }
2010
2011 /**
2012 Test whether two Pci devices has same parent bridge.
2013
2014 @param PciDevice1 The first pci device for testing.
2015 @param PciDevice2 The second pci device for testing.
2016
2017 @retval TRUE Two Pci device has the same parent bridge.
2018 @retval FALSE Two Pci device has not the same parent bridge.
2019
2020 **/
2021 BOOLEAN
2022 PciDevicesOnTheSamePath (
2023 IN PCI_IO_DEVICE *PciDevice1,
2024 IN PCI_IO_DEVICE *PciDevice2
2025 )
2026 {
2027 BOOLEAN Existed1;
2028 BOOLEAN Existed2;
2029
2030 if (PciDevice1->Parent == PciDevice2->Parent) {
2031 return TRUE;
2032 }
2033
2034 Existed1 = PciDeviceExisted (PciDevice1->Parent, PciDevice2);
2035 Existed2 = PciDeviceExisted (PciDevice2->Parent, PciDevice1);
2036
2037 return (BOOLEAN) (Existed1 || Existed2);
2038 }
2039
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