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[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciIo.c
1 /** @file
2 EFI PCI IO protocol functions implementation for PCI Bus module.
3
4 Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include "PciBus.h"
16
17 //
18 // Pci Io Protocol Interface
19 //
20 EFI_PCI_IO_PROTOCOL mPciIoInterface = {
21 PciIoPollMem,
22 PciIoPollIo,
23 {
24 PciIoMemRead,
25 PciIoMemWrite
26 },
27 {
28 PciIoIoRead,
29 PciIoIoWrite
30 },
31 {
32 PciIoConfigRead,
33 PciIoConfigWrite
34 },
35 PciIoCopyMem,
36 PciIoMap,
37 PciIoUnmap,
38 PciIoAllocateBuffer,
39 PciIoFreeBuffer,
40 PciIoFlush,
41 PciIoGetLocation,
42 PciIoAttributes,
43 PciIoGetBarAttributes,
44 PciIoSetBarAttributes,
45 0,
46 NULL
47 };
48
49 /**
50 Report a error Status code of PCI bus driver controller.
51
52 @param PciIoDevice Pci device instance.
53 @param Code Status code value.
54
55 **/
56 EFI_STATUS
57 ReportErrorStatusCode (
58 IN PCI_IO_DEVICE *PciIoDevice,
59 IN EFI_STATUS_CODE_VALUE Code
60 )
61 {
62 return REPORT_STATUS_CODE_WITH_DEVICE_PATH (
63 EFI_ERROR_CODE | EFI_ERROR_MINOR,
64 Code,
65 PciIoDevice->DevicePath
66 );
67 }
68
69 /**
70 Initializes a PCI I/O Instance.
71
72 @param PciIoDevice Pci device instance.
73
74 **/
75 VOID
76 InitializePciIoInstance (
77 IN PCI_IO_DEVICE *PciIoDevice
78 )
79 {
80 CopyMem (&PciIoDevice->PciIo, &mPciIoInterface, sizeof (EFI_PCI_IO_PROTOCOL));
81 }
82
83 /**
84 Verifies access to a PCI Base Address Register (BAR).
85
86 @param PciIoDevice Pci device instance.
87 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
88 base address for the memory or I/O operation to perform.
89 @param Type Operation type could be memory or I/O.
90 @param Width Signifies the width of the memory or I/O operations.
91 @param Count The number of memory or I/O operations to perform.
92 @param Offset The offset within the PCI configuration space for the PCI controller.
93
94 @retval EFI_INVALID_PARAMETER Invalid Width/BarIndex or Bar type.
95 @retval EFI_SUCCESS Successfully verified.
96
97 **/
98 EFI_STATUS
99 PciIoVerifyBarAccess (
100 IN PCI_IO_DEVICE *PciIoDevice,
101 IN UINT8 BarIndex,
102 IN PCI_BAR_TYPE Type,
103 IN IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
104 IN IN UINTN Count,
105 IN UINT64 *Offset
106 )
107 {
108 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
109 return EFI_INVALID_PARAMETER;
110 }
111
112 if (BarIndex == EFI_PCI_IO_PASS_THROUGH_BAR) {
113 return EFI_SUCCESS;
114 }
115
116 //
117 // BarIndex 0-5 is legal
118 //
119 if (BarIndex >= PCI_MAX_BAR) {
120 return EFI_INVALID_PARAMETER;
121 }
122
123 if (!CheckBarType (PciIoDevice, BarIndex, Type)) {
124 return EFI_INVALID_PARAMETER;
125 }
126
127 //
128 // If Width is EfiPciIoWidthFifoUintX then convert to EfiPciIoWidthUintX
129 // If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX
130 //
131 if (Width >= EfiPciIoWidthFifoUint8 && Width <= EfiPciIoWidthFifoUint64) {
132 Count = 1;
133 }
134
135 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & 0x03);
136
137 if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PciIoDevice->PciBar[BarIndex].Length) {
138 return EFI_INVALID_PARAMETER;
139 }
140
141 *Offset = *Offset + PciIoDevice->PciBar[BarIndex].BaseAddress;
142
143 return EFI_SUCCESS;
144 }
145
146 /**
147 Verifies access to a PCI Configuration Header.
148
149 @param PciIoDevice Pci device instance.
150 @param Width Signifies the width of the memory or I/O operations.
151 @param Count The number of memory or I/O operations to perform.
152 @param Offset The offset within the PCI configuration space for the PCI controller.
153
154 @retval EFI_INVALID_PARAMETER Invalid Width
155 @retval EFI_UNSUPPORTED Offset overflowed.
156 @retval EFI_SUCCESS Successfully verified.
157
158 **/
159 EFI_STATUS
160 PciIoVerifyConfigAccess (
161 IN PCI_IO_DEVICE *PciIoDevice,
162 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
163 IN UINTN Count,
164 IN UINT64 *Offset
165 )
166 {
167 UINT64 ExtendOffset;
168
169 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
170 return EFI_INVALID_PARAMETER;
171 }
172
173 //
174 // If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX
175 //
176 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & 0x03);
177
178 if (PciIoDevice->IsPciExp) {
179 if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PCI_EXP_MAX_CONFIG_OFFSET) {
180 return EFI_UNSUPPORTED;
181 }
182
183 ExtendOffset = LShiftU64 (*Offset, 32);
184 *Offset = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, 0);
185 *Offset = (*Offset) | ExtendOffset;
186
187 } else {
188 if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PCI_MAX_CONFIG_OFFSET) {
189 return EFI_UNSUPPORTED;
190 }
191
192 *Offset = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, *Offset);
193 }
194
195 return EFI_SUCCESS;
196 }
197
198 /**
199 Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is
200 satisfied or after a defined duration.
201
202 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
203 @param Width Signifies the width of the memory or I/O operations.
204 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
205 base address for the memory operation to perform.
206 @param Offset The offset within the selected BAR to start the memory operation.
207 @param Mask Mask used for the polling criteria.
208 @param Value The comparison value used for the polling exit criteria.
209 @param Delay The number of 100 ns units to poll.
210 @param Result Pointer to the last value read from the memory location.
211
212 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
213 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
214 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.
215 @retval EFI_TIMEOUT Delay expired before a match occurred.
216 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
217 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
218
219 **/
220 EFI_STATUS
221 EFIAPI
222 PciIoPollMem (
223 IN EFI_PCI_IO_PROTOCOL *This,
224 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
225 IN UINT8 BarIndex,
226 IN UINT64 Offset,
227 IN UINT64 Mask,
228 IN UINT64 Value,
229 IN UINT64 Delay,
230 OUT UINT64 *Result
231 )
232 {
233 EFI_STATUS Status;
234 PCI_IO_DEVICE *PciIoDevice;
235
236 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
237
238 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
239 return EFI_INVALID_PARAMETER;
240 }
241
242 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, 1, &Offset);
243 if (EFI_ERROR (Status)) {
244 return EFI_UNSUPPORTED;
245 }
246
247 if (Width > EfiPciIoWidthUint64) {
248 return EFI_INVALID_PARAMETER;
249 }
250
251 //
252 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
253 //
254 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
255 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
256 Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);
257 if (EFI_ERROR (Status)) {
258 return Status;
259 }
260 if ((*Result & Mask) == Value || Delay == 0) {
261 return EFI_SUCCESS;
262 }
263 do {
264 //
265 // Stall 10 us = 100 * 100ns
266 //
267 gBS->Stall (10);
268
269 Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);
270 if (EFI_ERROR (Status)) {
271 return Status;
272 }
273 if ((*Result & Mask) == Value) {
274 return EFI_SUCCESS;
275 }
276 if (Delay <= 100) {
277 return EFI_TIMEOUT;
278 }
279 Delay -= 100;
280 } while (TRUE);
281 }
282 }
283
284 Status = PciIoDevice->PciRootBridgeIo->PollMem (
285 PciIoDevice->PciRootBridgeIo,
286 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
287 Offset,
288 Mask,
289 Value,
290 Delay,
291 Result
292 );
293
294 if (EFI_ERROR (Status)) {
295 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
296 }
297
298 return Status;
299 }
300
301 /**
302 Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is
303 satisfied or after a defined duration.
304
305 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
306 @param Width Signifies the width of the memory or I/O operations.
307 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
308 base address for the memory operation to perform.
309 @param Offset The offset within the selected BAR to start the memory operation.
310 @param Mask Mask used for the polling criteria.
311 @param Value The comparison value used for the polling exit criteria.
312 @param Delay The number of 100 ns units to poll.
313 @param Result Pointer to the last value read from the memory location.
314
315 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
316 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
317 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.
318 @retval EFI_TIMEOUT Delay expired before a match occurred.
319 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
320 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
321
322 **/
323 EFI_STATUS
324 EFIAPI
325 PciIoPollIo (
326 IN EFI_PCI_IO_PROTOCOL *This,
327 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
328 IN UINT8 BarIndex,
329 IN UINT64 Offset,
330 IN UINT64 Mask,
331 IN UINT64 Value,
332 IN UINT64 Delay,
333 OUT UINT64 *Result
334 )
335 {
336 EFI_STATUS Status;
337 PCI_IO_DEVICE *PciIoDevice;
338
339 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
340
341 if (Width < 0 || Width > EfiPciIoWidthUint64) {
342 return EFI_INVALID_PARAMETER;
343 }
344
345 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, 1, &Offset);
346 if (EFI_ERROR (Status)) {
347 return EFI_UNSUPPORTED;
348 }
349
350 //
351 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
352 //
353 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
354 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
355 Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);
356 if (EFI_ERROR (Status)) {
357 return Status;
358 }
359 if ((*Result & Mask) == Value || Delay == 0) {
360 return EFI_SUCCESS;
361 }
362 do {
363 //
364 // Stall 10 us = 100 * 100ns
365 //
366 gBS->Stall (10);
367
368 Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);
369 if (EFI_ERROR (Status)) {
370 return Status;
371 }
372 if ((*Result & Mask) == Value) {
373 return EFI_SUCCESS;
374 }
375 if (Delay <= 100) {
376 return EFI_TIMEOUT;
377 }
378 Delay -= 100;
379 } while (TRUE);
380 }
381 }
382
383 Status = PciIoDevice->PciRootBridgeIo->PollIo (
384 PciIoDevice->PciRootBridgeIo,
385 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
386 Offset,
387 Mask,
388 Value,
389 Delay,
390 Result
391 );
392
393 if (EFI_ERROR (Status)) {
394 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
395 }
396
397 return Status;
398 }
399
400 /**
401 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
402
403 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
404 @param Width Signifies the width of the memory or I/O operations.
405 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
406 base address for the memory or I/O operation to perform.
407 @param Offset The offset within the selected BAR to start the memory or I/O operation.
408 @param Count The number of memory or I/O operations to perform.
409 @param Buffer For read operations, the destination buffer to store the results. For write
410 operations, the source buffer to write data from.
411
412 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
413 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
414 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
415 valid for the PCI BAR specified by BarIndex.
416 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
417 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
418
419 **/
420 EFI_STATUS
421 EFIAPI
422 PciIoMemRead (
423 IN EFI_PCI_IO_PROTOCOL *This,
424 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
425 IN UINT8 BarIndex,
426 IN UINT64 Offset,
427 IN UINTN Count,
428 IN OUT VOID *Buffer
429 )
430 {
431 EFI_STATUS Status;
432 PCI_IO_DEVICE *PciIoDevice;
433
434 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
435
436 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
437 return EFI_INVALID_PARAMETER;
438 }
439
440 if (Buffer == NULL) {
441 return EFI_INVALID_PARAMETER;
442 }
443
444 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, Count, &Offset);
445 if (EFI_ERROR (Status)) {
446 return EFI_UNSUPPORTED;
447 }
448
449 //
450 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
451 //
452 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
453 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
454 Count *= (UINTN)(1 << (Width & 0x03));
455 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
456 }
457 }
458
459
460 Status = PciIoDevice->PciRootBridgeIo->Mem.Read (
461 PciIoDevice->PciRootBridgeIo,
462 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
463 Offset,
464 Count,
465 Buffer
466 );
467
468 if (EFI_ERROR (Status)) {
469 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR);
470 }
471
472 return Status;
473 }
474
475 /**
476 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
477
478 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
479 @param Width Signifies the width of the memory or I/O operations.
480 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
481 base address for the memory or I/O operation to perform.
482 @param Offset The offset within the selected BAR to start the memory or I/O operation.
483 @param Count The number of memory or I/O operations to perform.
484 @param Buffer For read operations, the destination buffer to store the results. For write
485 operations, the source buffer to write data from.
486
487 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
488 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
489 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
490 valid for the PCI BAR specified by BarIndex.
491 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
492 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
493
494 **/
495 EFI_STATUS
496 EFIAPI
497 PciIoMemWrite (
498 IN EFI_PCI_IO_PROTOCOL *This,
499 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
500 IN UINT8 BarIndex,
501 IN UINT64 Offset,
502 IN UINTN Count,
503 IN OUT VOID *Buffer
504 )
505 {
506 EFI_STATUS Status;
507 PCI_IO_DEVICE *PciIoDevice;
508
509 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
510
511 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
512 return EFI_INVALID_PARAMETER;
513 }
514
515 if (Buffer == NULL) {
516 return EFI_INVALID_PARAMETER;
517 }
518
519 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, Count, &Offset);
520 if (EFI_ERROR (Status)) {
521 return EFI_UNSUPPORTED;
522 }
523
524 //
525 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
526 //
527 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
528 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
529 Count *= (UINTN)(1 << (Width & 0x03));
530 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
531 }
532 }
533
534 Status = PciIoDevice->PciRootBridgeIo->Mem.Write (
535 PciIoDevice->PciRootBridgeIo,
536 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
537 Offset,
538 Count,
539 Buffer
540 );
541
542 if (EFI_ERROR (Status)) {
543 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR);
544 }
545
546 return Status;
547 }
548
549 /**
550 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
551
552 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
553 @param Width Signifies the width of the memory or I/O operations.
554 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
555 base address for the memory or I/O operation to perform.
556 @param Offset The offset within the selected BAR to start the memory or I/O operation.
557 @param Count The number of memory or I/O operations to perform.
558 @param Buffer For read operations, the destination buffer to store the results. For write
559 operations, the source buffer to write data from.
560
561 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
562 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
563 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
564 valid for the PCI BAR specified by BarIndex.
565 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
566 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
567
568 **/
569 EFI_STATUS
570 EFIAPI
571 PciIoIoRead (
572 IN EFI_PCI_IO_PROTOCOL *This,
573 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
574 IN UINT8 BarIndex,
575 IN UINT64 Offset,
576 IN UINTN Count,
577 IN OUT VOID *Buffer
578 )
579 {
580 EFI_STATUS Status;
581 PCI_IO_DEVICE *PciIoDevice;
582
583 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
584
585 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
586 return EFI_INVALID_PARAMETER;
587 }
588
589 if (Buffer == NULL) {
590 return EFI_INVALID_PARAMETER;
591 }
592
593 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, Count, &Offset);
594 if (EFI_ERROR (Status)) {
595 return EFI_UNSUPPORTED;
596 }
597
598 //
599 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
600 //
601 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
602 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
603 Count *= (UINTN)(1 << (Width & 0x03));
604 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
605 }
606 }
607
608 Status = PciIoDevice->PciRootBridgeIo->Io.Read (
609 PciIoDevice->PciRootBridgeIo,
610 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
611 Offset,
612 Count,
613 Buffer
614 );
615
616 if (EFI_ERROR (Status)) {
617 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR);
618 }
619
620 return Status;
621 }
622
623 /**
624 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
625
626 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
627 @param Width Signifies the width of the memory or I/O operations.
628 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
629 base address for the memory or I/O operation to perform.
630 @param Offset The offset within the selected BAR to start the memory or I/O operation.
631 @param Count The number of memory or I/O operations to perform.
632 @param Buffer For read operations, the destination buffer to store the results. For write
633 operations, the source buffer to write data from.
634
635 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
636 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
637 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
638 valid for the PCI BAR specified by BarIndex.
639 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
640 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
641
642 **/
643 EFI_STATUS
644 EFIAPI
645 PciIoIoWrite (
646 IN EFI_PCI_IO_PROTOCOL *This,
647 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
648 IN UINT8 BarIndex,
649 IN UINT64 Offset,
650 IN UINTN Count,
651 IN OUT VOID *Buffer
652 )
653 {
654 EFI_STATUS Status;
655 PCI_IO_DEVICE *PciIoDevice;
656
657 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
658
659 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
660 return EFI_INVALID_PARAMETER;
661 }
662
663 if (Buffer == NULL) {
664 return EFI_INVALID_PARAMETER;
665 }
666
667 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, Count, &Offset);
668 if (EFI_ERROR (Status)) {
669 return EFI_UNSUPPORTED;
670 }
671
672 //
673 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
674 //
675 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
676 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
677 Count *= (UINTN)(1 << (Width & 0x03));
678 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
679 }
680 }
681
682 Status = PciIoDevice->PciRootBridgeIo->Io.Write (
683 PciIoDevice->PciRootBridgeIo,
684 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
685 Offset,
686 Count,
687 Buffer
688 );
689
690 if (EFI_ERROR (Status)) {
691 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR);
692 }
693
694 return Status;
695 }
696
697 /**
698 Enable a PCI driver to access PCI controller registers in PCI configuration space.
699
700 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
701 @param Width Signifies the width of the memory operations.
702 @param Offset The offset within the PCI configuration space for the PCI controller.
703 @param Count The number of PCI configuration operations to perform.
704 @param Buffer For read operations, the destination buffer to store the results. For write
705 operations, the source buffer to write data from.
706
707
708 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
709 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
710 valid for the PCI configuration header of the PCI controller.
711 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
712 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
713
714 **/
715 EFI_STATUS
716 EFIAPI
717 PciIoConfigRead (
718 IN EFI_PCI_IO_PROTOCOL *This,
719 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
720 IN UINT32 Offset,
721 IN UINTN Count,
722 IN OUT VOID *Buffer
723 )
724 {
725 EFI_STATUS Status;
726 PCI_IO_DEVICE *PciIoDevice;
727 UINT64 Address;
728
729 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
730
731 Address = Offset;
732 Status = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);
733 if (EFI_ERROR (Status)) {
734 return Status;
735 }
736
737 //
738 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
739 //
740 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
741 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
742 Count *= (UINTN)(1 << (Width & 0x03));
743 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
744 }
745 }
746
747 Status = PciIoDevice->PciRootBridgeIo->Pci.Read (
748 PciIoDevice->PciRootBridgeIo,
749 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
750 Address,
751 Count,
752 Buffer
753 );
754
755 if (EFI_ERROR (Status)) {
756 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR);
757 }
758
759 return Status;
760 }
761
762 /**
763 Enable a PCI driver to access PCI controller registers in PCI configuration space.
764
765 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
766 @param Width Signifies the width of the memory operations.
767 @param Offset The offset within the PCI configuration space for the PCI controller.
768 @param Count The number of PCI configuration operations to perform.
769 @param Buffer For read operations, the destination buffer to store the results. For write
770 operations, the source buffer to write data from.
771
772
773 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
774 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
775 valid for the PCI configuration header of the PCI controller.
776 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
777 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
778
779 **/
780 EFI_STATUS
781 EFIAPI
782 PciIoConfigWrite (
783 IN EFI_PCI_IO_PROTOCOL *This,
784 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
785 IN UINT32 Offset,
786 IN UINTN Count,
787 IN OUT VOID *Buffer
788 )
789 {
790 EFI_STATUS Status;
791 PCI_IO_DEVICE *PciIoDevice;
792 UINT64 Address;
793
794 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
795
796 Address = Offset;
797 Status = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);
798 if (EFI_ERROR (Status)) {
799 return Status;
800 }
801
802 //
803 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
804 //
805 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
806 if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
807 Count *= (UINTN)(1 << (Width & 0x03));
808 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
809 }
810 }
811
812 Status = PciIoDevice->PciRootBridgeIo->Pci.Write (
813 PciIoDevice->PciRootBridgeIo,
814 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
815 Address,
816 Count,
817 Buffer
818 );
819
820 if (EFI_ERROR (Status)) {
821 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR);
822 }
823
824 return Status;
825 }
826
827 /**
828 Enables a PCI driver to copy one region of PCI memory space to another region of PCI
829 memory space.
830
831 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
832 @param Width Signifies the width of the memory operations.
833 @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the
834 base address for the memory operation to perform.
835 @param DestOffset The destination offset within the BAR specified by DestBarIndex to
836 start the memory writes for the copy operation.
837 @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the
838 base address for the memory operation to perform.
839 @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start
840 the memory reads for the copy operation.
841 @param Count The number of memory operations to perform. Bytes moved is Width
842 size * Count, starting at DestOffset and SrcOffset.
843
844 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.
845 @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.
846 @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.
847 @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count
848 is not valid for the PCI BAR specified by DestBarIndex.
849 @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is
850 not valid for the PCI BAR specified by SrcBarIndex.
851 @retval EFI_INVALID_PARAMETER Width is invalid.
852 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
853
854 **/
855 EFI_STATUS
856 EFIAPI
857 PciIoCopyMem (
858 IN EFI_PCI_IO_PROTOCOL *This,
859 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
860 IN UINT8 DestBarIndex,
861 IN UINT64 DestOffset,
862 IN UINT8 SrcBarIndex,
863 IN UINT64 SrcOffset,
864 IN UINTN Count
865 )
866 {
867 EFI_STATUS Status;
868 PCI_IO_DEVICE *PciIoDevice;
869
870 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
871
872 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
873 return EFI_INVALID_PARAMETER;
874 }
875
876 if (Width == EfiPciIoWidthFifoUint8 ||
877 Width == EfiPciIoWidthFifoUint16 ||
878 Width == EfiPciIoWidthFifoUint32 ||
879 Width == EfiPciIoWidthFifoUint64 ||
880 Width == EfiPciIoWidthFillUint8 ||
881 Width == EfiPciIoWidthFillUint16 ||
882 Width == EfiPciIoWidthFillUint32 ||
883 Width == EfiPciIoWidthFillUint64) {
884 return EFI_INVALID_PARAMETER;
885 }
886
887 Status = PciIoVerifyBarAccess (PciIoDevice, DestBarIndex, PciBarTypeMem, Width, Count, &DestOffset);
888 if (EFI_ERROR (Status)) {
889 return EFI_UNSUPPORTED;
890 }
891
892 Status = PciIoVerifyBarAccess (PciIoDevice, SrcBarIndex, PciBarTypeMem, Width, Count, &SrcOffset);
893 if (EFI_ERROR (Status)) {
894 return EFI_UNSUPPORTED;
895 }
896
897 //
898 // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
899 //
900 if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
901 if ((SrcOffset & ((1 << (Width & 0x03)) - 1)) != 0 || (DestOffset & ((1 << (Width & 0x03)) - 1)) != 0) {
902 Count *= (UINTN)(1 << (Width & 0x03));
903 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & (~0x03));
904 }
905 }
906
907 Status = PciIoDevice->PciRootBridgeIo->CopyMem (
908 PciIoDevice->PciRootBridgeIo,
909 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
910 DestOffset,
911 SrcOffset,
912 Count
913 );
914
915 if (EFI_ERROR (Status)) {
916 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
917 }
918
919 return Status;
920 }
921
922 /**
923 Provides the PCI controller-specific addresses needed to access system memory.
924
925 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
926 @param Operation Indicates if the bus master is going to read or write to system memory.
927 @param HostAddress The system memory address to map to the PCI controller.
928 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes
929 that were mapped.
930 @param DeviceAddress The resulting map address for the bus master PCI controller to use to
931 access the hosts HostAddress.
932 @param Mapping A resulting value to pass to Unmap().
933
934 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
935 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
936 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
937 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
938 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
939
940 **/
941 EFI_STATUS
942 EFIAPI
943 PciIoMap (
944 IN EFI_PCI_IO_PROTOCOL *This,
945 IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,
946 IN VOID *HostAddress,
947 IN OUT UINTN *NumberOfBytes,
948 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
949 OUT VOID **Mapping
950 )
951 {
952 EFI_STATUS Status;
953 PCI_IO_DEVICE *PciIoDevice;
954
955 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
956
957 if (Operation < 0 || Operation >= EfiPciIoOperationMaximum) {
958 return EFI_INVALID_PARAMETER;
959 }
960
961 if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL) {
962 return EFI_INVALID_PARAMETER;
963 }
964
965 if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) != 0) {
966 Operation = (EFI_PCI_IO_PROTOCOL_OPERATION) (Operation + EfiPciOperationBusMasterRead64);
967 }
968
969 Status = PciIoDevice->PciRootBridgeIo->Map (
970 PciIoDevice->PciRootBridgeIo,
971 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) Operation,
972 HostAddress,
973 NumberOfBytes,
974 DeviceAddress,
975 Mapping
976 );
977
978 if (EFI_ERROR (Status)) {
979 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
980 }
981
982 return Status;
983 }
984
985 /**
986 Completes the Map() operation and releases any corresponding resources.
987
988 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
989 @param Mapping The mapping value returned from Map().
990
991 @retval EFI_SUCCESS The range was unmapped.
992 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
993
994 **/
995 EFI_STATUS
996 EFIAPI
997 PciIoUnmap (
998 IN EFI_PCI_IO_PROTOCOL *This,
999 IN VOID *Mapping
1000 )
1001 {
1002 EFI_STATUS Status;
1003 PCI_IO_DEVICE *PciIoDevice;
1004
1005 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1006
1007 Status = PciIoDevice->PciRootBridgeIo->Unmap (
1008 PciIoDevice->PciRootBridgeIo,
1009 Mapping
1010 );
1011
1012 if (EFI_ERROR (Status)) {
1013 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
1014 }
1015
1016 return Status;
1017 }
1018
1019 /**
1020 Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer
1021 mapping.
1022
1023 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1024 @param Type This parameter is not used and must be ignored.
1025 @param MemoryType The type of memory to allocate, EfiBootServicesData or
1026 EfiRuntimeServicesData.
1027 @param Pages The number of pages to allocate.
1028 @param HostAddress A pointer to store the base system memory address of the
1029 allocated range.
1030 @param Attributes The requested bit mask of attributes for the allocated range.
1031
1032 @retval EFI_SUCCESS The requested memory pages were allocated.
1033 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
1034 MEMORY_WRITE_COMBINE and MEMORY_CACHED.
1035 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1036 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
1037
1038 **/
1039 EFI_STATUS
1040 EFIAPI
1041 PciIoAllocateBuffer (
1042 IN EFI_PCI_IO_PROTOCOL *This,
1043 IN EFI_ALLOCATE_TYPE Type,
1044 IN EFI_MEMORY_TYPE MemoryType,
1045 IN UINTN Pages,
1046 OUT VOID **HostAddress,
1047 IN UINT64 Attributes
1048 )
1049 {
1050 EFI_STATUS Status;
1051 PCI_IO_DEVICE *PciIoDevice;
1052
1053 if ((Attributes &
1054 (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | EFI_PCI_ATTRIBUTE_MEMORY_CACHED))) != 0){
1055 return EFI_UNSUPPORTED;
1056 }
1057
1058 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1059
1060 if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) != 0) {
1061 Attributes |= EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE;
1062 }
1063
1064 Status = PciIoDevice->PciRootBridgeIo->AllocateBuffer (
1065 PciIoDevice->PciRootBridgeIo,
1066 Type,
1067 MemoryType,
1068 Pages,
1069 HostAddress,
1070 Attributes
1071 );
1072
1073 if (EFI_ERROR (Status)) {
1074 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
1075 }
1076
1077 return Status;
1078 }
1079
1080 /**
1081 Frees memory that was allocated with AllocateBuffer().
1082
1083 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1084 @param Pages The number of pages to free.
1085 @param HostAddress The base system memory address of the allocated range.
1086
1087 @retval EFI_SUCCESS The requested memory pages were freed.
1088 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
1089 was not allocated with AllocateBuffer().
1090
1091 **/
1092 EFI_STATUS
1093 EFIAPI
1094 PciIoFreeBuffer (
1095 IN EFI_PCI_IO_PROTOCOL *This,
1096 IN UINTN Pages,
1097 IN VOID *HostAddress
1098 )
1099 {
1100 EFI_STATUS Status;
1101 PCI_IO_DEVICE *PciIoDevice;
1102
1103 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1104
1105 Status = PciIoDevice->PciRootBridgeIo->FreeBuffer (
1106 PciIoDevice->PciRootBridgeIo,
1107 Pages,
1108 HostAddress
1109 );
1110
1111 if (EFI_ERROR (Status)) {
1112 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
1113 }
1114
1115 return Status;
1116 }
1117
1118 /**
1119 Flushes all PCI posted write transactions from a PCI host bridge to system memory.
1120
1121 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1122
1123 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host
1124 bridge to system memory.
1125 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI
1126 host bridge due to a hardware error.
1127
1128 **/
1129 EFI_STATUS
1130 EFIAPI
1131 PciIoFlush (
1132 IN EFI_PCI_IO_PROTOCOL *This
1133 )
1134 {
1135 EFI_STATUS Status;
1136 PCI_IO_DEVICE *PciIoDevice;
1137
1138 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1139
1140 Status = PciIoDevice->PciRootBridgeIo->Flush (
1141 PciIoDevice->PciRootBridgeIo
1142 );
1143 if (EFI_ERROR (Status)) {
1144 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
1145 }
1146
1147 return Status;
1148 }
1149
1150 /**
1151 Retrieves this PCI controller's current PCI bus number, device number, and function number.
1152
1153 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1154 @param SegmentNumber The PCI controller's current PCI segment number.
1155 @param BusNumber The PCI controller's current PCI bus number.
1156 @param DeviceNumber The PCI controller's current PCI device number.
1157 @param FunctionNumber The PCI controller's current PCI function number.
1158
1159 @retval EFI_SUCCESS The PCI controller location was returned.
1160 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1161
1162 **/
1163 EFI_STATUS
1164 EFIAPI
1165 PciIoGetLocation (
1166 IN EFI_PCI_IO_PROTOCOL *This,
1167 OUT UINTN *Segment,
1168 OUT UINTN *Bus,
1169 OUT UINTN *Device,
1170 OUT UINTN *Function
1171 )
1172 {
1173 PCI_IO_DEVICE *PciIoDevice;
1174
1175 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1176
1177 if (Segment == NULL || Bus == NULL || Device == NULL || Function == NULL) {
1178 return EFI_INVALID_PARAMETER;
1179 }
1180
1181 *Segment = PciIoDevice->PciRootBridgeIo->SegmentNumber;
1182 *Bus = PciIoDevice->BusNumber;
1183 *Device = PciIoDevice->DeviceNumber;
1184 *Function = PciIoDevice->FunctionNumber;
1185
1186 return EFI_SUCCESS;
1187 }
1188
1189 /**
1190 Check BAR type for PCI resource.
1191
1192 @param PciIoDevice PCI device instance.
1193 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
1194 base address for the memory or I/O operation to perform.
1195 @param BarType Memory or I/O.
1196
1197 @retval TRUE Pci device's bar type is same with input BarType.
1198 @retval TRUE Pci device's bar type is not same with input BarType.
1199
1200 **/
1201 BOOLEAN
1202 CheckBarType (
1203 IN PCI_IO_DEVICE *PciIoDevice,
1204 IN UINT8 BarIndex,
1205 IN PCI_BAR_TYPE BarType
1206 )
1207 {
1208 switch (BarType) {
1209
1210 case PciBarTypeMem:
1211
1212 if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem32 &&
1213 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem32 &&
1214 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem64 &&
1215 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem64 ) {
1216 return FALSE;
1217 }
1218
1219 return TRUE;
1220
1221 case PciBarTypeIo:
1222 if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo32 &&
1223 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo16){
1224 return FALSE;
1225 }
1226
1227 return TRUE;
1228
1229 default:
1230 break;
1231 }
1232
1233 return FALSE;
1234 }
1235
1236 /**
1237 Set/Disable new attributes to a Root Bridge.
1238
1239 @param PciIoDevice Pci device instance.
1240 @param Attributes New attribute want to be set.
1241 @param Operation Set or Disable.
1242
1243 @retval EFI_UNSUPPORTED If root bridge does not support change attribute.
1244 @retval EFI_SUCCESS Successfully set new attributs.
1245
1246 **/
1247 EFI_STATUS
1248 ModifyRootBridgeAttributes (
1249 IN PCI_IO_DEVICE *PciIoDevice,
1250 IN UINT64 Attributes,
1251 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation
1252 )
1253 {
1254 UINT64 PciRootBridgeSupports;
1255 UINT64 PciRootBridgeAttributes;
1256 UINT64 NewPciRootBridgeAttributes;
1257 EFI_STATUS Status;
1258
1259 //
1260 // Get the current attributes of this PCI device's PCI Root Bridge
1261 //
1262 Status = PciIoDevice->PciRootBridgeIo->GetAttributes (
1263 PciIoDevice->PciRootBridgeIo,
1264 &PciRootBridgeSupports,
1265 &PciRootBridgeAttributes
1266 );
1267 if (EFI_ERROR (Status)) {
1268 return EFI_UNSUPPORTED;
1269 }
1270
1271 //
1272 // Record the new attribute of the Root Bridge
1273 //
1274 if (Operation == EfiPciIoAttributeOperationEnable) {
1275 NewPciRootBridgeAttributes = PciRootBridgeAttributes | Attributes;
1276 } else {
1277 NewPciRootBridgeAttributes = PciRootBridgeAttributes & (~Attributes);
1278 }
1279
1280 //
1281 // Call the PCI Root Bridge to attempt to modify the attributes
1282 //
1283 if ((NewPciRootBridgeAttributes ^ PciRootBridgeAttributes) != 0) {
1284
1285 Status = PciIoDevice->PciRootBridgeIo->SetAttributes (
1286 PciIoDevice->PciRootBridgeIo,
1287 NewPciRootBridgeAttributes,
1288 NULL,
1289 NULL
1290 );
1291 if (EFI_ERROR (Status)) {
1292 //
1293 // The PCI Root Bridge could not modify the attributes, so return the error.
1294 //
1295 return EFI_UNSUPPORTED;
1296 }
1297 }
1298
1299 //
1300 // Also update the attributes for this Root Bridge structure
1301 //
1302 PciIoDevice->Attributes = NewPciRootBridgeAttributes;
1303
1304 return EFI_SUCCESS;
1305 }
1306
1307 /**
1308 Check whether this device can be enable/disable to snoop.
1309
1310 @param PciIoDevice Pci device instance.
1311 @param Operation Enable/Disable.
1312
1313 @retval EFI_UNSUPPORTED Pci device is not GFX device or not support snoop.
1314 @retval EFI_SUCCESS Snoop can be supported.
1315
1316 **/
1317 EFI_STATUS
1318 SupportPaletteSnoopAttributes (
1319 IN PCI_IO_DEVICE *PciIoDevice,
1320 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation
1321 )
1322 {
1323 PCI_IO_DEVICE *Temp;
1324 UINT16 VGACommand;
1325
1326 //
1327 // Snoop attribute can be only modified by GFX
1328 //
1329 if (!IS_PCI_GFX (&PciIoDevice->Pci)) {
1330 return EFI_UNSUPPORTED;
1331 }
1332
1333 //
1334 // Get the boot VGA on the same segement
1335 //
1336 Temp = ActiveVGADeviceOnTheSameSegment (PciIoDevice);
1337
1338 if (Temp == NULL) {
1339 //
1340 // If there is no VGA device on the segement, set
1341 // this graphics card to decode the palette range
1342 //
1343 return EFI_SUCCESS;
1344 }
1345
1346 //
1347 // Check these two agents are on the same path
1348 //
1349 if (!PciDevicesOnTheSamePath (Temp, PciIoDevice)) {
1350 //
1351 // they are not on the same path, so snoop can be enabled or disabled
1352 //
1353 return EFI_SUCCESS;
1354 }
1355 //
1356 // Check if they are on the same bus
1357 //
1358 if (Temp->Parent == PciIoDevice->Parent) {
1359
1360 PCI_READ_COMMAND_REGISTER (Temp, &VGACommand);
1361
1362 //
1363 // If they are on the same bus, either one can
1364 // be set to snoop, the other set to decode
1365 //
1366 if ((VGACommand & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {
1367 //
1368 // VGA has set to snoop, so GFX can be only set to disable snoop
1369 //
1370 if (Operation == EfiPciIoAttributeOperationEnable) {
1371 return EFI_UNSUPPORTED;
1372 }
1373 } else {
1374 //
1375 // VGA has disabled to snoop, so GFX can be only enabled
1376 //
1377 if (Operation == EfiPciIoAttributeOperationDisable) {
1378 return EFI_UNSUPPORTED;
1379 }
1380 }
1381
1382 return EFI_SUCCESS;
1383 }
1384
1385 //
1386 // If they are on the same path but on the different bus
1387 // The first agent is set to snoop, the second one set to
1388 // decode
1389 //
1390
1391 if (Temp->BusNumber < PciIoDevice->BusNumber) {
1392 //
1393 // GFX should be set to decode
1394 //
1395 if (Operation == EfiPciIoAttributeOperationDisable) {
1396 PCI_ENABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);
1397 Temp->Attributes |= EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;
1398 } else {
1399 return EFI_UNSUPPORTED;
1400 }
1401
1402 } else {
1403 //
1404 // GFX should be set to snoop
1405 //
1406 if (Operation == EfiPciIoAttributeOperationEnable) {
1407 PCI_DISABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);
1408 Temp->Attributes &= (~EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);
1409 } else {
1410 return EFI_UNSUPPORTED;
1411 }
1412
1413 }
1414
1415 return EFI_SUCCESS;
1416 }
1417
1418 /**
1419 Performs an operation on the attributes that this PCI controller supports. The operations include
1420 getting the set of supported attributes, retrieving the current attributes, setting the current
1421 attributes, enabling attributes, and disabling attributes.
1422
1423 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1424 @param Operation The operation to perform on the attributes for this PCI controller.
1425 @param Attributes The mask of attributes that are used for Set, Enable, and Disable
1426 operations.
1427 @param Result A pointer to the result mask of attributes that are returned for the Get
1428 and Supported operations.
1429
1430 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.
1431 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1432 @retval EFI_UNSUPPORTED one or more of the bits set in
1433 Attributes are not supported by this PCI controller or one of
1434 its parent bridges when Operation is Set, Enable or Disable.
1435
1436 **/
1437 EFI_STATUS
1438 EFIAPI
1439 PciIoAttributes (
1440 IN EFI_PCI_IO_PROTOCOL * This,
1441 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
1442 IN UINT64 Attributes,
1443 OUT UINT64 *Result OPTIONAL
1444 )
1445 {
1446 EFI_STATUS Status;
1447
1448 PCI_IO_DEVICE *PciIoDevice;
1449 PCI_IO_DEVICE *UpStreamBridge;
1450 PCI_IO_DEVICE *Temp;
1451
1452 UINT64 Supports;
1453 UINT64 UpStreamAttributes;
1454 UINT16 BridgeControl;
1455 UINT16 Command;
1456
1457 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1458
1459 switch (Operation) {
1460 case EfiPciIoAttributeOperationGet:
1461 if (Result == NULL) {
1462 return EFI_INVALID_PARAMETER;
1463 }
1464
1465 *Result = PciIoDevice->Attributes;
1466 return EFI_SUCCESS;
1467
1468 case EfiPciIoAttributeOperationSupported:
1469 if (Result == NULL) {
1470 return EFI_INVALID_PARAMETER;
1471 }
1472
1473 *Result = PciIoDevice->Supports;
1474 return EFI_SUCCESS;
1475
1476 case EfiPciIoAttributeOperationSet:
1477 Status = PciIoDevice->PciIo.Attributes (
1478 &(PciIoDevice->PciIo),
1479 EfiPciIoAttributeOperationEnable,
1480 Attributes,
1481 NULL
1482 );
1483 if (EFI_ERROR (Status)) {
1484 return EFI_UNSUPPORTED;
1485 }
1486
1487 Status = PciIoDevice->PciIo.Attributes (
1488 &(PciIoDevice->PciIo),
1489 EfiPciIoAttributeOperationDisable,
1490 (~Attributes) & (PciIoDevice->Supports),
1491 NULL
1492 );
1493 if (EFI_ERROR (Status)) {
1494 return EFI_UNSUPPORTED;
1495 }
1496
1497 return EFI_SUCCESS;
1498
1499 case EfiPciIoAttributeOperationEnable:
1500 case EfiPciIoAttributeOperationDisable:
1501 break;
1502
1503 default:
1504 return EFI_INVALID_PARAMETER;
1505 }
1506 //
1507 // Just a trick for ENABLE attribute
1508 // EFI_PCI_DEVICE_ENABLE is not defined in UEFI spec, which is the internal usage.
1509 // So, this logic doesn't confrom to UEFI spec, which should be removed.
1510 // But this trick logic is still kept for some binary drivers that depend on it.
1511 //
1512 if ((Attributes & EFI_PCI_DEVICE_ENABLE) == EFI_PCI_DEVICE_ENABLE) {
1513 Attributes &= (PciIoDevice->Supports);
1514
1515 //
1516 // Raise the EFI_P_PC_ENABLE Status code
1517 //
1518 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
1519 EFI_PROGRESS_CODE,
1520 EFI_IO_BUS_PCI | EFI_P_PC_ENABLE,
1521 PciIoDevice->DevicePath
1522 );
1523 }
1524
1525 //
1526 // If no attributes can be supported, then return.
1527 // Otherwise, set the attributes that it can support.
1528 //
1529 Supports = (PciIoDevice->Supports) & Attributes;
1530 if (Supports != Attributes) {
1531 return EFI_UNSUPPORTED;
1532 }
1533
1534 //
1535 // For Root Bridge, just call RootBridgeIo to set attributes;
1536 //
1537 if (PciIoDevice->Parent == NULL) {
1538 Status = ModifyRootBridgeAttributes (PciIoDevice, Attributes, Operation);
1539 return Status;
1540 }
1541
1542 Command = 0;
1543 BridgeControl = 0;
1544
1545 //
1546 // Check VGA and VGA16, they can not be set at the same time
1547 //
1548 if (((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0 &&
1549 (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16) != 0) ||
1550 ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0 &&
1551 (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16) != 0) ||
1552 ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0 &&
1553 (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16) != 0) ||
1554 ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0 &&
1555 (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16) != 0) ) {
1556 return EFI_UNSUPPORTED;
1557 }
1558
1559 //
1560 // For PPB & P2C, set relevant attribute bits
1561 //
1562 if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
1563
1564 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {
1565 BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA;
1566 }
1567
1568 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_ISA_IO) != 0) {
1569 BridgeControl |= EFI_PCI_BRIDGE_CONTROL_ISA;
1570 }
1571
1572 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {
1573 Command |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;
1574 }
1575
1576 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {
1577 BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA_16;
1578 }
1579
1580 } else {
1581 //
1582 // Do with the attributes on VGA
1583 // Only for VGA's legacy resource, we just can enable once.
1584 //
1585 if ((Attributes &
1586 (EFI_PCI_IO_ATTRIBUTE_VGA_IO |
1587 EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 |
1588 EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY)) != 0) {
1589 //
1590 // Check if a VGA has been enabled before enabling a new one
1591 //
1592 if (Operation == EfiPciIoAttributeOperationEnable) {
1593 //
1594 // Check if there have been an active VGA device on the same segment
1595 //
1596 Temp = ActiveVGADeviceOnTheSameSegment (PciIoDevice);
1597 if (Temp != NULL && Temp != PciIoDevice) {
1598 //
1599 // An active VGA has been detected, so can not enable another
1600 //
1601 return EFI_UNSUPPORTED;
1602 }
1603 }
1604 }
1605
1606 //
1607 // Do with the attributes on GFX
1608 //
1609 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {
1610
1611 if (Operation == EfiPciIoAttributeOperationEnable) {
1612 //
1613 // Check if snoop can be enabled in current configuration
1614 //
1615 Status = SupportPaletteSnoopAttributes (PciIoDevice, Operation);
1616
1617 if (EFI_ERROR (Status)) {
1618
1619 //
1620 // Enable operation is forbidden, so mask the bit in attributes
1621 // so as to keep consistent with the actual Status
1622 //
1623 // Attributes &= (~EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO);
1624 //
1625 //
1626 //
1627 return EFI_UNSUPPORTED;
1628
1629 }
1630 }
1631
1632 //
1633 // It can be supported, so get ready to set the bit
1634 //
1635 Command |= EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;
1636 }
1637 }
1638
1639 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_IO) != 0) {
1640 Command |= EFI_PCI_COMMAND_IO_SPACE;
1641 }
1642
1643 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_MEMORY) != 0) {
1644 Command |= EFI_PCI_COMMAND_MEMORY_SPACE;
1645 }
1646
1647 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_BUS_MASTER) != 0) {
1648 Command |= EFI_PCI_COMMAND_BUS_MASTER;
1649 }
1650 //
1651 // The upstream bridge should be also set to revelant attribute
1652 // expect for IO, Mem and BusMaster
1653 //
1654 UpStreamAttributes = Attributes &
1655 (~(EFI_PCI_IO_ATTRIBUTE_IO |
1656 EFI_PCI_IO_ATTRIBUTE_MEMORY |
1657 EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
1658 )
1659 );
1660 UpStreamBridge = PciIoDevice->Parent;
1661
1662 if (Operation == EfiPciIoAttributeOperationEnable) {
1663 //
1664 // Enable relevant attributes to command register and bridge control register
1665 //
1666 Status = PCI_ENABLE_COMMAND_REGISTER (PciIoDevice, Command);
1667 if (BridgeControl != 0) {
1668 Status = PCI_ENABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);
1669 }
1670
1671 PciIoDevice->Attributes |= Attributes;
1672
1673 //
1674 // Enable attributes of the upstream bridge
1675 //
1676 Status = UpStreamBridge->PciIo.Attributes (
1677 &(UpStreamBridge->PciIo),
1678 EfiPciIoAttributeOperationEnable,
1679 UpStreamAttributes,
1680 NULL
1681 );
1682 } else {
1683
1684 //
1685 // Disable relevant attributes to command register and bridge control register
1686 //
1687 Status = PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, Command);
1688 if (BridgeControl != 0) {
1689 Status = PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);
1690 }
1691
1692 PciIoDevice->Attributes &= (~Attributes);
1693 Status = EFI_SUCCESS;
1694
1695 }
1696
1697 if (EFI_ERROR (Status)) {
1698 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
1699 }
1700
1701 return Status;
1702 }
1703
1704 /**
1705 Gets the attributes that this PCI controller supports setting on a BAR using
1706 SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.
1707
1708 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1709 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
1710 base address for resource range. The legal range for this field is 0..5.
1711 @param Supports A pointer to the mask of attributes that this PCI controller supports
1712 setting for this BAR with SetBarAttributes().
1713 @param Resources A pointer to the ACPI 2.0 resource descriptors that describe the current
1714 configuration of this BAR of the PCI controller.
1715
1716 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI
1717 controller supports are returned in Supports. If Resources
1718 is not NULL, then the ACPI 2.0 resource descriptors that the PCI
1719 controller is currently using are returned in Resources.
1720 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
1721 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
1722 @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate
1723 Resources.
1724
1725 **/
1726 EFI_STATUS
1727 EFIAPI
1728 PciIoGetBarAttributes (
1729 IN EFI_PCI_IO_PROTOCOL * This,
1730 IN UINT8 BarIndex,
1731 OUT UINT64 *Supports, OPTIONAL
1732 OUT VOID **Resources OPTIONAL
1733 )
1734 {
1735
1736 UINT8 *Configuration;
1737 UINT8 NumConfig;
1738 PCI_IO_DEVICE *PciIoDevice;
1739 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
1740 EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;
1741
1742 NumConfig = 0;
1743
1744 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1745
1746 if (Supports == NULL && Resources == NULL) {
1747 return EFI_INVALID_PARAMETER;
1748 }
1749
1750 if (BarIndex >= PCI_MAX_BAR) {
1751 return EFI_UNSUPPORTED;
1752 }
1753
1754 //
1755 // This driver does not support modifications to the WRITE_COMBINE or
1756 // CACHED attributes for BAR ranges.
1757 //
1758 if (Supports != NULL) {
1759 *Supports = PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED & EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE;
1760 }
1761
1762 if (Resources != NULL) {
1763
1764 if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeUnknown) {
1765 NumConfig = 1;
1766 }
1767
1768 Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
1769 if (Configuration == NULL) {
1770 return EFI_OUT_OF_RESOURCES;
1771 }
1772
1773 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
1774
1775 if (NumConfig == 1) {
1776 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1777 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
1778
1779 Ptr->AddrRangeMin = PciIoDevice->PciBar[BarIndex].BaseAddress;
1780 Ptr->AddrLen = PciIoDevice->PciBar[BarIndex].Length;
1781 Ptr->AddrRangeMax = PciIoDevice->PciBar[BarIndex].Alignment;
1782
1783 switch (PciIoDevice->PciBar[BarIndex].BarType) {
1784 case PciBarTypeIo16:
1785 case PciBarTypeIo32:
1786 //
1787 // Io
1788 //
1789 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
1790 break;
1791
1792 case PciBarTypeMem32:
1793 //
1794 // Mem
1795 //
1796 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1797 //
1798 // 32 bit
1799 //
1800 Ptr->AddrSpaceGranularity = 32;
1801 break;
1802
1803 case PciBarTypePMem32:
1804 //
1805 // Mem
1806 //
1807 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1808 //
1809 // prefechable
1810 //
1811 Ptr->SpecificFlag = 0x6;
1812 //
1813 // 32 bit
1814 //
1815 Ptr->AddrSpaceGranularity = 32;
1816 break;
1817
1818 case PciBarTypeMem64:
1819 //
1820 // Mem
1821 //
1822 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1823 //
1824 // 64 bit
1825 //
1826 Ptr->AddrSpaceGranularity = 64;
1827 break;
1828
1829 case PciBarTypePMem64:
1830 //
1831 // Mem
1832 //
1833 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1834 //
1835 // prefechable
1836 //
1837 Ptr->SpecificFlag = 0x6;
1838 //
1839 // 64 bit
1840 //
1841 Ptr->AddrSpaceGranularity = 64;
1842 break;
1843
1844 default:
1845 break;
1846 }
1847
1848 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ((UINT8 *) Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR));
1849 }
1850
1851 //
1852 // put the checksum
1853 //
1854 PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) ((UINT8 *) Ptr);
1855 PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;
1856 PtrEnd->Checksum = 0;
1857
1858 *Resources = Configuration;
1859 }
1860
1861 return EFI_SUCCESS;
1862 }
1863
1864 /**
1865 Sets the attributes for a range of a BAR on a PCI controller.
1866
1867 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1868 @param Attributes The mask of attributes to set for the resource range specified by
1869 BarIndex, Offset, and Length.
1870 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
1871 base address for resource range. The legal range for this field is 0..5.
1872 @param Offset A pointer to the BAR relative base address of the resource range to be
1873 modified by the attributes specified by Attributes.
1874 @param Length A pointer to the length of the resource range to be modified by the
1875 attributes specified by Attributes.
1876
1877 @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource
1878 range specified by BarIndex, Offset, and Length were
1879 set on the PCI controller, and the actual resource range is returned
1880 in Offset and Length.
1881 @retval EFI_INVALID_PARAMETER Offset or Length is NULL.
1882 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
1883 @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the
1884 resource range specified by BarIndex, Offset, and
1885 Length.
1886
1887 **/
1888 EFI_STATUS
1889 EFIAPI
1890 PciIoSetBarAttributes (
1891 IN EFI_PCI_IO_PROTOCOL *This,
1892 IN UINT64 Attributes,
1893 IN UINT8 BarIndex,
1894 IN OUT UINT64 *Offset,
1895 IN OUT UINT64 *Length
1896 )
1897 {
1898 EFI_STATUS Status;
1899 PCI_IO_DEVICE *PciIoDevice;
1900 UINT64 NonRelativeOffset;
1901 UINT64 Supports;
1902
1903 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1904
1905 //
1906 // Make sure Offset and Length are not NULL
1907 //
1908 if (Offset == NULL || Length == NULL) {
1909 return EFI_INVALID_PARAMETER;
1910 }
1911
1912 if (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeUnknown) {
1913 return EFI_UNSUPPORTED;
1914 }
1915 //
1916 // This driver does not support setting the WRITE_COMBINE or the CACHED attributes.
1917 // If Attributes is not 0, then return EFI_UNSUPPORTED.
1918 //
1919 Supports = PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED & EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE;
1920
1921 if (Attributes != (Attributes & Supports)) {
1922 return EFI_UNSUPPORTED;
1923 }
1924 //
1925 // Attributes must be supported. Make sure the BAR range describd by BarIndex, Offset, and
1926 // Length are valid for this PCI device.
1927 //
1928 NonRelativeOffset = *Offset;
1929 Status = PciIoVerifyBarAccess (
1930 PciIoDevice,
1931 BarIndex,
1932 PciBarTypeMem,
1933 EfiPciIoWidthUint8,
1934 (UINT32) *Length,
1935 &NonRelativeOffset
1936 );
1937 if (EFI_ERROR (Status)) {
1938 return EFI_UNSUPPORTED;
1939 }
1940
1941 return EFI_SUCCESS;
1942 }
1943
1944 /**
1945 Program parent bridge's attribute recurrently.
1946
1947 @param PciIoDevice Child Pci device instance
1948 @param Operation The operation to perform on the attributes for this PCI controller.
1949 @param Attributes The mask of attributes that are used for Set, Enable, and Disable
1950 operations.
1951
1952 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.
1953 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1954 @retval EFI_UNSUPPORTED one or more of the bits set in
1955 Attributes are not supported by this PCI controller or one of
1956 its parent bridges when Operation is Set, Enable or Disable.
1957
1958 **/
1959 EFI_STATUS
1960 UpStreamBridgesAttributes (
1961 IN PCI_IO_DEVICE *PciIoDevice,
1962 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
1963 IN UINT64 Attributes
1964 )
1965 {
1966 PCI_IO_DEVICE *Parent;
1967 EFI_PCI_IO_PROTOCOL *PciIo;
1968
1969 Parent = PciIoDevice->Parent;
1970
1971 while (Parent != NULL && IS_PCI_BRIDGE (&Parent->Pci)) {
1972
1973 //
1974 // Get the PciIo Protocol
1975 //
1976 PciIo = &Parent->PciIo;
1977
1978 PciIo->Attributes (PciIo, Operation, Attributes, NULL);
1979
1980 Parent = Parent->Parent;
1981 }
1982
1983 return EFI_SUCCESS;
1984 }
1985
1986 /**
1987 Test whether two Pci devices has same parent bridge.
1988
1989 @param PciDevice1 The first pci device for testing.
1990 @param PciDevice2 The second pci device for testing.
1991
1992 @retval TRUE Two Pci device has the same parent bridge.
1993 @retval FALSE Two Pci device has not the same parent bridge.
1994
1995 **/
1996 BOOLEAN
1997 PciDevicesOnTheSamePath (
1998 IN PCI_IO_DEVICE *PciDevice1,
1999 IN PCI_IO_DEVICE *PciDevice2
2000 )
2001 {
2002 BOOLEAN Existed1;
2003 BOOLEAN Existed2;
2004
2005 if (PciDevice1->Parent == PciDevice2->Parent) {
2006 return TRUE;
2007 }
2008
2009 Existed1 = PciDeviceExisted (PciDevice1->Parent, PciDevice2);
2010 Existed2 = PciDeviceExisted (PciDevice2->Parent, PciDevice1);
2011
2012 return (BOOLEAN) (Existed1 || Existed2);
2013 }
2014
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