MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c

   1 /** @file
   2   EFI PCI IO protocol functions implementation for PCI Bus module.
   3
   4 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
   5 SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9 #include "PciBus.h"
  10
  11 extern EDKII_IOMMU_PROTOCOL  *mIoMmuProtocol;
  12
  13 //
  14 // Pci Io Protocol Interface
  15 //
  16 EFI_PCI_IO_PROTOCOL  mPciIoInterface = {
  17   PciIoPollMem,
  18   PciIoPollIo,
  19   {
  20     PciIoMemRead,
  21     PciIoMemWrite
  22   },
  23   {
  24     PciIoIoRead,
  25     PciIoIoWrite
  26   },
  27   {
  28     PciIoConfigRead,
  29     PciIoConfigWrite
  30   },
  31   PciIoCopyMem,
  32   PciIoMap,
  33   PciIoUnmap,
  34   PciIoAllocateBuffer,
  35   PciIoFreeBuffer,
  36   PciIoFlush,
  37   PciIoGetLocation,
  38   PciIoAttributes,
  39   PciIoGetBarAttributes,
  40   PciIoSetBarAttributes,
  41   0,
  42   NULL
  43 };
  44
  45 /**
  46   Initializes a PCI I/O Instance.
  47
  48   @param PciIoDevice    Pci device instance.
  49
  50 **/
  51 VOID
  52 InitializePciIoInstance (
  53   IN PCI_IO_DEVICE  *PciIoDevice
  54   )
  55 {
  56   CopyMem (&PciIoDevice->PciIo, &mPciIoInterface, sizeof (EFI_PCI_IO_PROTOCOL));
  57 }
  58
  59 /**
  60   Verifies access to a PCI Base Address Register (BAR).
  61
  62   @param PciIoDevice  Pci device instance.
  63   @param BarIndex     The BAR index of the standard PCI Configuration header to use as the
  64                       base address for the memory or I/O operation to perform.
  65   @param Type         Operation type could be memory or I/O.
  66   @param Width        Signifies the width of the memory or I/O operations.
  67   @param Count        The number of memory or I/O operations to perform.
  68   @param Offset       The offset within the PCI configuration space for the PCI controller.
  69
  70   @retval EFI_INVALID_PARAMETER Invalid Width/BarIndex or Bar type.
  71   @retval EFI_SUCCESS           Successfully verified.
  72
  73 **/
  74 EFI_STATUS
  75 PciIoVerifyBarAccess (
  76   IN PCI_IO_DEVICE                 *PciIoDevice,
  77   IN UINT8                         BarIndex,
  78   IN PCI_BAR_TYPE                  Type,
  79   IN IN EFI_PCI_IO_PROTOCOL_WIDTH  Width,
  80   IN IN UINTN                      Count,
  81   IN UINT64                        *Offset
  82   )
  83 {
  84   if ((UINT32)Width >= EfiPciIoWidthMaximum) {
  85     return EFI_INVALID_PARAMETER;
  86   }
  87
  88   if (BarIndex == EFI_PCI_IO_PASS_THROUGH_BAR) {
  89     return EFI_SUCCESS;
  90   }
  91
  92   //
  93   // BarIndex 0-5 is legal
  94   //
  95   if (BarIndex >= PCI_MAX_BAR) {
  96     return EFI_INVALID_PARAMETER;
  97   }
  98
  99   if (!CheckBarType (PciIoDevice, BarIndex, Type)) {
 100     return EFI_INVALID_PARAMETER;
 101   }
 102
 103   //
 104   // If Width is EfiPciIoWidthFifoUintX then convert to EfiPciIoWidthUintX
 105   // If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX
 106   //
 107   if ((Width >= EfiPciIoWidthFifoUint8) && (Width <= EfiPciIoWidthFifoUint64)) {
 108     Count = 1;
 109   }
 110
 111   Width = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & 0x03);
 112
 113   if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PciIoDevice->PciBar[BarIndex].Length) {
 114     return EFI_INVALID_PARAMETER;
 115   }
 116
 117   *Offset = *Offset + PciIoDevice->PciBar[BarIndex].BaseAddress;
 118
 119   return EFI_SUCCESS;
 120 }
 121
 122 /**
 123   Verifies access to a PCI Configuration Header.
 124
 125   @param PciIoDevice  Pci device instance.
 126   @param Width        Signifies the width of the memory or I/O operations.
 127   @param Count        The number of memory or I/O operations to perform.
 128   @param Offset       The offset within the PCI configuration space for the PCI controller.
 129
 130   @retval EFI_INVALID_PARAMETER  Invalid Width
 131   @retval EFI_UNSUPPORTED        Offset overflowed.
 132   @retval EFI_SUCCESS            Successfully verified.
 133
 134 **/
 135 EFI_STATUS
 136 PciIoVerifyConfigAccess (
 137   IN PCI_IO_DEVICE              *PciIoDevice,
 138   IN EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 139   IN UINTN                      Count,
 140   IN UINT64                     *Offset
 141   )
 142 {
 143   UINT64  ExtendOffset;
 144
 145   if ((UINT32)Width >= EfiPciIoWidthMaximum) {
 146     return EFI_INVALID_PARAMETER;
 147   }
 148
 149   //
 150   // If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX
 151   //
 152   Width = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & 0x03);
 153
 154   if (PciIoDevice->IsPciExp) {
 155     if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PCI_EXP_MAX_CONFIG_OFFSET) {
 156       return EFI_UNSUPPORTED;
 157     }
 158
 159     ExtendOffset = LShiftU64 (*Offset, 32);
 160     *Offset      = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, 0);
 161     *Offset      = (*Offset) | ExtendOffset;
 162   } else {
 163     if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PCI_MAX_CONFIG_OFFSET) {
 164       return EFI_UNSUPPORTED;
 165     }
 166
 167     *Offset = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, *Offset);
 168   }
 169
 170   return EFI_SUCCESS;
 171 }
 172
 173 /**
 174   Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is
 175   satisfied or after a defined duration.
 176
 177   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 178   @param  Width                 Signifies the width of the memory or I/O operations.
 179   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
 180                                 base address for the memory operation to perform.
 181   @param  Offset                The offset within the selected BAR to start the memory operation.
 182   @param  Mask                  Mask used for the polling criteria.
 183   @param  Value                 The comparison value used for the polling exit criteria.
 184   @param  Delay                 The number of 100 ns units to poll.
 185   @param  Result                Pointer to the last value read from the memory location.
 186
 187   @retval EFI_SUCCESS           The last data returned from the access matched the poll exit criteria.
 188   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
 189   @retval EFI_UNSUPPORTED       Offset is not valid for the BarIndex of this PCI controller.
 190   @retval EFI_TIMEOUT           Delay expired before a match occurred.
 191   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 192   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 193
 194 **/
 195 EFI_STATUS
 196 EFIAPI
 197 PciIoPollMem (
 198   IN  EFI_PCI_IO_PROTOCOL        *This,
 199   IN  EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 200   IN  UINT8                      BarIndex,
 201   IN  UINT64                     Offset,
 202   IN  UINT64                     Mask,
 203   IN  UINT64                     Value,
 204   IN  UINT64                     Delay,
 205   OUT UINT64                     *Result
 206   )
 207 {
 208   EFI_STATUS     Status;
 209   PCI_IO_DEVICE  *PciIoDevice;
 210
 211   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
 212
 213   if ((UINT32)Width >= EfiPciIoWidthMaximum) {
 214     return EFI_INVALID_PARAMETER;
 215   }
 216
 217   Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, 1, &Offset);
 218   if (EFI_ERROR (Status)) {
 219     return EFI_UNSUPPORTED;
 220   }
 221
 222   if (Width > EfiPciIoWidthUint64) {
 223     return EFI_INVALID_PARAMETER;
 224   }
 225
 226   //
 227   // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
 228   //
 229   if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
 230     if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
 231       Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);
 232       if (EFI_ERROR (Status)) {
 233         return Status;
 234       }
 235
 236       if (((*Result & Mask) == Value) || (Delay == 0)) {
 237         return EFI_SUCCESS;
 238       }
 239
 240       do {
 241         //
 242         // Stall 10 us = 100 * 100ns
 243         //
 244         gBS->Stall (10);
 245
 246         Status = PciIoMemRead (This, Width, BarIndex, Offset, 1, Result);
 247         if (EFI_ERROR (Status)) {
 248           return Status;
 249         }
 250
 251         if ((*Result & Mask) == Value) {
 252           return EFI_SUCCESS;
 253         }
 254
 255         if (Delay <= 100) {
 256           return EFI_TIMEOUT;
 257         }
 258
 259         Delay -= 100;
 260       } while (TRUE);
 261     }
 262   }
 263
 264   Status = PciIoDevice->PciRootBridgeIo->PollMem (
 265                                            PciIoDevice->PciRootBridgeIo,
 266                                            (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
 267                                            Offset,
 268                                            Mask,
 269                                            Value,
 270                                            Delay,
 271                                            Result
 272                                            );
 273
 274   if (EFI_ERROR (Status)) {
 275     REPORT_STATUS_CODE_WITH_DEVICE_PATH (
 276       EFI_ERROR_CODE | EFI_ERROR_MINOR,
 277       EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,
 278       PciIoDevice->DevicePath
 279       );
 280   }
 281
 282   return Status;
 283 }
 284
 285 /**
 286   Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is
 287   satisfied or after a defined duration.
 288
 289   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 290   @param  Width                 Signifies the width of the memory or I/O operations.
 291   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
 292                                 base address for the memory operation to perform.
 293   @param  Offset                The offset within the selected BAR to start the memory operation.
 294   @param  Mask                  Mask used for the polling criteria.
 295   @param  Value                 The comparison value used for the polling exit criteria.
 296   @param  Delay                 The number of 100 ns units to poll.
 297   @param  Result                Pointer to the last value read from the memory location.
 298
 299   @retval EFI_SUCCESS           The last data returned from the access matched the poll exit criteria.
 300   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
 301   @retval EFI_UNSUPPORTED       Offset is not valid for the BarIndex of this PCI controller.
 302   @retval EFI_TIMEOUT           Delay expired before a match occurred.
 303   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 304   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 305
 306 **/
 307 EFI_STATUS
 308 EFIAPI
 309 PciIoPollIo (
 310   IN  EFI_PCI_IO_PROTOCOL        *This,
 311   IN  EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 312   IN  UINT8                      BarIndex,
 313   IN  UINT64                     Offset,
 314   IN  UINT64                     Mask,
 315   IN  UINT64                     Value,
 316   IN  UINT64                     Delay,
 317   OUT UINT64                     *Result
 318   )
 319 {
 320   EFI_STATUS     Status;
 321   PCI_IO_DEVICE  *PciIoDevice;
 322
 323   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
 324
 325   if ((UINT32)Width > EfiPciIoWidthUint64) {
 326     return EFI_INVALID_PARAMETER;
 327   }
 328
 329   Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, 1, &Offset);
 330   if (EFI_ERROR (Status)) {
 331     return EFI_UNSUPPORTED;
 332   }
 333
 334   //
 335   // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
 336   //
 337   if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
 338     if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
 339       Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);
 340       if (EFI_ERROR (Status)) {
 341         return Status;
 342       }
 343
 344       if (((*Result & Mask) == Value) || (Delay == 0)) {
 345         return EFI_SUCCESS;
 346       }
 347
 348       do {
 349         //
 350         // Stall 10 us = 100 * 100ns
 351         //
 352         gBS->Stall (10);
 353
 354         Status = PciIoIoRead (This, Width, BarIndex, Offset, 1, Result);
 355         if (EFI_ERROR (Status)) {
 356           return Status;
 357         }
 358
 359         if ((*Result & Mask) == Value) {
 360           return EFI_SUCCESS;
 361         }
 362
 363         if (Delay <= 100) {
 364           return EFI_TIMEOUT;
 365         }
 366
 367         Delay -= 100;
 368       } while (TRUE);
 369     }
 370   }
 371
 372   Status = PciIoDevice->PciRootBridgeIo->PollIo (
 373                                            PciIoDevice->PciRootBridgeIo,
 374                                            (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
 375                                            Offset,
 376                                            Mask,
 377                                            Value,
 378                                            Delay,
 379                                            Result
 380                                            );
 381
 382   if (EFI_ERROR (Status)) {
 383     REPORT_STATUS_CODE_WITH_DEVICE_PATH (
 384       EFI_ERROR_CODE | EFI_ERROR_MINOR,
 385       EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,
 386       PciIoDevice->DevicePath
 387       );
 388   }
 389
 390   return Status;
 391 }
 392
 393 /**
 394   Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
 395
 396   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 397   @param  Width                 Signifies the width of the memory or I/O operations.
 398   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
 399                                 base address for the memory or I/O operation to perform.
 400   @param  Offset                The offset within the selected BAR to start the memory or I/O operation.
 401   @param  Count                 The number of memory or I/O operations to perform.
 402   @param  Buffer                For read operations, the destination buffer to store the results. For write
 403                                 operations, the source buffer to write data from.
 404
 405   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
 406   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
 407   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
 408                                 valid for the PCI BAR specified by BarIndex.
 409   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 410   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 411
 412 **/
 413 EFI_STATUS
 414 EFIAPI
 415 PciIoMemRead (
 416   IN     EFI_PCI_IO_PROTOCOL        *This,
 417   IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 418   IN     UINT8                      BarIndex,
 419   IN     UINT64                     Offset,
 420   IN     UINTN                      Count,
 421   IN OUT VOID                       *Buffer
 422   )
 423 {
 424   EFI_STATUS     Status;
 425   PCI_IO_DEVICE  *PciIoDevice;
 426
 427   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
 428
 429   if ((UINT32)Width >= EfiPciIoWidthMaximum) {
 430     return EFI_INVALID_PARAMETER;
 431   }
 432
 433   if (Buffer == NULL) {
 434     return EFI_INVALID_PARAMETER;
 435   }
 436
 437   Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, Count, &Offset);
 438   if (EFI_ERROR (Status)) {
 439     return EFI_UNSUPPORTED;
 440   }
 441
 442   //
 443   // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
 444   //
 445   if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
 446     if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
 447       Count *=  (UINTN)(1 << (Width & 0x03));
 448       Width  = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & (~0x03));
 449     }
 450   }
 451
 452   Status = PciIoDevice->PciRootBridgeIo->Mem.Read (
 453                                                PciIoDevice->PciRootBridgeIo,
 454                                                (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
 455                                                Offset,
 456                                                Count,
 457                                                Buffer
 458                                                );
 459
 460   if (EFI_ERROR (Status)) {
 461     REPORT_STATUS_CODE_WITH_DEVICE_PATH (
 462       EFI_ERROR_CODE | EFI_ERROR_MINOR,
 463       EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR,
 464       PciIoDevice->DevicePath
 465       );
 466   }
 467
 468   return Status;
 469 }
 470
 471 /**
 472   Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
 473
 474   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 475   @param  Width                 Signifies the width of the memory or I/O operations.
 476   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
 477                                 base address for the memory or I/O operation to perform.
 478   @param  Offset                The offset within the selected BAR to start the memory or I/O operation.
 479   @param  Count                 The number of memory or I/O operations to perform.
 480   @param  Buffer                For read operations, the destination buffer to store the results. For write
 481                                 operations, the source buffer to write data from.
 482
 483   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
 484   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
 485   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
 486                                 valid for the PCI BAR specified by BarIndex.
 487   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 488   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 489
 490 **/
 491 EFI_STATUS
 492 EFIAPI
 493 PciIoMemWrite (
 494   IN     EFI_PCI_IO_PROTOCOL        *This,
 495   IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 496   IN     UINT8                      BarIndex,
 497   IN     UINT64                     Offset,
 498   IN     UINTN                      Count,
 499   IN OUT VOID                       *Buffer
 500   )
 501 {
 502   EFI_STATUS     Status;
 503   PCI_IO_DEVICE  *PciIoDevice;
 504
 505   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
 506
 507   if ((UINT32)Width >= EfiPciIoWidthMaximum) {
 508     return EFI_INVALID_PARAMETER;
 509   }
 510
 511   if (Buffer == NULL) {
 512     return EFI_INVALID_PARAMETER;
 513   }
 514
 515   Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, Count, &Offset);
 516   if (EFI_ERROR (Status)) {
 517     return EFI_UNSUPPORTED;
 518   }
 519
 520   //
 521   // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
 522   //
 523   if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
 524     if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
 525       Count *=  (UINTN)(1 << (Width & 0x03));
 526       Width  = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & (~0x03));
 527     }
 528   }
 529
 530   Status = PciIoDevice->PciRootBridgeIo->Mem.Write (
 531                                                PciIoDevice->PciRootBridgeIo,
 532                                                (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
 533                                                Offset,
 534                                                Count,
 535                                                Buffer
 536                                                );
 537
 538   if (EFI_ERROR (Status)) {
 539     REPORT_STATUS_CODE_WITH_DEVICE_PATH (
 540       EFI_ERROR_CODE | EFI_ERROR_MINOR,
 541       EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR,
 542       PciIoDevice->DevicePath
 543       );
 544   }
 545
 546   return Status;
 547 }
 548
 549 /**
 550   Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
 551
 552   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 553   @param  Width                 Signifies the width of the memory or I/O operations.
 554   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
 555                                 base address for the memory or I/O operation to perform.
 556   @param  Offset                The offset within the selected BAR to start the memory or I/O operation.
 557   @param  Count                 The number of memory or I/O operations to perform.
 558   @param  Buffer                For read operations, the destination buffer to store the results. For write
 559                                 operations, the source buffer to write data from.
 560
 561   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
 562   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
 563   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
 564                                 valid for the PCI BAR specified by BarIndex.
 565   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 566   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 567
 568 **/
 569 EFI_STATUS
 570 EFIAPI
 571 PciIoIoRead (
 572   IN     EFI_PCI_IO_PROTOCOL        *This,
 573   IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 574   IN     UINT8                      BarIndex,
 575   IN     UINT64                     Offset,
 576   IN     UINTN                      Count,
 577   IN OUT VOID                       *Buffer
 578   )
 579 {
 580   EFI_STATUS     Status;
 581   PCI_IO_DEVICE  *PciIoDevice;
 582
 583   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
 584
 585   if ((UINT32)Width >= EfiPciIoWidthMaximum) {
 586     return EFI_INVALID_PARAMETER;
 587   }
 588
 589   if (Buffer == NULL) {
 590     return EFI_INVALID_PARAMETER;
 591   }
 592
 593   Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, Count, &Offset);
 594   if (EFI_ERROR (Status)) {
 595     return EFI_UNSUPPORTED;
 596   }
 597
 598   //
 599   // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
 600   //
 601   if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
 602     if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
 603       Count *=  (UINTN)(1 << (Width & 0x03));
 604       Width  = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & (~0x03));
 605     }
 606   }
 607
 608   Status = PciIoDevice->PciRootBridgeIo->Io.Read (
 609                                               PciIoDevice->PciRootBridgeIo,
 610                                               (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
 611                                               Offset,
 612                                               Count,
 613                                               Buffer
 614                                               );
 615
 616   if (EFI_ERROR (Status)) {
 617     REPORT_STATUS_CODE_WITH_DEVICE_PATH (
 618       EFI_ERROR_CODE | EFI_ERROR_MINOR,
 619       EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR,
 620       PciIoDevice->DevicePath
 621       );
 622   }
 623
 624   return Status;
 625 }
 626
 627 /**
 628   Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
 629
 630   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 631   @param  Width                 Signifies the width of the memory or I/O operations.
 632   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
 633                                 base address for the memory or I/O operation to perform.
 634   @param  Offset                The offset within the selected BAR to start the memory or I/O operation.
 635   @param  Count                 The number of memory or I/O operations to perform.
 636   @param  Buffer                For read operations, the destination buffer to store the results. For write
 637                                 operations, the source buffer to write data from.
 638
 639   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
 640   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
 641   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
 642                                 valid for the PCI BAR specified by BarIndex.
 643   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 644   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 645
 646 **/
 647 EFI_STATUS
 648 EFIAPI
 649 PciIoIoWrite (
 650   IN     EFI_PCI_IO_PROTOCOL        *This,
 651   IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 652   IN     UINT8                      BarIndex,
 653   IN     UINT64                     Offset,
 654   IN     UINTN                      Count,
 655   IN OUT VOID                       *Buffer
 656   )
 657 {
 658   EFI_STATUS     Status;
 659   PCI_IO_DEVICE  *PciIoDevice;
 660
 661   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
 662
 663   if ((UINT32)Width >= EfiPciIoWidthMaximum) {
 664     return EFI_INVALID_PARAMETER;
 665   }
 666
 667   if (Buffer == NULL) {
 668     return EFI_INVALID_PARAMETER;
 669   }
 670
 671   Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, Count, &Offset);
 672   if (EFI_ERROR (Status)) {
 673     return EFI_UNSUPPORTED;
 674   }
 675
 676   //
 677   // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
 678   //
 679   if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
 680     if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
 681       Count *=  (UINTN)(1 << (Width & 0x03));
 682       Width  = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & (~0x03));
 683     }
 684   }
 685
 686   Status = PciIoDevice->PciRootBridgeIo->Io.Write (
 687                                               PciIoDevice->PciRootBridgeIo,
 688                                               (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
 689                                               Offset,
 690                                               Count,
 691                                               Buffer
 692                                               );
 693
 694   if (EFI_ERROR (Status)) {
 695     REPORT_STATUS_CODE_WITH_DEVICE_PATH (
 696       EFI_ERROR_CODE | EFI_ERROR_MINOR,
 697       EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR,
 698       PciIoDevice->DevicePath
 699       );
 700   }
 701
 702   return Status;
 703 }
 704
 705 /**
 706   Enable a PCI driver to access PCI controller registers in PCI configuration space.
 707
 708   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 709   @param  Width                 Signifies the width of the memory operations.
 710   @param  Offset                The offset within the PCI configuration space for the PCI controller.
 711   @param  Count                 The number of PCI configuration operations to perform.
 712   @param  Buffer                For read operations, the destination buffer to store the results. For write
 713                                 operations, the source buffer to write data from.
 714
 715
 716   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
 717   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
 718                                 valid for the PCI configuration header of the PCI controller.
 719   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 720   @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
 721
 722 **/
 723 EFI_STATUS
 724 EFIAPI
 725 PciIoConfigRead (
 726   IN     EFI_PCI_IO_PROTOCOL        *This,
 727   IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 728   IN     UINT32                     Offset,
 729   IN     UINTN                      Count,
 730   IN OUT VOID                       *Buffer
 731   )
 732 {
 733   EFI_STATUS     Status;
 734   PCI_IO_DEVICE  *PciIoDevice;
 735   UINT64         Address;
 736
 737   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
 738
 739   Address = Offset;
 740   Status  = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);
 741   if (EFI_ERROR (Status)) {
 742     return Status;
 743   }
 744
 745   //
 746   // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
 747   //
 748   if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
 749     if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
 750       Count *=  (UINTN)(1 << (Width & 0x03));
 751       Width  = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & (~0x03));
 752     }
 753   }
 754
 755   Status = PciIoDevice->PciRootBridgeIo->Pci.Read (
 756                                                PciIoDevice->PciRootBridgeIo,
 757                                                (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
 758                                                Address,
 759                                                Count,
 760                                                Buffer
 761                                                );
 762
 763   if (EFI_ERROR (Status)) {
 764     REPORT_STATUS_CODE_WITH_DEVICE_PATH (
 765       EFI_ERROR_CODE | EFI_ERROR_MINOR,
 766       EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR,
 767       PciIoDevice->DevicePath
 768       );
 769   }
 770
 771   return Status;
 772 }
 773
 774 /**
 775   Enable a PCI driver to access PCI controller registers in PCI configuration space.
 776
 777   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 778   @param  Width                 Signifies the width of the memory operations.
 779   @param  Offset                The offset within the PCI configuration space for the PCI controller.
 780   @param  Count                 The number of PCI configuration operations to perform.
 781   @param  Buffer                For read operations, the destination buffer to store the results. For write
 782                                 operations, the source buffer to write data from.
 783
 784
 785   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
 786   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
 787                                 valid for the PCI configuration header of the PCI controller.
 788   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 789   @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
 790
 791 **/
 792 EFI_STATUS
 793 EFIAPI
 794 PciIoConfigWrite (
 795   IN     EFI_PCI_IO_PROTOCOL        *This,
 796   IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 797   IN     UINT32                     Offset,
 798   IN     UINTN                      Count,
 799   IN OUT VOID                       *Buffer
 800   )
 801 {
 802   EFI_STATUS     Status;
 803   PCI_IO_DEVICE  *PciIoDevice;
 804   UINT64         Address;
 805
 806   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
 807
 808   Address = Offset;
 809   Status  = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);
 810   if (EFI_ERROR (Status)) {
 811     return Status;
 812   }
 813
 814   //
 815   // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
 816   //
 817   if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
 818     if ((Offset & ((1 << (Width & 0x03)) - 1)) != 0) {
 819       Count *=  (UINTN)(1 << (Width & 0x03));
 820       Width  = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & (~0x03));
 821     }
 822   }
 823
 824   Status = PciIoDevice->PciRootBridgeIo->Pci.Write (
 825                                                PciIoDevice->PciRootBridgeIo,
 826                                                (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
 827                                                Address,
 828                                                Count,
 829                                                Buffer
 830                                                );
 831
 832   if (EFI_ERROR (Status)) {
 833     REPORT_STATUS_CODE_WITH_DEVICE_PATH (
 834       EFI_ERROR_CODE | EFI_ERROR_MINOR,
 835       EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR,
 836       PciIoDevice->DevicePath
 837       );
 838   }
 839
 840   return Status;
 841 }
 842
 843 /**
 844   Enables a PCI driver to copy one region of PCI memory space to another region of PCI
 845   memory space.
 846
 847   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 848   @param  Width                 Signifies the width of the memory operations.
 849   @param  DestBarIndex          The BAR index in the standard PCI Configuration header to use as the
 850                                 base address for the memory operation to perform.
 851   @param  DestOffset            The destination offset within the BAR specified by DestBarIndex to
 852                                 start the memory writes for the copy operation.
 853   @param  SrcBarIndex           The BAR index in the standard PCI Configuration header to use as the
 854                                 base address for the memory operation to perform.
 855   @param  SrcOffset             The source offset within the BAR specified by SrcBarIndex to start
 856                                 the memory reads for the copy operation.
 857   @param  Count                 The number of memory operations to perform. Bytes moved is Width
 858                                 size * Count, starting at DestOffset and SrcOffset.
 859
 860   @retval EFI_SUCCESS           The data was copied from one memory region to another memory region.
 861   @retval EFI_UNSUPPORTED       DestBarIndex not valid for this PCI controller.
 862   @retval EFI_UNSUPPORTED       SrcBarIndex not valid for this PCI controller.
 863   @retval EFI_UNSUPPORTED       The address range specified by DestOffset, Width, and Count
 864                                 is not valid for the PCI BAR specified by DestBarIndex.
 865   @retval EFI_UNSUPPORTED       The address range specified by SrcOffset, Width, and Count is
 866                                 not valid for the PCI BAR specified by SrcBarIndex.
 867   @retval EFI_INVALID_PARAMETER Width is invalid.
 868   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 869
 870 **/
 871 EFI_STATUS
 872 EFIAPI
 873 PciIoCopyMem (
 874   IN EFI_PCI_IO_PROTOCOL            *This,
 875   IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 876   IN     UINT8                      DestBarIndex,
 877   IN     UINT64                     DestOffset,
 878   IN     UINT8                      SrcBarIndex,
 879   IN     UINT64                     SrcOffset,
 880   IN     UINTN                      Count
 881   )
 882 {
 883   EFI_STATUS     Status;
 884   PCI_IO_DEVICE  *PciIoDevice;
 885
 886   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
 887
 888   if ((UINT32)Width >= EfiPciIoWidthMaximum) {
 889     return EFI_INVALID_PARAMETER;
 890   }
 891
 892   if ((Width == EfiPciIoWidthFifoUint8) ||
 893       (Width == EfiPciIoWidthFifoUint16) ||
 894       (Width == EfiPciIoWidthFifoUint32) ||
 895       (Width == EfiPciIoWidthFifoUint64) ||
 896       (Width == EfiPciIoWidthFillUint8) ||
 897       (Width == EfiPciIoWidthFillUint16) ||
 898       (Width == EfiPciIoWidthFillUint32) ||
 899       (Width == EfiPciIoWidthFillUint64))
 900   {
 901     return EFI_INVALID_PARAMETER;
 902   }
 903
 904   Status = PciIoVerifyBarAccess (PciIoDevice, DestBarIndex, PciBarTypeMem, Width, Count, &DestOffset);
 905   if (EFI_ERROR (Status)) {
 906     return EFI_UNSUPPORTED;
 907   }
 908
 909   Status = PciIoVerifyBarAccess (PciIoDevice, SrcBarIndex, PciBarTypeMem, Width, Count, &SrcOffset);
 910   if (EFI_ERROR (Status)) {
 911     return EFI_UNSUPPORTED;
 912   }
 913
 914   //
 915   // If request is not aligned, then convert request to EfiPciIoWithXXXUint8
 916   //
 917   if (FeaturePcdGet (PcdUnalignedPciIoEnable)) {
 918     if (((SrcOffset & ((1 << (Width & 0x03)) - 1)) != 0) || ((DestOffset & ((1 << (Width & 0x03)) - 1)) != 0)) {
 919       Count *=  (UINTN)(1 << (Width & 0x03));
 920       Width  = (EFI_PCI_IO_PROTOCOL_WIDTH)(Width & (~0x03));
 921     }
 922   }
 923
 924   Status = PciIoDevice->PciRootBridgeIo->CopyMem (
 925                                            PciIoDevice->PciRootBridgeIo,
 926                                            (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
 927                                            DestOffset,
 928                                            SrcOffset,
 929                                            Count
 930                                            );
 931
 932   if (EFI_ERROR (Status)) {
 933     REPORT_STATUS_CODE_WITH_DEVICE_PATH (
 934       EFI_ERROR_CODE | EFI_ERROR_MINOR,
 935       EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,
 936       PciIoDevice->DevicePath
 937       );
 938   }
 939
 940   return Status;
 941 }
 942
 943 /**
 944   Provides the PCI controller-specific addresses needed to access system memory.
 945
 946   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 947   @param  Operation             Indicates if the bus master is going to read or write to system memory.
 948   @param  HostAddress           The system memory address to map to the PCI controller.
 949   @param  NumberOfBytes         On input the number of bytes to map. On output the number of bytes
 950                                 that were mapped.
 951   @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to
 952                                 access the hosts HostAddress.
 953   @param  Mapping               A resulting value to pass to Unmap().
 954
 955   @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.
 956   @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.
 957   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 958   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 959   @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.
 960
 961 **/
 962 EFI_STATUS
 963 EFIAPI
 964 PciIoMap (
 965   IN     EFI_PCI_IO_PROTOCOL            *This,
 966   IN     EFI_PCI_IO_PROTOCOL_OPERATION  Operation,
 967   IN     VOID                           *HostAddress,
 968   IN OUT UINTN                          *NumberOfBytes,
 969   OUT    EFI_PHYSICAL_ADDRESS           *DeviceAddress,
 970   OUT    VOID                           **Mapping
 971   )
 972 {
 973   EFI_STATUS                                 Status;
 974   PCI_IO_DEVICE                              *PciIoDevice;
 975   UINT64                                     IoMmuAttribute;
 976   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  RootBridgeIoOperation;
 977
 978   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
 979
 980   if ((UINT32)Operation >= EfiPciIoOperationMaximum) {
 981     return EFI_INVALID_PARAMETER;
 982   }
 983
 984   if ((HostAddress == NULL) || (NumberOfBytes == NULL) || (DeviceAddress == NULL) || (Mapping == NULL)) {
 985     return EFI_INVALID_PARAMETER;
 986   }
 987
 988   RootBridgeIoOperation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION)Operation;
 989   if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) != 0) {
 990     RootBridgeIoOperation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION)(Operation + EfiPciOperationBusMasterRead64);
 991   }
 992
 993   Status = PciIoDevice->PciRootBridgeIo->Map (
 994                                            PciIoDevice->PciRootBridgeIo,
 995                                            RootBridgeIoOperation,
 996                                            HostAddress,
 997                                            NumberOfBytes,
 998                                            DeviceAddress,
 999                                            Mapping
1000                                            );
1001
1002   if (EFI_ERROR (Status)) {
1003     REPORT_STATUS_CODE_WITH_DEVICE_PATH (
1004       EFI_ERROR_CODE | EFI_ERROR_MINOR,
1005       EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,
1006       PciIoDevice->DevicePath
1007       );
1008   }
1009
1010   if (mIoMmuProtocol != NULL) {
1011     if (!EFI_ERROR (Status)) {
1012       switch (Operation) {
1013         case EfiPciIoOperationBusMasterRead:
1014           IoMmuAttribute = EDKII_IOMMU_ACCESS_READ;
1015           break;
1016         case EfiPciIoOperationBusMasterWrite:
1017           IoMmuAttribute = EDKII_IOMMU_ACCESS_WRITE;
1018           break;
1019         case EfiPciIoOperationBusMasterCommonBuffer:
1020           IoMmuAttribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
1021           break;
1022         default:
1023           ASSERT (FALSE);
1024           return EFI_INVALID_PARAMETER;
1025       }
1026
1027       mIoMmuProtocol->SetAttribute (
1028                         mIoMmuProtocol,
1029                         PciIoDevice->Handle,
1030                         *Mapping,
1031                         IoMmuAttribute
1032                         );
1033     }
1034   }
1035
1036   return Status;
1037 }
1038
1039 /**
1040   Completes the Map() operation and releases any corresponding resources.
1041
1042   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
1043   @param  Mapping               The mapping value returned from Map().
1044
1045   @retval EFI_SUCCESS           The range was unmapped.
1046   @retval EFI_DEVICE_ERROR      The data was not committed to the target system memory.
1047
1048 **/
1049 EFI_STATUS
1050 EFIAPI
1051 PciIoUnmap (
1052   IN  EFI_PCI_IO_PROTOCOL  *This,
1053   IN  VOID                 *Mapping
1054   )
1055 {
1056   EFI_STATUS     Status;
1057   PCI_IO_DEVICE  *PciIoDevice;
1058
1059   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1060
1061   if (mIoMmuProtocol != NULL) {
1062     mIoMmuProtocol->SetAttribute (
1063                       mIoMmuProtocol,
1064                       PciIoDevice->Handle,
1065                       Mapping,
1066                       0
1067                       );
1068   }
1069
1070   Status = PciIoDevice->PciRootBridgeIo->Unmap (
1071                                            PciIoDevice->PciRootBridgeIo,
1072                                            Mapping
1073                                            );
1074
1075   if (EFI_ERROR (Status)) {
1076     REPORT_STATUS_CODE_WITH_DEVICE_PATH (
1077       EFI_ERROR_CODE | EFI_ERROR_MINOR,
1078       EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,
1079       PciIoDevice->DevicePath
1080       );
1081   }
1082
1083   return Status;
1084 }
1085
1086 /**
1087   Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer
1088   or EfiPciOperationBusMasterCommonBuffer64 mapping.
1089
1090   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
1091   @param  Type                  This parameter is not used and must be ignored.
1092   @param  MemoryType            The type of memory to allocate, EfiBootServicesData or
1093                                 EfiRuntimeServicesData.
1094   @param  Pages                 The number of pages to allocate.
1095   @param  HostAddress           A pointer to store the base system memory address of the
1096                                 allocated range.
1097   @param  Attributes            The requested bit mask of attributes for the allocated range.
1098
1099   @retval EFI_SUCCESS           The requested memory pages were allocated.
1100   @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are
1101                                 MEMORY_WRITE_COMBINE, MEMORY_CACHED and DUAL_ADDRESS_CYCLE.
1102   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1103   @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.
1104
1105 **/
1106 EFI_STATUS
1107 EFIAPI
1108 PciIoAllocateBuffer (
1109   IN  EFI_PCI_IO_PROTOCOL  *This,
1110   IN  EFI_ALLOCATE_TYPE    Type,
1111   IN  EFI_MEMORY_TYPE      MemoryType,
1112   IN  UINTN                Pages,
1113   OUT VOID                 **HostAddress,
1114   IN  UINT64               Attributes
1115   )
1116 {
1117   EFI_STATUS     Status;
1118   PCI_IO_DEVICE  *PciIoDevice;
1119
1120   if ((Attributes &
1121        (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | EFI_PCI_ATTRIBUTE_MEMORY_CACHED))) != 0)
1122   {
1123     return EFI_UNSUPPORTED;
1124   }
1125
1126   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1127
1128   if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) != 0) {
1129     Attributes |= EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE;
1130   }
1131
1132   Status = PciIoDevice->PciRootBridgeIo->AllocateBuffer (
1133                                            PciIoDevice->PciRootBridgeIo,
1134                                            Type,
1135                                            MemoryType,
1136                                            Pages,
1137                                            HostAddress,
1138                                            Attributes
1139                                            );
1140
1141   if (EFI_ERROR (Status)) {
1142     REPORT_STATUS_CODE_WITH_DEVICE_PATH (
1143       EFI_ERROR_CODE | EFI_ERROR_MINOR,
1144       EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,
1145       PciIoDevice->DevicePath
1146       );
1147   }
1148
1149   return Status;
1150 }
1151
1152 /**
1153   Frees memory that was allocated with AllocateBuffer().
1154
1155   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
1156   @param  Pages                 The number of pages to free.
1157   @param  HostAddress           The base system memory address of the allocated range.
1158
1159   @retval EFI_SUCCESS           The requested memory pages were freed.
1160   @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
1161                                 was not allocated with AllocateBuffer().
1162
1163 **/
1164 EFI_STATUS
1165 EFIAPI
1166 PciIoFreeBuffer (
1167   IN  EFI_PCI_IO_PROTOCOL  *This,
1168   IN  UINTN                Pages,
1169   IN  VOID                 *HostAddress
1170   )
1171 {
1172   EFI_STATUS     Status;
1173   PCI_IO_DEVICE  *PciIoDevice;
1174
1175   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1176
1177   Status = PciIoDevice->PciRootBridgeIo->FreeBuffer (
1178                                            PciIoDevice->PciRootBridgeIo,
1179                                            Pages,
1180                                            HostAddress
1181                                            );
1182
1183   if (EFI_ERROR (Status)) {
1184     REPORT_STATUS_CODE_WITH_DEVICE_PATH (
1185       EFI_ERROR_CODE | EFI_ERROR_MINOR,
1186       EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,
1187       PciIoDevice->DevicePath
1188       );
1189   }
1190
1191   return Status;
1192 }
1193
1194 /**
1195   Flushes all PCI posted write transactions from a PCI host bridge to system memory.
1196
1197   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
1198
1199   @retval EFI_SUCCESS           The PCI posted write transactions were flushed from the PCI host
1200                                 bridge to system memory.
1201   @retval EFI_DEVICE_ERROR      The PCI posted write transactions were not flushed from the PCI
1202                                 host bridge due to a hardware error.
1203
1204 **/
1205 EFI_STATUS
1206 EFIAPI
1207 PciIoFlush (
1208   IN  EFI_PCI_IO_PROTOCOL  *This
1209   )
1210 {
1211   EFI_STATUS     Status;
1212   PCI_IO_DEVICE  *PciIoDevice;
1213
1214   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1215
1216   Status = PciIoDevice->PciRootBridgeIo->Flush (
1217                                            PciIoDevice->PciRootBridgeIo
1218                                            );
1219   if (EFI_ERROR (Status)) {
1220     REPORT_STATUS_CODE_WITH_DEVICE_PATH (
1221       EFI_ERROR_CODE | EFI_ERROR_MINOR,
1222       EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,
1223       PciIoDevice->DevicePath
1224       );
1225   }
1226
1227   return Status;
1228 }
1229
1230 /**
1231   Retrieves this PCI controller's current PCI bus number, device number, and function number.
1232
1233   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
1234   @param  SegmentNumber         The PCI controller's current PCI segment number.
1235   @param  BusNumber             The PCI controller's current PCI bus number.
1236   @param  DeviceNumber          The PCI controller's current PCI device number.
1237   @param  FunctionNumber        The PCI controller's current PCI function number.
1238
1239   @retval EFI_SUCCESS           The PCI controller location was returned.
1240   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1241
1242 **/
1243 EFI_STATUS
1244 EFIAPI
1245 PciIoGetLocation (
1246   IN  EFI_PCI_IO_PROTOCOL  *This,
1247   OUT UINTN                *Segment,
1248   OUT UINTN                *Bus,
1249   OUT UINTN                *Device,
1250   OUT UINTN                *Function
1251   )
1252 {
1253   PCI_IO_DEVICE  *PciIoDevice;
1254
1255   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1256
1257   if ((Segment == NULL) || (Bus == NULL) || (Device == NULL) || (Function == NULL)) {
1258     return EFI_INVALID_PARAMETER;
1259   }
1260
1261   *Segment  = PciIoDevice->PciRootBridgeIo->SegmentNumber;
1262   *Bus      = PciIoDevice->BusNumber;
1263   *Device   = PciIoDevice->DeviceNumber;
1264   *Function = PciIoDevice->FunctionNumber;
1265
1266   return EFI_SUCCESS;
1267 }
1268
1269 /**
1270   Check BAR type for PCI resource.
1271
1272   @param PciIoDevice   PCI device instance.
1273   @param BarIndex      The BAR index of the standard PCI Configuration header to use as the
1274                        base address for the memory or I/O operation to perform.
1275   @param BarType       Memory or I/O.
1276
1277   @retval TRUE         Pci device's bar type is same with input BarType.
1278   @retval TRUE         Pci device's bar type is not same with input BarType.
1279
1280 **/
1281 BOOLEAN
1282 CheckBarType (
1283   IN PCI_IO_DEVICE  *PciIoDevice,
1284   IN UINT8          BarIndex,
1285   IN PCI_BAR_TYPE   BarType
1286   )
1287 {
1288   switch (BarType) {
1289     case PciBarTypeMem:
1290
1291       if ((PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem32) &&
1292           (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem32) &&
1293           (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem64) &&
1294           (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem64))
1295       {
1296         return FALSE;
1297       }
1298
1299       return TRUE;
1300
1301     case PciBarTypeIo:
1302       if ((PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo32) &&
1303           (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo16))
1304       {
1305         return FALSE;
1306       }
1307
1308       return TRUE;
1309
1310     default:
1311       break;
1312   }
1313
1314   return FALSE;
1315 }
1316
1317 /**
1318   Set/Disable new attributes to a Root Bridge.
1319
1320   @param  PciIoDevice  Pci device instance.
1321   @param  Attributes   New attribute want to be set.
1322   @param  Operation    Set or Disable.
1323
1324   @retval  EFI_UNSUPPORTED  If root bridge does not support change attribute.
1325   @retval  EFI_SUCCESS      Successfully set new attributes.
1326
1327 **/
1328 EFI_STATUS
1329 ModifyRootBridgeAttributes (
1330   IN  PCI_IO_DEVICE                            *PciIoDevice,
1331   IN  UINT64                                   Attributes,
1332   IN  EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION  Operation
1333   )
1334 {
1335   UINT64      PciRootBridgeSupports;
1336   UINT64      PciRootBridgeAttributes;
1337   UINT64      NewPciRootBridgeAttributes;
1338   EFI_STATUS  Status;
1339
1340   //
1341   // Get the current attributes of this PCI device's PCI Root Bridge
1342   //
1343   Status = PciIoDevice->PciRootBridgeIo->GetAttributes (
1344                                            PciIoDevice->PciRootBridgeIo,
1345                                            &PciRootBridgeSupports,
1346                                            &PciRootBridgeAttributes
1347                                            );
1348   if (EFI_ERROR (Status)) {
1349     return EFI_UNSUPPORTED;
1350   }
1351
1352   //
1353   // Mask off attributes not supported by PCI root bridge.
1354   //
1355   Attributes &= ~(UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |
1356                           EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |
1357                           EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
1358
1359   //
1360   // Record the new attribute of the Root Bridge
1361   //
1362   if (Operation == EfiPciIoAttributeOperationEnable) {
1363     NewPciRootBridgeAttributes = PciRootBridgeAttributes | Attributes;
1364   } else {
1365     NewPciRootBridgeAttributes = PciRootBridgeAttributes & (~Attributes);
1366   }
1367
1368   //
1369   // Call the PCI Root Bridge to attempt to modify the attributes
1370   //
1371   if ((NewPciRootBridgeAttributes ^ PciRootBridgeAttributes) != 0) {
1372     Status = PciIoDevice->PciRootBridgeIo->SetAttributes (
1373                                              PciIoDevice->PciRootBridgeIo,
1374                                              NewPciRootBridgeAttributes,
1375                                              NULL,
1376                                              NULL
1377                                              );
1378     if (EFI_ERROR (Status)) {
1379       //
1380       // The PCI Root Bridge could not modify the attributes, so return the error.
1381       //
1382       return EFI_UNSUPPORTED;
1383     }
1384   }
1385
1386   //
1387   // Also update the attributes for this Root Bridge structure
1388   //
1389   PciIoDevice->Attributes = NewPciRootBridgeAttributes;
1390
1391   return EFI_SUCCESS;
1392 }
1393
1394 /**
1395   Check whether this device can be enable/disable to snoop.
1396
1397   @param PciIoDevice  Pci device instance.
1398   @param Operation    Enable/Disable.
1399
1400   @retval EFI_UNSUPPORTED  Pci device is not GFX device or not support snoop.
1401   @retval EFI_SUCCESS      Snoop can be supported.
1402
1403 **/
1404 EFI_STATUS
1405 SupportPaletteSnoopAttributes (
1406   IN PCI_IO_DEVICE                            *PciIoDevice,
1407   IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION  Operation
1408   )
1409 {
1410   PCI_IO_DEVICE  *Temp;
1411   UINT16         VGACommand;
1412
1413   //
1414   // Snoop attribute can be only modified by GFX
1415   //
1416   if (!IS_PCI_GFX (&PciIoDevice->Pci)) {
1417     return EFI_UNSUPPORTED;
1418   }
1419
1420   //
1421   // Get the boot VGA on the same Host Bridge
1422   //
1423   Temp = LocateVgaDeviceOnHostBridge (PciIoDevice->PciRootBridgeIo->ParentHandle);
1424
1425   if (Temp == NULL) {
1426     //
1427     // If there is no VGA device on the segment, set
1428     // this graphics card to decode the palette range
1429     //
1430     return EFI_SUCCESS;
1431   }
1432
1433   //
1434   // Check these two agents are on the same path
1435   //
1436   if (!PciDevicesOnTheSamePath (Temp, PciIoDevice)) {
1437     //
1438     // they are not on the same path, so snoop can be enabled or disabled
1439     //
1440     return EFI_SUCCESS;
1441   }
1442
1443   //
1444   // Check if they are on the same bus
1445   //
1446   if (Temp->Parent == PciIoDevice->Parent) {
1447     PCI_READ_COMMAND_REGISTER (Temp, &VGACommand);
1448
1449     //
1450     // If they are on the same bus, either one can
1451     // be set to snoop, the other set to decode
1452     //
1453     if ((VGACommand & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {
1454       //
1455       // VGA has set to snoop, so GFX can be only set to disable snoop
1456       //
1457       if (Operation == EfiPciIoAttributeOperationEnable) {
1458         return EFI_UNSUPPORTED;
1459       }
1460     } else {
1461       //
1462       // VGA has disabled to snoop, so GFX can be only enabled
1463       //
1464       if (Operation == EfiPciIoAttributeOperationDisable) {
1465         return EFI_UNSUPPORTED;
1466       }
1467     }
1468
1469     return EFI_SUCCESS;
1470   }
1471
1472   //
1473   // If they are on  the same path but on the different bus
1474   // The first agent is set to snoop, the second one set to
1475   // decode
1476   //
1477
1478   if (Temp->BusNumber < PciIoDevice->BusNumber) {
1479     //
1480     // GFX should be set to decode
1481     //
1482     if (Operation == EfiPciIoAttributeOperationDisable) {
1483       PCI_ENABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);
1484       Temp->Attributes |= EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;
1485     } else {
1486       return EFI_UNSUPPORTED;
1487     }
1488   } else {
1489     //
1490     // GFX should be set to snoop
1491     //
1492     if (Operation == EfiPciIoAttributeOperationEnable) {
1493       PCI_DISABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);
1494       Temp->Attributes &= (~(UINT64)EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);
1495     } else {
1496       return EFI_UNSUPPORTED;
1497     }
1498   }
1499
1500   return EFI_SUCCESS;
1501 }
1502
1503 /**
1504   Performs an operation on the attributes that this PCI controller supports. The operations include
1505   getting the set of supported attributes, retrieving the current attributes, setting the current
1506   attributes, enabling attributes, and disabling attributes.
1507
1508   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
1509   @param  Operation             The operation to perform on the attributes for this PCI controller.
1510   @param  Attributes            The mask of attributes that are used for Set, Enable, and Disable
1511                                 operations.
1512   @param  Result                A pointer to the result mask of attributes that are returned for the Get
1513                                 and Supported operations.
1514
1515   @retval EFI_SUCCESS           The operation on the PCI controller's attributes was completed.
1516   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1517   @retval EFI_UNSUPPORTED       one or more of the bits set in
1518                                 Attributes are not supported by this PCI controller or one of
1519                                 its parent bridges when Operation is Set, Enable or Disable.
1520
1521 **/
1522 EFI_STATUS
1523 EFIAPI
1524 PciIoAttributes (
1525   IN EFI_PCI_IO_PROTOCOL                       *This,
1526   IN  EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION  Operation,
1527   IN  UINT64                                   Attributes,
1528   OUT UINT64                                   *Result OPTIONAL
1529   )
1530 {
1531   EFI_STATUS  Status;
1532
1533   PCI_IO_DEVICE  *PciIoDevice;
1534   PCI_IO_DEVICE  *UpStreamBridge;
1535   PCI_IO_DEVICE  *Temp;
1536
1537   UINT64  Supports;
1538   UINT64  UpStreamAttributes;
1539   UINT16  BridgeControl;
1540   UINT16  Command;
1541
1542   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1543
1544   switch (Operation) {
1545     case EfiPciIoAttributeOperationGet:
1546       if (Result == NULL) {
1547         return EFI_INVALID_PARAMETER;
1548       }
1549
1550       *Result = PciIoDevice->Attributes;
1551       return EFI_SUCCESS;
1552
1553     case EfiPciIoAttributeOperationSupported:
1554       if (Result == NULL) {
1555         return EFI_INVALID_PARAMETER;
1556       }
1557
1558       *Result = PciIoDevice->Supports;
1559       return EFI_SUCCESS;
1560
1561     case EfiPciIoAttributeOperationSet:
1562       Status = PciIoDevice->PciIo.Attributes (
1563                                     &(PciIoDevice->PciIo),
1564                                     EfiPciIoAttributeOperationEnable,
1565                                     Attributes,
1566                                     NULL
1567                                     );
1568       if (EFI_ERROR (Status)) {
1569         return EFI_UNSUPPORTED;
1570       }
1571
1572       Status = PciIoDevice->PciIo.Attributes (
1573                                     &(PciIoDevice->PciIo),
1574                                     EfiPciIoAttributeOperationDisable,
1575                                     (~Attributes) & (PciIoDevice->Supports),
1576                                     NULL
1577                                     );
1578       if (EFI_ERROR (Status)) {
1579         return EFI_UNSUPPORTED;
1580       }
1581
1582       return EFI_SUCCESS;
1583
1584     case EfiPciIoAttributeOperationEnable:
1585     case EfiPciIoAttributeOperationDisable:
1586       break;
1587
1588     default:
1589       return EFI_INVALID_PARAMETER;
1590   }
1591
1592   //
1593   // Just a trick for ENABLE attribute
1594   // EFI_PCI_DEVICE_ENABLE is not defined in UEFI spec, which is the internal usage.
1595   // So, this logic doesn't conform to UEFI spec, which should be removed.
1596   // But this trick logic is still kept for some binary drivers that depend on it.
1597   //
1598   if ((Attributes & EFI_PCI_DEVICE_ENABLE) == EFI_PCI_DEVICE_ENABLE) {
1599     Attributes &= (PciIoDevice->Supports);
1600
1601     //
1602     // Raise the EFI_P_PC_ENABLE Status code
1603     //
1604     REPORT_STATUS_CODE_WITH_DEVICE_PATH (
1605       EFI_PROGRESS_CODE,
1606       EFI_IO_BUS_PCI | EFI_P_PC_ENABLE,
1607       PciIoDevice->DevicePath
1608       );
1609   }
1610
1611   //
1612   // Check VGA and VGA16, they can not be set at the same time
1613   //
1614   if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO)) != 0) {
1615     if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {
1616       return EFI_UNSUPPORTED;
1617     }
1618   }
1619
1620   //
1621   // If no attributes can be supported, then return.
1622   // Otherwise, set the attributes that it can support.
1623   //
1624   Supports = (PciIoDevice->Supports) & Attributes;
1625   if (Supports != Attributes) {
1626     return EFI_UNSUPPORTED;
1627   }
1628
1629   //
1630   // For Root Bridge, just call RootBridgeIo to set attributes;
1631   //
1632   if (PciIoDevice->Parent == NULL) {
1633     Status = ModifyRootBridgeAttributes (PciIoDevice, Attributes, Operation);
1634     return Status;
1635   }
1636
1637   Command       = 0;
1638   BridgeControl = 0;
1639
1640   //
1641   // For PPB & P2C, set relevant attribute bits
1642   //
1643   if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
1644     if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {
1645       BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA;
1646     }
1647
1648     if ((Attributes & EFI_PCI_IO_ATTRIBUTE_ISA_IO) != 0) {
1649       BridgeControl |= EFI_PCI_BRIDGE_CONTROL_ISA;
1650     }
1651
1652     if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {
1653       Command |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;
1654     }
1655
1656     if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {
1657       BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA_16;
1658     }
1659   } else {
1660     //
1661     // Do with the attributes on VGA
1662     // Only for VGA's legacy resource, we just can enable once.
1663     //
1664     if ((Attributes &
1665          (EFI_PCI_IO_ATTRIBUTE_VGA_IO    |
1666           EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 |
1667           EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY)) != 0)
1668     {
1669       //
1670       // Check if a VGA has been enabled before enabling a new one
1671       //
1672       if (Operation == EfiPciIoAttributeOperationEnable) {
1673         //
1674         // Check if there have been an active VGA device on the same Host Bridge
1675         //
1676         Temp = LocateVgaDeviceOnHostBridge (PciIoDevice->PciRootBridgeIo->ParentHandle);
1677         if ((Temp != NULL) && (Temp != PciIoDevice)) {
1678           //
1679           // An active VGA has been detected, so can not enable another
1680           //
1681           return EFI_UNSUPPORTED;
1682         }
1683       }
1684     }
1685
1686     //
1687     // Do with the attributes on GFX
1688     //
1689     if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {
1690       if (Operation == EfiPciIoAttributeOperationEnable) {
1691         //
1692         // Check if snoop can be enabled in current configuration
1693         //
1694         Status = SupportPaletteSnoopAttributes (PciIoDevice, Operation);
1695
1696         if (EFI_ERROR (Status)) {
1697           //
1698           // Enable operation is forbidden, so mask the bit in attributes
1699           // so as to keep consistent with the actual Status
1700           //
1701           // Attributes &= (~EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO);
1702           //
1703           //
1704           //
1705           return EFI_UNSUPPORTED;
1706         }
1707       }
1708
1709       //
1710       // It can be supported, so get ready to set the bit
1711       //
1712       Command |= EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;
1713     }
1714   }
1715
1716   if ((Attributes & EFI_PCI_IO_ATTRIBUTE_IO) != 0) {
1717     Command |= EFI_PCI_COMMAND_IO_SPACE;
1718   }
1719
1720   if ((Attributes & EFI_PCI_IO_ATTRIBUTE_MEMORY) != 0) {
1721     Command |= EFI_PCI_COMMAND_MEMORY_SPACE;
1722   }
1723
1724   if ((Attributes & EFI_PCI_IO_ATTRIBUTE_BUS_MASTER) != 0) {
1725     Command |= EFI_PCI_COMMAND_BUS_MASTER;
1726   }
1727
1728   //
1729   // The upstream bridge should be also set to relevant attribute
1730   // expect for IO, Mem and BusMaster
1731   //
1732   UpStreamAttributes = Attributes &
1733                        (~(EFI_PCI_IO_ATTRIBUTE_IO     |
1734                           EFI_PCI_IO_ATTRIBUTE_MEMORY |
1735                           EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
1736                           )
1737                        );
1738   UpStreamBridge = PciIoDevice->Parent;
1739
1740   if (Operation == EfiPciIoAttributeOperationEnable) {
1741     //
1742     // Enable relevant attributes to command register and bridge control register
1743     //
1744     Status = PCI_ENABLE_COMMAND_REGISTER (PciIoDevice, Command);
1745     if (BridgeControl != 0) {
1746       Status = PCI_ENABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);
1747     }
1748
1749     PciIoDevice->Attributes |= Attributes;
1750
1751     //
1752     // Enable attributes of the upstream bridge
1753     //
1754     Status = UpStreamBridge->PciIo.Attributes (
1755                                      &(UpStreamBridge->PciIo),
1756                                      EfiPciIoAttributeOperationEnable,
1757                                      UpStreamAttributes,
1758                                      NULL
1759                                      );
1760   } else {
1761     //
1762     // Disable relevant attributes to command register and bridge control register
1763     //
1764     Status = PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, Command);
1765     if (BridgeControl != 0) {
1766       Status = PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);
1767     }
1768
1769     PciIoDevice->Attributes &= (~Attributes);
1770     Status                   = EFI_SUCCESS;
1771   }
1772
1773   if (EFI_ERROR (Status)) {
1774     REPORT_STATUS_CODE_WITH_DEVICE_PATH (
1775       EFI_ERROR_CODE | EFI_ERROR_MINOR,
1776       EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR,
1777       PciIoDevice->DevicePath
1778       );
1779   }
1780
1781   return Status;
1782 }
1783
1784 /**
1785   Retrieve the AddrTranslationOffset from RootBridgeIo for the
1786   specified range.
1787
1788   @param RootBridgeIo    Root Bridge IO instance.
1789   @param AddrRangeMin    The base address of the MMIO.
1790   @param AddrLen         The length of the MMIO.
1791
1792   @retval The AddrTranslationOffset from RootBridgeIo for the
1793           specified range, or (UINT64) -1 if the range is not
1794           found in RootBridgeIo.
1795 **/
1796 UINT64
1797 GetMmioAddressTranslationOffset (
1798   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *RootBridgeIo,
1799   UINT64                           AddrRangeMin,
1800   UINT64                           AddrLen
1801   )
1802 {
1803   EFI_STATUS                         Status;
1804   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  *Configuration;
1805
1806   Status = RootBridgeIo->Configuration (
1807                            RootBridgeIo,
1808                            (VOID **)&Configuration
1809                            );
1810   if (EFI_ERROR (Status)) {
1811     return (UINT64)-1;
1812   }
1813
1814   // According to UEFI 2.7, EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL::Configuration()
1815   // returns host address instead of device address, while AddrTranslationOffset
1816   // is not zero, and device address = host address + AddrTranslationOffset, so
1817   // we convert host address to device address for range compare.
1818   while (Configuration->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
1819     if ((Configuration->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) &&
1820         (Configuration->AddrRangeMin + Configuration->AddrTranslationOffset <= AddrRangeMin) &&
1821         (Configuration->AddrRangeMin + Configuration->AddrLen + Configuration->AddrTranslationOffset >= AddrRangeMin + AddrLen)
1822         )
1823     {
1824       return Configuration->AddrTranslationOffset;
1825     }
1826
1827     Configuration++;
1828   }
1829
1830   //
1831   // The resource occupied by BAR should be in the range reported by RootBridge.
1832   //
1833   ASSERT (FALSE);
1834   return (UINT64)-1;
1835 }
1836
1837 /**
1838   Gets the attributes that this PCI controller supports setting on a BAR using
1839   SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.
1840
1841   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
1842   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
1843                                 base address for resource range. The legal range for this field is 0..5.
1844   @param  Supports              A pointer to the mask of attributes that this PCI controller supports
1845                                 setting for this BAR with SetBarAttributes().
1846   @param  Resources             A pointer to the resource descriptors that describe the current
1847                                 configuration of this BAR of the PCI controller.
1848
1849   @retval EFI_SUCCESS           If Supports is not NULL, then the attributes that the PCI
1850                                 controller supports are returned in Supports. If Resources
1851                                 is not NULL, then the resource descriptors that the PCI
1852                                 controller is currently using are returned in Resources.
1853   @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
1854   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
1855   @retval EFI_OUT_OF_RESOURCES  There are not enough resources available to allocate
1856                                 Resources.
1857
1858 **/
1859 EFI_STATUS
1860 EFIAPI
1861 PciIoGetBarAttributes (
1862   IN EFI_PCI_IO_PROTOCOL  *This,
1863   IN  UINT8               BarIndex,
1864   OUT UINT64              *Supports  OPTIONAL,
1865   OUT VOID                **Resources OPTIONAL
1866   )
1867 {
1868   PCI_IO_DEVICE                      *PciIoDevice;
1869   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  *Descriptor;
1870   EFI_ACPI_END_TAG_DESCRIPTOR        *End;
1871
1872   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1873
1874   if ((Supports == NULL) && (Resources == NULL)) {
1875     return EFI_INVALID_PARAMETER;
1876   }
1877
1878   if ((BarIndex >= PCI_MAX_BAR) || (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeUnknown)) {
1879     return EFI_UNSUPPORTED;
1880   }
1881
1882   //
1883   // This driver does not support modifications to the WRITE_COMBINE or
1884   // CACHED attributes for BAR ranges.
1885   //
1886   if (Supports != NULL) {
1887     *Supports = PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED & EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE;
1888   }
1889
1890   if (Resources != NULL) {
1891     Descriptor = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
1892     if (Descriptor == NULL) {
1893       return EFI_OUT_OF_RESOURCES;
1894     }
1895
1896     *Resources = Descriptor;
1897
1898     Descriptor->Desc         = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1899     Descriptor->Len          = (UINT16)(sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
1900     Descriptor->AddrRangeMin = PciIoDevice->PciBar[BarIndex].BaseAddress;
1901     Descriptor->AddrLen      = PciIoDevice->PciBar[BarIndex].Length;
1902     Descriptor->AddrRangeMax = PciIoDevice->PciBar[BarIndex].Alignment;
1903
1904     switch (PciIoDevice->PciBar[BarIndex].BarType) {
1905       case PciBarTypeIo16:
1906       case PciBarTypeIo32:
1907         //
1908         // Io
1909         //
1910         Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
1911         break;
1912
1913       case PciBarTypePMem32:
1914         //
1915         // prefetchable
1916         //
1917         Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
1918       //
1919       // Fall through
1920       //
1921       case PciBarTypeMem32:
1922         //
1923         // Mem
1924         //
1925         Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1926         //
1927         // 32 bit
1928         //
1929         Descriptor->AddrSpaceGranularity = 32;
1930         break;
1931
1932       case PciBarTypePMem64:
1933         //
1934         // prefetchable
1935         //
1936         Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
1937       //
1938       // Fall through
1939       //
1940       case PciBarTypeMem64:
1941         //
1942         // Mem
1943         //
1944         Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1945         //
1946         // 64 bit
1947         //
1948         Descriptor->AddrSpaceGranularity = 64;
1949         break;
1950
1951       default:
1952         break;
1953     }
1954
1955     //
1956     // put the checksum
1957     //
1958     End           = (EFI_ACPI_END_TAG_DESCRIPTOR *)(Descriptor + 1);
1959     End->Desc     = ACPI_END_TAG_DESCRIPTOR;
1960     End->Checksum = 0;
1961
1962     //
1963     // Get the Address Translation Offset
1964     //
1965     if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
1966       Descriptor->AddrTranslationOffset = GetMmioAddressTranslationOffset (
1967                                             PciIoDevice->PciRootBridgeIo,
1968                                             Descriptor->AddrRangeMin,
1969                                             Descriptor->AddrLen
1970                                             );
1971       if (Descriptor->AddrTranslationOffset == (UINT64)-1) {
1972         FreePool (Descriptor);
1973         return EFI_UNSUPPORTED;
1974       }
1975     }
1976
1977     // According to UEFI spec 2.7, we need return host address for
1978     // PciIo->GetBarAttributes, and host address = device address - translation.
1979     Descriptor->AddrRangeMin -= Descriptor->AddrTranslationOffset;
1980   }
1981
1982   return EFI_SUCCESS;
1983 }
1984
1985 /**
1986   Sets the attributes for a range of a BAR on a PCI controller.
1987
1988   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
1989   @param  Attributes            The mask of attributes to set for the resource range specified by
1990                                 BarIndex, Offset, and Length.
1991   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
1992                                 base address for resource range. The legal range for this field is 0..5.
1993   @param  Offset                A pointer to the BAR relative base address of the resource range to be
1994                                 modified by the attributes specified by Attributes.
1995   @param  Length                A pointer to the length of the resource range to be modified by the
1996                                 attributes specified by Attributes.
1997
1998   @retval EFI_SUCCESS           The set of attributes specified by Attributes for the resource
1999                                 range specified by BarIndex, Offset, and Length were
2000                                 set on the PCI controller, and the actual resource range is returned
2001                                 in Offset and Length.
2002   @retval EFI_INVALID_PARAMETER Offset or Length is NULL.
2003   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
2004   @retval EFI_OUT_OF_RESOURCES  There are not enough resources to set the attributes on the
2005                                 resource range specified by BarIndex, Offset, and
2006                                 Length.
2007
2008 **/
2009 EFI_STATUS
2010 EFIAPI
2011 PciIoSetBarAttributes (
2012   IN EFI_PCI_IO_PROTOCOL  *This,
2013   IN     UINT64           Attributes,
2014   IN     UINT8            BarIndex,
2015   IN OUT UINT64           *Offset,
2016   IN OUT UINT64           *Length
2017   )
2018 {
2019   EFI_STATUS     Status;
2020   PCI_IO_DEVICE  *PciIoDevice;
2021   UINT64         NonRelativeOffset;
2022   UINT64         Supports;
2023
2024   PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
2025
2026   //
2027   // Make sure Offset and Length are not NULL
2028   //
2029   if ((Offset == NULL) || (Length == NULL)) {
2030     return EFI_INVALID_PARAMETER;
2031   }
2032
2033   if (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeUnknown) {
2034     return EFI_UNSUPPORTED;
2035   }
2036
2037   //
2038   // This driver does not support setting the WRITE_COMBINE or the CACHED attributes.
2039   // If Attributes is not 0, then return EFI_UNSUPPORTED.
2040   //
2041   Supports = PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED & EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE;
2042
2043   if (Attributes != (Attributes & Supports)) {
2044     return EFI_UNSUPPORTED;
2045   }
2046
2047   //
2048   // Attributes must be supported.  Make sure the BAR range described by BarIndex, Offset, and
2049   // Length are valid for this PCI device.
2050   //
2051   NonRelativeOffset = *Offset;
2052   Status            = PciIoVerifyBarAccess (
2053                         PciIoDevice,
2054                         BarIndex,
2055                         PciBarTypeMem,
2056                         EfiPciIoWidthUint8,
2057                         (UINT32)*Length,
2058                         &NonRelativeOffset
2059                         );
2060   if (EFI_ERROR (Status)) {
2061     return EFI_UNSUPPORTED;
2062   }
2063
2064   return EFI_SUCCESS;
2065 }
2066
2067 /**
2068   Test whether two Pci devices has same parent bridge.
2069
2070   @param PciDevice1  The first pci device for testing.
2071   @param PciDevice2  The second pci device for testing.
2072
2073   @retval TRUE       Two Pci device has the same parent bridge.
2074   @retval FALSE      Two Pci device has not the same parent bridge.
2075
2076 **/
2077 BOOLEAN
2078 PciDevicesOnTheSamePath (
2079   IN PCI_IO_DEVICE  *PciDevice1,
2080   IN PCI_IO_DEVICE  *PciDevice2
2081   )
2082 {
2083   BOOLEAN  Existed1;
2084   BOOLEAN  Existed2;
2085
2086   if (PciDevice1->Parent == PciDevice2->Parent) {
2087     return TRUE;
2088   }
2089
2090   Existed1 = PciDeviceExisted (PciDevice1->Parent, PciDevice2);
2091   Existed2 = PciDeviceExisted (PciDevice2->Parent, PciDevice1);
2092
2093   return (BOOLEAN)(Existed1 || Existed2);
2094 }