The PCI host bridge can signal failures in its initialization to
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciLib.c
1 /** @file
2 Internal library implementation for PCI Bus module.
3
4 Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include "PciBus.h"
16
17 GLOBAL_REMOVE_IF_UNREFERENCED
18 CHAR16 *mBarTypeStr[] = {
19 L"Unknow",
20 L" Io16",
21 L" Io32",
22 L" Mem32",
23 L"PMem32",
24 L" Mem64",
25 L"PMem64",
26 L" Io",
27 L" Mem",
28 L"Unknow"
29 };
30
31 /**
32 Retrieve the PCI Card device BAR information via PciIo interface.
33
34 @param PciIoDevice PCI Card device instance.
35
36 **/
37 VOID
38 GetBackPcCardBar (
39 IN PCI_IO_DEVICE *PciIoDevice
40 )
41 {
42 UINT32 Address;
43
44 if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
45 return;
46 }
47
48 //
49 // Read PciBar information from the bar register
50 //
51 if (!gFullEnumeration) {
52 Address = 0;
53 PciIoDevice->PciIo.Pci.Read (
54 &(PciIoDevice->PciIo),
55 EfiPciIoWidthUint32,
56 PCI_CARD_MEMORY_BASE_0,
57 1,
58 &Address
59 );
60
61 (PciIoDevice->PciBar)[P2C_MEM_1].BaseAddress = (UINT64) (Address);
62 (PciIoDevice->PciBar)[P2C_MEM_1].Length = 0x2000000;
63 (PciIoDevice->PciBar)[P2C_MEM_1].BarType = PciBarTypeMem32;
64
65 Address = 0;
66 PciIoDevice->PciIo.Pci.Read (
67 &(PciIoDevice->PciIo),
68 EfiPciIoWidthUint32,
69 PCI_CARD_MEMORY_BASE_1,
70 1,
71 &Address
72 );
73 (PciIoDevice->PciBar)[P2C_MEM_2].BaseAddress = (UINT64) (Address);
74 (PciIoDevice->PciBar)[P2C_MEM_2].Length = 0x2000000;
75 (PciIoDevice->PciBar)[P2C_MEM_2].BarType = PciBarTypePMem32;
76
77 Address = 0;
78 PciIoDevice->PciIo.Pci.Read (
79 &(PciIoDevice->PciIo),
80 EfiPciIoWidthUint32,
81 PCI_CARD_IO_BASE_0_LOWER,
82 1,
83 &Address
84 );
85 (PciIoDevice->PciBar)[P2C_IO_1].BaseAddress = (UINT64) (Address);
86 (PciIoDevice->PciBar)[P2C_IO_1].Length = 0x100;
87 (PciIoDevice->PciBar)[P2C_IO_1].BarType = PciBarTypeIo16;
88
89 Address = 0;
90 PciIoDevice->PciIo.Pci.Read (
91 &(PciIoDevice->PciIo),
92 EfiPciIoWidthUint32,
93 PCI_CARD_IO_BASE_1_LOWER,
94 1,
95 &Address
96 );
97 (PciIoDevice->PciBar)[P2C_IO_2].BaseAddress = (UINT64) (Address);
98 (PciIoDevice->PciBar)[P2C_IO_2].Length = 0x100;
99 (PciIoDevice->PciBar)[P2C_IO_2].BarType = PciBarTypeIo16;
100
101 }
102
103 if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
104 GetResourcePaddingForHpb (PciIoDevice);
105 }
106 }
107
108 /**
109 Remove rejected pci device from specific root bridge
110 handle.
111
112 @param RootBridgeHandle Specific parent root bridge handle.
113 @param Bridge Bridge device instance.
114
115 **/
116 VOID
117 RemoveRejectedPciDevices (
118 IN EFI_HANDLE RootBridgeHandle,
119 IN PCI_IO_DEVICE *Bridge
120 )
121 {
122 PCI_IO_DEVICE *Temp;
123 LIST_ENTRY *CurrentLink;
124 LIST_ENTRY *LastLink;
125
126 if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
127 return;
128 }
129
130 CurrentLink = Bridge->ChildList.ForwardLink;
131
132 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
133
134 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
135
136 if (IS_PCI_BRIDGE (&Temp->Pci)) {
137 //
138 // Remove rejected devices recusively
139 //
140 RemoveRejectedPciDevices (RootBridgeHandle, Temp);
141 } else {
142 //
143 // Skip rejection for all PPBs, while detect rejection for others
144 //
145 if (IsPciDeviceRejected (Temp)) {
146
147 //
148 // For P2C, remove all devices on it
149 //
150 if (!IsListEmpty (&Temp->ChildList)) {
151 RemoveAllPciDeviceOnBridge (RootBridgeHandle, Temp);
152 }
153
154 //
155 // Finally remove itself
156 //
157 LastLink = CurrentLink->BackLink;
158 RemoveEntryList (CurrentLink);
159 FreePciDevice (Temp);
160
161 CurrentLink = LastLink;
162 }
163 }
164
165 CurrentLink = CurrentLink->ForwardLink;
166 }
167 }
168
169 /**
170 Dump the resourc map of the bridge device.
171
172 @param[in] BridgeResource Resource descriptor of the bridge device.
173 **/
174 VOID
175 DumpBridgeResource (
176 IN PCI_RESOURCE_NODE *BridgeResource
177 )
178 {
179 LIST_ENTRY *Link;
180 PCI_RESOURCE_NODE *Resource;
181 PCI_BAR *Bar;
182
183 if ((BridgeResource != NULL) && (BridgeResource->Length != 0)) {
184 DEBUG ((
185 EFI_D_INFO, "Type = %s; Base = 0x%lx;\tLength = 0x%lx;\tAlignment = 0x%lx\n",
186 mBarTypeStr[MIN (BridgeResource->ResType, PciBarTypeMaxType)],
187 BridgeResource->PciDev->PciBar[BridgeResource->Bar].BaseAddress,
188 BridgeResource->Length, BridgeResource->Alignment
189 ));
190 for ( Link = BridgeResource->ChildList.ForwardLink
191 ; Link != &BridgeResource->ChildList
192 ; Link = Link->ForwardLink
193 ) {
194 Resource = RESOURCE_NODE_FROM_LINK (Link);
195 if (Resource->ResourceUsage == PciResUsageTypical) {
196 Bar = Resource->Virtual ? Resource->PciDev->VfPciBar : Resource->PciDev->PciBar;
197 DEBUG ((
198 EFI_D_INFO, " Base = 0x%lx;\tLength = 0x%lx;\tAlignment = 0x%lx;\tOwner = %s ",
199 Bar[Resource->Bar].BaseAddress, Resource->Length, Resource->Alignment,
200 IS_PCI_BRIDGE (&Resource->PciDev->Pci) ? L"PPB" :
201 IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci) ? L"P2C" :
202 L"PCI"
203 ));
204
205 if ((!IS_PCI_BRIDGE (&Resource->PciDev->Pci) && !IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci)) ||
206 (IS_PCI_BRIDGE (&Resource->PciDev->Pci) && (Resource->Bar < PPB_IO_RANGE)) ||
207 (IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci) && (Resource->Bar < P2C_MEM_1))
208 ) {
209 //
210 // The resource requirement comes from the device itself.
211 //
212 DEBUG ((
213 EFI_D_INFO, " [%02x|%02x|%02x:%02x]\n",
214 Resource->PciDev->BusNumber, Resource->PciDev->DeviceNumber,
215 Resource->PciDev->FunctionNumber, Bar[Resource->Bar].Offset
216 ));
217 } else {
218 //
219 // The resource requirement comes from the subordinate devices.
220 //
221 DEBUG ((
222 EFI_D_INFO, " [%02x|%02x|%02x:**]\n",
223 Resource->PciDev->BusNumber, Resource->PciDev->DeviceNumber,
224 Resource->PciDev->FunctionNumber
225 ));
226 }
227 } else {
228 DEBUG ((EFI_D_INFO, " Padding:Length = 0x%lx;\tAlignment = 0x%lx\n", Resource->Length, Resource->Alignment));
229 }
230 }
231 }
232 }
233
234 /**
235 Find the corresponding resource node for the Device in child list of BridgeResource.
236
237 @param[in] Device Pointer to PCI_IO_DEVICE.
238 @param[in] BridgeResource Pointer to PCI_RESOURCE_NODE.
239
240 @return !NULL The corresponding resource node for the Device.
241 @return NULL No corresponding resource node for the Device.
242 **/
243 PCI_RESOURCE_NODE *
244 FindResourceNode (
245 IN PCI_IO_DEVICE *Device,
246 IN PCI_RESOURCE_NODE *BridgeResource
247 )
248 {
249 LIST_ENTRY *Link;
250 PCI_RESOURCE_NODE *Resource;
251
252 for ( Link = BridgeResource->ChildList.ForwardLink
253 ; Link != &BridgeResource->ChildList
254 ; Link = Link->ForwardLink
255 ) {
256 Resource = RESOURCE_NODE_FROM_LINK (Link);
257 if (Resource->PciDev == Device) {
258 return Resource;
259 }
260 }
261
262 return NULL;
263 }
264
265 /**
266 Dump the resource map of all the devices under Bridge.
267
268 @param[in] Bridge Bridge device instance.
269 @param[in] IoNode IO resource descriptor for the bridge device.
270 @param[in] Mem32Node Mem32 resource descriptor for the bridge device.
271 @param[in] PMem32Node PMem32 resource descriptor for the bridge device.
272 @param[in] Mem64Node Mem64 resource descriptor for the bridge device.
273 @param[in] PMem64Node PMem64 resource descriptor for the bridge device.
274 **/
275 VOID
276 DumpResourceMap (
277 IN PCI_IO_DEVICE *Bridge,
278 IN PCI_RESOURCE_NODE *IoNode,
279 IN PCI_RESOURCE_NODE *Mem32Node,
280 IN PCI_RESOURCE_NODE *PMem32Node,
281 IN PCI_RESOURCE_NODE *Mem64Node,
282 IN PCI_RESOURCE_NODE *PMem64Node
283 )
284 {
285 EFI_STATUS Status;
286 LIST_ENTRY *Link;
287 PCI_IO_DEVICE *Device;
288 PCI_RESOURCE_NODE *ChildIoNode;
289 PCI_RESOURCE_NODE *ChildMem32Node;
290 PCI_RESOURCE_NODE *ChildPMem32Node;
291 PCI_RESOURCE_NODE *ChildMem64Node;
292 PCI_RESOURCE_NODE *ChildPMem64Node;
293 EFI_DEVICE_PATH_TO_TEXT_PROTOCOL *ToText;
294 CHAR16 *Str;
295
296 DEBUG ((EFI_D_INFO, "PciBus: Resource Map for "));
297
298 Status = gBS->OpenProtocol (
299 Bridge->Handle,
300 &gEfiPciRootBridgeIoProtocolGuid,
301 NULL,
302 NULL,
303 NULL,
304 EFI_OPEN_PROTOCOL_TEST_PROTOCOL
305 );
306 if (EFI_ERROR (Status)) {
307 DEBUG ((
308 EFI_D_INFO, "Bridge [%02x|%02x|%02x]\n",
309 Bridge->BusNumber, Bridge->DeviceNumber, Bridge->FunctionNumber
310 ));
311 } else {
312 Status = gBS->LocateProtocol (
313 &gEfiDevicePathToTextProtocolGuid,
314 NULL,
315 (VOID **) &ToText
316 );
317 Str = NULL;
318 if (!EFI_ERROR (Status)) {
319 Str = ToText->ConvertDevicePathToText (
320 DevicePathFromHandle (Bridge->Handle),
321 FALSE,
322 FALSE
323 );
324 }
325 DEBUG ((EFI_D_INFO, "Root Bridge %s\n", Str != NULL ? Str : L""));
326 if (Str != NULL) {
327 FreePool (Str);
328 }
329 }
330
331 DumpBridgeResource (IoNode);
332 DumpBridgeResource (Mem32Node);
333 DumpBridgeResource (PMem32Node);
334 DumpBridgeResource (Mem64Node);
335 DumpBridgeResource (PMem64Node);
336 DEBUG ((EFI_D_INFO, "\n"));
337
338 for ( Link = Bridge->ChildList.ForwardLink
339 ; Link != &Bridge->ChildList
340 ; Link = Link->ForwardLink
341 ) {
342 Device = PCI_IO_DEVICE_FROM_LINK (Link);
343 if (IS_PCI_BRIDGE (&Device->Pci)) {
344
345 ChildIoNode = (IoNode == NULL ? NULL : FindResourceNode (Device, IoNode));
346 ChildMem32Node = (Mem32Node == NULL ? NULL : FindResourceNode (Device, Mem32Node));
347 ChildPMem32Node = (PMem32Node == NULL ? NULL : FindResourceNode (Device, PMem32Node));
348 ChildMem64Node = (Mem64Node == NULL ? NULL : FindResourceNode (Device, Mem64Node));
349 ChildPMem64Node = (PMem64Node == NULL ? NULL : FindResourceNode (Device, PMem64Node));
350
351 DumpResourceMap (
352 Device,
353 ChildIoNode,
354 ChildMem32Node,
355 ChildPMem32Node,
356 ChildMem64Node,
357 ChildPMem64Node
358 );
359 }
360 }
361 }
362
363 /**
364 Submits the I/O and memory resource requirements for the specified PCI Host Bridge.
365
366 @param PciResAlloc Point to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
367
368 @retval EFI_SUCCESS Successfully finished resource allocation.
369 @retval EFI_NOT_FOUND Cannot get root bridge instance.
370 @retval EFI_OUT_OF_RESOURCES Platform failed to program the resources if no hot plug supported.
371 @retval other Some error occurred when allocating resources for the PCI Host Bridge.
372
373 @note Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.
374
375 **/
376 EFI_STATUS
377 PciHostBridgeResourceAllocator (
378 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
379 )
380 {
381 PCI_IO_DEVICE *RootBridgeDev;
382 EFI_HANDLE RootBridgeHandle;
383 VOID *AcpiConfig;
384 EFI_STATUS Status;
385 UINT64 IoBase;
386 UINT64 Mem32Base;
387 UINT64 PMem32Base;
388 UINT64 Mem64Base;
389 UINT64 PMem64Base;
390 UINT64 IoResStatus;
391 UINT64 Mem32ResStatus;
392 UINT64 PMem32ResStatus;
393 UINT64 Mem64ResStatus;
394 UINT64 PMem64ResStatus;
395 UINT64 MaxOptionRomSize;
396 PCI_RESOURCE_NODE *IoBridge;
397 PCI_RESOURCE_NODE *Mem32Bridge;
398 PCI_RESOURCE_NODE *PMem32Bridge;
399 PCI_RESOURCE_NODE *Mem64Bridge;
400 PCI_RESOURCE_NODE *PMem64Bridge;
401 PCI_RESOURCE_NODE IoPool;
402 PCI_RESOURCE_NODE Mem32Pool;
403 PCI_RESOURCE_NODE PMem32Pool;
404 PCI_RESOURCE_NODE Mem64Pool;
405 PCI_RESOURCE_NODE PMem64Pool;
406 BOOLEAN ReAllocate;
407 EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD HandleExtendedData;
408 EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData;
409
410 //
411 // Reallocate flag
412 //
413 ReAllocate = FALSE;
414
415 //
416 // It may try several times if the resource allocation fails
417 //
418 while (TRUE) {
419 //
420 // Initialize resource pool
421 //
422 InitializeResourcePool (&IoPool, PciBarTypeIo16);
423 InitializeResourcePool (&Mem32Pool, PciBarTypeMem32);
424 InitializeResourcePool (&PMem32Pool, PciBarTypePMem32);
425 InitializeResourcePool (&Mem64Pool, PciBarTypeMem64);
426 InitializeResourcePool (&PMem64Pool, PciBarTypePMem64);
427
428 RootBridgeDev = NULL;
429 RootBridgeHandle = 0;
430
431 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
432 //
433 // Get Root Bridge Device by handle
434 //
435 RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);
436
437 if (RootBridgeDev == NULL) {
438 return EFI_NOT_FOUND;
439 }
440
441 //
442 // Create the entire system resource map from the information collected by
443 // enumerator. Several resource tree was created
444 //
445
446 //
447 // If non-stardard PCI Bridge I/O window alignment is supported,
448 // set I/O aligment to minimum possible alignment for root bridge.
449 //
450 IoBridge = CreateResourceNode (
451 RootBridgeDev,
452 0,
453 FeaturePcdGet (PcdPciBridgeIoAlignmentProbe) ? 0x1FF: 0xFFF,
454 RB_IO_RANGE,
455 PciBarTypeIo16,
456 PciResUsageTypical
457 );
458
459 Mem32Bridge = CreateResourceNode (
460 RootBridgeDev,
461 0,
462 0xFFFFF,
463 RB_MEM32_RANGE,
464 PciBarTypeMem32,
465 PciResUsageTypical
466 );
467
468 PMem32Bridge = CreateResourceNode (
469 RootBridgeDev,
470 0,
471 0xFFFFF,
472 RB_PMEM32_RANGE,
473 PciBarTypePMem32,
474 PciResUsageTypical
475 );
476
477 Mem64Bridge = CreateResourceNode (
478 RootBridgeDev,
479 0,
480 0xFFFFF,
481 RB_MEM64_RANGE,
482 PciBarTypeMem64,
483 PciResUsageTypical
484 );
485
486 PMem64Bridge = CreateResourceNode (
487 RootBridgeDev,
488 0,
489 0xFFFFF,
490 RB_PMEM64_RANGE,
491 PciBarTypePMem64,
492 PciResUsageTypical
493 );
494
495 //
496 // Create resourcemap by going through all the devices subject to this root bridge
497 //
498 CreateResourceMap (
499 RootBridgeDev,
500 IoBridge,
501 Mem32Bridge,
502 PMem32Bridge,
503 Mem64Bridge,
504 PMem64Bridge
505 );
506
507 //
508 // Get the max ROM size that the root bridge can process
509 //
510 RootBridgeDev->RomSize = Mem32Bridge->Length;
511
512 //
513 // Skip to enlarge the resource request during realloction
514 //
515 if (!ReAllocate) {
516 //
517 // Get Max Option Rom size for current root bridge
518 //
519 MaxOptionRomSize = GetMaxOptionRomSize (RootBridgeDev);
520
521 //
522 // Enlarger the mem32 resource to accomdate the option rom
523 // if the mem32 resource is not enough to hold the rom
524 //
525 if (MaxOptionRomSize > Mem32Bridge->Length) {
526
527 Mem32Bridge->Length = MaxOptionRomSize;
528 RootBridgeDev->RomSize = MaxOptionRomSize;
529
530 //
531 // Alignment should be adjusted as well
532 //
533 if (Mem32Bridge->Alignment < MaxOptionRomSize - 1) {
534 Mem32Bridge->Alignment = MaxOptionRomSize - 1;
535 }
536 }
537 }
538
539 //
540 // Based on the all the resource tree, contruct ACPI resource node to
541 // submit the resource aperture to pci host bridge protocol
542 //
543 Status = ConstructAcpiResourceRequestor (
544 RootBridgeDev,
545 IoBridge,
546 Mem32Bridge,
547 PMem32Bridge,
548 Mem64Bridge,
549 PMem64Bridge,
550 &AcpiConfig
551 );
552
553 //
554 // Insert these resource nodes into the database
555 //
556 InsertResourceNode (&IoPool, IoBridge);
557 InsertResourceNode (&Mem32Pool, Mem32Bridge);
558 InsertResourceNode (&PMem32Pool, PMem32Bridge);
559 InsertResourceNode (&Mem64Pool, Mem64Bridge);
560 InsertResourceNode (&PMem64Pool, PMem64Bridge);
561
562 if (Status == EFI_SUCCESS) {
563 //
564 // Submit the resource requirement
565 //
566 Status = PciResAlloc->SubmitResources (
567 PciResAlloc,
568 RootBridgeDev->Handle,
569 AcpiConfig
570 );
571 //
572 // If SubmitResources returns error, PciBus isn't able to start.
573 // It's a fatal error so assertion is added.
574 //
575 DEBUG ((EFI_D_INFO, "PciBus: HostBridge->SubmitResources() - %r\n", Status));
576 ASSERT_EFI_ERROR (Status);
577 }
578
579 //
580 // Free acpi resource node
581 //
582 if (AcpiConfig != NULL) {
583 FreePool (AcpiConfig);
584 }
585
586 if (EFI_ERROR (Status)) {
587 //
588 // Destroy all the resource tree
589 //
590 DestroyResourceTree (&IoPool);
591 DestroyResourceTree (&Mem32Pool);
592 DestroyResourceTree (&PMem32Pool);
593 DestroyResourceTree (&Mem64Pool);
594 DestroyResourceTree (&PMem64Pool);
595 return Status;
596 }
597 }
598 //
599 // End while, at least one Root Bridge should be found.
600 //
601 ASSERT (RootBridgeDev != NULL);
602
603 //
604 // Notify platform to start to program the resource
605 //
606 Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeAllocateResources);
607 DEBUG ((EFI_D_INFO, "PciBus: HostBridge->NotifyPhase(AllocateResources) - %r\n", Status));
608 if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
609 //
610 // If Hot Plug is not supported
611 //
612 if (EFI_ERROR (Status)) {
613 //
614 // Allocation failed, then return
615 //
616 return EFI_OUT_OF_RESOURCES;
617 }
618 //
619 // Allocation succeed.
620 // Get host bridge handle for status report, and then skip the main while
621 //
622 HandleExtendedData.Handle = RootBridgeDev->PciRootBridgeIo->ParentHandle;
623
624 break;
625
626 } else {
627 //
628 // If Hot Plug is supported
629 //
630 if (!EFI_ERROR (Status)) {
631 //
632 // Allocation succeed, then continue the following
633 //
634 break;
635 }
636
637 //
638 // If the resource allocation is unsuccessful, free resources on bridge
639 //
640
641 RootBridgeDev = NULL;
642 RootBridgeHandle = 0;
643
644 IoResStatus = EFI_RESOURCE_SATISFIED;
645 Mem32ResStatus = EFI_RESOURCE_SATISFIED;
646 PMem32ResStatus = EFI_RESOURCE_SATISFIED;
647 Mem64ResStatus = EFI_RESOURCE_SATISFIED;
648 PMem64ResStatus = EFI_RESOURCE_SATISFIED;
649
650 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
651 //
652 // Get RootBridg Device by handle
653 //
654 RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);
655 if (RootBridgeDev == NULL) {
656 return EFI_NOT_FOUND;
657 }
658
659 //
660 // Get host bridge handle for status report
661 //
662 HandleExtendedData.Handle = RootBridgeDev->PciRootBridgeIo->ParentHandle;
663
664 //
665 // Get acpi resource node for all the resource types
666 //
667 AcpiConfig = NULL;
668
669 Status = PciResAlloc->GetProposedResources (
670 PciResAlloc,
671 RootBridgeDev->Handle,
672 &AcpiConfig
673 );
674
675 if (EFI_ERROR (Status)) {
676 return Status;
677 }
678
679 if (AcpiConfig != NULL) {
680 //
681 // Adjust resource allocation policy for each RB
682 //
683 GetResourceAllocationStatus (
684 AcpiConfig,
685 &IoResStatus,
686 &Mem32ResStatus,
687 &PMem32ResStatus,
688 &Mem64ResStatus,
689 &PMem64ResStatus
690 );
691 FreePool (AcpiConfig);
692 }
693 }
694 //
695 // End while
696 //
697
698 //
699 // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code
700 //
701 //
702 // It is very difficult to follow the spec here
703 // Device path , Bar index can not be get here
704 //
705 ZeroMem (&AllocFailExtendedData, sizeof (AllocFailExtendedData));
706
707 REPORT_STATUS_CODE_WITH_EXTENDED_DATA (
708 EFI_PROGRESS_CODE,
709 EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT,
710 (VOID *) &AllocFailExtendedData,
711 sizeof (AllocFailExtendedData)
712 );
713
714 Status = PciHostBridgeAdjustAllocation (
715 &IoPool,
716 &Mem32Pool,
717 &PMem32Pool,
718 &Mem64Pool,
719 &PMem64Pool,
720 IoResStatus,
721 Mem32ResStatus,
722 PMem32ResStatus,
723 Mem64ResStatus,
724 PMem64ResStatus
725 );
726
727 //
728 // Destroy all the resource tree
729 //
730 DestroyResourceTree (&IoPool);
731 DestroyResourceTree (&Mem32Pool);
732 DestroyResourceTree (&PMem32Pool);
733 DestroyResourceTree (&Mem64Pool);
734 DestroyResourceTree (&PMem64Pool);
735
736 NotifyPhase (PciResAlloc, EfiPciHostBridgeFreeResources);
737
738 if (EFI_ERROR (Status)) {
739 return Status;
740 }
741
742 ReAllocate = TRUE;
743 }
744 }
745 //
746 // End main while
747 //
748
749 //
750 // Raise the EFI_IOB_PCI_RES_ALLOC status code
751 //
752 REPORT_STATUS_CODE_WITH_EXTENDED_DATA (
753 EFI_PROGRESS_CODE,
754 EFI_IO_BUS_PCI | EFI_IOB_PCI_RES_ALLOC,
755 (VOID *) &HandleExtendedData,
756 sizeof (HandleExtendedData)
757 );
758
759 //
760 // Notify pci bus driver starts to program the resource
761 //
762 Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeSetResources);
763
764 if (EFI_ERROR (Status)) {
765 return Status;
766 }
767
768 RootBridgeDev = NULL;
769
770 RootBridgeHandle = 0;
771
772 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
773 //
774 // Get RootBridg Device by handle
775 //
776 RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);
777
778 if (RootBridgeDev == NULL) {
779 return EFI_NOT_FOUND;
780 }
781
782 //
783 // Get acpi resource node for all the resource types
784 //
785 AcpiConfig = NULL;
786 Status = PciResAlloc->GetProposedResources (
787 PciResAlloc,
788 RootBridgeDev->Handle,
789 &AcpiConfig
790 );
791
792 if (EFI_ERROR (Status)) {
793 return Status;
794 }
795
796 //
797 // Get the resource base by interpreting acpi resource node
798 //
799 //
800 GetResourceBase (
801 AcpiConfig,
802 &IoBase,
803 &Mem32Base,
804 &PMem32Base,
805 &Mem64Base,
806 &PMem64Base
807 );
808
809 //
810 // Process option rom for this root bridge
811 //
812 ProcessOptionRom (RootBridgeDev, Mem32Base, RootBridgeDev->RomSize);
813
814 //
815 // Create the entire system resource map from the information collected by
816 // enumerator. Several resource tree was created
817 //
818 IoBridge = FindResourceNode (RootBridgeDev, &IoPool);
819 Mem32Bridge = FindResourceNode (RootBridgeDev, &Mem32Pool);
820 PMem32Bridge = FindResourceNode (RootBridgeDev, &PMem32Pool);
821 Mem64Bridge = FindResourceNode (RootBridgeDev, &Mem64Pool);
822 PMem64Bridge = FindResourceNode (RootBridgeDev, &PMem64Pool);
823
824 ASSERT (IoBridge != NULL);
825 ASSERT (Mem32Bridge != NULL);
826 ASSERT (PMem32Bridge != NULL);
827 ASSERT (Mem64Bridge != NULL);
828 ASSERT (PMem64Bridge != NULL);
829
830 //
831 // Program IO resources
832 //
833 ProgramResource (
834 IoBase,
835 IoBridge
836 );
837
838 //
839 // Program Mem32 resources
840 //
841 ProgramResource (
842 Mem32Base,
843 Mem32Bridge
844 );
845
846 //
847 // Program PMem32 resources
848 //
849 ProgramResource (
850 PMem32Base,
851 PMem32Bridge
852 );
853
854 //
855 // Program Mem64 resources
856 //
857 ProgramResource (
858 Mem64Base,
859 Mem64Bridge
860 );
861
862 //
863 // Program PMem64 resources
864 //
865 ProgramResource (
866 PMem64Base,
867 PMem64Bridge
868 );
869
870 IoBridge ->PciDev->PciBar[IoBridge ->Bar].BaseAddress = IoBase;
871 Mem32Bridge ->PciDev->PciBar[Mem32Bridge ->Bar].BaseAddress = Mem32Base;
872 PMem32Bridge->PciDev->PciBar[PMem32Bridge->Bar].BaseAddress = PMem32Base;
873 Mem64Bridge ->PciDev->PciBar[Mem64Bridge ->Bar].BaseAddress = Mem64Base;
874 PMem64Bridge->PciDev->PciBar[PMem64Bridge->Bar].BaseAddress = PMem64Base;
875
876 //
877 // Dump the resource map for current root bridge
878 //
879 DEBUG_CODE (
880 DumpResourceMap (
881 RootBridgeDev,
882 IoBridge,
883 Mem32Bridge,
884 PMem32Bridge,
885 Mem64Bridge,
886 PMem64Bridge
887 );
888 );
889
890 FreePool (AcpiConfig);
891 }
892
893 //
894 // Destroy all the resource tree
895 //
896 DestroyResourceTree (&IoPool);
897 DestroyResourceTree (&Mem32Pool);
898 DestroyResourceTree (&PMem32Pool);
899 DestroyResourceTree (&Mem64Pool);
900 DestroyResourceTree (&PMem64Pool);
901
902 //
903 // Notify the resource allocation phase is to end
904 //
905 Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeEndResourceAllocation);
906
907 return Status;
908 }
909
910 /**
911 Allocate NumberOfBuses buses and return the next available PCI bus number.
912
913 @param Bridge Bridge device instance.
914 @param StartBusNumber Current available PCI bus number.
915 @param NumberOfBuses Number of buses enumerated below the StartBusNumber.
916 @param NextBusNumber Next available PCI bus number.
917
918 @retval EFI_SUCCESS Available bus number resource is enough. Next available PCI bus number
919 is returned in NextBusNumber.
920 @retval EFI_OUT_OF_RESOURCES Available bus number resource is not enough for allocation.
921
922 **/
923 EFI_STATUS
924 PciAllocateBusNumber (
925 IN PCI_IO_DEVICE *Bridge,
926 IN UINT8 StartBusNumber,
927 IN UINT8 NumberOfBuses,
928 OUT UINT8 *NextBusNumber
929 )
930 {
931 PCI_IO_DEVICE *RootBridge;
932 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BusNumberRanges;
933 UINT8 NextNumber;
934 UINT64 MaxNumberInRange;
935
936 //
937 // Get PCI Root Bridge device
938 //
939 RootBridge = Bridge;
940 while (RootBridge->Parent != NULL) {
941 RootBridge = RootBridge->Parent;
942 }
943
944 //
945 // Get next available PCI bus number
946 //
947 BusNumberRanges = RootBridge->BusNumberRanges;
948 while (BusNumberRanges->Desc != ACPI_END_TAG_DESCRIPTOR) {
949 MaxNumberInRange = BusNumberRanges->AddrRangeMin + BusNumberRanges->AddrLen - 1;
950 if (StartBusNumber >= BusNumberRanges->AddrRangeMin && StartBusNumber <= MaxNumberInRange) {
951 NextNumber = (UINT8)(StartBusNumber + NumberOfBuses);
952 while (NextNumber > MaxNumberInRange) {
953 ++BusNumberRanges;
954 if (BusNumberRanges->Desc == ACPI_END_TAG_DESCRIPTOR) {
955 return EFI_OUT_OF_RESOURCES;
956 }
957 NextNumber = (UINT8)(NextNumber + (BusNumberRanges->AddrRangeMin - (MaxNumberInRange + 1)));
958 MaxNumberInRange = BusNumberRanges->AddrRangeMin + BusNumberRanges->AddrLen - 1;
959 }
960 *NextBusNumber = NextNumber;
961 return EFI_SUCCESS;
962 }
963 BusNumberRanges++;
964 }
965 return EFI_OUT_OF_RESOURCES;
966 }
967
968 /**
969 Scan pci bus and assign bus number to the given PCI bus system.
970
971 @param Bridge Bridge device instance.
972 @param StartBusNumber start point.
973 @param SubBusNumber Point to sub bus number.
974 @param PaddedBusRange Customized bus number.
975
976 @retval EFI_SUCCESS Successfully scanned and assigned bus number.
977 @retval other Some error occurred when scanning pci bus.
978
979 @note Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.
980
981 **/
982 EFI_STATUS
983 PciScanBus (
984 IN PCI_IO_DEVICE *Bridge,
985 IN UINT8 StartBusNumber,
986 OUT UINT8 *SubBusNumber,
987 OUT UINT8 *PaddedBusRange
988 )
989 {
990 EFI_STATUS Status;
991 PCI_TYPE00 Pci;
992 UINT8 Device;
993 UINT8 Func;
994 UINT64 Address;
995 UINTN SecondBus;
996 UINT16 Register;
997 UINTN HpIndex;
998 PCI_IO_DEVICE *PciDevice;
999 EFI_EVENT Event;
1000 EFI_HPC_STATE State;
1001 UINT64 PciAddress;
1002 EFI_HPC_PADDING_ATTRIBUTES Attributes;
1003 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
1004 UINT16 BusRange;
1005 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
1006 BOOLEAN BusPadding;
1007 UINT32 TempReservedBusNum;
1008
1009 PciRootBridgeIo = Bridge->PciRootBridgeIo;
1010 SecondBus = 0;
1011 Register = 0;
1012 State = 0;
1013 Attributes = (EFI_HPC_PADDING_ATTRIBUTES) 0;
1014 BusRange = 0;
1015 BusPadding = FALSE;
1016 PciDevice = NULL;
1017 PciAddress = 0;
1018
1019 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
1020 TempReservedBusNum = 0;
1021 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
1022
1023 //
1024 // Check to see whether a pci device is present
1025 //
1026 Status = PciDevicePresent (
1027 PciRootBridgeIo,
1028 &Pci,
1029 StartBusNumber,
1030 Device,
1031 Func
1032 );
1033
1034 if (EFI_ERROR (Status)) {
1035 continue;
1036 }
1037
1038 //
1039 // Get the PCI device information
1040 //
1041 Status = PciSearchDevice (
1042 Bridge,
1043 &Pci,
1044 StartBusNumber,
1045 Device,
1046 Func,
1047 &PciDevice
1048 );
1049
1050 ASSERT (!EFI_ERROR (Status));
1051
1052 PciAddress = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0);
1053
1054 if (!IS_PCI_BRIDGE (&Pci)) {
1055 //
1056 // PCI bridges will be called later
1057 // Here just need for PCI device or PCI to cardbus controller
1058 // EfiPciBeforeChildBusEnumeration for PCI Device Node
1059 //
1060 PreprocessController (
1061 PciDevice,
1062 PciDevice->BusNumber,
1063 PciDevice->DeviceNumber,
1064 PciDevice->FunctionNumber,
1065 EfiPciBeforeChildBusEnumeration
1066 );
1067 }
1068
1069 if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
1070 //
1071 // For Pci Hotplug controller devcie only
1072 //
1073 if (gPciHotPlugInit != NULL) {
1074 //
1075 // Check if it is a Hotplug PCI controller
1076 //
1077 if (IsRootPciHotPlugController (PciDevice->DevicePath, &HpIndex)) {
1078 gPciRootHpcData[HpIndex].Found = TRUE;
1079
1080 if (!gPciRootHpcData[HpIndex].Initialized) {
1081
1082 Status = CreateEventForHpc (HpIndex, &Event);
1083
1084 ASSERT (!EFI_ERROR (Status));
1085
1086 Status = gPciHotPlugInit->InitializeRootHpc (
1087 gPciHotPlugInit,
1088 gPciRootHpcPool[HpIndex].HpcDevicePath,
1089 PciAddress,
1090 Event,
1091 &State
1092 );
1093
1094 PreprocessController (
1095 PciDevice,
1096 PciDevice->BusNumber,
1097 PciDevice->DeviceNumber,
1098 PciDevice->FunctionNumber,
1099 EfiPciBeforeChildBusEnumeration
1100 );
1101 }
1102 }
1103 }
1104 }
1105
1106 if (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci)) {
1107 //
1108 // For PPB
1109 //
1110 if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
1111 //
1112 // If Hot Plug is not supported,
1113 // get the bridge information
1114 //
1115 Status = PciSearchDevice (
1116 Bridge,
1117 &Pci,
1118 StartBusNumber,
1119 Device,
1120 Func,
1121 &PciDevice
1122 );
1123
1124 if (EFI_ERROR (Status)) {
1125 return Status;
1126 }
1127 } else {
1128 //
1129 // If Hot Plug is supported,
1130 // Get the bridge information
1131 //
1132 BusPadding = FALSE;
1133 if (gPciHotPlugInit != NULL) {
1134
1135 if (IsRootPciHotPlugBus (PciDevice->DevicePath, &HpIndex)) {
1136
1137 //
1138 // If it is initialized, get the padded bus range
1139 //
1140 Status = gPciHotPlugInit->GetResourcePadding (
1141 gPciHotPlugInit,
1142 gPciRootHpcPool[HpIndex].HpbDevicePath,
1143 PciAddress,
1144 &State,
1145 (VOID **) &Descriptors,
1146 &Attributes
1147 );
1148
1149 if (EFI_ERROR (Status)) {
1150 return Status;
1151 }
1152
1153 BusRange = 0;
1154 Status = PciGetBusRange (
1155 &Descriptors,
1156 NULL,
1157 NULL,
1158 &BusRange
1159 );
1160
1161 FreePool (Descriptors);
1162
1163 if (EFI_ERROR (Status)) {
1164 return Status;
1165 }
1166
1167 BusPadding = TRUE;
1168 }
1169 }
1170 }
1171
1172 Status = PciAllocateBusNumber (Bridge, *SubBusNumber, 1, SubBusNumber);
1173 if (EFI_ERROR (Status)) {
1174 return Status;
1175 }
1176 SecondBus = *SubBusNumber;
1177
1178 Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);
1179 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET);
1180
1181 Status = PciRootBridgeIo->Pci.Write (
1182 PciRootBridgeIo,
1183 EfiPciWidthUint16,
1184 Address,
1185 1,
1186 &Register
1187 );
1188
1189
1190 //
1191 // If it is PPB, resursively search down this bridge
1192 //
1193 if (IS_PCI_BRIDGE (&Pci)) {
1194
1195 //
1196 // Temporarily initialize SubBusNumber to maximum bus number to ensure the
1197 // PCI configuration transaction to go through any PPB
1198 //
1199 Register = 0xFF;
1200 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
1201 Status = PciRootBridgeIo->Pci.Write (
1202 PciRootBridgeIo,
1203 EfiPciWidthUint8,
1204 Address,
1205 1,
1206 &Register
1207 );
1208
1209 //
1210 // Nofify EfiPciBeforeChildBusEnumeration for PCI Brige
1211 //
1212 PreprocessController (
1213 PciDevice,
1214 PciDevice->BusNumber,
1215 PciDevice->DeviceNumber,
1216 PciDevice->FunctionNumber,
1217 EfiPciBeforeChildBusEnumeration
1218 );
1219
1220 Status = PciScanBus (
1221 PciDevice,
1222 (UINT8) (SecondBus),
1223 SubBusNumber,
1224 PaddedBusRange
1225 );
1226 if (EFI_ERROR (Status)) {
1227 return Status;
1228 }
1229 }
1230
1231 if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport) && BusPadding) {
1232 //
1233 // Ensure the device is enabled and initialized
1234 //
1235 if ((Attributes == EfiPaddingPciRootBridge) &&
1236 (State & EFI_HPC_STATE_ENABLED) != 0 &&
1237 (State & EFI_HPC_STATE_INITIALIZED) != 0) {
1238 *PaddedBusRange = (UINT8) ((UINT8) (BusRange) +*PaddedBusRange);
1239 } else {
1240 Status = PciAllocateBusNumber (PciDevice, *SubBusNumber, (UINT8) (BusRange), SubBusNumber);
1241 if (EFI_ERROR (Status)) {
1242 return Status;
1243 }
1244 }
1245 }
1246
1247 //
1248 // Set the current maximum bus number under the PPB
1249 //
1250 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
1251
1252 Status = PciRootBridgeIo->Pci.Write (
1253 PciRootBridgeIo,
1254 EfiPciWidthUint8,
1255 Address,
1256 1,
1257 SubBusNumber
1258 );
1259 } else {
1260 //
1261 // It is device. Check PCI IOV for Bus reservation
1262 // Go through each function, just reserve the MAX ReservedBusNum for one device
1263 //
1264 if (PcdGetBool (PcdSrIovSupport) && PciDevice->SrIovCapabilityOffset != 0) {
1265 if (TempReservedBusNum < PciDevice->ReservedBusNum) {
1266
1267 Status = PciAllocateBusNumber (PciDevice, *SubBusNumber, (UINT8) (PciDevice->ReservedBusNum - TempReservedBusNum), SubBusNumber);
1268 if (EFI_ERROR (Status)) {
1269 return Status;
1270 }
1271 TempReservedBusNum = PciDevice->ReservedBusNum;
1272
1273 if (Func == 0) {
1274 DEBUG ((EFI_D_INFO, "PCI-IOV ScanBus - SubBusNumber - 0x%x\n", *SubBusNumber));
1275 } else {
1276 DEBUG ((EFI_D_INFO, "PCI-IOV ScanBus - SubBusNumber - 0x%x (Update)\n", *SubBusNumber));
1277 }
1278 }
1279 }
1280 }
1281
1282 if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
1283
1284 //
1285 // Skip sub functions, this is not a multi function device
1286 //
1287
1288 Func = PCI_MAX_FUNC;
1289 }
1290 }
1291 }
1292
1293 return EFI_SUCCESS;
1294 }
1295
1296 /**
1297 Process Option Rom on the specified root bridge.
1298
1299 @param Bridge Pci root bridge device instance.
1300
1301 @retval EFI_SUCCESS Success process.
1302 @retval other Some error occurred when processing Option Rom on the root bridge.
1303
1304 **/
1305 EFI_STATUS
1306 PciRootBridgeP2CProcess (
1307 IN PCI_IO_DEVICE *Bridge
1308 )
1309 {
1310 LIST_ENTRY *CurrentLink;
1311 PCI_IO_DEVICE *Temp;
1312 EFI_HPC_STATE State;
1313 UINT64 PciAddress;
1314 EFI_STATUS Status;
1315
1316 CurrentLink = Bridge->ChildList.ForwardLink;
1317
1318 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
1319
1320 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
1321
1322 if (IS_CARDBUS_BRIDGE (&Temp->Pci)) {
1323
1324 if (gPciHotPlugInit != NULL && Temp->Allocated && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
1325
1326 //
1327 // Raise the EFI_IOB_PCI_HPC_INIT status code
1328 //
1329 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
1330 EFI_PROGRESS_CODE,
1331 EFI_IO_BUS_PCI | EFI_IOB_PCI_HPC_INIT,
1332 Temp->DevicePath
1333 );
1334
1335 PciAddress = EFI_PCI_ADDRESS (Temp->BusNumber, Temp->DeviceNumber, Temp->FunctionNumber, 0);
1336 Status = gPciHotPlugInit->InitializeRootHpc (
1337 gPciHotPlugInit,
1338 Temp->DevicePath,
1339 PciAddress,
1340 NULL,
1341 &State
1342 );
1343
1344 if (!EFI_ERROR (Status)) {
1345 Status = PciBridgeEnumerator (Temp);
1346
1347 if (EFI_ERROR (Status)) {
1348 return Status;
1349 }
1350 }
1351
1352 CurrentLink = CurrentLink->ForwardLink;
1353 continue;
1354
1355 }
1356 }
1357
1358 if (!IsListEmpty (&Temp->ChildList)) {
1359 Status = PciRootBridgeP2CProcess (Temp);
1360 }
1361
1362 CurrentLink = CurrentLink->ForwardLink;
1363 }
1364
1365 return EFI_SUCCESS;
1366 }
1367
1368 /**
1369 Process Option Rom on the specified host bridge.
1370
1371 @param PciResAlloc Pointer to instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
1372
1373 @retval EFI_SUCCESS Success process.
1374 @retval EFI_NOT_FOUND Can not find the root bridge instance.
1375 @retval other Some error occurred when processing Option Rom on the host bridge.
1376
1377 **/
1378 EFI_STATUS
1379 PciHostBridgeP2CProcess (
1380 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
1381 )
1382 {
1383 EFI_HANDLE RootBridgeHandle;
1384 PCI_IO_DEVICE *RootBridgeDev;
1385 EFI_STATUS Status;
1386
1387 if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
1388 return EFI_SUCCESS;
1389 }
1390
1391 RootBridgeHandle = NULL;
1392
1393 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
1394
1395 //
1396 // Get RootBridg Device by handle
1397 //
1398 RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);
1399
1400 if (RootBridgeDev == NULL) {
1401 return EFI_NOT_FOUND;
1402 }
1403
1404 Status = PciRootBridgeP2CProcess (RootBridgeDev);
1405 if (EFI_ERROR (Status)) {
1406 return Status;
1407 }
1408
1409 }
1410
1411 return EFI_SUCCESS;
1412 }
1413
1414 /**
1415 This function is used to enumerate the entire host bridge
1416 in a given platform.
1417
1418 @param PciResAlloc A pointer to the PCI Host Resource Allocation protocol.
1419
1420 @retval EFI_SUCCESS Successfully enumerated the host bridge.
1421 @retval EFI_OUT_OF_RESOURCES No enough memory available.
1422 @retval other Some error occurred when enumerating the host bridge.
1423
1424 **/
1425 EFI_STATUS
1426 PciHostBridgeEnumerator (
1427 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
1428 )
1429 {
1430 EFI_HANDLE RootBridgeHandle;
1431 PCI_IO_DEVICE *RootBridgeDev;
1432 EFI_STATUS Status;
1433 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
1434 UINT16 MinBus;
1435 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
1436 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;
1437 UINT8 StartBusNumber;
1438 LIST_ENTRY RootBridgeList;
1439 LIST_ENTRY *Link;
1440
1441 if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
1442 InitializeHotPlugSupport ();
1443 }
1444
1445 InitializeListHead (&RootBridgeList);
1446
1447 //
1448 // Notify the bus allocation phase is about to start
1449 //
1450 Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);
1451
1452 if (EFI_ERROR (Status)) {
1453 return Status;
1454 }
1455
1456 DEBUG((EFI_D_INFO, "PCI Bus First Scanning\n"));
1457 RootBridgeHandle = NULL;
1458 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
1459
1460 //
1461 // if a root bridge instance is found, create root bridge device for it
1462 //
1463
1464 RootBridgeDev = CreateRootBridge (RootBridgeHandle);
1465
1466 if (RootBridgeDev == NULL) {
1467 return EFI_OUT_OF_RESOURCES;
1468 }
1469
1470 //
1471 // Enumerate all the buses under this root bridge
1472 //
1473 Status = PciRootBridgeEnumerator (
1474 PciResAlloc,
1475 RootBridgeDev
1476 );
1477
1478 if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
1479 InsertTailList (&RootBridgeList, &(RootBridgeDev->Link));
1480 } else {
1481 DestroyRootBridge (RootBridgeDev);
1482 }
1483 if (EFI_ERROR (Status)) {
1484 return Status;
1485 }
1486 }
1487
1488 //
1489 // Notify the bus allocation phase is finished for the first time
1490 //
1491 NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);
1492
1493 if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
1494 //
1495 // Reset all assigned PCI bus number in all PPB
1496 //
1497 RootBridgeHandle = NULL;
1498 Link = GetFirstNode (&RootBridgeList);
1499 while ((PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) &&
1500 (!IsNull (&RootBridgeList, Link))) {
1501 RootBridgeDev = PCI_IO_DEVICE_FROM_LINK (Link);
1502 //
1503 // Get the Bus information
1504 //
1505 Status = PciResAlloc->StartBusEnumeration (
1506 PciResAlloc,
1507 RootBridgeHandle,
1508 (VOID **) &Configuration
1509 );
1510 if (EFI_ERROR (Status)) {
1511 return Status;
1512 }
1513
1514 //
1515 // Get the bus number to start with
1516 //
1517 StartBusNumber = (UINT8) (Configuration->AddrRangeMin);
1518
1519 ResetAllPpbBusNumber (
1520 RootBridgeDev,
1521 StartBusNumber
1522 );
1523
1524 FreePool (Configuration);
1525 Link = RemoveEntryList (Link);
1526 DestroyRootBridge (RootBridgeDev);
1527 }
1528
1529 //
1530 // Wait for all HPC initialized
1531 //
1532 Status = AllRootHPCInitialized (STALL_1_SECOND * 15);
1533
1534 if (EFI_ERROR (Status)) {
1535 DEBUG ((EFI_D_ERROR, "Some root HPC failed to initialize\n"));
1536 return Status;
1537 }
1538
1539 //
1540 // Notify the bus allocation phase is about to start for the 2nd time
1541 //
1542 Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);
1543
1544 if (EFI_ERROR (Status)) {
1545 return Status;
1546 }
1547
1548 DEBUG((EFI_D_INFO, "PCI Bus Second Scanning\n"));
1549 RootBridgeHandle = NULL;
1550 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
1551
1552 //
1553 // if a root bridge instance is found, create root bridge device for it
1554 //
1555 RootBridgeDev = CreateRootBridge (RootBridgeHandle);
1556
1557 if (RootBridgeDev == NULL) {
1558 return EFI_OUT_OF_RESOURCES;
1559 }
1560
1561 //
1562 // Enumerate all the buses under this root bridge
1563 //
1564 Status = PciRootBridgeEnumerator (
1565 PciResAlloc,
1566 RootBridgeDev
1567 );
1568
1569 DestroyRootBridge (RootBridgeDev);
1570 if (EFI_ERROR (Status)) {
1571 return Status;
1572 }
1573 }
1574
1575 //
1576 // Notify the bus allocation phase is to end for the 2nd time
1577 //
1578 NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);
1579 }
1580
1581 //
1582 // Notify the resource allocation phase is to start
1583 //
1584 Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginResourceAllocation);
1585
1586 if (EFI_ERROR (Status)) {
1587 return Status;
1588 }
1589
1590 RootBridgeHandle = NULL;
1591 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
1592
1593 //
1594 // if a root bridge instance is found, create root bridge device for it
1595 //
1596 RootBridgeDev = CreateRootBridge (RootBridgeHandle);
1597
1598 if (RootBridgeDev == NULL) {
1599 return EFI_OUT_OF_RESOURCES;
1600 }
1601
1602 Status = StartManagingRootBridge (RootBridgeDev);
1603
1604 if (EFI_ERROR (Status)) {
1605 return Status;
1606 }
1607
1608 PciRootBridgeIo = RootBridgeDev->PciRootBridgeIo;
1609 Status = PciRootBridgeIo->Configuration (PciRootBridgeIo, (VOID **) &Descriptors);
1610
1611 if (EFI_ERROR (Status)) {
1612 return Status;
1613 }
1614
1615 Status = PciGetBusRange (&Descriptors, &MinBus, NULL, NULL);
1616
1617 if (EFI_ERROR (Status)) {
1618 return Status;
1619 }
1620
1621 //
1622 // Determine root bridge attribute by calling interface of Pcihostbridge
1623 // protocol
1624 //
1625 DetermineRootBridgeAttributes (
1626 PciResAlloc,
1627 RootBridgeDev
1628 );
1629
1630 //
1631 // Collect all the resource information under this root bridge
1632 // A database that records all the information about pci device subject to this
1633 // root bridge will then be created
1634 //
1635 Status = PciPciDeviceInfoCollector (
1636 RootBridgeDev,
1637 (UINT8) MinBus
1638 );
1639
1640 if (EFI_ERROR (Status)) {
1641 return Status;
1642 }
1643
1644 InsertRootBridge (RootBridgeDev);
1645
1646 //
1647 // Record the hostbridge handle
1648 //
1649 AddHostBridgeEnumerator (RootBridgeDev->PciRootBridgeIo->ParentHandle);
1650 }
1651
1652 return EFI_SUCCESS;
1653 }