3 PCI Root Bridge Io Protocol code.
5 Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include "PciHostBridge.h"
17 #include "PciRootBridge.h"
18 #include "PciHostResource.h"
20 #define NO_MAPPING (VOID *) (UINTN) -1
23 // Lookup table for increment values based on transfer widths
26 1, // EfiPciWidthUint8
27 2, // EfiPciWidthUint16
28 4, // EfiPciWidthUint32
29 8, // EfiPciWidthUint64
30 0, // EfiPciWidthFifoUint8
31 0, // EfiPciWidthFifoUint16
32 0, // EfiPciWidthFifoUint32
33 0, // EfiPciWidthFifoUint64
34 1, // EfiPciWidthFillUint8
35 2, // EfiPciWidthFillUint16
36 4, // EfiPciWidthFillUint32
37 8 // EfiPciWidthFillUint64
41 // Lookup table for increment values based on transfer widths
43 UINT8 mOutStride
[] = {
44 1, // EfiPciWidthUint8
45 2, // EfiPciWidthUint16
46 4, // EfiPciWidthUint32
47 8, // EfiPciWidthUint64
48 1, // EfiPciWidthFifoUint8
49 2, // EfiPciWidthFifoUint16
50 4, // EfiPciWidthFifoUint32
51 8, // EfiPciWidthFifoUint64
52 0, // EfiPciWidthFillUint8
53 0, // EfiPciWidthFillUint16
54 0, // EfiPciWidthFillUint32
55 0 // EfiPciWidthFillUint64
59 Construct the Pci Root Bridge instance.
61 @param Bridge The root bridge instance.
63 @return The pointer to PCI_ROOT_BRIDGE_INSTANCE just created
64 or NULL if creation fails.
66 PCI_ROOT_BRIDGE_INSTANCE
*
68 IN PCI_ROOT_BRIDGE
*Bridge
71 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
72 PCI_RESOURCE_TYPE Index
;
73 CHAR16
*DevicePathStr
;
74 PCI_ROOT_BRIDGE_APERTURE
*Aperture
;
78 DEBUG ((EFI_D_INFO
, "RootBridge: "));
79 DEBUG ((EFI_D_INFO
, "%s\n", DevicePathStr
= ConvertDevicePathToText (Bridge
->DevicePath
, FALSE
, FALSE
)));
80 DEBUG ((EFI_D_INFO
, " Support/Attr: %lx / %lx\n", Bridge
->Supports
, Bridge
->Attributes
));
81 DEBUG ((EFI_D_INFO
, " DmaAbove4G: %s\n", Bridge
->DmaAbove4G
? L
"Yes" : L
"No"));
82 DEBUG ((EFI_D_INFO
, "NoExtConfSpace: %s\n", Bridge
->NoExtendedConfigSpace
? L
"Yes" : L
"No"));
83 DEBUG ((EFI_D_INFO
, " AllocAttr: %lx (%s%s)\n", Bridge
->AllocationAttributes
,
84 (Bridge
->AllocationAttributes
& EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM
) != 0 ? L
"CombineMemPMem " : L
"",
85 (Bridge
->AllocationAttributes
& EFI_PCI_HOST_BRIDGE_MEM64_DECODE
) != 0 ? L
"Mem64Decode" : L
""
87 DEBUG ((EFI_D_INFO
, " Bus: %lx - %lx\n", Bridge
->Bus
.Base
, Bridge
->Bus
.Limit
));
88 DEBUG ((EFI_D_INFO
, " Io: %lx - %lx\n", Bridge
->Io
.Base
, Bridge
->Io
.Limit
));
89 DEBUG ((EFI_D_INFO
, " Mem: %lx - %lx\n", Bridge
->Mem
.Base
, Bridge
->Mem
.Limit
));
90 DEBUG ((EFI_D_INFO
, " MemAbove4G: %lx - %lx\n", Bridge
->MemAbove4G
.Base
, Bridge
->MemAbove4G
.Limit
));
91 DEBUG ((EFI_D_INFO
, " PMem: %lx - %lx\n", Bridge
->PMem
.Base
, Bridge
->PMem
.Limit
));
92 DEBUG ((EFI_D_INFO
, " PMemAbove4G: %lx - %lx\n", Bridge
->PMemAbove4G
.Base
, Bridge
->PMemAbove4G
.Limit
));
95 // Make sure Mem and MemAbove4G apertures are valid
97 if (Bridge
->Mem
.Base
<= Bridge
->Mem
.Limit
) {
98 ASSERT (Bridge
->Mem
.Limit
< SIZE_4GB
);
99 if (Bridge
->Mem
.Limit
>= SIZE_4GB
) {
103 if (Bridge
->MemAbove4G
.Base
<= Bridge
->MemAbove4G
.Limit
) {
104 ASSERT (Bridge
->MemAbove4G
.Base
>= SIZE_4GB
);
105 if (Bridge
->MemAbove4G
.Base
< SIZE_4GB
) {
109 if (Bridge
->PMem
.Base
<= Bridge
->PMem
.Limit
) {
110 ASSERT (Bridge
->PMem
.Limit
< SIZE_4GB
);
111 if (Bridge
->PMem
.Limit
>= SIZE_4GB
) {
115 if (Bridge
->PMemAbove4G
.Base
<= Bridge
->PMemAbove4G
.Limit
) {
116 ASSERT (Bridge
->PMemAbove4G
.Base
>= SIZE_4GB
);
117 if (Bridge
->PMemAbove4G
.Base
< SIZE_4GB
) {
123 // Ignore AllocationAttributes when resources were already assigned.
125 if (!Bridge
->ResourceAssigned
) {
126 if ((Bridge
->AllocationAttributes
& EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM
) != 0) {
128 // If this bit is set, then the PCI Root Bridge does not
129 // support separate windows for Non-prefetchable and Prefetchable
132 ASSERT (Bridge
->PMem
.Base
> Bridge
->PMem
.Limit
);
133 ASSERT (Bridge
->PMemAbove4G
.Base
> Bridge
->PMemAbove4G
.Limit
);
134 if ((Bridge
->PMem
.Base
<= Bridge
->PMem
.Limit
) ||
135 (Bridge
->PMemAbove4G
.Base
<= Bridge
->PMemAbove4G
.Limit
)
141 if ((Bridge
->AllocationAttributes
& EFI_PCI_HOST_BRIDGE_MEM64_DECODE
) == 0) {
143 // If this bit is not set, then the PCI Root Bridge does not support
144 // 64 bit memory windows.
146 ASSERT (Bridge
->MemAbove4G
.Base
> Bridge
->MemAbove4G
.Limit
);
147 ASSERT (Bridge
->PMemAbove4G
.Base
> Bridge
->PMemAbove4G
.Limit
);
148 if ((Bridge
->MemAbove4G
.Base
<= Bridge
->MemAbove4G
.Limit
) ||
149 (Bridge
->PMemAbove4G
.Base
<= Bridge
->PMemAbove4G
.Limit
)
156 RootBridge
= AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE_INSTANCE
));
157 ASSERT (RootBridge
!= NULL
);
159 RootBridge
->Signature
= PCI_ROOT_BRIDGE_SIGNATURE
;
160 RootBridge
->Supports
= Bridge
->Supports
;
161 RootBridge
->Attributes
= Bridge
->Attributes
;
162 RootBridge
->DmaAbove4G
= Bridge
->DmaAbove4G
;
163 RootBridge
->NoExtendedConfigSpace
= Bridge
->NoExtendedConfigSpace
;
164 RootBridge
->AllocationAttributes
= Bridge
->AllocationAttributes
;
165 RootBridge
->DevicePath
= DuplicateDevicePath (Bridge
->DevicePath
);
166 RootBridge
->DevicePathStr
= DevicePathStr
;
167 RootBridge
->ConfigBuffer
= AllocatePool (
168 TypeMax
* sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR
)
170 ASSERT (RootBridge
->ConfigBuffer
!= NULL
);
171 InitializeListHead (&RootBridge
->Maps
);
173 CopyMem (&RootBridge
->Bus
, &Bridge
->Bus
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
174 CopyMem (&RootBridge
->Io
, &Bridge
->Io
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
175 CopyMem (&RootBridge
->Mem
, &Bridge
->Mem
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
176 CopyMem (&RootBridge
->MemAbove4G
, &Bridge
->MemAbove4G
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
177 CopyMem (&RootBridge
->PMem
, &Bridge
->PMem
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
178 CopyMem (&RootBridge
->PMemAbove4G
, &Bridge
->PMemAbove4G
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
180 for (Index
= TypeIo
; Index
< TypeMax
; Index
++) {
183 Aperture
= &RootBridge
->Bus
;
186 Aperture
= &RootBridge
->Io
;
189 Aperture
= &RootBridge
->Mem
;
192 Aperture
= &RootBridge
->MemAbove4G
;
195 Aperture
= &RootBridge
->PMem
;
198 Aperture
= &RootBridge
->PMemAbove4G
;
205 RootBridge
->ResAllocNode
[Index
].Type
= Index
;
206 if (Bridge
->ResourceAssigned
&& (Aperture
->Limit
>= Aperture
->Base
)) {
207 RootBridge
->ResAllocNode
[Index
].Base
= Aperture
->Base
;
208 RootBridge
->ResAllocNode
[Index
].Length
= Aperture
->Limit
- Aperture
->Base
+ 1;
209 RootBridge
->ResAllocNode
[Index
].Status
= ResAllocated
;
211 RootBridge
->ResAllocNode
[Index
].Base
= 0;
212 RootBridge
->ResAllocNode
[Index
].Length
= 0;
213 RootBridge
->ResAllocNode
[Index
].Status
= ResNone
;
217 RootBridge
->RootBridgeIo
.SegmentNumber
= Bridge
->Segment
;
218 RootBridge
->RootBridgeIo
.PollMem
= RootBridgeIoPollMem
;
219 RootBridge
->RootBridgeIo
.PollIo
= RootBridgeIoPollIo
;
220 RootBridge
->RootBridgeIo
.Mem
.Read
= RootBridgeIoMemRead
;
221 RootBridge
->RootBridgeIo
.Mem
.Write
= RootBridgeIoMemWrite
;
222 RootBridge
->RootBridgeIo
.Io
.Read
= RootBridgeIoIoRead
;
223 RootBridge
->RootBridgeIo
.Io
.Write
= RootBridgeIoIoWrite
;
224 RootBridge
->RootBridgeIo
.CopyMem
= RootBridgeIoCopyMem
;
225 RootBridge
->RootBridgeIo
.Pci
.Read
= RootBridgeIoPciRead
;
226 RootBridge
->RootBridgeIo
.Pci
.Write
= RootBridgeIoPciWrite
;
227 RootBridge
->RootBridgeIo
.Map
= RootBridgeIoMap
;
228 RootBridge
->RootBridgeIo
.Unmap
= RootBridgeIoUnmap
;
229 RootBridge
->RootBridgeIo
.AllocateBuffer
= RootBridgeIoAllocateBuffer
;
230 RootBridge
->RootBridgeIo
.FreeBuffer
= RootBridgeIoFreeBuffer
;
231 RootBridge
->RootBridgeIo
.Flush
= RootBridgeIoFlush
;
232 RootBridge
->RootBridgeIo
.GetAttributes
= RootBridgeIoGetAttributes
;
233 RootBridge
->RootBridgeIo
.SetAttributes
= RootBridgeIoSetAttributes
;
234 RootBridge
->RootBridgeIo
.Configuration
= RootBridgeIoConfiguration
;
240 Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.
242 The I/O operations are carried out exactly as requested. The caller is
243 responsible for satisfying any alignment and I/O width restrictions that a PI
244 System on a platform might require. For example on some platforms, width
245 requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other
246 hand, will be handled by the driver.
248 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
250 @param[in] OperationType I/O operation type: IO/MMIO/PCI.
252 @param[in] Width Signifies the width of the I/O or Memory operation.
254 @param[in] Address The base address of the I/O operation.
256 @param[in] Count The number of I/O operations to perform. The number
257 of bytes moved is Width size * Count, starting at
260 @param[in] Buffer For read operations, the destination buffer to
261 store the results. For write operations, the source
262 buffer from which to write data.
264 @retval EFI_SUCCESS The parameters for this request pass the
267 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
269 @retval EFI_INVALID_PARAMETER Buffer is NULL.
271 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
273 @retval EFI_UNSUPPORTED The address range specified by Address, Width,
274 and Count is not valid for this PI system.
277 RootBridgeIoCheckParameter (
278 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
279 IN OPERATION_TYPE OperationType
,
280 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
286 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
287 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS
*PciRbAddr
;
293 // Check to see if Buffer is NULL
295 if (Buffer
== NULL
) {
296 return EFI_INVALID_PARAMETER
;
300 // Check to see if Width is in the valid range
302 if ((UINT32
) Width
>= EfiPciWidthMaximum
) {
303 return EFI_INVALID_PARAMETER
;
307 // For FIFO type, the target address won't increase during the access,
308 // so treat Count as 1
310 if (Width
>= EfiPciWidthFifoUint8
&& Width
<= EfiPciWidthFifoUint64
) {
314 Width
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
318 // Check to see if Address is aligned
320 if ((Address
& (Size
- 1)) != 0) {
321 return EFI_UNSUPPORTED
;
324 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
327 // Check to see if any address associated with this transfer exceeds the
328 // maximum allowed address. The maximum address implied by the parameters
329 // passed in is Address + Size * Count. If the following condition is met,
330 // then the transfer is not supported.
332 // Address + Size * Count > Limit + 1
334 // Since Limit can be the maximum integer value supported by the CPU and
335 // Count can also be the maximum integer value supported by the CPU, this
336 // range check must be adjusted to avoid all oveflow conditions.
338 if (OperationType
== IoOperation
) {
340 // Allow Legacy IO access
342 if (Address
+ MultU64x32 (Count
, Size
) <= 0x1000) {
343 if ((RootBridge
->Attributes
& (
344 EFI_PCI_ATTRIBUTE_ISA_IO
| EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO
| EFI_PCI_ATTRIBUTE_VGA_IO
|
345 EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO
| EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO
|
346 EFI_PCI_ATTRIBUTE_ISA_IO_16
| EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16
| EFI_PCI_ATTRIBUTE_VGA_IO_16
)) != 0) {
350 Base
= RootBridge
->Io
.Base
;
351 Limit
= RootBridge
->Io
.Limit
;
352 } else if (OperationType
== MemOperation
) {
354 // Allow Legacy MMIO access
356 if ((Address
>= 0xA0000) && (Address
+ MultU64x32 (Count
, Size
)) <= 0xC0000) {
357 if ((RootBridge
->Attributes
& EFI_PCI_ATTRIBUTE_VGA_MEMORY
) != 0) {
362 // By comparing the Address against Limit we know which range to be used
365 if (Address
+ MultU64x32 (Count
, Size
) <= RootBridge
->Mem
.Limit
+ 1) {
366 Base
= RootBridge
->Mem
.Base
;
367 Limit
= RootBridge
->Mem
.Limit
;
369 Base
= RootBridge
->MemAbove4G
.Base
;
370 Limit
= RootBridge
->MemAbove4G
.Limit
;
373 PciRbAddr
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS
*) &Address
;
374 if (PciRbAddr
->Bus
< RootBridge
->Bus
.Base
||
375 PciRbAddr
->Bus
> RootBridge
->Bus
.Limit
) {
376 return EFI_INVALID_PARAMETER
;
379 if (PciRbAddr
->Device
> PCI_MAX_DEVICE
||
380 PciRbAddr
->Function
> PCI_MAX_FUNC
) {
381 return EFI_INVALID_PARAMETER
;
384 if (PciRbAddr
->ExtendedRegister
!= 0) {
385 Address
= PciRbAddr
->ExtendedRegister
;
387 Address
= PciRbAddr
->Register
;
390 Limit
= RootBridge
->NoExtendedConfigSpace
? 0xFF : 0xFFF;
393 if (Address
< Base
) {
394 return EFI_INVALID_PARAMETER
;
397 if (Address
+ MultU64x32 (Count
, Size
) > Limit
+ 1) {
398 return EFI_INVALID_PARAMETER
;
405 Polls an address in memory mapped I/O space until an exit condition is met,
408 This function provides a standard way to poll a PCI memory location. A PCI
409 memory read operation is performed at the PCI memory address specified by
410 Address for the width specified by Width. The result of this PCI memory read
411 operation is stored in Result. This PCI memory read operation is repeated
412 until either a timeout of Delay 100 ns units has expired, or (Result & Mask)
415 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
416 @param[in] Width Signifies the width of the memory operations.
417 @param[in] Address The base address of the memory operations. The caller
418 is responsible for aligning Address if required.
419 @param[in] Mask Mask used for the polling criteria. Bytes above Width
420 in Mask are ignored. The bits in the bytes below Width
421 which are zero in Mask are ignored when polling the
423 @param[in] Value The comparison value used for the polling exit
425 @param[in] Delay The number of 100 ns units to poll. Note that timer
426 available may be of poorer granularity.
427 @param[out] Result Pointer to the last value read from the memory
430 @retval EFI_SUCCESS The last data returned from the access matched
431 the poll exit criteria.
432 @retval EFI_INVALID_PARAMETER Width is invalid.
433 @retval EFI_INVALID_PARAMETER Result is NULL.
434 @retval EFI_TIMEOUT Delay expired before a match occurred.
435 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
440 RootBridgeIoPollMem (
441 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
442 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
451 UINT64 NumberOfTicks
;
454 if (Result
== NULL
) {
455 return EFI_INVALID_PARAMETER
;
458 if ((UINT32
)Width
> EfiPciWidthUint64
) {
459 return EFI_INVALID_PARAMETER
;
463 // No matter what, always do a single poll.
465 Status
= This
->Mem
.Read (This
, Width
, Address
, 1, Result
);
466 if (EFI_ERROR (Status
)) {
470 if ((*Result
& Mask
) == Value
) {
480 // Determine the proper # of metronome ticks to wait for polling the
481 // location. The nuber of ticks is Roundup (Delay /
482 // mMetronome->TickPeriod)+1
483 // The "+1" to account for the possibility of the first tick being short
484 // because we started in the middle of a tick.
486 // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome
487 // protocol definition is updated.
489 NumberOfTicks
= DivU64x32Remainder (Delay
, (UINT32
) mMetronome
->TickPeriod
,
491 if (Remainder
!= 0) {
496 while (NumberOfTicks
!= 0) {
498 mMetronome
->WaitForTick (mMetronome
, 1);
500 Status
= This
->Mem
.Read (This
, Width
, Address
, 1, Result
);
501 if (EFI_ERROR (Status
)) {
505 if ((*Result
& Mask
) == Value
) {
516 Reads from the I/O space of a PCI Root Bridge. Returns when either the
517 polling exit criteria is satisfied or after a defined duration.
519 This function provides a standard way to poll a PCI I/O location. A PCI I/O
520 read operation is performed at the PCI I/O address specified by Address for
521 the width specified by Width.
522 The result of this PCI I/O read operation is stored in Result. This PCI I/O
523 read operation is repeated until either a timeout of Delay 100 ns units has
524 expired, or (Result & Mask) is equal to Value.
526 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
527 @param[in] Width Signifies the width of the I/O operations.
528 @param[in] Address The base address of the I/O operations. The caller is
529 responsible for aligning Address if required.
530 @param[in] Mask Mask used for the polling criteria. Bytes above Width in
531 Mask are ignored. The bits in the bytes below Width
532 which are zero in Mask are ignored when polling the I/O
534 @param[in] Value The comparison value used for the polling exit criteria.
535 @param[in] Delay The number of 100 ns units to poll. Note that timer
536 available may be of poorer granularity.
537 @param[out] Result Pointer to the last value read from the memory location.
539 @retval EFI_SUCCESS The last data returned from the access matched
540 the poll exit criteria.
541 @retval EFI_INVALID_PARAMETER Width is invalid.
542 @retval EFI_INVALID_PARAMETER Result is NULL.
543 @retval EFI_TIMEOUT Delay expired before a match occurred.
544 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
550 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
551 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
560 UINT64 NumberOfTicks
;
564 // No matter what, always do a single poll.
567 if (Result
== NULL
) {
568 return EFI_INVALID_PARAMETER
;
571 if ((UINT32
)Width
> EfiPciWidthUint64
) {
572 return EFI_INVALID_PARAMETER
;
575 Status
= This
->Io
.Read (This
, Width
, Address
, 1, Result
);
576 if (EFI_ERROR (Status
)) {
579 if ((*Result
& Mask
) == Value
) {
589 // Determine the proper # of metronome ticks to wait for polling the
590 // location. The number of ticks is Roundup (Delay /
591 // mMetronome->TickPeriod)+1
592 // The "+1" to account for the possibility of the first tick being short
593 // because we started in the middle of a tick.
595 NumberOfTicks
= DivU64x32Remainder (Delay
, (UINT32
)mMetronome
->TickPeriod
,
597 if (Remainder
!= 0) {
602 while (NumberOfTicks
!= 0) {
604 mMetronome
->WaitForTick (mMetronome
, 1);
606 Status
= This
->Io
.Read (This
, Width
, Address
, 1, Result
);
607 if (EFI_ERROR (Status
)) {
611 if ((*Result
& Mask
) == Value
) {
622 Enables a PCI driver to access PCI controller registers in the PCI root
625 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI
626 controller registers in the PCI root bridge memory space.
627 The memory operations are carried out exactly as requested. The caller is
628 responsible for satisfying any alignment and memory width restrictions that a
629 PCI Root Bridge on a platform might require.
631 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
632 @param[in] Width Signifies the width of the memory operation.
633 @param[in] Address The base address of the memory operation. The caller
634 is responsible for aligning the Address if required.
635 @param[in] Count The number of memory operations to perform. Bytes
636 moved is Width size * Count, starting at Address.
637 @param[out] Buffer For read operations, the destination buffer to store
638 the results. For write operations, the source buffer
641 @retval EFI_SUCCESS The data was read from or written to the PCI
643 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
644 @retval EFI_INVALID_PARAMETER Buffer is NULL.
645 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
650 RootBridgeIoMemRead (
651 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
652 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
660 Status
= RootBridgeIoCheckParameter (This
, MemOperation
, Width
, Address
,
662 if (EFI_ERROR (Status
)) {
665 return mCpuIo
->Mem
.Read (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
, Address
, Count
, Buffer
);
669 Enables a PCI driver to access PCI controller registers in the PCI root
672 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI
673 controller registers in the PCI root bridge memory space.
674 The memory operations are carried out exactly as requested. The caller is
675 responsible for satisfying any alignment and memory width restrictions that a
676 PCI Root Bridge on a platform might require.
678 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
679 @param[in] Width Signifies the width of the memory operation.
680 @param[in] Address The base address of the memory operation. The caller
681 is responsible for aligning the Address if required.
682 @param[in] Count The number of memory operations to perform. Bytes
683 moved is Width size * Count, starting at Address.
684 @param[in] Buffer For read operations, the destination buffer to store
685 the results. For write operations, the source buffer
688 @retval EFI_SUCCESS The data was read from or written to the PCI
690 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
691 @retval EFI_INVALID_PARAMETER Buffer is NULL.
692 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
697 RootBridgeIoMemWrite (
698 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
699 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
707 Status
= RootBridgeIoCheckParameter (This
, MemOperation
, Width
, Address
,
709 if (EFI_ERROR (Status
)) {
712 return mCpuIo
->Mem
.Write (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
, Address
, Count
, Buffer
);
716 Enables a PCI driver to access PCI controller registers in the PCI root
719 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
720 @param[in] Width Signifies the width of the memory operations.
721 @param[in] Address The base address of the I/O operation. The caller is
722 responsible for aligning the Address if required.
723 @param[in] Count The number of I/O operations to perform. Bytes moved
724 is Width size * Count, starting at Address.
725 @param[out] Buffer For read operations, the destination buffer to store
726 the results. For write operations, the source buffer
729 @retval EFI_SUCCESS The data was read from or written to the PCI
731 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
732 @retval EFI_INVALID_PARAMETER Buffer is NULL.
733 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
739 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
740 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
747 Status
= RootBridgeIoCheckParameter (
748 This
, IoOperation
, Width
,
749 Address
, Count
, Buffer
751 if (EFI_ERROR (Status
)) {
754 return mCpuIo
->Io
.Read (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
, Address
, Count
, Buffer
);
758 Enables a PCI driver to access PCI controller registers in the PCI root
761 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
762 @param[in] Width Signifies the width of the memory operations.
763 @param[in] Address The base address of the I/O operation. The caller is
764 responsible for aligning the Address if required.
765 @param[in] Count The number of I/O operations to perform. Bytes moved
766 is Width size * Count, starting at Address.
767 @param[in] Buffer For read operations, the destination buffer to store
768 the results. For write operations, the source buffer
771 @retval EFI_SUCCESS The data was read from or written to the PCI
773 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
774 @retval EFI_INVALID_PARAMETER Buffer is NULL.
775 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
780 RootBridgeIoIoWrite (
781 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
782 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
789 Status
= RootBridgeIoCheckParameter (
790 This
, IoOperation
, Width
,
791 Address
, Count
, Buffer
793 if (EFI_ERROR (Status
)) {
796 return mCpuIo
->Io
.Write (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
, Address
, Count
, Buffer
);
800 Enables a PCI driver to copy one region of PCI root bridge memory space to
801 another region of PCI root bridge memory space.
803 The CopyMem() function enables a PCI driver to copy one region of PCI root
804 bridge memory space to another region of PCI root bridge memory space. This
805 is especially useful for video scroll operation on a memory mapped video
807 The memory operations are carried out exactly as requested. The caller is
808 responsible for satisfying any alignment and memory width restrictions that a
809 PCI root bridge on a platform might require.
811 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
813 @param[in] Width Signifies the width of the memory operations.
814 @param[in] DestAddress The destination address of the memory operation. The
815 caller is responsible for aligning the DestAddress if
817 @param[in] SrcAddress The source address of the memory operation. The caller
818 is responsible for aligning the SrcAddress if
820 @param[in] Count The number of memory operations to perform. Bytes
821 moved is Width size * Count, starting at DestAddress
824 @retval EFI_SUCCESS The data was copied from one memory region
825 to another memory region.
826 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
827 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
832 RootBridgeIoCopyMem (
833 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
834 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
835 IN UINT64 DestAddress
,
836 IN UINT64 SrcAddress
,
846 if ((UINT32
) Width
> EfiPciWidthUint64
) {
847 return EFI_INVALID_PARAMETER
;
850 if (DestAddress
== SrcAddress
) {
854 Stride
= (UINTN
) (1 << Width
);
857 if ((DestAddress
> SrcAddress
) &&
858 (DestAddress
< (SrcAddress
+ Count
* Stride
))) {
860 SrcAddress
= SrcAddress
+ (Count
- 1) * Stride
;
861 DestAddress
= DestAddress
+ (Count
- 1) * Stride
;
864 for (Index
= 0; Index
< Count
; Index
++) {
865 Status
= RootBridgeIoMemRead (
872 if (EFI_ERROR (Status
)) {
875 Status
= RootBridgeIoMemWrite (
882 if (EFI_ERROR (Status
)) {
886 SrcAddress
+= Stride
;
887 DestAddress
+= Stride
;
889 SrcAddress
-= Stride
;
890 DestAddress
-= Stride
;
898 PCI configuration space access.
900 @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
901 @param Read TRUE indicating it's a read operation.
902 @param Width Signifies the width of the memory operation.
903 @param Address The address within the PCI configuration space
904 for the PCI controller.
905 @param Count The number of PCI configuration operations
907 @param Buffer The destination buffer to store the results.
909 @retval EFI_SUCCESS The data was read/written from/to the PCI root bridge.
910 @retval EFI_INVALID_PARAMETER Invalid parameters found.
914 RootBridgeIoPciAccess (
915 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
917 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
924 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
925 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress
;
931 Status
= RootBridgeIoCheckParameter (This
, PciOperation
, Width
, Address
, Count
, Buffer
);
932 if (EFI_ERROR (Status
)) {
937 // Read Pci configuration space
939 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
940 CopyMem (&PciAddress
, &Address
, sizeof (PciAddress
));
942 if (PciAddress
.ExtendedRegister
== 0) {
943 PciAddress
.ExtendedRegister
= PciAddress
.Register
;
946 Address
= PCI_SEGMENT_LIB_ADDRESS (
947 RootBridge
->RootBridgeIo
.SegmentNumber
,
951 PciAddress
.ExtendedRegister
955 // Select loop based on the width of the transfer
957 InStride
= mInStride
[Width
];
958 OutStride
= mOutStride
[Width
];
959 Size
= (UINTN
) (1 << (Width
& 0x03));
960 for (Uint8Buffer
= Buffer
; Count
> 0; Address
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
962 PciSegmentReadBuffer (Address
, Size
, Uint8Buffer
);
964 PciSegmentWriteBuffer (Address
, Size
, Uint8Buffer
);
971 Allows read from PCI configuration space.
973 @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
974 @param Width Signifies the width of the memory operation.
975 @param Address The address within the PCI configuration space
976 for the PCI controller.
977 @param Count The number of PCI configuration operations
979 @param Buffer The destination buffer to store the results.
981 @retval EFI_SUCCESS The data was read from the PCI root bridge.
982 @retval EFI_INVALID_PARAMETER Invalid parameters found.
986 RootBridgeIoPciRead (
987 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
988 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
994 return RootBridgeIoPciAccess (This
, TRUE
, Width
, Address
, Count
, Buffer
);
998 Allows write to PCI configuration space.
1000 @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1001 @param Width Signifies the width of the memory operation.
1002 @param Address The address within the PCI configuration space
1003 for the PCI controller.
1004 @param Count The number of PCI configuration operations
1006 @param Buffer The source buffer to get the results.
1008 @retval EFI_SUCCESS The data was written to the PCI root bridge.
1009 @retval EFI_INVALID_PARAMETER Invalid parameters found.
1013 RootBridgeIoPciWrite (
1014 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1015 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1021 return RootBridgeIoPciAccess (This
, FALSE
, Width
, Address
, Count
, Buffer
);
1025 Provides the PCI controller-specific address needed to access
1026 system memory for DMA.
1028 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1029 @param Operation Indicate if the bus master is going to read or write
1031 @param HostAddress The system memory address to map on the PCI controller.
1032 @param NumberOfBytes On input the number of bytes to map.
1033 On output the number of bytes that were mapped.
1034 @param DeviceAddress The resulting map address for the bus master PCI
1035 controller to use to access the system memory's HostAddress.
1036 @param Mapping The value to pass to Unmap() when the bus master DMA
1037 operation is complete.
1039 @retval EFI_SUCCESS Success.
1040 @retval EFI_INVALID_PARAMETER Invalid parameters found.
1041 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
1042 @retval EFI_DEVICE_ERROR The System hardware could not map the requested address.
1043 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to lack of resources.
1048 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1049 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation
,
1050 IN VOID
*HostAddress
,
1051 IN OUT UINTN
*NumberOfBytes
,
1052 OUT EFI_PHYSICAL_ADDRESS
*DeviceAddress
,
1057 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1058 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
1061 if (HostAddress
== NULL
|| NumberOfBytes
== NULL
|| DeviceAddress
== NULL
||
1063 return EFI_INVALID_PARAMETER
;
1067 // Make sure that Operation is valid
1069 if ((UINT32
) Operation
>= EfiPciOperationMaximum
) {
1070 return EFI_INVALID_PARAMETER
;
1073 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1075 PhysicalAddress
= (EFI_PHYSICAL_ADDRESS
) (UINTN
) HostAddress
;
1076 if (!RootBridge
->DmaAbove4G
&& ((PhysicalAddress
+ *NumberOfBytes
) > SIZE_4GB
)) {
1078 // If the root bridge can not handle performing DMA above 4GB but
1079 // any part of the DMA transfer being mapped is above 4GB, then
1080 // map the DMA transfer to a buffer below 4GB.
1083 if (Operation
== EfiPciOperationBusMasterCommonBuffer
||
1084 Operation
== EfiPciOperationBusMasterCommonBuffer64
) {
1086 // Common Buffer operations can not be remapped. If the common buffer
1087 // if above 4GB, then it is not possible to generate a mapping, so return
1090 return EFI_UNSUPPORTED
;
1094 // Allocate a MAP_INFO structure to remember the mapping when Unmap() is
1097 MapInfo
= AllocatePool (sizeof (MAP_INFO
));
1098 if (MapInfo
== NULL
) {
1100 return EFI_OUT_OF_RESOURCES
;
1104 // Initialize the MAP_INFO structure
1106 MapInfo
->Signature
= MAP_INFO_SIGNATURE
;
1107 MapInfo
->Operation
= Operation
;
1108 MapInfo
->NumberOfBytes
= *NumberOfBytes
;
1109 MapInfo
->NumberOfPages
= EFI_SIZE_TO_PAGES (MapInfo
->NumberOfBytes
);
1110 MapInfo
->HostAddress
= PhysicalAddress
;
1111 MapInfo
->MappedHostAddress
= SIZE_4GB
- 1;
1114 // Allocate a buffer below 4GB to map the transfer to.
1116 Status
= gBS
->AllocatePages (
1118 EfiBootServicesData
,
1119 MapInfo
->NumberOfPages
,
1120 &MapInfo
->MappedHostAddress
1122 if (EFI_ERROR (Status
)) {
1129 // If this is a read operation from the Bus Master's point of view,
1130 // then copy the contents of the real buffer into the mapped buffer
1131 // so the Bus Master can read the contents of the real buffer.
1133 if (Operation
== EfiPciOperationBusMasterRead
||
1134 Operation
== EfiPciOperationBusMasterRead64
) {
1136 (VOID
*) (UINTN
) MapInfo
->MappedHostAddress
,
1137 (VOID
*) (UINTN
) MapInfo
->HostAddress
,
1138 MapInfo
->NumberOfBytes
1142 InsertTailList (&RootBridge
->Maps
, &MapInfo
->Link
);
1145 // The DeviceAddress is the address of the maped buffer below 4GB
1147 *DeviceAddress
= MapInfo
->MappedHostAddress
;
1149 // Return a pointer to the MAP_INFO structure in Mapping
1154 // If the root bridge CAN handle performing DMA above 4GB or
1155 // the transfer is below 4GB, so the DeviceAddress is simply the
1158 *DeviceAddress
= PhysicalAddress
;
1159 *Mapping
= NO_MAPPING
;
1166 Completes the Map() operation and releases any corresponding resources.
1168 The Unmap() function completes the Map() operation and releases any
1169 corresponding resources.
1170 If the operation was an EfiPciOperationBusMasterWrite or
1171 EfiPciOperationBusMasterWrite64, the data is committed to the target system
1173 Any resources used for the mapping are freed.
1175 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1176 @param[in] Mapping The mapping value returned from Map().
1178 @retval EFI_SUCCESS The range was unmapped.
1179 @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
1180 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
1185 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1191 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1193 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1195 // See if the Map() operation associated with this Unmap() required a mapping
1196 // buffer. If a mapping buffer was not required, then this function simply
1197 // returns EFI_SUCCESS.
1199 if (Mapping
== NO_MAPPING
) {
1203 MapInfo
= NO_MAPPING
;
1204 for (Link
= GetFirstNode (&RootBridge
->Maps
)
1205 ; !IsNull (&RootBridge
->Maps
, Link
)
1206 ; Link
= GetNextNode (&RootBridge
->Maps
, Link
)
1208 MapInfo
= MAP_INFO_FROM_LINK (Link
);
1209 if (MapInfo
== Mapping
) {
1214 // Mapping is not a valid value returned by Map()
1216 if (MapInfo
!= Mapping
) {
1217 return EFI_INVALID_PARAMETER
;
1219 RemoveEntryList (&MapInfo
->Link
);
1222 // If this is a write operation from the Bus Master's point of view,
1223 // then copy the contents of the mapped buffer into the real buffer
1224 // so the processor can read the contents of the real buffer.
1226 if (MapInfo
->Operation
== EfiPciOperationBusMasterWrite
||
1227 MapInfo
->Operation
== EfiPciOperationBusMasterWrite64
) {
1229 (VOID
*) (UINTN
) MapInfo
->HostAddress
,
1230 (VOID
*) (UINTN
) MapInfo
->MappedHostAddress
,
1231 MapInfo
->NumberOfBytes
1236 // Free the mapped buffer and the MAP_INFO structure.
1238 gBS
->FreePages (MapInfo
->MappedHostAddress
, MapInfo
->NumberOfPages
);
1244 Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer
1245 or EfiPciOperationBusMasterCommonBuffer64 mapping.
1247 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1248 @param Type This parameter is not used and must be ignored.
1249 @param MemoryType The type of memory to allocate, EfiBootServicesData or
1250 EfiRuntimeServicesData.
1251 @param Pages The number of pages to allocate.
1252 @param HostAddress A pointer to store the base system memory address of the
1254 @param Attributes The requested bit mask of attributes for the allocated
1255 range. Only the attributes
1256 EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE,
1257 EFI_PCI_ATTRIBUTE_MEMORY_CACHED, and
1258 EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this
1261 @retval EFI_SUCCESS The requested memory pages were allocated.
1262 @retval EFI_INVALID_PARAMETER MemoryType is invalid.
1263 @retval EFI_INVALID_PARAMETER HostAddress is NULL.
1264 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal
1265 attribute bits are MEMORY_WRITE_COMBINE,
1266 MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
1267 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
1271 RootBridgeIoAllocateBuffer (
1272 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1273 IN EFI_ALLOCATE_TYPE Type
,
1274 IN EFI_MEMORY_TYPE MemoryType
,
1276 OUT VOID
**HostAddress
,
1277 IN UINT64 Attributes
1281 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
1282 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1283 EFI_ALLOCATE_TYPE AllocateType
;
1286 // Validate Attributes
1288 if ((Attributes
& EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER
) != 0) {
1289 return EFI_UNSUPPORTED
;
1293 // Check for invalid inputs
1295 if (HostAddress
== NULL
) {
1296 return EFI_INVALID_PARAMETER
;
1300 // The only valid memory types are EfiBootServicesData and
1301 // EfiRuntimeServicesData
1303 if (MemoryType
!= EfiBootServicesData
&&
1304 MemoryType
!= EfiRuntimeServicesData
) {
1305 return EFI_INVALID_PARAMETER
;
1308 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1310 AllocateType
= AllocateAnyPages
;
1311 if (!RootBridge
->DmaAbove4G
) {
1313 // Limit allocations to memory below 4GB
1315 AllocateType
= AllocateMaxAddress
;
1316 PhysicalAddress
= (EFI_PHYSICAL_ADDRESS
) (SIZE_4GB
- 1);
1318 Status
= gBS
->AllocatePages (
1324 if (!EFI_ERROR (Status
)) {
1325 *HostAddress
= (VOID
*) (UINTN
) PhysicalAddress
;
1332 Frees memory that was allocated with AllocateBuffer().
1334 The FreeBuffer() function frees memory that was allocated with
1337 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1338 @param Pages The number of pages to free.
1339 @param HostAddress The base system memory address of the allocated range.
1341 @retval EFI_SUCCESS The requested memory pages were freed.
1342 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and
1343 Pages was not allocated with AllocateBuffer().
1347 RootBridgeIoFreeBuffer (
1348 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1350 OUT VOID
*HostAddress
1353 return gBS
->FreePages ((EFI_PHYSICAL_ADDRESS
) (UINTN
) HostAddress
, Pages
);
1357 Flushes all PCI posted write transactions from a PCI host bridge to system
1360 The Flush() function flushes any PCI posted write transactions from a PCI
1361 host bridge to system memory. Posted write transactions are generated by PCI
1362 bus masters when they perform write transactions to target addresses in
1364 This function does not flush posted write transactions from any PCI bridges.
1365 A PCI controller specific action must be taken to guarantee that the posted
1366 write transactions have been flushed from the PCI controller and from all the
1367 PCI bridges into the PCI host bridge. This is typically done with a PCI read
1368 transaction from the PCI controller prior to calling Flush().
1370 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1372 @retval EFI_SUCCESS The PCI posted write transactions were flushed
1373 from the PCI host bridge to system memory.
1374 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed
1375 from the PCI host bridge due to a hardware error.
1380 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
1387 Gets the attributes that a PCI root bridge supports setting with
1388 SetAttributes(), and the attributes that a PCI root bridge is currently
1391 The GetAttributes() function returns the mask of attributes that this PCI
1392 root bridge supports and the mask of attributes that the PCI root bridge is
1395 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1396 @param Supported A pointer to the mask of attributes that this PCI root
1397 bridge supports setting with SetAttributes().
1398 @param Attributes A pointer to the mask of attributes that this PCI root
1399 bridge is currently using.
1401 @retval EFI_SUCCESS If Supports is not NULL, then the attributes
1402 that the PCI root bridge supports is returned
1403 in Supports. If Attributes is not NULL, then
1404 the attributes that the PCI root bridge is
1405 currently using is returned in Attributes.
1406 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
1410 RootBridgeIoGetAttributes (
1411 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1412 OUT UINT64
*Supported
,
1413 OUT UINT64
*Attributes
1416 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1418 if (Attributes
== NULL
&& Supported
== NULL
) {
1419 return EFI_INVALID_PARAMETER
;
1422 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1424 // Set the return value for Supported and Attributes
1426 if (Supported
!= NULL
) {
1427 *Supported
= RootBridge
->Supports
;
1430 if (Attributes
!= NULL
) {
1431 *Attributes
= RootBridge
->Attributes
;
1438 Sets attributes for a resource range on a PCI root bridge.
1440 The SetAttributes() function sets the attributes specified in Attributes for
1441 the PCI root bridge on the resource range specified by ResourceBase and
1442 ResourceLength. Since the granularity of setting these attributes may vary
1443 from resource type to resource type, and from platform to platform, the
1444 actual resource range and the one passed in by the caller may differ. As a
1445 result, this function may set the attributes specified by Attributes on a
1446 larger resource range than the caller requested. The actual range is returned
1447 in ResourceBase and ResourceLength. The caller is responsible for verifying
1448 that the actual range for which the attributes were set is acceptable.
1450 @param This A pointer to the
1451 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1452 @param Attributes The mask of attributes to set. If the
1453 attribute bit MEMORY_WRITE_COMBINE,
1454 MEMORY_CACHED, or MEMORY_DISABLE is set,
1455 then the resource range is specified by
1456 ResourceBase and ResourceLength. If
1457 MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
1458 MEMORY_DISABLE are not set, then
1459 ResourceBase and ResourceLength are ignored,
1461 @param ResourceBase A pointer to the base address of the
1462 resource range to be modified by the
1463 attributes specified by Attributes.
1464 @param ResourceLength A pointer to the length of the resource
1465 range to be modified by the attributes
1466 specified by Attributes.
1468 @retval EFI_SUCCESS The current configuration of this PCI root bridge
1469 was returned in Resources.
1470 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge
1471 could not be retrieved.
1475 RootBridgeIoSetAttributes (
1476 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1477 IN UINT64 Attributes
,
1478 IN OUT UINT64
*ResourceBase
,
1479 IN OUT UINT64
*ResourceLength
1482 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1484 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1486 if ((Attributes
& (~RootBridge
->Supports
)) != 0) {
1487 return EFI_UNSUPPORTED
;
1490 RootBridge
->Attributes
= Attributes
;
1495 Retrieves the current resource settings of this PCI root bridge in the form
1496 of a set of ACPI 2.0 resource descriptors.
1498 There are only two resource descriptor types from the ACPI Specification that
1499 may be used to describe the current resources allocated to a PCI root bridge.
1500 These are the QWORD Address Space Descriptor (ACPI 2.0 Section 6.4.3.5.1),
1501 and the End Tag (ACPI 2.0 Section 6.4.2.8). The QWORD Address Space
1502 Descriptor can describe memory, I/O, and bus number ranges for dynamic or
1503 fixed resources. The configuration of a PCI root bridge is described with one
1504 or more QWORD Address Space Descriptors followed by an End Tag.
1506 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1507 @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that
1508 describe the current configuration of this PCI root
1509 bridge. The storage for the ACPI 2.0 resource
1510 descriptors is allocated by this function. The
1511 caller must treat the return buffer as read-only
1512 data, and the buffer must not be freed by the
1515 @retval EFI_SUCCESS The current configuration of this PCI root bridge
1516 was returned in Resources.
1517 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge
1518 could not be retrieved.
1522 RootBridgeIoConfiguration (
1523 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1524 OUT VOID
**Resources
1527 PCI_RESOURCE_TYPE Index
;
1528 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1529 PCI_RES_NODE
*ResAllocNode
;
1530 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptor
;
1531 EFI_ACPI_END_TAG_DESCRIPTOR
*End
;
1534 // Get this instance of the Root Bridge.
1536 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1538 RootBridge
->ConfigBuffer
,
1539 TypeMax
* sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR
)
1541 Descriptor
= RootBridge
->ConfigBuffer
;
1542 for (Index
= TypeIo
; Index
< TypeMax
; Index
++) {
1544 ResAllocNode
= &RootBridge
->ResAllocNode
[Index
];
1546 if (ResAllocNode
->Status
!= ResAllocated
) {
1550 Descriptor
->Desc
= ACPI_ADDRESS_SPACE_DESCRIPTOR
;
1551 Descriptor
->Len
= sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) - 3;
1552 Descriptor
->AddrRangeMin
= ResAllocNode
->Base
;
1553 Descriptor
->AddrRangeMax
= ResAllocNode
->Base
+ ResAllocNode
->Length
- 1;
1554 Descriptor
->AddrLen
= ResAllocNode
->Length
;
1555 switch (ResAllocNode
->Type
) {
1558 Descriptor
->ResType
= ACPI_ADDRESS_SPACE_TYPE_IO
;
1562 Descriptor
->SpecificFlag
= EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
;
1564 Descriptor
->ResType
= ACPI_ADDRESS_SPACE_TYPE_MEM
;
1565 Descriptor
->AddrSpaceGranularity
= 32;
1569 Descriptor
->SpecificFlag
= EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
;
1571 Descriptor
->ResType
= ACPI_ADDRESS_SPACE_TYPE_MEM
;
1572 Descriptor
->AddrSpaceGranularity
= 64;
1576 Descriptor
->ResType
= ACPI_ADDRESS_SPACE_TYPE_BUS
;
1586 // Terminate the entries.
1588 End
= (EFI_ACPI_END_TAG_DESCRIPTOR
*) Descriptor
;
1589 End
->Desc
= ACPI_END_TAG_DESCRIPTOR
;
1590 End
->Checksum
= 0x0;
1592 *Resources
= RootBridge
->ConfigBuffer
;