MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c

   1 /** @file
   2
   3   PCI Root Bridge Io Protocol code.
   4
   5 Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #include "PciHostBridge.h"
  11 #include "PciRootBridge.h"
  12 #include "PciHostResource.h"
  13
  14 #define NO_MAPPING  (VOID *) (UINTN) -1
  15
  16 #define RESOURCE_VALID(Resource)  ((Resource)->Base <= (Resource)->Limit)
  17
  18 //
  19 // Lookup table for increment values based on transfer widths
  20 //
  21 UINT8  mInStride[] = {
  22   1, // EfiPciWidthUint8
  23   2, // EfiPciWidthUint16
  24   4, // EfiPciWidthUint32
  25   8, // EfiPciWidthUint64
  26   0, // EfiPciWidthFifoUint8
  27   0, // EfiPciWidthFifoUint16
  28   0, // EfiPciWidthFifoUint32
  29   0, // EfiPciWidthFifoUint64
  30   1, // EfiPciWidthFillUint8
  31   2, // EfiPciWidthFillUint16
  32   4, // EfiPciWidthFillUint32
  33   8  // EfiPciWidthFillUint64
  34 };
  35
  36 //
  37 // Lookup table for increment values based on transfer widths
  38 //
  39 UINT8  mOutStride[] = {
  40   1, // EfiPciWidthUint8
  41   2, // EfiPciWidthUint16
  42   4, // EfiPciWidthUint32
  43   8, // EfiPciWidthUint64
  44   1, // EfiPciWidthFifoUint8
  45   2, // EfiPciWidthFifoUint16
  46   4, // EfiPciWidthFifoUint32
  47   8, // EfiPciWidthFifoUint64
  48   0, // EfiPciWidthFillUint8
  49   0, // EfiPciWidthFillUint16
  50   0, // EfiPciWidthFillUint32
  51   0  // EfiPciWidthFillUint64
  52 };
  53
  54 /**
  55   Construct the Pci Root Bridge instance.
  56
  57   @param Bridge            The root bridge instance.
  58
  59   @return The pointer to PCI_ROOT_BRIDGE_INSTANCE just created
  60           or NULL if creation fails.
  61 **/
  62 PCI_ROOT_BRIDGE_INSTANCE *
  63 CreateRootBridge (
  64   IN PCI_ROOT_BRIDGE  *Bridge
  65   )
  66 {
  67   PCI_ROOT_BRIDGE_INSTANCE  *RootBridge;
  68   PCI_RESOURCE_TYPE         Index;
  69   CHAR16                    *DevicePathStr;
  70   PCI_ROOT_BRIDGE_APERTURE  *Aperture;
  71
  72   DevicePathStr = NULL;
  73
  74   DEBUG ((DEBUG_INFO, "RootBridge: "));
  75   DEBUG ((DEBUG_INFO, "%s\n", DevicePathStr = ConvertDevicePathToText (Bridge->DevicePath, FALSE, FALSE)));
  76   DEBUG ((DEBUG_INFO, "  Support/Attr: %lx / %lx\n", Bridge->Supports, Bridge->Attributes));
  77   DEBUG ((DEBUG_INFO, "    DmaAbove4G: %s\n", Bridge->DmaAbove4G ? L"Yes" : L"No"));
  78   DEBUG ((DEBUG_INFO, "NoExtConfSpace: %s\n", Bridge->NoExtendedConfigSpace ? L"Yes" : L"No"));
  79   DEBUG ((
  80     DEBUG_INFO,
  81     "     AllocAttr: %lx (%s%s)\n",
  82     Bridge->AllocationAttributes,
  83     (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0 ? L"CombineMemPMem " : L"",
  84     (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0 ? L"Mem64Decode" : L""
  85     ));
  86   DEBUG ((
  87     DEBUG_INFO,
  88     "           Bus: %lx - %lx Translation=%lx\n",
  89     Bridge->Bus.Base,
  90     Bridge->Bus.Limit,
  91     Bridge->Bus.Translation
  92     ));
  93   //
  94   // Translation for bus is not supported.
  95   //
  96   ASSERT (Bridge->Bus.Translation == 0);
  97   if (Bridge->Bus.Translation != 0) {
  98     return NULL;
  99   }
 100
 101   DEBUG ((
 102     DEBUG_INFO,
 103     "            Io: %lx - %lx Translation=%lx\n",
 104     Bridge->Io.Base,
 105     Bridge->Io.Limit,
 106     Bridge->Io.Translation
 107     ));
 108   DEBUG ((
 109     DEBUG_INFO,
 110     "           Mem: %lx - %lx Translation=%lx\n",
 111     Bridge->Mem.Base,
 112     Bridge->Mem.Limit,
 113     Bridge->Mem.Translation
 114     ));
 115   DEBUG ((
 116     DEBUG_INFO,
 117     "    MemAbove4G: %lx - %lx Translation=%lx\n",
 118     Bridge->MemAbove4G.Base,
 119     Bridge->MemAbove4G.Limit,
 120     Bridge->MemAbove4G.Translation
 121     ));
 122   DEBUG ((
 123     DEBUG_INFO,
 124     "          PMem: %lx - %lx Translation=%lx\n",
 125     Bridge->PMem.Base,
 126     Bridge->PMem.Limit,
 127     Bridge->PMem.Translation
 128     ));
 129   DEBUG ((
 130     DEBUG_INFO,
 131     "   PMemAbove4G: %lx - %lx Translation=%lx\n",
 132     Bridge->PMemAbove4G.Base,
 133     Bridge->PMemAbove4G.Limit,
 134     Bridge->PMemAbove4G.Translation
 135     ));
 136
 137   //
 138   // Make sure Mem and MemAbove4G apertures are valid
 139   //
 140   if (RESOURCE_VALID (&Bridge->Mem)) {
 141     ASSERT (Bridge->Mem.Limit < SIZE_4GB);
 142     if (Bridge->Mem.Limit >= SIZE_4GB) {
 143       return NULL;
 144     }
 145   }
 146
 147   if (RESOURCE_VALID (&Bridge->MemAbove4G)) {
 148     ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB);
 149     if (Bridge->MemAbove4G.Base < SIZE_4GB) {
 150       return NULL;
 151     }
 152   }
 153
 154   if (RESOURCE_VALID (&Bridge->PMem)) {
 155     ASSERT (Bridge->PMem.Limit < SIZE_4GB);
 156     if (Bridge->PMem.Limit >= SIZE_4GB) {
 157       return NULL;
 158     }
 159   }
 160
 161   if (RESOURCE_VALID (&Bridge->PMemAbove4G)) {
 162     ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB);
 163     if (Bridge->PMemAbove4G.Base < SIZE_4GB) {
 164       return NULL;
 165     }
 166   }
 167
 168   //
 169   // Ignore AllocationAttributes when resources were already assigned.
 170   //
 171   if (!Bridge->ResourceAssigned) {
 172     if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) {
 173       //
 174       // If this bit is set, then the PCI Root Bridge does not
 175       // support separate windows for Non-prefetchable and Prefetchable
 176       // memory.
 177       //
 178       ASSERT (!RESOURCE_VALID (&Bridge->PMem));
 179       ASSERT (!RESOURCE_VALID (&Bridge->PMemAbove4G));
 180       if (RESOURCE_VALID (&Bridge->PMem) || RESOURCE_VALID (&Bridge->PMemAbove4G)) {
 181         return NULL;
 182       }
 183     }
 184
 185     if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) == 0) {
 186       //
 187       // If this bit is not set, then the PCI Root Bridge does not support
 188       // 64 bit memory windows.
 189       //
 190       ASSERT (!RESOURCE_VALID (&Bridge->MemAbove4G));
 191       ASSERT (!RESOURCE_VALID (&Bridge->PMemAbove4G));
 192       if (RESOURCE_VALID (&Bridge->MemAbove4G) || RESOURCE_VALID (&Bridge->PMemAbove4G)) {
 193         return NULL;
 194       }
 195     }
 196   }
 197
 198   RootBridge = AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE_INSTANCE));
 199   ASSERT (RootBridge != NULL);
 200
 201   RootBridge->Signature             = PCI_ROOT_BRIDGE_SIGNATURE;
 202   RootBridge->Supports              = Bridge->Supports;
 203   RootBridge->Attributes            = Bridge->Attributes;
 204   RootBridge->DmaAbove4G            = Bridge->DmaAbove4G;
 205   RootBridge->NoExtendedConfigSpace = Bridge->NoExtendedConfigSpace;
 206   RootBridge->AllocationAttributes  = Bridge->AllocationAttributes;
 207   RootBridge->DevicePath            = DuplicateDevicePath (Bridge->DevicePath);
 208   RootBridge->DevicePathStr         = DevicePathStr;
 209   RootBridge->ConfigBuffer          = AllocatePool (
 210                                         TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)
 211                                         );
 212   ASSERT (RootBridge->ConfigBuffer != NULL);
 213   InitializeListHead (&RootBridge->Maps);
 214
 215   CopyMem (&RootBridge->Bus, &Bridge->Bus, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 216   CopyMem (&RootBridge->Io, &Bridge->Io, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 217   CopyMem (&RootBridge->Mem, &Bridge->Mem, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 218   CopyMem (&RootBridge->MemAbove4G, &Bridge->MemAbove4G, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 219   CopyMem (&RootBridge->PMem, &Bridge->PMem, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 220   CopyMem (&RootBridge->PMemAbove4G, &Bridge->PMemAbove4G, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 221
 222   for (Index = TypeIo; Index < TypeMax; Index++) {
 223     switch (Index) {
 224       case TypeBus:
 225         Aperture = &RootBridge->Bus;
 226         break;
 227       case TypeIo:
 228         Aperture = &RootBridge->Io;
 229         break;
 230       case TypeMem32:
 231         Aperture = &RootBridge->Mem;
 232         break;
 233       case TypeMem64:
 234         Aperture = &RootBridge->MemAbove4G;
 235         break;
 236       case TypePMem32:
 237         Aperture = &RootBridge->PMem;
 238         break;
 239       case TypePMem64:
 240         Aperture = &RootBridge->PMemAbove4G;
 241         break;
 242       default:
 243         ASSERT (FALSE);
 244         Aperture = NULL;
 245         break;
 246     }
 247
 248     RootBridge->ResAllocNode[Index].Type = Index;
 249     if (Bridge->ResourceAssigned && (Aperture->Limit >= Aperture->Base)) {
 250       //
 251       // Base in ResAllocNode is a host address, while Base in Aperture is a
 252       // device address.
 253       //
 254       RootBridge->ResAllocNode[Index].Base = TO_HOST_ADDRESS (
 255                                                Aperture->Base,
 256                                                Aperture->Translation
 257                                                );
 258       RootBridge->ResAllocNode[Index].Length = Aperture->Limit - Aperture->Base + 1;
 259       RootBridge->ResAllocNode[Index].Status = ResAllocated;
 260     } else {
 261       RootBridge->ResAllocNode[Index].Base   = 0;
 262       RootBridge->ResAllocNode[Index].Length = 0;
 263       RootBridge->ResAllocNode[Index].Status = ResNone;
 264     }
 265   }
 266
 267   RootBridge->RootBridgeIo.SegmentNumber  = Bridge->Segment;
 268   RootBridge->RootBridgeIo.PollMem        = RootBridgeIoPollMem;
 269   RootBridge->RootBridgeIo.PollIo         = RootBridgeIoPollIo;
 270   RootBridge->RootBridgeIo.Mem.Read       = RootBridgeIoMemRead;
 271   RootBridge->RootBridgeIo.Mem.Write      = RootBridgeIoMemWrite;
 272   RootBridge->RootBridgeIo.Io.Read        = RootBridgeIoIoRead;
 273   RootBridge->RootBridgeIo.Io.Write       = RootBridgeIoIoWrite;
 274   RootBridge->RootBridgeIo.CopyMem        = RootBridgeIoCopyMem;
 275   RootBridge->RootBridgeIo.Pci.Read       = RootBridgeIoPciRead;
 276   RootBridge->RootBridgeIo.Pci.Write      = RootBridgeIoPciWrite;
 277   RootBridge->RootBridgeIo.Map            = RootBridgeIoMap;
 278   RootBridge->RootBridgeIo.Unmap          = RootBridgeIoUnmap;
 279   RootBridge->RootBridgeIo.AllocateBuffer = RootBridgeIoAllocateBuffer;
 280   RootBridge->RootBridgeIo.FreeBuffer     = RootBridgeIoFreeBuffer;
 281   RootBridge->RootBridgeIo.Flush          = RootBridgeIoFlush;
 282   RootBridge->RootBridgeIo.GetAttributes  = RootBridgeIoGetAttributes;
 283   RootBridge->RootBridgeIo.SetAttributes  = RootBridgeIoSetAttributes;
 284   RootBridge->RootBridgeIo.Configuration  = RootBridgeIoConfiguration;
 285
 286   return RootBridge;
 287 }
 288
 289 /**
 290   Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.
 291
 292   The I/O operations are carried out exactly as requested. The caller is
 293   responsible for satisfying any alignment and I/O width restrictions that a PI
 294   System on a platform might require. For example on some platforms, width
 295   requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other
 296   hand, will be handled by the driver.
 297
 298   @param[in] This           A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 299
 300   @param[in] OperationType  I/O operation type: IO/MMIO/PCI.
 301
 302   @param[in] Width          Signifies the width of the I/O or Memory operation.
 303
 304   @param[in] Address        The base address of the I/O operation.
 305
 306   @param[in] Count          The number of I/O operations to perform. The number
 307                             of bytes moved is Width size * Count, starting at
 308                             Address.
 309
 310   @param[in] Buffer         For read operations, the destination buffer to
 311                             store the results. For write operations, the source
 312                             buffer from which to write data.
 313
 314   @retval EFI_SUCCESS            The parameters for this request pass the
 315                                  checks.
 316
 317   @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
 318
 319   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
 320
 321   @retval EFI_INVALID_PARAMETER  Address or Count is invalid.
 322
 323   @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
 324
 325   @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
 326                                  and Count is not valid for this PI system.
 327 **/
 328 EFI_STATUS
 329 RootBridgeIoCheckParameter (
 330   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 331   IN OPERATION_TYPE                         OperationType,
 332   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 333   IN UINT64                                 Address,
 334   IN UINTN                                  Count,
 335   IN VOID                                   *Buffer
 336   )
 337 {
 338   PCI_ROOT_BRIDGE_INSTANCE                     *RootBridge;
 339   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS  *PciRbAddr;
 340   UINT64                                       Base;
 341   UINT64                                       Limit;
 342   UINT32                                       Size;
 343   UINT64                                       Length;
 344
 345   //
 346   // Check to see if Buffer is NULL
 347   //
 348   if (Buffer == NULL) {
 349     return EFI_INVALID_PARAMETER;
 350   }
 351
 352   //
 353   // Check to see if Width is in the valid range
 354   //
 355   if ((UINT32)Width >= EfiPciWidthMaximum) {
 356     return EFI_INVALID_PARAMETER;
 357   }
 358
 359   //
 360   // For FIFO type, the device address won't increase during the access,
 361   // so treat Count as 1
 362   //
 363   if ((Width >= EfiPciWidthFifoUint8) && (Width <= EfiPciWidthFifoUint64)) {
 364     Count = 1;
 365   }
 366
 367   Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)(Width & 0x03);
 368   Size  = 1 << Width;
 369
 370   //
 371   // Make sure (Count * Size) doesn't exceed MAX_UINT64
 372   //
 373   if (Count > DivU64x32 (MAX_UINT64, Size)) {
 374     return EFI_INVALID_PARAMETER;
 375   }
 376
 377   //
 378   // Check to see if Address is aligned
 379   //
 380   if ((Address & (Size - 1)) != 0) {
 381     return EFI_UNSUPPORTED;
 382   }
 383
 384   //
 385   // Make sure (Address + Count * Size) doesn't exceed MAX_UINT64
 386   //
 387   Length = MultU64x32 (Count, Size);
 388   if (Address > MAX_UINT64 - Length) {
 389     return EFI_INVALID_PARAMETER;
 390   }
 391
 392   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
 393
 394   //
 395   // Check to see if any address associated with this transfer exceeds the
 396   // maximum allowed address.  The maximum address implied by the parameters
 397   // passed in is Address + Size * Count.  If the following condition is met,
 398   // then the transfer is not supported.
 399   //
 400   //    Address + Size * Count > Limit + 1
 401   //
 402   // Since Limit can be the maximum integer value supported by the CPU and
 403   // Count can also be the maximum integer value supported by the CPU, this
 404   // range check must be adjusted to avoid all oveflow conditions.
 405   //
 406   if (OperationType == IoOperation) {
 407     //
 408     // Allow Legacy IO access
 409     //
 410     if (Address + Length <= 0x1000) {
 411       if ((RootBridge->Attributes & (
 412                                      EFI_PCI_ATTRIBUTE_ISA_IO | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_ATTRIBUTE_VGA_IO |
 413                                      EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |
 414                                      EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_ATTRIBUTE_VGA_IO_16)) != 0)
 415       {
 416         return EFI_SUCCESS;
 417       }
 418     }
 419
 420     Base  = RootBridge->Io.Base;
 421     Limit = RootBridge->Io.Limit;
 422   } else if (OperationType == MemOperation) {
 423     //
 424     // Allow Legacy MMIO access
 425     //
 426     if ((Address >= 0xA0000) && ((Address + Length) <= 0xC0000)) {
 427       if ((RootBridge->Attributes & EFI_PCI_ATTRIBUTE_VGA_MEMORY) != 0) {
 428         return EFI_SUCCESS;
 429       }
 430     }
 431
 432     //
 433     // By comparing the Address against Limit we know which range to be used
 434     // for checking
 435     //
 436     if ((Address >= RootBridge->Mem.Base) && (Address + Length <= RootBridge->Mem.Limit + 1)) {
 437       Base  = RootBridge->Mem.Base;
 438       Limit = RootBridge->Mem.Limit;
 439     } else if ((Address >= RootBridge->PMem.Base) && (Address + Length <= RootBridge->PMem.Limit + 1)) {
 440       Base  = RootBridge->PMem.Base;
 441       Limit = RootBridge->PMem.Limit;
 442     } else if ((Address >= RootBridge->MemAbove4G.Base) && (Address + Length <= RootBridge->MemAbove4G.Limit + 1)) {
 443       Base  = RootBridge->MemAbove4G.Base;
 444       Limit = RootBridge->MemAbove4G.Limit;
 445     } else {
 446       Base  = RootBridge->PMemAbove4G.Base;
 447       Limit = RootBridge->PMemAbove4G.Limit;
 448     }
 449   } else {
 450     PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *)&Address;
 451     if ((PciRbAddr->Bus < RootBridge->Bus.Base) ||
 452         (PciRbAddr->Bus > RootBridge->Bus.Limit))
 453     {
 454       return EFI_INVALID_PARAMETER;
 455     }
 456
 457     if ((PciRbAddr->Device > PCI_MAX_DEVICE) ||
 458         (PciRbAddr->Function > PCI_MAX_FUNC))
 459     {
 460       return EFI_INVALID_PARAMETER;
 461     }
 462
 463     if (PciRbAddr->ExtendedRegister != 0) {
 464       Address = PciRbAddr->ExtendedRegister;
 465     } else {
 466       Address = PciRbAddr->Register;
 467     }
 468
 469     Base  = 0;
 470     Limit = RootBridge->NoExtendedConfigSpace ? 0xFF : 0xFFF;
 471   }
 472
 473   if (Address < Base) {
 474     return EFI_INVALID_PARAMETER;
 475   }
 476
 477   if (Address + Length > Limit + 1) {
 478     return EFI_INVALID_PARAMETER;
 479   }
 480
 481   return EFI_SUCCESS;
 482 }
 483
 484 /**
 485   Use address to match apertures of memory type and then get the corresponding
 486   translation.
 487
 488   @param RootBridge              The root bridge instance.
 489   @param Address                 The address used to match aperture.
 490   @param Translation             Pointer containing the output translation.
 491
 492   @return EFI_SUCCESS            Get translation successfully.
 493   @return EFI_INVALID_PARAMETER  No matched memory aperture; the input Address
 494                                  must be invalid.
 495 **/
 496 EFI_STATUS
 497 RootBridgeIoGetMemTranslationByAddress (
 498   IN PCI_ROOT_BRIDGE_INSTANCE  *RootBridge,
 499   IN UINT64                    Address,
 500   IN OUT UINT64                *Translation
 501   )
 502 {
 503   if ((Address >= RootBridge->Mem.Base) && (Address <= RootBridge->Mem.Limit)) {
 504     *Translation = RootBridge->Mem.Translation;
 505   } else if ((Address >= RootBridge->PMem.Base) && (Address <= RootBridge->PMem.Limit)) {
 506     *Translation = RootBridge->PMem.Translation;
 507   } else if ((Address >= RootBridge->MemAbove4G.Base) && (Address <= RootBridge->MemAbove4G.Limit)) {
 508     *Translation = RootBridge->MemAbove4G.Translation;
 509   } else if ((Address >= RootBridge->PMemAbove4G.Base) && (Address <= RootBridge->PMemAbove4G.Limit)) {
 510     *Translation = RootBridge->PMemAbove4G.Translation;
 511   } else {
 512     return EFI_INVALID_PARAMETER;
 513   }
 514
 515   return EFI_SUCCESS;
 516 }
 517
 518 /**
 519   Return the result of (Multiplicand * Multiplier / Divisor).
 520
 521   @param Multiplicand A 64-bit unsigned value.
 522   @param Multiplier   A 64-bit unsigned value.
 523   @param Divisor      A 32-bit unsigned value.
 524   @param Remainder    A pointer to a 32-bit unsigned value. This parameter is
 525                       optional and may be NULL.
 526
 527   @return Multiplicand * Multiplier / Divisor.
 528 **/
 529 UINT64
 530 MultThenDivU64x64x32 (
 531   IN      UINT64  Multiplicand,
 532   IN      UINT64  Multiplier,
 533   IN      UINT32  Divisor,
 534   OUT     UINT32  *Remainder  OPTIONAL
 535   )
 536 {
 537   UINT64  Uint64;
 538   UINT32  LocalRemainder;
 539   UINT32  Uint32;
 540
 541   if (Multiplicand > DivU64x64Remainder (MAX_UINT64, Multiplier, NULL)) {
 542     //
 543     // Make sure Multiplicand is the bigger one.
 544     //
 545     if (Multiplicand < Multiplier) {
 546       Uint64       = Multiplicand;
 547       Multiplicand = Multiplier;
 548       Multiplier   = Uint64;
 549     }
 550
 551     //
 552     // Because Multiplicand * Multiplier overflows,
 553     //   Multiplicand * Multiplier / Divisor
 554     // = (2 * Multiplicand' + 1) * Multiplier / Divisor
 555     // = 2 * (Multiplicand' * Multiplier / Divisor) + Multiplier / Divisor
 556     //
 557     Uint64 = MultThenDivU64x64x32 (RShiftU64 (Multiplicand, 1), Multiplier, Divisor, &LocalRemainder);
 558     Uint64 = LShiftU64 (Uint64, 1);
 559     Uint32 = 0;
 560     if ((Multiplicand & 0x1) == 1) {
 561       Uint64 += DivU64x32Remainder (Multiplier, Divisor, &Uint32);
 562     }
 563
 564     return Uint64 + DivU64x32Remainder (Uint32 + LShiftU64 (LocalRemainder, 1), Divisor, Remainder);
 565   } else {
 566     return DivU64x32Remainder (MultU64x64 (Multiplicand, Multiplier), Divisor, Remainder);
 567   }
 568 }
 569
 570 /**
 571   Return the elapsed tick count from CurrentTick.
 572
 573   @param  CurrentTick  On input, the previous tick count.
 574                        On output, the current tick count.
 575   @param  StartTick    The value the performance counter starts with when it
 576                        rolls over.
 577   @param  EndTick      The value that the performance counter ends with before
 578                        it rolls over.
 579
 580   @return  The elapsed tick count from CurrentTick.
 581 **/
 582 UINT64
 583 GetElapsedTick (
 584   UINT64  *CurrentTick,
 585   UINT64  StartTick,
 586   UINT64  EndTick
 587   )
 588 {
 589   UINT64  PreviousTick;
 590
 591   PreviousTick = *CurrentTick;
 592   *CurrentTick = GetPerformanceCounter ();
 593   if (StartTick < EndTick) {
 594     return *CurrentTick - PreviousTick;
 595   } else {
 596     return PreviousTick - *CurrentTick;
 597   }
 598 }
 599
 600 /**
 601   Polls an address in memory mapped I/O space until an exit condition is met,
 602   or a timeout occurs.
 603
 604   This function provides a standard way to poll a PCI memory location. A PCI
 605   memory read operation is performed at the PCI memory address specified by
 606   Address for the width specified by Width. The result of this PCI memory read
 607   operation is stored in Result. This PCI memory read operation is repeated
 608   until either a timeout of Delay 100 ns units has expired, or (Result & Mask)
 609   is equal to Value.
 610
 611   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 612   @param[in]   Width     Signifies the width of the memory operations.
 613   @param[in]   Address   The base address of the memory operations. The caller
 614                          is responsible for aligning Address if required.
 615   @param[in]   Mask      Mask used for the polling criteria. Bytes above Width
 616                          in Mask are ignored. The bits in the bytes below Width
 617                          which are zero in Mask are ignored when polling the
 618                          memory address.
 619   @param[in]   Value     The comparison value used for the polling exit
 620                          criteria.
 621   @param[in]   Delay     The number of 100 ns units to poll. Note that timer
 622                          available may be of poorer granularity.
 623   @param[out]  Result    Pointer to the last value read from the memory
 624                          location.
 625
 626   @retval EFI_SUCCESS            The last data returned from the access matched
 627                                  the poll exit criteria.
 628   @retval EFI_INVALID_PARAMETER  Width is invalid.
 629   @retval EFI_INVALID_PARAMETER  Result is NULL.
 630   @retval EFI_TIMEOUT            Delay expired before a match occurred.
 631   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
 632                                  lack of resources.
 633 **/
 634 EFI_STATUS
 635 EFIAPI
 636 RootBridgeIoPollMem (
 637   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 638   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 639   IN  UINT64                                 Address,
 640   IN  UINT64                                 Mask,
 641   IN  UINT64                                 Value,
 642   IN  UINT64                                 Delay,
 643   OUT UINT64                                 *Result
 644   )
 645 {
 646   EFI_STATUS  Status;
 647   UINT64      NumberOfTicks;
 648   UINT32      Remainder;
 649   UINT64      StartTick;
 650   UINT64      EndTick;
 651   UINT64      CurrentTick;
 652   UINT64      ElapsedTick;
 653   UINT64      Frequency;
 654
 655   if (Result == NULL) {
 656     return EFI_INVALID_PARAMETER;
 657   }
 658
 659   if ((UINT32)Width > EfiPciWidthUint64) {
 660     return EFI_INVALID_PARAMETER;
 661   }
 662
 663   //
 664   // No matter what, always do a single poll.
 665   //
 666   Status = This->Mem.Read (This, Width, Address, 1, Result);
 667   if (EFI_ERROR (Status)) {
 668     return Status;
 669   }
 670
 671   if ((*Result & Mask) == Value) {
 672     return EFI_SUCCESS;
 673   }
 674
 675   if (Delay == 0) {
 676     return EFI_SUCCESS;
 677   } else {
 678     //
 679     // NumberOfTicks = Frenquency * Delay / EFI_TIMER_PERIOD_SECONDS(1)
 680     //
 681     Frequency     = GetPerformanceCounterProperties (&StartTick, &EndTick);
 682     NumberOfTicks = MultThenDivU64x64x32 (Frequency, Delay, (UINT32)EFI_TIMER_PERIOD_SECONDS (1), &Remainder);
 683     if (Remainder >= (UINTN)EFI_TIMER_PERIOD_SECONDS (1) / 2) {
 684       NumberOfTicks++;
 685     }
 686
 687     for ( ElapsedTick = 0, CurrentTick = GetPerformanceCounter ()
 688           ; ElapsedTick <= NumberOfTicks
 689           ; ElapsedTick += GetElapsedTick (&CurrentTick, StartTick, EndTick)
 690           )
 691     {
 692       Status = This->Mem.Read (This, Width, Address, 1, Result);
 693       if (EFI_ERROR (Status)) {
 694         return Status;
 695       }
 696
 697       if ((*Result & Mask) == Value) {
 698         return EFI_SUCCESS;
 699       }
 700     }
 701   }
 702
 703   return EFI_TIMEOUT;
 704 }
 705
 706 /**
 707   Reads from the I/O space of a PCI Root Bridge. Returns when either the
 708   polling exit criteria is satisfied or after a defined duration.
 709
 710   This function provides a standard way to poll a PCI I/O location. A PCI I/O
 711   read operation is performed at the PCI I/O address specified by Address for
 712   the width specified by Width.
 713   The result of this PCI I/O read operation is stored in Result. This PCI I/O
 714   read operation is repeated until either a timeout of Delay 100 ns units has
 715   expired, or (Result & Mask) is equal to Value.
 716
 717   @param[in] This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 718   @param[in] Width     Signifies the width of the I/O operations.
 719   @param[in] Address   The base address of the I/O operations. The caller is
 720                        responsible for aligning Address if required.
 721   @param[in] Mask      Mask used for the polling criteria. Bytes above Width in
 722                        Mask are ignored. The bits in the bytes below Width
 723                        which are zero in Mask are ignored when polling the I/O
 724                        address.
 725   @param[in] Value     The comparison value used for the polling exit criteria.
 726   @param[in] Delay     The number of 100 ns units to poll. Note that timer
 727                        available may be of poorer granularity.
 728   @param[out] Result   Pointer to the last value read from the memory location.
 729
 730   @retval EFI_SUCCESS            The last data returned from the access matched
 731                                  the poll exit criteria.
 732   @retval EFI_INVALID_PARAMETER  Width is invalid.
 733   @retval EFI_INVALID_PARAMETER  Result is NULL.
 734   @retval EFI_TIMEOUT            Delay expired before a match occurred.
 735   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
 736                                  lack of resources.
 737 **/
 738 EFI_STATUS
 739 EFIAPI
 740 RootBridgeIoPollIo (
 741   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 742   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 743   IN  UINT64                                 Address,
 744   IN  UINT64                                 Mask,
 745   IN  UINT64                                 Value,
 746   IN  UINT64                                 Delay,
 747   OUT UINT64                                 *Result
 748   )
 749 {
 750   EFI_STATUS  Status;
 751   UINT64      NumberOfTicks;
 752   UINT32      Remainder;
 753   UINT64      StartTick;
 754   UINT64      EndTick;
 755   UINT64      CurrentTick;
 756   UINT64      ElapsedTick;
 757   UINT64      Frequency;
 758
 759   //
 760   // No matter what, always do a single poll.
 761   //
 762
 763   if (Result == NULL) {
 764     return EFI_INVALID_PARAMETER;
 765   }
 766
 767   if ((UINT32)Width > EfiPciWidthUint64) {
 768     return EFI_INVALID_PARAMETER;
 769   }
 770
 771   Status = This->Io.Read (This, Width, Address, 1, Result);
 772   if (EFI_ERROR (Status)) {
 773     return Status;
 774   }
 775
 776   if ((*Result & Mask) == Value) {
 777     return EFI_SUCCESS;
 778   }
 779
 780   if (Delay == 0) {
 781     return EFI_SUCCESS;
 782   } else {
 783     //
 784     // NumberOfTicks = Frenquency * Delay / EFI_TIMER_PERIOD_SECONDS(1)
 785     //
 786     Frequency     = GetPerformanceCounterProperties (&StartTick, &EndTick);
 787     NumberOfTicks = MultThenDivU64x64x32 (Frequency, Delay, (UINT32)EFI_TIMER_PERIOD_SECONDS (1), &Remainder);
 788     if (Remainder >= (UINTN)EFI_TIMER_PERIOD_SECONDS (1) / 2) {
 789       NumberOfTicks++;
 790     }
 791
 792     for ( ElapsedTick = 0, CurrentTick = GetPerformanceCounter ()
 793           ; ElapsedTick <= NumberOfTicks
 794           ; ElapsedTick += GetElapsedTick (&CurrentTick, StartTick, EndTick)
 795           )
 796     {
 797       Status = This->Io.Read (This, Width, Address, 1, Result);
 798       if (EFI_ERROR (Status)) {
 799         return Status;
 800       }
 801
 802       if ((*Result & Mask) == Value) {
 803         return EFI_SUCCESS;
 804       }
 805     }
 806   }
 807
 808   return EFI_TIMEOUT;
 809 }
 810
 811 /**
 812   Enables a PCI driver to access PCI controller registers in the PCI root
 813   bridge memory space.
 814
 815   The Mem.Read(), and Mem.Write() functions enable a driver to access PCI
 816   controller registers in the PCI root bridge memory space.
 817   The memory operations are carried out exactly as requested. The caller is
 818   responsible for satisfying any alignment and memory width restrictions that a
 819   PCI Root Bridge on a platform might require.
 820
 821   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 822   @param[in]   Width     Signifies the width of the memory operation.
 823   @param[in]   Address   The base address of the memory operation. The caller
 824                          is responsible for aligning the Address if required.
 825   @param[in]   Count     The number of memory operations to perform. Bytes
 826                          moved is Width size * Count, starting at Address.
 827   @param[out]  Buffer    For read operations, the destination buffer to store
 828                          the results. For write operations, the source buffer
 829                          to write data from.
 830
 831   @retval EFI_SUCCESS            The data was read from or written to the PCI
 832                                  root bridge.
 833   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.
 834   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
 835   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
 836                                  lack of resources.
 837 **/
 838 EFI_STATUS
 839 EFIAPI
 840 RootBridgeIoMemRead (
 841   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 842   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 843   IN     UINT64                                 Address,
 844   IN     UINTN                                  Count,
 845   OUT    VOID                                   *Buffer
 846   )
 847 {
 848   EFI_STATUS                Status;
 849   PCI_ROOT_BRIDGE_INSTANCE  *RootBridge;
 850   UINT64                    Translation;
 851
 852   Status = RootBridgeIoCheckParameter (
 853              This,
 854              MemOperation,
 855              Width,
 856              Address,
 857              Count,
 858              Buffer
 859              );
 860   if (EFI_ERROR (Status)) {
 861     return Status;
 862   }
 863
 864   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
 865   Status     = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation);
 866   if (EFI_ERROR (Status)) {
 867     return Status;
 868   }
 869
 870   // Address passed to CpuIo->Mem.Read needs to be a host address instead of
 871   // device address.
 872   return mCpuIo->Mem.Read (
 873                        mCpuIo,
 874                        (EFI_CPU_IO_PROTOCOL_WIDTH)Width,
 875                        TO_HOST_ADDRESS (Address, Translation),
 876                        Count,
 877                        Buffer
 878                        );
 879 }
 880
 881 /**
 882   Enables a PCI driver to access PCI controller registers in the PCI root
 883   bridge memory space.
 884
 885   The Mem.Read(), and Mem.Write() functions enable a driver to access PCI
 886   controller registers in the PCI root bridge memory space.
 887   The memory operations are carried out exactly as requested. The caller is
 888   responsible for satisfying any alignment and memory width restrictions that a
 889   PCI Root Bridge on a platform might require.
 890
 891   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 892   @param[in]   Width     Signifies the width of the memory operation.
 893   @param[in]   Address   The base address of the memory operation. The caller
 894                          is responsible for aligning the Address if required.
 895   @param[in]   Count     The number of memory operations to perform. Bytes
 896                          moved is Width size * Count, starting at Address.
 897   @param[in]   Buffer    For read operations, the destination buffer to store
 898                          the results. For write operations, the source buffer
 899                          to write data from.
 900
 901   @retval EFI_SUCCESS            The data was read from or written to the PCI
 902                                  root bridge.
 903   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.
 904   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
 905   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
 906                                  lack of resources.
 907 **/
 908 EFI_STATUS
 909 EFIAPI
 910 RootBridgeIoMemWrite (
 911   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 912   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 913   IN     UINT64                                 Address,
 914   IN     UINTN                                  Count,
 915   IN     VOID                                   *Buffer
 916   )
 917 {
 918   EFI_STATUS                Status;
 919   PCI_ROOT_BRIDGE_INSTANCE  *RootBridge;
 920   UINT64                    Translation;
 921
 922   Status = RootBridgeIoCheckParameter (
 923              This,
 924              MemOperation,
 925              Width,
 926              Address,
 927              Count,
 928              Buffer
 929              );
 930   if (EFI_ERROR (Status)) {
 931     return Status;
 932   }
 933
 934   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
 935   Status     = RootBridgeIoGetMemTranslationByAddress (RootBridge, Address, &Translation);
 936   if (EFI_ERROR (Status)) {
 937     return Status;
 938   }
 939
 940   // Address passed to CpuIo->Mem.Write needs to be a host address instead of
 941   // device address.
 942   return mCpuIo->Mem.Write (
 943                        mCpuIo,
 944                        (EFI_CPU_IO_PROTOCOL_WIDTH)Width,
 945                        TO_HOST_ADDRESS (Address, Translation),
 946                        Count,
 947                        Buffer
 948                        );
 949 }
 950
 951 /**
 952   Enables a PCI driver to access PCI controller registers in the PCI root
 953   bridge I/O space.
 954
 955   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 956   @param[in]   Width       Signifies the width of the memory operations.
 957   @param[in]   Address     The base address of the I/O operation. The caller is
 958                            responsible for aligning the Address if required.
 959   @param[in]   Count       The number of I/O operations to perform. Bytes moved
 960                            is Width size * Count, starting at Address.
 961   @param[out]  Buffer      For read operations, the destination buffer to store
 962                            the results. For write operations, the source buffer
 963                            to write data from.
 964
 965   @retval EFI_SUCCESS              The data was read from or written to the PCI
 966                                    root bridge.
 967   @retval EFI_INVALID_PARAMETER    Width is invalid for this PCI root bridge.
 968   @retval EFI_INVALID_PARAMETER    Buffer is NULL.
 969   @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a
 970                                    lack of resources.
 971 **/
 972 EFI_STATUS
 973 EFIAPI
 974 RootBridgeIoIoRead (
 975   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 976   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 977   IN     UINT64                                 Address,
 978   IN     UINTN                                  Count,
 979   OUT    VOID                                   *Buffer
 980   )
 981 {
 982   EFI_STATUS                Status;
 983   PCI_ROOT_BRIDGE_INSTANCE  *RootBridge;
 984
 985   Status = RootBridgeIoCheckParameter (
 986              This,
 987              IoOperation,
 988              Width,
 989              Address,
 990              Count,
 991              Buffer
 992              );
 993   if (EFI_ERROR (Status)) {
 994     return Status;
 995   }
 996
 997   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
 998
 999   // Address passed to CpuIo->Io.Read needs to be a host address instead of
1000   // device address.
1001   return mCpuIo->Io.Read (
1002                       mCpuIo,
1003                       (EFI_CPU_IO_PROTOCOL_WIDTH)Width,
1004                       TO_HOST_ADDRESS (Address, RootBridge->Io.Translation),
1005                       Count,
1006                       Buffer
1007                       );
1008 }
1009
1010 /**
1011   Enables a PCI driver to access PCI controller registers in the PCI root
1012   bridge I/O space.
1013
1014   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1015   @param[in]   Width       Signifies the width of the memory operations.
1016   @param[in]   Address     The base address of the I/O operation. The caller is
1017                            responsible for aligning the Address if required.
1018   @param[in]   Count       The number of I/O operations to perform. Bytes moved
1019                            is Width size * Count, starting at Address.
1020   @param[in]   Buffer      For read operations, the destination buffer to store
1021                            the results. For write operations, the source buffer
1022                            to write data from.
1023
1024   @retval EFI_SUCCESS              The data was read from or written to the PCI
1025                                    root bridge.
1026   @retval EFI_INVALID_PARAMETER    Width is invalid for this PCI root bridge.
1027   @retval EFI_INVALID_PARAMETER    Buffer is NULL.
1028   @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a
1029                                    lack of resources.
1030 **/
1031 EFI_STATUS
1032 EFIAPI
1033 RootBridgeIoIoWrite (
1034   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
1035   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
1036   IN       UINT64                                 Address,
1037   IN       UINTN                                  Count,
1038   IN       VOID                                   *Buffer
1039   )
1040 {
1041   EFI_STATUS                Status;
1042   PCI_ROOT_BRIDGE_INSTANCE  *RootBridge;
1043
1044   Status = RootBridgeIoCheckParameter (
1045              This,
1046              IoOperation,
1047              Width,
1048              Address,
1049              Count,
1050              Buffer
1051              );
1052   if (EFI_ERROR (Status)) {
1053     return Status;
1054   }
1055
1056   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1057
1058   // Address passed to CpuIo->Io.Write needs to be a host address instead of
1059   // device address.
1060   return mCpuIo->Io.Write (
1061                       mCpuIo,
1062                       (EFI_CPU_IO_PROTOCOL_WIDTH)Width,
1063                       TO_HOST_ADDRESS (Address, RootBridge->Io.Translation),
1064                       Count,
1065                       Buffer
1066                       );
1067 }
1068
1069 /**
1070   Enables a PCI driver to copy one region of PCI root bridge memory space to
1071   another region of PCI root bridge memory space.
1072
1073   The CopyMem() function enables a PCI driver to copy one region of PCI root
1074   bridge memory space to another region of PCI root bridge memory space. This
1075   is especially useful for video scroll operation on a memory mapped video
1076   buffer.
1077   The memory operations are carried out exactly as requested. The caller is
1078   responsible for satisfying any alignment and memory width restrictions that a
1079   PCI root bridge on a platform might require.
1080
1081   @param[in] This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1082                          instance.
1083   @param[in] Width       Signifies the width of the memory operations.
1084   @param[in] DestAddress The destination address of the memory operation. The
1085                          caller is responsible for aligning the DestAddress if
1086                          required.
1087   @param[in] SrcAddress  The source address of the memory operation. The caller
1088                          is responsible for aligning the SrcAddress if
1089                          required.
1090   @param[in] Count       The number of memory operations to perform. Bytes
1091                          moved is Width size * Count, starting at DestAddress
1092                          and SrcAddress.
1093
1094   @retval  EFI_SUCCESS             The data was copied from one memory region
1095                                    to another memory region.
1096   @retval  EFI_INVALID_PARAMETER   Width is invalid for this PCI root bridge.
1097   @retval  EFI_OUT_OF_RESOURCES    The request could not be completed due to a
1098                                    lack of resources.
1099 **/
1100 EFI_STATUS
1101 EFIAPI
1102 RootBridgeIoCopyMem (
1103   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
1104   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
1105   IN UINT64                                 DestAddress,
1106   IN UINT64                                 SrcAddress,
1107   IN UINTN                                  Count
1108   )
1109 {
1110   EFI_STATUS  Status;
1111   BOOLEAN     Forward;
1112   UINTN       Stride;
1113   UINTN       Index;
1114   UINT64      Result;
1115
1116   if ((UINT32)Width > EfiPciWidthUint64) {
1117     return EFI_INVALID_PARAMETER;
1118   }
1119
1120   if (DestAddress == SrcAddress) {
1121     return EFI_SUCCESS;
1122   }
1123
1124   Stride = (UINTN)(1 << Width);
1125
1126   Forward = TRUE;
1127   if ((DestAddress > SrcAddress) &&
1128       (DestAddress < (SrcAddress + Count * Stride)))
1129   {
1130     Forward     = FALSE;
1131     SrcAddress  = SrcAddress + (Count - 1) * Stride;
1132     DestAddress = DestAddress + (Count - 1) * Stride;
1133   }
1134
1135   for (Index = 0; Index < Count; Index++) {
1136     Status = RootBridgeIoMemRead (
1137                This,
1138                Width,
1139                SrcAddress,
1140                1,
1141                &Result
1142                );
1143     if (EFI_ERROR (Status)) {
1144       return Status;
1145     }
1146
1147     Status = RootBridgeIoMemWrite (
1148                This,
1149                Width,
1150                DestAddress,
1151                1,
1152                &Result
1153                );
1154     if (EFI_ERROR (Status)) {
1155       return Status;
1156     }
1157
1158     if (Forward) {
1159       SrcAddress  += Stride;
1160       DestAddress += Stride;
1161     } else {
1162       SrcAddress  -= Stride;
1163       DestAddress -= Stride;
1164     }
1165   }
1166
1167   return EFI_SUCCESS;
1168 }
1169
1170 /**
1171   PCI configuration space access.
1172
1173   @param This     A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1174   @param Read     TRUE indicating it's a read operation.
1175   @param Width    Signifies the width of the memory operation.
1176   @param Address  The address within the PCI configuration space
1177                   for the PCI controller.
1178   @param Count    The number of PCI configuration operations
1179                   to perform.
1180   @param Buffer   The destination buffer to store the results.
1181
1182   @retval EFI_SUCCESS            The data was read/written from/to the PCI root bridge.
1183   @retval EFI_INVALID_PARAMETER  Invalid parameters found.
1184 **/
1185 EFI_STATUS
1186 EFIAPI
1187 RootBridgeIoPciAccess (
1188   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
1189   IN     BOOLEAN                                Read,
1190   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
1191   IN     UINT64                                 Address,
1192   IN     UINTN                                  Count,
1193   IN OUT VOID                                   *Buffer
1194   )
1195 {
1196   EFI_STATUS                                   Status;
1197   PCI_ROOT_BRIDGE_INSTANCE                     *RootBridge;
1198   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS  PciAddress;
1199   UINT8                                        *Uint8Buffer;
1200   UINT8                                        InStride;
1201   UINT8                                        OutStride;
1202   UINTN                                        Size;
1203
1204   Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address, Count, Buffer);
1205   if (EFI_ERROR (Status)) {
1206     return Status;
1207   }
1208
1209   //
1210   // Read Pci configuration space
1211   //
1212   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1213   CopyMem (&PciAddress, &Address, sizeof (PciAddress));
1214
1215   if (PciAddress.ExtendedRegister == 0) {
1216     PciAddress.ExtendedRegister = PciAddress.Register;
1217   }
1218
1219   Address = PCI_SEGMENT_LIB_ADDRESS (
1220               RootBridge->RootBridgeIo.SegmentNumber,
1221               PciAddress.Bus,
1222               PciAddress.Device,
1223               PciAddress.Function,
1224               PciAddress.ExtendedRegister
1225               );
1226
1227   //
1228   // Select loop based on the width of the transfer
1229   //
1230   InStride  = mInStride[Width];
1231   OutStride = mOutStride[Width];
1232   Size      = (UINTN)(1 << (Width & 0x03));
1233   for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
1234     if (Read) {
1235       PciSegmentReadBuffer (Address, Size, Uint8Buffer);
1236     } else {
1237       PciSegmentWriteBuffer (Address, Size, Uint8Buffer);
1238     }
1239   }
1240
1241   return EFI_SUCCESS;
1242 }
1243
1244 /**
1245   Allows read from PCI configuration space.
1246
1247   @param This     A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1248   @param Width    Signifies the width of the memory operation.
1249   @param Address  The address within the PCI configuration space
1250                   for the PCI controller.
1251   @param Count    The number of PCI configuration operations
1252                   to perform.
1253   @param Buffer   The destination buffer to store the results.
1254
1255   @retval EFI_SUCCESS           The data was read from the PCI root bridge.
1256   @retval EFI_INVALID_PARAMETER Invalid parameters found.
1257 **/
1258 EFI_STATUS
1259 EFIAPI
1260 RootBridgeIoPciRead (
1261   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
1262   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
1263   IN     UINT64                                 Address,
1264   IN     UINTN                                  Count,
1265   IN OUT VOID                                   *Buffer
1266   )
1267 {
1268   return RootBridgeIoPciAccess (This, TRUE, Width, Address, Count, Buffer);
1269 }
1270
1271 /**
1272   Allows write to PCI configuration space.
1273
1274   @param This     A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1275   @param Width    Signifies the width of the memory operation.
1276   @param Address  The address within the PCI configuration space
1277                   for the PCI controller.
1278   @param Count    The number of PCI configuration operations
1279                   to perform.
1280   @param Buffer   The source buffer to get the results.
1281
1282   @retval EFI_SUCCESS            The data was written to the PCI root bridge.
1283   @retval EFI_INVALID_PARAMETER  Invalid parameters found.
1284 **/
1285 EFI_STATUS
1286 EFIAPI
1287 RootBridgeIoPciWrite (
1288   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
1289   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
1290   IN     UINT64                                 Address,
1291   IN     UINTN                                  Count,
1292   IN OUT VOID                                   *Buffer
1293   )
1294 {
1295   return RootBridgeIoPciAccess (This, FALSE, Width, Address, Count, Buffer);
1296 }
1297
1298 /**
1299   Provides the PCI controller-specific address needed to access
1300   system memory for DMA.
1301
1302   @param This           A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1303   @param Operation      Indicate if the bus master is going to read or write
1304                         to system memory.
1305   @param HostAddress    The system memory address to map on the PCI controller.
1306   @param NumberOfBytes  On input the number of bytes to map.
1307                         On output the number of bytes that were mapped.
1308   @param DeviceAddress  The resulting map address for the bus master PCI
1309                         controller to use to access the system memory's HostAddress.
1310   @param Mapping        The value to pass to Unmap() when the bus master DMA
1311                         operation is complete.
1312
1313   @retval EFI_SUCCESS            Success.
1314   @retval EFI_INVALID_PARAMETER  Invalid parameters found.
1315   @retval EFI_UNSUPPORTED        The HostAddress cannot be mapped as a common buffer.
1316   @retval EFI_DEVICE_ERROR       The System hardware could not map the requested address.
1317   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to lack of resources.
1318 **/
1319 EFI_STATUS
1320 EFIAPI
1321 RootBridgeIoMap (
1322   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL            *This,
1323   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  Operation,
1324   IN     VOID                                       *HostAddress,
1325   IN OUT UINTN                                      *NumberOfBytes,
1326   OUT    EFI_PHYSICAL_ADDRESS                       *DeviceAddress,
1327   OUT    VOID                                       **Mapping
1328   )
1329 {
1330   EFI_STATUS                Status;
1331   PCI_ROOT_BRIDGE_INSTANCE  *RootBridge;
1332   EFI_PHYSICAL_ADDRESS      PhysicalAddress;
1333   MAP_INFO                  *MapInfo;
1334
1335   if ((HostAddress == NULL) || (NumberOfBytes == NULL) || (DeviceAddress == NULL) ||
1336       (Mapping == NULL))
1337   {
1338     return EFI_INVALID_PARAMETER;
1339   }
1340
1341   //
1342   // Make sure that Operation is valid
1343   //
1344   if ((UINT32)Operation >= EfiPciOperationMaximum) {
1345     return EFI_INVALID_PARAMETER;
1346   }
1347
1348   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1349
1350   if (mIoMmu != NULL) {
1351     if (!RootBridge->DmaAbove4G) {
1352       //
1353       // Clear 64bit support
1354       //
1355       if (Operation > EfiPciOperationBusMasterCommonBuffer) {
1356         Operation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION)(Operation - EfiPciOperationBusMasterRead64);
1357       }
1358     }
1359
1360     Status = mIoMmu->Map (
1361                        mIoMmu,
1362                        (EDKII_IOMMU_OPERATION)Operation,
1363                        HostAddress,
1364                        NumberOfBytes,
1365                        DeviceAddress,
1366                        Mapping
1367                        );
1368     return Status;
1369   }
1370
1371   PhysicalAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress;
1372   if ((!RootBridge->DmaAbove4G ||
1373        ((Operation != EfiPciOperationBusMasterRead64) &&
1374         (Operation != EfiPciOperationBusMasterWrite64) &&
1375         (Operation != EfiPciOperationBusMasterCommonBuffer64))) &&
1376       ((PhysicalAddress + *NumberOfBytes) > SIZE_4GB))
1377   {
1378     //
1379     // If the root bridge or the device cannot handle performing DMA above
1380     // 4GB but any part of the DMA transfer being mapped is above 4GB, then
1381     // map the DMA transfer to a buffer below 4GB.
1382     //
1383
1384     if ((Operation == EfiPciOperationBusMasterCommonBuffer) ||
1385         (Operation == EfiPciOperationBusMasterCommonBuffer64))
1386     {
1387       //
1388       // Common Buffer operations can not be remapped.  If the common buffer
1389       // if above 4GB, then it is not possible to generate a mapping, so return
1390       // an error.
1391       //
1392       return EFI_UNSUPPORTED;
1393     }
1394
1395     //
1396     // Allocate a MAP_INFO structure to remember the mapping when Unmap() is
1397     // called later.
1398     //
1399     MapInfo = AllocatePool (sizeof (MAP_INFO));
1400     if (MapInfo == NULL) {
1401       *NumberOfBytes = 0;
1402       return EFI_OUT_OF_RESOURCES;
1403     }
1404
1405     //
1406     // Initialize the MAP_INFO structure
1407     //
1408     MapInfo->Signature         = MAP_INFO_SIGNATURE;
1409     MapInfo->Operation         = Operation;
1410     MapInfo->NumberOfBytes     = *NumberOfBytes;
1411     MapInfo->NumberOfPages     = EFI_SIZE_TO_PAGES (MapInfo->NumberOfBytes);
1412     MapInfo->HostAddress       = PhysicalAddress;
1413     MapInfo->MappedHostAddress = SIZE_4GB - 1;
1414
1415     //
1416     // Allocate a buffer below 4GB to map the transfer to.
1417     //
1418     Status = gBS->AllocatePages (
1419                     AllocateMaxAddress,
1420                     EfiBootServicesData,
1421                     MapInfo->NumberOfPages,
1422                     &MapInfo->MappedHostAddress
1423                     );
1424     if (EFI_ERROR (Status)) {
1425       FreePool (MapInfo);
1426       *NumberOfBytes = 0;
1427       return Status;
1428     }
1429
1430     //
1431     // If this is a read operation from the Bus Master's point of view,
1432     // then copy the contents of the real buffer into the mapped buffer
1433     // so the Bus Master can read the contents of the real buffer.
1434     //
1435     if ((Operation == EfiPciOperationBusMasterRead) ||
1436         (Operation == EfiPciOperationBusMasterRead64))
1437     {
1438       CopyMem (
1439         (VOID *)(UINTN)MapInfo->MappedHostAddress,
1440         (VOID *)(UINTN)MapInfo->HostAddress,
1441         MapInfo->NumberOfBytes
1442         );
1443     }
1444
1445     InsertTailList (&RootBridge->Maps, &MapInfo->Link);
1446
1447     //
1448     // The DeviceAddress is the address of the maped buffer below 4GB
1449     //
1450     *DeviceAddress = MapInfo->MappedHostAddress;
1451     //
1452     // Return a pointer to the MAP_INFO structure in Mapping
1453     //
1454     *Mapping = MapInfo;
1455   } else {
1456     //
1457     // If the root bridge CAN handle performing DMA above 4GB or
1458     // the transfer is below 4GB, so the DeviceAddress is simply the
1459     // HostAddress
1460     //
1461     *DeviceAddress = PhysicalAddress;
1462     *Mapping       = NO_MAPPING;
1463   }
1464
1465   return EFI_SUCCESS;
1466 }
1467
1468 /**
1469   Completes the Map() operation and releases any corresponding resources.
1470
1471   The Unmap() function completes the Map() operation and releases any
1472   corresponding resources.
1473   If the operation was an EfiPciOperationBusMasterWrite or
1474   EfiPciOperationBusMasterWrite64, the data is committed to the target system
1475   memory.
1476   Any resources used for the mapping are freed.
1477
1478   @param[in] This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1479   @param[in] Mapping   The mapping value returned from Map().
1480
1481   @retval EFI_SUCCESS            The range was unmapped.
1482   @retval EFI_INVALID_PARAMETER  Mapping is not a value that was returned by Map().
1483   @retval EFI_DEVICE_ERROR       The data was not committed to the target system memory.
1484 **/
1485 EFI_STATUS
1486 EFIAPI
1487 RootBridgeIoUnmap (
1488   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
1489   IN VOID                             *Mapping
1490   )
1491 {
1492   MAP_INFO                  *MapInfo;
1493   LIST_ENTRY                *Link;
1494   PCI_ROOT_BRIDGE_INSTANCE  *RootBridge;
1495   EFI_STATUS                Status;
1496
1497   if (mIoMmu != NULL) {
1498     Status = mIoMmu->Unmap (
1499                        mIoMmu,
1500                        Mapping
1501                        );
1502     return Status;
1503   }
1504
1505   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1506
1507   //
1508   // See if the Map() operation associated with this Unmap() required a mapping
1509   // buffer. If a mapping buffer was not required, then this function simply
1510   // returns EFI_SUCCESS.
1511   //
1512   if (Mapping == NO_MAPPING) {
1513     return EFI_SUCCESS;
1514   }
1515
1516   MapInfo = NO_MAPPING;
1517   for (Link = GetFirstNode (&RootBridge->Maps)
1518        ; !IsNull (&RootBridge->Maps, Link)
1519        ; Link = GetNextNode (&RootBridge->Maps, Link)
1520        )
1521   {
1522     MapInfo = MAP_INFO_FROM_LINK (Link);
1523     if (MapInfo == Mapping) {
1524       break;
1525     }
1526   }
1527
1528   //
1529   // Mapping is not a valid value returned by Map()
1530   //
1531   if (MapInfo != Mapping) {
1532     return EFI_INVALID_PARAMETER;
1533   }
1534
1535   RemoveEntryList (&MapInfo->Link);
1536
1537   //
1538   // If this is a write operation from the Bus Master's point of view,
1539   // then copy the contents of the mapped buffer into the real buffer
1540   // so the processor can read the contents of the real buffer.
1541   //
1542   if ((MapInfo->Operation == EfiPciOperationBusMasterWrite) ||
1543       (MapInfo->Operation == EfiPciOperationBusMasterWrite64))
1544   {
1545     CopyMem (
1546       (VOID *)(UINTN)MapInfo->HostAddress,
1547       (VOID *)(UINTN)MapInfo->MappedHostAddress,
1548       MapInfo->NumberOfBytes
1549       );
1550   }
1551
1552   //
1553   // Free the mapped buffer and the MAP_INFO structure.
1554   //
1555   gBS->FreePages (MapInfo->MappedHostAddress, MapInfo->NumberOfPages);
1556   FreePool (Mapping);
1557   return EFI_SUCCESS;
1558 }
1559
1560 /**
1561   Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer
1562   or EfiPciOperationBusMasterCommonBuffer64 mapping.
1563
1564   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1565   @param Type        This parameter is not used and must be ignored.
1566   @param MemoryType  The type of memory to allocate, EfiBootServicesData or
1567                      EfiRuntimeServicesData.
1568   @param Pages       The number of pages to allocate.
1569   @param HostAddress A pointer to store the base system memory address of the
1570                      allocated range.
1571   @param Attributes  The requested bit mask of attributes for the allocated
1572                      range. Only the attributes
1573                      EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE,
1574                      EFI_PCI_ATTRIBUTE_MEMORY_CACHED, and
1575                      EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this
1576                      function.
1577
1578   @retval EFI_SUCCESS            The requested memory pages were allocated.
1579   @retval EFI_INVALID_PARAMETER  MemoryType is invalid.
1580   @retval EFI_INVALID_PARAMETER  HostAddress is NULL.
1581   @retval EFI_UNSUPPORTED        Attributes is unsupported. The only legal
1582                                  attribute bits are MEMORY_WRITE_COMBINE,
1583                                  MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
1584   @retval EFI_OUT_OF_RESOURCES   The memory pages could not be allocated.
1585 **/
1586 EFI_STATUS
1587 EFIAPI
1588 RootBridgeIoAllocateBuffer (
1589   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
1590   IN  EFI_ALLOCATE_TYPE                Type,
1591   IN  EFI_MEMORY_TYPE                  MemoryType,
1592   IN  UINTN                            Pages,
1593   OUT VOID                             **HostAddress,
1594   IN  UINT64                           Attributes
1595   )
1596 {
1597   EFI_STATUS                Status;
1598   EFI_PHYSICAL_ADDRESS      PhysicalAddress;
1599   PCI_ROOT_BRIDGE_INSTANCE  *RootBridge;
1600   EFI_ALLOCATE_TYPE         AllocateType;
1601
1602   //
1603   // Validate Attributes
1604   //
1605   if ((Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) != 0) {
1606     return EFI_UNSUPPORTED;
1607   }
1608
1609   //
1610   // Check for invalid inputs
1611   //
1612   if (HostAddress == NULL) {
1613     return EFI_INVALID_PARAMETER;
1614   }
1615
1616   //
1617   // The only valid memory types are EfiBootServicesData and
1618   // EfiRuntimeServicesData
1619   //
1620   if ((MemoryType != EfiBootServicesData) &&
1621       (MemoryType != EfiRuntimeServicesData))
1622   {
1623     return EFI_INVALID_PARAMETER;
1624   }
1625
1626   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1627
1628   if (mIoMmu != NULL) {
1629     if (!RootBridge->DmaAbove4G) {
1630       //
1631       // Clear DUAL_ADDRESS_CYCLE
1632       //
1633       Attributes &= ~((UINT64)EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
1634     }
1635
1636     Status = mIoMmu->AllocateBuffer (
1637                        mIoMmu,
1638                        Type,
1639                        MemoryType,
1640                        Pages,
1641                        HostAddress,
1642                        Attributes
1643                        );
1644     return Status;
1645   }
1646
1647   AllocateType = AllocateAnyPages;
1648   if (!RootBridge->DmaAbove4G ||
1649       ((Attributes & EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE) == 0))
1650   {
1651     //
1652     // Limit allocations to memory below 4GB
1653     //
1654     AllocateType    = AllocateMaxAddress;
1655     PhysicalAddress = (EFI_PHYSICAL_ADDRESS)(SIZE_4GB - 1);
1656   }
1657
1658   Status = gBS->AllocatePages (
1659                   AllocateType,
1660                   MemoryType,
1661                   Pages,
1662                   &PhysicalAddress
1663                   );
1664   if (!EFI_ERROR (Status)) {
1665     *HostAddress = (VOID *)(UINTN)PhysicalAddress;
1666   }
1667
1668   return Status;
1669 }
1670
1671 /**
1672   Frees memory that was allocated with AllocateBuffer().
1673
1674   The FreeBuffer() function frees memory that was allocated with
1675   AllocateBuffer().
1676
1677   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1678   @param Pages       The number of pages to free.
1679   @param HostAddress The base system memory address of the allocated range.
1680
1681   @retval EFI_SUCCESS            The requested memory pages were freed.
1682   @retval EFI_INVALID_PARAMETER  The memory range specified by HostAddress and
1683                                  Pages was not allocated with AllocateBuffer().
1684 **/
1685 EFI_STATUS
1686 EFIAPI
1687 RootBridgeIoFreeBuffer (
1688   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
1689   IN  UINTN                            Pages,
1690   OUT VOID                             *HostAddress
1691   )
1692 {
1693   EFI_STATUS  Status;
1694
1695   if (mIoMmu != NULL) {
1696     Status = mIoMmu->FreeBuffer (
1697                        mIoMmu,
1698                        Pages,
1699                        HostAddress
1700                        );
1701     return Status;
1702   }
1703
1704   return gBS->FreePages ((EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress, Pages);
1705 }
1706
1707 /**
1708   Flushes all PCI posted write transactions from a PCI host bridge to system
1709   memory.
1710
1711   The Flush() function flushes any PCI posted write transactions from a PCI
1712   host bridge to system memory. Posted write transactions are generated by PCI
1713   bus masters when they perform write transactions to target addresses in
1714   system memory.
1715   This function does not flush posted write transactions from any PCI bridges.
1716   A PCI controller specific action must be taken to guarantee that the posted
1717   write transactions have been flushed from the PCI controller and from all the
1718   PCI bridges into the PCI host bridge. This is typically done with a PCI read
1719   transaction from the PCI controller prior to calling Flush().
1720
1721   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1722
1723   @retval EFI_SUCCESS        The PCI posted write transactions were flushed
1724                              from the PCI host bridge to system memory.
1725   @retval EFI_DEVICE_ERROR   The PCI posted write transactions were not flushed
1726                              from the PCI host bridge due to a hardware error.
1727 **/
1728 EFI_STATUS
1729 EFIAPI
1730 RootBridgeIoFlush (
1731   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This
1732   )
1733 {
1734   return EFI_SUCCESS;
1735 }
1736
1737 /**
1738   Gets the attributes that a PCI root bridge supports setting with
1739   SetAttributes(), and the attributes that a PCI root bridge is currently
1740   using.
1741
1742   The GetAttributes() function returns the mask of attributes that this PCI
1743   root bridge supports and the mask of attributes that the PCI root bridge is
1744   currently using.
1745
1746   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1747   @param Supported   A pointer to the mask of attributes that this PCI root
1748                      bridge supports setting with SetAttributes().
1749   @param Attributes  A pointer to the mask of attributes that this PCI root
1750                      bridge is currently using.
1751
1752   @retval  EFI_SUCCESS           If Supports is not NULL, then the attributes
1753                                  that the PCI root bridge supports is returned
1754                                  in Supports. If Attributes is not NULL, then
1755                                  the attributes that the PCI root bridge is
1756                                  currently using is returned in Attributes.
1757   @retval  EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
1758 **/
1759 EFI_STATUS
1760 EFIAPI
1761 RootBridgeIoGetAttributes (
1762   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
1763   OUT UINT64                           *Supported,
1764   OUT UINT64                           *Attributes
1765   )
1766 {
1767   PCI_ROOT_BRIDGE_INSTANCE  *RootBridge;
1768
1769   if ((Attributes == NULL) && (Supported == NULL)) {
1770     return EFI_INVALID_PARAMETER;
1771   }
1772
1773   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1774   //
1775   // Set the return value for Supported and Attributes
1776   //
1777   if (Supported != NULL) {
1778     *Supported = RootBridge->Supports;
1779   }
1780
1781   if (Attributes != NULL) {
1782     *Attributes = RootBridge->Attributes;
1783   }
1784
1785   return EFI_SUCCESS;
1786 }
1787
1788 /**
1789   Sets attributes for a resource range on a PCI root bridge.
1790
1791   The SetAttributes() function sets the attributes specified in Attributes for
1792   the PCI root bridge on the resource range specified by ResourceBase and
1793   ResourceLength. Since the granularity of setting these attributes may vary
1794   from resource type to resource type, and from platform to platform, the
1795   actual resource range and the one passed in by the caller may differ. As a
1796   result, this function may set the attributes specified by Attributes on a
1797   larger resource range than the caller requested. The actual range is returned
1798   in ResourceBase and ResourceLength. The caller is responsible for verifying
1799   that the actual range for which the attributes were set is acceptable.
1800
1801   @param This            A pointer to the
1802                          EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1803   @param Attributes      The mask of attributes to set. If the
1804                          attribute bit MEMORY_WRITE_COMBINE,
1805                          MEMORY_CACHED, or MEMORY_DISABLE is set,
1806                          then the resource range is specified by
1807                          ResourceBase and ResourceLength. If
1808                          MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
1809                          MEMORY_DISABLE are not set, then
1810                          ResourceBase and ResourceLength are ignored,
1811                          and may be NULL.
1812   @param ResourceBase    A pointer to the base address of the
1813                          resource range to be modified by the
1814                          attributes specified by Attributes.
1815   @param ResourceLength  A pointer to the length of the resource
1816                                    range to be modified by the attributes
1817                                    specified by Attributes.
1818
1819   @retval  EFI_SUCCESS           The current configuration of this PCI root bridge
1820                                  was returned in Resources.
1821   @retval  EFI_UNSUPPORTED       The current configuration of this PCI root bridge
1822                                  could not be retrieved.
1823 **/
1824 EFI_STATUS
1825 EFIAPI
1826 RootBridgeIoSetAttributes (
1827   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
1828   IN     UINT64                           Attributes,
1829   IN OUT UINT64                           *ResourceBase,
1830   IN OUT UINT64                           *ResourceLength
1831   )
1832 {
1833   PCI_ROOT_BRIDGE_INSTANCE  *RootBridge;
1834
1835   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1836
1837   if ((Attributes & (~RootBridge->Supports)) != 0) {
1838     return EFI_UNSUPPORTED;
1839   }
1840
1841   RootBridge->Attributes = Attributes;
1842   return EFI_SUCCESS;
1843 }
1844
1845 /**
1846   Retrieves the current resource settings of this PCI root bridge in the form
1847   of a set of ACPI resource descriptors.
1848
1849   There are only two resource descriptor types from the ACPI Specification that
1850   may be used to describe the current resources allocated to a PCI root bridge.
1851   These are the QWORD Address Space Descriptor, and the End Tag. The QWORD
1852   Address Space Descriptor can describe memory, I/O, and bus number ranges for
1853   dynamic or fixed resources. The configuration of a PCI root bridge is described
1854   with one or more QWORD Address Space Descriptors followed by an End Tag.
1855
1856   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1857   @param[out]  Resources   A pointer to the resource descriptors that
1858                            describe the current configuration of this PCI root
1859                            bridge. The storage for the resource
1860                            descriptors is allocated by this function. The
1861                            caller must treat the return buffer as read-only
1862                            data, and the buffer must not be freed by the
1863                            caller.
1864
1865   @retval  EFI_SUCCESS     The current configuration of this PCI root bridge
1866                            was returned in Resources.
1867   @retval  EFI_UNSUPPORTED The current configuration of this PCI root bridge
1868                            could not be retrieved.
1869 **/
1870 EFI_STATUS
1871 EFIAPI
1872 RootBridgeIoConfiguration (
1873   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
1874   OUT VOID                             **Resources
1875   )
1876 {
1877   PCI_RESOURCE_TYPE                  Index;
1878   PCI_ROOT_BRIDGE_INSTANCE           *RootBridge;
1879   PCI_RES_NODE                       *ResAllocNode;
1880   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  *Descriptor;
1881   EFI_ACPI_END_TAG_DESCRIPTOR        *End;
1882
1883   //
1884   // Get this instance of the Root Bridge.
1885   //
1886   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1887   ZeroMem (
1888     RootBridge->ConfigBuffer,
1889     TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)
1890     );
1891   Descriptor = RootBridge->ConfigBuffer;
1892   for (Index = TypeIo; Index < TypeMax; Index++) {
1893     ResAllocNode = &RootBridge->ResAllocNode[Index];
1894
1895     if (ResAllocNode->Status != ResAllocated) {
1896       continue;
1897     }
1898
1899     Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1900     Descriptor->Len  = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
1901     // According to UEFI 2.7, RootBridgeIo->Configuration should return address
1902     // range in CPU view (host address), and ResAllocNode->Base is already a CPU
1903     // view address (host address).
1904     Descriptor->AddrRangeMin          = ResAllocNode->Base;
1905     Descriptor->AddrRangeMax          = ResAllocNode->Base + ResAllocNode->Length - 1;
1906     Descriptor->AddrLen               = ResAllocNode->Length;
1907     Descriptor->AddrTranslationOffset = GetTranslationByResourceType (
1908                                           RootBridge,
1909                                           ResAllocNode->Type
1910                                           );
1911
1912     switch (ResAllocNode->Type) {
1913       case TypeIo:
1914         Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
1915         break;
1916
1917       case TypePMem32:
1918         Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
1919       case TypeMem32:
1920         Descriptor->ResType              = ACPI_ADDRESS_SPACE_TYPE_MEM;
1921         Descriptor->AddrSpaceGranularity = 32;
1922         break;
1923
1924       case TypePMem64:
1925         Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
1926       case TypeMem64:
1927         Descriptor->ResType              = ACPI_ADDRESS_SPACE_TYPE_MEM;
1928         Descriptor->AddrSpaceGranularity = 64;
1929         break;
1930
1931       case TypeBus:
1932         Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;
1933         break;
1934
1935       default:
1936         break;
1937     }
1938
1939     Descriptor++;
1940   }
1941
1942   //
1943   // Terminate the entries.
1944   //
1945   End           = (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor;
1946   End->Desc     = ACPI_END_TAG_DESCRIPTOR;
1947   End->Checksum = 0x0;
1948
1949   *Resources = RootBridge->ConfigBuffer;
1950   return EFI_SUCCESS;
1951 }