MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c

   1 /** @file
   2
   3   PCI Root Bridge Io Protocol code.
   4
   5 Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
   6 This program and the accompanying materials
   7 are licensed and made available under the terms and conditions of the BSD License
   8 which accompanies this distribution.  The full text of the license may be found at
   9 http://opensource.org/licenses/bsd-license.php
  10
  11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #include "PciHostBridge.h"
  17 #include "PciRootBridge.h"
  18 #include "PciHostResource.h"
  19
  20 extern EDKII_IOMMU_PROTOCOL        *mIoMmuProtocol;
  21
  22 #define NO_MAPPING  (VOID *) (UINTN) -1
  23
  24 //
  25 // Lookup table for increment values based on transfer widths
  26 //
  27 UINT8 mInStride[] = {
  28   1, // EfiPciWidthUint8
  29   2, // EfiPciWidthUint16
  30   4, // EfiPciWidthUint32
  31   8, // EfiPciWidthUint64
  32   0, // EfiPciWidthFifoUint8
  33   0, // EfiPciWidthFifoUint16
  34   0, // EfiPciWidthFifoUint32
  35   0, // EfiPciWidthFifoUint64
  36   1, // EfiPciWidthFillUint8
  37   2, // EfiPciWidthFillUint16
  38   4, // EfiPciWidthFillUint32
  39   8  // EfiPciWidthFillUint64
  40 };
  41
  42 //
  43 // Lookup table for increment values based on transfer widths
  44 //
  45 UINT8 mOutStride[] = {
  46   1, // EfiPciWidthUint8
  47   2, // EfiPciWidthUint16
  48   4, // EfiPciWidthUint32
  49   8, // EfiPciWidthUint64
  50   1, // EfiPciWidthFifoUint8
  51   2, // EfiPciWidthFifoUint16
  52   4, // EfiPciWidthFifoUint32
  53   8, // EfiPciWidthFifoUint64
  54   0, // EfiPciWidthFillUint8
  55   0, // EfiPciWidthFillUint16
  56   0, // EfiPciWidthFillUint32
  57   0  // EfiPciWidthFillUint64
  58 };
  59
  60 /**
  61   Construct the Pci Root Bridge instance.
  62
  63   @param Bridge            The root bridge instance.
  64
  65   @return The pointer to PCI_ROOT_BRIDGE_INSTANCE just created
  66           or NULL if creation fails.
  67 **/
  68 PCI_ROOT_BRIDGE_INSTANCE *
  69 CreateRootBridge (
  70   IN PCI_ROOT_BRIDGE       *Bridge
  71   )
  72 {
  73   PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
  74   PCI_RESOURCE_TYPE        Index;
  75   CHAR16                   *DevicePathStr;
  76   PCI_ROOT_BRIDGE_APERTURE *Aperture;
  77
  78   DevicePathStr = NULL;
  79
  80   DEBUG ((EFI_D_INFO, "RootBridge: "));
  81   DEBUG ((EFI_D_INFO, "%s\n", DevicePathStr = ConvertDevicePathToText (Bridge->DevicePath, FALSE, FALSE)));
  82   DEBUG ((EFI_D_INFO, "  Support/Attr: %lx / %lx\n", Bridge->Supports, Bridge->Attributes));
  83   DEBUG ((EFI_D_INFO, "    DmaAbove4G: %s\n", Bridge->DmaAbove4G ? L"Yes" : L"No"));
  84   DEBUG ((EFI_D_INFO, "NoExtConfSpace: %s\n", Bridge->NoExtendedConfigSpace ? L"Yes" : L"No"));
  85   DEBUG ((EFI_D_INFO, "     AllocAttr: %lx (%s%s)\n", Bridge->AllocationAttributes,
  86           (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0 ? L"CombineMemPMem " : L"",
  87           (Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0 ? L"Mem64Decode" : L""
  88           ));
  89   DEBUG ((EFI_D_INFO, "           Bus: %lx - %lx\n", Bridge->Bus.Base, Bridge->Bus.Limit));
  90   DEBUG ((EFI_D_INFO, "            Io: %lx - %lx\n", Bridge->Io.Base, Bridge->Io.Limit));
  91   DEBUG ((EFI_D_INFO, "           Mem: %lx - %lx\n", Bridge->Mem.Base, Bridge->Mem.Limit));
  92   DEBUG ((EFI_D_INFO, "    MemAbove4G: %lx - %lx\n", Bridge->MemAbove4G.Base, Bridge->MemAbove4G.Limit));
  93   DEBUG ((EFI_D_INFO, "          PMem: %lx - %lx\n", Bridge->PMem.Base, Bridge->PMem.Limit));
  94   DEBUG ((EFI_D_INFO, "   PMemAbove4G: %lx - %lx\n", Bridge->PMemAbove4G.Base, Bridge->PMemAbove4G.Limit));
  95
  96   //
  97   // Make sure Mem and MemAbove4G apertures are valid
  98   //
  99   if (Bridge->Mem.Base <= Bridge->Mem.Limit) {
 100     ASSERT (Bridge->Mem.Limit < SIZE_4GB);
 101     if (Bridge->Mem.Limit >= SIZE_4GB) {
 102       return NULL;
 103     }
 104   }
 105   if (Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) {
 106     ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB);
 107     if (Bridge->MemAbove4G.Base < SIZE_4GB) {
 108       return NULL;
 109     }
 110   }
 111   if (Bridge->PMem.Base <= Bridge->PMem.Limit) {
 112     ASSERT (Bridge->PMem.Limit < SIZE_4GB);
 113     if (Bridge->PMem.Limit >= SIZE_4GB) {
 114       return NULL;
 115     }
 116   }
 117   if (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) {
 118     ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB);
 119     if (Bridge->PMemAbove4G.Base < SIZE_4GB) {
 120       return NULL;
 121     }
 122   }
 123
 124   //
 125   // Ignore AllocationAttributes when resources were already assigned.
 126   //
 127   if (!Bridge->ResourceAssigned) {
 128     if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) {
 129       //
 130       // If this bit is set, then the PCI Root Bridge does not
 131       // support separate windows for Non-prefetchable and Prefetchable
 132       // memory.
 133       //
 134       ASSERT (Bridge->PMem.Base > Bridge->PMem.Limit);
 135       ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);
 136       if ((Bridge->PMem.Base <= Bridge->PMem.Limit) ||
 137           (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)
 138           ) {
 139         return NULL;
 140       }
 141     }
 142
 143     if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) == 0) {
 144       //
 145       // If this bit is not set, then the PCI Root Bridge does not support
 146       // 64 bit memory windows.
 147       //
 148       ASSERT (Bridge->MemAbove4G.Base > Bridge->MemAbove4G.Limit);
 149       ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);
 150       if ((Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) ||
 151           (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)
 152           ) {
 153         return NULL;
 154       }
 155     }
 156   }
 157
 158   RootBridge = AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE_INSTANCE));
 159   ASSERT (RootBridge != NULL);
 160
 161   RootBridge->Signature = PCI_ROOT_BRIDGE_SIGNATURE;
 162   RootBridge->Supports = Bridge->Supports;
 163   RootBridge->Attributes = Bridge->Attributes;
 164   RootBridge->DmaAbove4G = Bridge->DmaAbove4G;
 165   RootBridge->NoExtendedConfigSpace = Bridge->NoExtendedConfigSpace;
 166   RootBridge->AllocationAttributes = Bridge->AllocationAttributes;
 167   RootBridge->DevicePath = DuplicateDevicePath (Bridge->DevicePath);
 168   RootBridge->DevicePathStr = DevicePathStr;
 169   RootBridge->ConfigBuffer = AllocatePool (
 170     TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)
 171     );
 172   ASSERT (RootBridge->ConfigBuffer != NULL);
 173   InitializeListHead (&RootBridge->Maps);
 174
 175   CopyMem (&RootBridge->Bus, &Bridge->Bus, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 176   CopyMem (&RootBridge->Io, &Bridge->Io, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 177   CopyMem (&RootBridge->Mem, &Bridge->Mem, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 178   CopyMem (&RootBridge->MemAbove4G, &Bridge->MemAbove4G, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 179   CopyMem (&RootBridge->PMem, &Bridge->PMem, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 180   CopyMem (&RootBridge->PMemAbove4G, &Bridge->PMemAbove4G, sizeof (PCI_ROOT_BRIDGE_APERTURE));
 181
 182   for (Index = TypeIo; Index < TypeMax; Index++) {
 183     switch (Index) {
 184     case TypeBus:
 185       Aperture = &RootBridge->Bus;
 186       break;
 187     case TypeIo:
 188       Aperture = &RootBridge->Io;
 189       break;
 190     case TypeMem32:
 191       Aperture = &RootBridge->Mem;
 192       break;
 193     case TypeMem64:
 194       Aperture = &RootBridge->MemAbove4G;
 195       break;
 196     case TypePMem32:
 197       Aperture = &RootBridge->PMem;
 198       break;
 199     case TypePMem64:
 200       Aperture = &RootBridge->PMemAbove4G;
 201       break;
 202     default:
 203       ASSERT (FALSE);
 204       Aperture = NULL;
 205       break;
 206     }
 207     RootBridge->ResAllocNode[Index].Type     = Index;
 208     if (Bridge->ResourceAssigned && (Aperture->Limit >= Aperture->Base)) {
 209       RootBridge->ResAllocNode[Index].Base   = Aperture->Base;
 210       RootBridge->ResAllocNode[Index].Length = Aperture->Limit - Aperture->Base + 1;
 211       RootBridge->ResAllocNode[Index].Status = ResAllocated;
 212     } else {
 213       RootBridge->ResAllocNode[Index].Base   = 0;
 214       RootBridge->ResAllocNode[Index].Length = 0;
 215       RootBridge->ResAllocNode[Index].Status = ResNone;
 216     }
 217   }
 218
 219   RootBridge->RootBridgeIo.SegmentNumber  = Bridge->Segment;
 220   RootBridge->RootBridgeIo.PollMem        = RootBridgeIoPollMem;
 221   RootBridge->RootBridgeIo.PollIo         = RootBridgeIoPollIo;
 222   RootBridge->RootBridgeIo.Mem.Read       = RootBridgeIoMemRead;
 223   RootBridge->RootBridgeIo.Mem.Write      = RootBridgeIoMemWrite;
 224   RootBridge->RootBridgeIo.Io.Read        = RootBridgeIoIoRead;
 225   RootBridge->RootBridgeIo.Io.Write       = RootBridgeIoIoWrite;
 226   RootBridge->RootBridgeIo.CopyMem        = RootBridgeIoCopyMem;
 227   RootBridge->RootBridgeIo.Pci.Read       = RootBridgeIoPciRead;
 228   RootBridge->RootBridgeIo.Pci.Write      = RootBridgeIoPciWrite;
 229   RootBridge->RootBridgeIo.Map            = RootBridgeIoMap;
 230   RootBridge->RootBridgeIo.Unmap          = RootBridgeIoUnmap;
 231   RootBridge->RootBridgeIo.AllocateBuffer = RootBridgeIoAllocateBuffer;
 232   RootBridge->RootBridgeIo.FreeBuffer     = RootBridgeIoFreeBuffer;
 233   RootBridge->RootBridgeIo.Flush          = RootBridgeIoFlush;
 234   RootBridge->RootBridgeIo.GetAttributes  = RootBridgeIoGetAttributes;
 235   RootBridge->RootBridgeIo.SetAttributes  = RootBridgeIoSetAttributes;
 236   RootBridge->RootBridgeIo.Configuration  = RootBridgeIoConfiguration;
 237
 238   return RootBridge;
 239 }
 240
 241 /**
 242   Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.
 243
 244   The I/O operations are carried out exactly as requested. The caller is
 245   responsible for satisfying any alignment and I/O width restrictions that a PI
 246   System on a platform might require. For example on some platforms, width
 247   requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other
 248   hand, will be handled by the driver.
 249
 250   @param[in] This           A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 251
 252   @param[in] OperationType  I/O operation type: IO/MMIO/PCI.
 253
 254   @param[in] Width          Signifies the width of the I/O or Memory operation.
 255
 256   @param[in] Address        The base address of the I/O operation.
 257
 258   @param[in] Count          The number of I/O operations to perform. The number
 259                             of bytes moved is Width size * Count, starting at
 260                             Address.
 261
 262   @param[in] Buffer         For read operations, the destination buffer to
 263                             store the results. For write operations, the source
 264                             buffer from which to write data.
 265
 266   @retval EFI_SUCCESS            The parameters for this request pass the
 267                                  checks.
 268
 269   @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
 270
 271   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
 272
 273   @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
 274
 275   @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
 276                                  and Count is not valid for this PI system.
 277 **/
 278 EFI_STATUS
 279 RootBridgeIoCheckParameter (
 280   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 281   IN OPERATION_TYPE                         OperationType,
 282   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 283   IN UINT64                                 Address,
 284   IN UINTN                                  Count,
 285   IN VOID                                   *Buffer
 286   )
 287 {
 288   PCI_ROOT_BRIDGE_INSTANCE                     *RootBridge;
 289   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS  *PciRbAddr;
 290   UINT64                                       Base;
 291   UINT64                                       Limit;
 292   UINT32                                       Size;
 293
 294   //
 295   // Check to see if Buffer is NULL
 296   //
 297   if (Buffer == NULL) {
 298     return EFI_INVALID_PARAMETER;
 299   }
 300
 301   //
 302   // Check to see if Width is in the valid range
 303   //
 304   if ((UINT32) Width >= EfiPciWidthMaximum) {
 305     return EFI_INVALID_PARAMETER;
 306   }
 307
 308   //
 309   // For FIFO type, the target address won't increase during the access,
 310   // so treat Count as 1
 311   //
 312   if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
 313     Count = 1;
 314   }
 315
 316   Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
 317   Size  = 1 << Width;
 318
 319   //
 320   // Check to see if Address is aligned
 321   //
 322   if ((Address & (Size - 1)) != 0) {
 323     return EFI_UNSUPPORTED;
 324   }
 325
 326   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
 327
 328   //
 329   // Check to see if any address associated with this transfer exceeds the
 330   // maximum allowed address.  The maximum address implied by the parameters
 331   // passed in is Address + Size * Count.  If the following condition is met,
 332   // then the transfer is not supported.
 333   //
 334   //    Address + Size * Count > Limit + 1
 335   //
 336   // Since Limit can be the maximum integer value supported by the CPU and
 337   // Count can also be the maximum integer value supported by the CPU, this
 338   // range check must be adjusted to avoid all oveflow conditions.
 339   //
 340   if (OperationType == IoOperation) {
 341     //
 342     // Allow Legacy IO access
 343     //
 344     if (Address + MultU64x32 (Count, Size) <= 0x1000) {
 345       if ((RootBridge->Attributes & (
 346            EFI_PCI_ATTRIBUTE_ISA_IO | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_ATTRIBUTE_VGA_IO |
 347            EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |
 348            EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_ATTRIBUTE_VGA_IO_16)) != 0) {
 349         return EFI_SUCCESS;
 350       }
 351     }
 352     Base = RootBridge->Io.Base;
 353     Limit = RootBridge->Io.Limit;
 354   } else if (OperationType == MemOperation) {
 355     //
 356     // Allow Legacy MMIO access
 357     //
 358     if ((Address >= 0xA0000) && (Address + MultU64x32 (Count, Size)) <= 0xC0000) {
 359       if ((RootBridge->Attributes & EFI_PCI_ATTRIBUTE_VGA_MEMORY) != 0) {
 360         return EFI_SUCCESS;
 361       }
 362     }
 363     //
 364     // By comparing the Address against Limit we know which range to be used
 365     // for checking
 366     //
 367     if (Address + MultU64x32 (Count, Size) <= RootBridge->Mem.Limit + 1) {
 368       Base = RootBridge->Mem.Base;
 369       Limit = RootBridge->Mem.Limit;
 370     } else {
 371       Base = RootBridge->MemAbove4G.Base;
 372       Limit = RootBridge->MemAbove4G.Limit;
 373     }
 374   } else {
 375     PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;
 376     if (PciRbAddr->Bus < RootBridge->Bus.Base ||
 377         PciRbAddr->Bus > RootBridge->Bus.Limit) {
 378       return EFI_INVALID_PARAMETER;
 379     }
 380
 381     if (PciRbAddr->Device > PCI_MAX_DEVICE ||
 382         PciRbAddr->Function > PCI_MAX_FUNC) {
 383       return EFI_INVALID_PARAMETER;
 384     }
 385
 386     if (PciRbAddr->ExtendedRegister != 0) {
 387       Address = PciRbAddr->ExtendedRegister;
 388     } else {
 389       Address = PciRbAddr->Register;
 390     }
 391     Base = 0;
 392     Limit = RootBridge->NoExtendedConfigSpace ? 0xFF : 0xFFF;
 393   }
 394
 395   if (Address < Base) {
 396       return EFI_INVALID_PARAMETER;
 397   }
 398
 399   if (Address + MultU64x32 (Count, Size) > Limit + 1) {
 400     return EFI_INVALID_PARAMETER;
 401   }
 402
 403   return EFI_SUCCESS;
 404 }
 405
 406 /**
 407   Polls an address in memory mapped I/O space until an exit condition is met,
 408   or a timeout occurs.
 409
 410   This function provides a standard way to poll a PCI memory location. A PCI
 411   memory read operation is performed at the PCI memory address specified by
 412   Address for the width specified by Width. The result of this PCI memory read
 413   operation is stored in Result. This PCI memory read operation is repeated
 414   until either a timeout of Delay 100 ns units has expired, or (Result & Mask)
 415   is equal to Value.
 416
 417   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 418   @param[in]   Width     Signifies the width of the memory operations.
 419   @param[in]   Address   The base address of the memory operations. The caller
 420                          is responsible for aligning Address if required.
 421   @param[in]   Mask      Mask used for the polling criteria. Bytes above Width
 422                          in Mask are ignored. The bits in the bytes below Width
 423                          which are zero in Mask are ignored when polling the
 424                          memory address.
 425   @param[in]   Value     The comparison value used for the polling exit
 426                          criteria.
 427   @param[in]   Delay     The number of 100 ns units to poll. Note that timer
 428                          available may be of poorer granularity.
 429   @param[out]  Result    Pointer to the last value read from the memory
 430                          location.
 431
 432   @retval EFI_SUCCESS            The last data returned from the access matched
 433                                  the poll exit criteria.
 434   @retval EFI_INVALID_PARAMETER  Width is invalid.
 435   @retval EFI_INVALID_PARAMETER  Result is NULL.
 436   @retval EFI_TIMEOUT            Delay expired before a match occurred.
 437   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
 438                                  lack of resources.
 439 **/
 440 EFI_STATUS
 441 EFIAPI
 442 RootBridgeIoPollMem (
 443   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 444   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 445   IN  UINT64                                 Address,
 446   IN  UINT64                                 Mask,
 447   IN  UINT64                                 Value,
 448   IN  UINT64                                 Delay,
 449   OUT UINT64                                 *Result
 450   )
 451 {
 452   EFI_STATUS  Status;
 453   UINT64      NumberOfTicks;
 454   UINT32      Remainder;
 455
 456   if (Result == NULL) {
 457     return EFI_INVALID_PARAMETER;
 458   }
 459
 460   if ((UINT32)Width > EfiPciWidthUint64) {
 461     return EFI_INVALID_PARAMETER;
 462   }
 463
 464   //
 465   // No matter what, always do a single poll.
 466   //
 467   Status = This->Mem.Read (This, Width, Address, 1, Result);
 468   if (EFI_ERROR (Status)) {
 469     return Status;
 470   }
 471
 472   if ((*Result & Mask) == Value) {
 473     return EFI_SUCCESS;
 474   }
 475
 476   if (Delay == 0) {
 477     return EFI_SUCCESS;
 478
 479   } else {
 480
 481     //
 482     // Determine the proper # of metronome ticks to wait for polling the
 483     // location.  The nuber of ticks is Roundup (Delay /
 484     // mMetronome->TickPeriod)+1
 485     // The "+1" to account for the possibility of the first tick being short
 486     // because we started in the middle of a tick.
 487     //
 488     // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome
 489     // protocol definition is updated.
 490     //
 491     NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod,
 492                       &Remainder);
 493     if (Remainder != 0) {
 494       NumberOfTicks += 1;
 495     }
 496     NumberOfTicks += 1;
 497
 498     while (NumberOfTicks != 0) {
 499
 500       mMetronome->WaitForTick (mMetronome, 1);
 501
 502       Status = This->Mem.Read (This, Width, Address, 1, Result);
 503       if (EFI_ERROR (Status)) {
 504         return Status;
 505       }
 506
 507       if ((*Result & Mask) == Value) {
 508         return EFI_SUCCESS;
 509       }
 510
 511       NumberOfTicks -= 1;
 512     }
 513   }
 514   return EFI_TIMEOUT;
 515 }
 516
 517 /**
 518   Reads from the I/O space of a PCI Root Bridge. Returns when either the
 519   polling exit criteria is satisfied or after a defined duration.
 520
 521   This function provides a standard way to poll a PCI I/O location. A PCI I/O
 522   read operation is performed at the PCI I/O address specified by Address for
 523   the width specified by Width.
 524   The result of this PCI I/O read operation is stored in Result. This PCI I/O
 525   read operation is repeated until either a timeout of Delay 100 ns units has
 526   expired, or (Result & Mask) is equal to Value.
 527
 528   @param[in] This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 529   @param[in] Width     Signifies the width of the I/O operations.
 530   @param[in] Address   The base address of the I/O operations. The caller is
 531                        responsible for aligning Address if required.
 532   @param[in] Mask      Mask used for the polling criteria. Bytes above Width in
 533                        Mask are ignored. The bits in the bytes below Width
 534                        which are zero in Mask are ignored when polling the I/O
 535                        address.
 536   @param[in] Value     The comparison value used for the polling exit criteria.
 537   @param[in] Delay     The number of 100 ns units to poll. Note that timer
 538                        available may be of poorer granularity.
 539   @param[out] Result   Pointer to the last value read from the memory location.
 540
 541   @retval EFI_SUCCESS            The last data returned from the access matched
 542                                  the poll exit criteria.
 543   @retval EFI_INVALID_PARAMETER  Width is invalid.
 544   @retval EFI_INVALID_PARAMETER  Result is NULL.
 545   @retval EFI_TIMEOUT            Delay expired before a match occurred.
 546   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
 547                                  lack of resources.
 548 **/
 549 EFI_STATUS
 550 EFIAPI
 551 RootBridgeIoPollIo (
 552   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 553   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 554   IN  UINT64                                 Address,
 555   IN  UINT64                                 Mask,
 556   IN  UINT64                                 Value,
 557   IN  UINT64                                 Delay,
 558   OUT UINT64                                 *Result
 559   )
 560 {
 561   EFI_STATUS  Status;
 562   UINT64      NumberOfTicks;
 563   UINT32      Remainder;
 564
 565   //
 566   // No matter what, always do a single poll.
 567   //
 568
 569   if (Result == NULL) {
 570     return EFI_INVALID_PARAMETER;
 571   }
 572
 573   if ((UINT32)Width > EfiPciWidthUint64) {
 574     return EFI_INVALID_PARAMETER;
 575   }
 576
 577   Status = This->Io.Read (This, Width, Address, 1, Result);
 578   if (EFI_ERROR (Status)) {
 579     return Status;
 580   }
 581   if ((*Result & Mask) == Value) {
 582     return EFI_SUCCESS;
 583   }
 584
 585   if (Delay == 0) {
 586     return EFI_SUCCESS;
 587
 588   } else {
 589
 590     //
 591     // Determine the proper # of metronome ticks to wait for polling the
 592     // location.  The number of ticks is Roundup (Delay /
 593     // mMetronome->TickPeriod)+1
 594     // The "+1" to account for the possibility of the first tick being short
 595     // because we started in the middle of a tick.
 596     //
 597     NumberOfTicks = DivU64x32Remainder (Delay, (UINT32)mMetronome->TickPeriod,
 598                       &Remainder);
 599     if (Remainder != 0) {
 600       NumberOfTicks += 1;
 601     }
 602     NumberOfTicks += 1;
 603
 604     while (NumberOfTicks != 0) {
 605
 606       mMetronome->WaitForTick (mMetronome, 1);
 607
 608       Status = This->Io.Read (This, Width, Address, 1, Result);
 609       if (EFI_ERROR (Status)) {
 610         return Status;
 611       }
 612
 613       if ((*Result & Mask) == Value) {
 614         return EFI_SUCCESS;
 615       }
 616
 617       NumberOfTicks -= 1;
 618     }
 619   }
 620   return EFI_TIMEOUT;
 621 }
 622
 623 /**
 624   Enables a PCI driver to access PCI controller registers in the PCI root
 625   bridge memory space.
 626
 627   The Mem.Read(), and Mem.Write() functions enable a driver to access PCI
 628   controller registers in the PCI root bridge memory space.
 629   The memory operations are carried out exactly as requested. The caller is
 630   responsible for satisfying any alignment and memory width restrictions that a
 631   PCI Root Bridge on a platform might require.
 632
 633   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 634   @param[in]   Width     Signifies the width of the memory operation.
 635   @param[in]   Address   The base address of the memory operation. The caller
 636                          is responsible for aligning the Address if required.
 637   @param[in]   Count     The number of memory operations to perform. Bytes
 638                          moved is Width size * Count, starting at Address.
 639   @param[out]  Buffer    For read operations, the destination buffer to store
 640                          the results. For write operations, the source buffer
 641                          to write data from.
 642
 643   @retval EFI_SUCCESS            The data was read from or written to the PCI
 644                                  root bridge.
 645   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.
 646   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
 647   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
 648                                  lack of resources.
 649 **/
 650 EFI_STATUS
 651 EFIAPI
 652 RootBridgeIoMemRead (
 653   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 654   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 655   IN     UINT64                                 Address,
 656   IN     UINTN                                  Count,
 657   OUT    VOID                                   *Buffer
 658   )
 659 {
 660   EFI_STATUS                             Status;
 661
 662   Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address,
 663                                        Count, Buffer);
 664   if (EFI_ERROR (Status)) {
 665     return Status;
 666   }
 667   return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address, Count, Buffer);
 668 }
 669
 670 /**
 671   Enables a PCI driver to access PCI controller registers in the PCI root
 672   bridge memory space.
 673
 674   The Mem.Read(), and Mem.Write() functions enable a driver to access PCI
 675   controller registers in the PCI root bridge memory space.
 676   The memory operations are carried out exactly as requested. The caller is
 677   responsible for satisfying any alignment and memory width restrictions that a
 678   PCI Root Bridge on a platform might require.
 679
 680   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 681   @param[in]   Width     Signifies the width of the memory operation.
 682   @param[in]   Address   The base address of the memory operation. The caller
 683                          is responsible for aligning the Address if required.
 684   @param[in]   Count     The number of memory operations to perform. Bytes
 685                          moved is Width size * Count, starting at Address.
 686   @param[in]   Buffer    For read operations, the destination buffer to store
 687                          the results. For write operations, the source buffer
 688                          to write data from.
 689
 690   @retval EFI_SUCCESS            The data was read from or written to the PCI
 691                                  root bridge.
 692   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.
 693   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
 694   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
 695                                  lack of resources.
 696 **/
 697 EFI_STATUS
 698 EFIAPI
 699 RootBridgeIoMemWrite (
 700   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 701   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 702   IN     UINT64                                 Address,
 703   IN     UINTN                                  Count,
 704   IN     VOID                                   *Buffer
 705   )
 706 {
 707   EFI_STATUS                             Status;
 708
 709   Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address,
 710                                        Count, Buffer);
 711   if (EFI_ERROR (Status)) {
 712     return Status;
 713   }
 714   return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address, Count, Buffer);
 715 }
 716
 717 /**
 718   Enables a PCI driver to access PCI controller registers in the PCI root
 719   bridge I/O space.
 720
 721   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 722   @param[in]   Width       Signifies the width of the memory operations.
 723   @param[in]   Address     The base address of the I/O operation. The caller is
 724                            responsible for aligning the Address if required.
 725   @param[in]   Count       The number of I/O operations to perform. Bytes moved
 726                            is Width size * Count, starting at Address.
 727   @param[out]  Buffer      For read operations, the destination buffer to store
 728                            the results. For write operations, the source buffer
 729                            to write data from.
 730
 731   @retval EFI_SUCCESS              The data was read from or written to the PCI
 732                                    root bridge.
 733   @retval EFI_INVALID_PARAMETER    Width is invalid for this PCI root bridge.
 734   @retval EFI_INVALID_PARAMETER    Buffer is NULL.
 735   @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a
 736                                    lack of resources.
 737 **/
 738 EFI_STATUS
 739 EFIAPI
 740 RootBridgeIoIoRead (
 741   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,
 742   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 743   IN     UINT64                                 Address,
 744   IN     UINTN                                  Count,
 745   OUT    VOID                                   *Buffer
 746   )
 747 {
 748   EFI_STATUS                                    Status;
 749   Status = RootBridgeIoCheckParameter (
 750              This, IoOperation, Width,
 751              Address, Count, Buffer
 752              );
 753   if (EFI_ERROR (Status)) {
 754     return Status;
 755   }
 756   return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address, Count, Buffer);
 757 }
 758
 759 /**
 760   Enables a PCI driver to access PCI controller registers in the PCI root
 761   bridge I/O space.
 762
 763   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 764   @param[in]   Width       Signifies the width of the memory operations.
 765   @param[in]   Address     The base address of the I/O operation. The caller is
 766                            responsible for aligning the Address if required.
 767   @param[in]   Count       The number of I/O operations to perform. Bytes moved
 768                            is Width size * Count, starting at Address.
 769   @param[in]   Buffer      For read operations, the destination buffer to store
 770                            the results. For write operations, the source buffer
 771                            to write data from.
 772
 773   @retval EFI_SUCCESS              The data was read from or written to the PCI
 774                                    root bridge.
 775   @retval EFI_INVALID_PARAMETER    Width is invalid for this PCI root bridge.
 776   @retval EFI_INVALID_PARAMETER    Buffer is NULL.
 777   @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a
 778                                    lack of resources.
 779 **/
 780 EFI_STATUS
 781 EFIAPI
 782 RootBridgeIoIoWrite (
 783   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL         *This,
 784   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH   Width,
 785   IN       UINT64                                  Address,
 786   IN       UINTN                                   Count,
 787   IN       VOID                                    *Buffer
 788   )
 789 {
 790   EFI_STATUS                                    Status;
 791   Status = RootBridgeIoCheckParameter (
 792              This, IoOperation, Width,
 793              Address, Count, Buffer
 794              );
 795   if (EFI_ERROR (Status)) {
 796     return Status;
 797   }
 798   return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) Width, Address, Count, Buffer);
 799 }
 800
 801 /**
 802   Enables a PCI driver to copy one region of PCI root bridge memory space to
 803   another region of PCI root bridge memory space.
 804
 805   The CopyMem() function enables a PCI driver to copy one region of PCI root
 806   bridge memory space to another region of PCI root bridge memory space. This
 807   is especially useful for video scroll operation on a memory mapped video
 808   buffer.
 809   The memory operations are carried out exactly as requested. The caller is
 810   responsible for satisfying any alignment and memory width restrictions that a
 811   PCI root bridge on a platform might require.
 812
 813   @param[in] This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
 814                          instance.
 815   @param[in] Width       Signifies the width of the memory operations.
 816   @param[in] DestAddress The destination address of the memory operation. The
 817                          caller is responsible for aligning the DestAddress if
 818                          required.
 819   @param[in] SrcAddress  The source address of the memory operation. The caller
 820                          is responsible for aligning the SrcAddress if
 821                          required.
 822   @param[in] Count       The number of memory operations to perform. Bytes
 823                          moved is Width size * Count, starting at DestAddress
 824                          and SrcAddress.
 825
 826   @retval  EFI_SUCCESS             The data was copied from one memory region
 827                                    to another memory region.
 828   @retval  EFI_INVALID_PARAMETER   Width is invalid for this PCI root bridge.
 829   @retval  EFI_OUT_OF_RESOURCES    The request could not be completed due to a
 830                                    lack of resources.
 831 **/
 832 EFI_STATUS
 833 EFIAPI
 834 RootBridgeIoCopyMem (
 835   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,
 836   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH        Width,
 837   IN UINT64                                       DestAddress,
 838   IN UINT64                                       SrcAddress,
 839   IN UINTN                                        Count
 840   )
 841 {
 842   EFI_STATUS  Status;
 843   BOOLEAN     Forward;
 844   UINTN       Stride;
 845   UINTN       Index;
 846   UINT64      Result;
 847
 848   if ((UINT32) Width > EfiPciWidthUint64) {
 849     return EFI_INVALID_PARAMETER;
 850   }
 851
 852   if (DestAddress == SrcAddress) {
 853     return EFI_SUCCESS;
 854   }
 855
 856   Stride = (UINTN) (1 << Width);
 857
 858   Forward = TRUE;
 859   if ((DestAddress > SrcAddress) &&
 860       (DestAddress < (SrcAddress + Count * Stride))) {
 861     Forward = FALSE;
 862     SrcAddress = SrcAddress + (Count - 1) * Stride;
 863     DestAddress = DestAddress + (Count - 1) * Stride;
 864   }
 865
 866   for (Index = 0; Index < Count; Index++) {
 867     Status = RootBridgeIoMemRead (
 868                This,
 869                Width,
 870                SrcAddress,
 871                1,
 872                &Result
 873                );
 874     if (EFI_ERROR (Status)) {
 875       return Status;
 876     }
 877     Status = RootBridgeIoMemWrite (
 878                This,
 879                Width,
 880                DestAddress,
 881                1,
 882                &Result
 883                );
 884     if (EFI_ERROR (Status)) {
 885       return Status;
 886     }
 887     if (Forward) {
 888       SrcAddress += Stride;
 889       DestAddress += Stride;
 890     } else {
 891       SrcAddress -= Stride;
 892       DestAddress -= Stride;
 893     }
 894   }
 895   return EFI_SUCCESS;
 896 }
 897
 898
 899 /**
 900   PCI configuration space access.
 901
 902   @param This     A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
 903   @param Read     TRUE indicating it's a read operation.
 904   @param Width    Signifies the width of the memory operation.
 905   @param Address  The address within the PCI configuration space
 906                   for the PCI controller.
 907   @param Count    The number of PCI configuration operations
 908                   to perform.
 909   @param Buffer   The destination buffer to store the results.
 910
 911   @retval EFI_SUCCESS            The data was read/written from/to the PCI root bridge.
 912   @retval EFI_INVALID_PARAMETER  Invalid parameters found.
 913 **/
 914 EFI_STATUS
 915 EFIAPI
 916 RootBridgeIoPciAccess (
 917   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       *This,
 918   IN     BOOLEAN                               Read,
 919   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
 920   IN     UINT64                                Address,
 921   IN     UINTN                                 Count,
 922   IN OUT VOID                                  *Buffer
 923   )
 924 {
 925   EFI_STATUS                                   Status;
 926   PCI_ROOT_BRIDGE_INSTANCE                     *RootBridge;
 927   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS  PciAddress;
 928   UINT8                                        *Uint8Buffer;
 929   UINT8                                        InStride;
 930   UINT8                                        OutStride;
 931   UINTN                                        Size;
 932
 933   Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address, Count, Buffer);
 934   if (EFI_ERROR (Status)) {
 935     return Status;
 936   }
 937
 938   //
 939   // Read Pci configuration space
 940   //
 941   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
 942   CopyMem (&PciAddress, &Address, sizeof (PciAddress));
 943
 944   if (PciAddress.ExtendedRegister == 0) {
 945     PciAddress.ExtendedRegister = PciAddress.Register;
 946   }
 947
 948   Address = PCI_SEGMENT_LIB_ADDRESS (
 949               RootBridge->RootBridgeIo.SegmentNumber,
 950               PciAddress.Bus,
 951               PciAddress.Device,
 952               PciAddress.Function,
 953               PciAddress.ExtendedRegister
 954               );
 955
 956   //
 957   // Select loop based on the width of the transfer
 958   //
 959   InStride  = mInStride[Width];
 960   OutStride = mOutStride[Width];
 961   Size      = (UINTN) (1 << (Width & 0x03));
 962   for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
 963     if (Read) {
 964       PciSegmentReadBuffer (Address, Size, Uint8Buffer);
 965     } else {
 966       PciSegmentWriteBuffer (Address, Size, Uint8Buffer);
 967     }
 968   }
 969   return EFI_SUCCESS;
 970 }
 971
 972 /**
 973   Allows read from PCI configuration space.
 974
 975   @param This     A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
 976   @param Width    Signifies the width of the memory operation.
 977   @param Address  The address within the PCI configuration space
 978                   for the PCI controller.
 979   @param Count    The number of PCI configuration operations
 980                   to perform.
 981   @param Buffer   The destination buffer to store the results.
 982
 983   @retval EFI_SUCCESS           The data was read from the PCI root bridge.
 984   @retval EFI_INVALID_PARAMETER Invalid parameters found.
 985 **/
 986 EFI_STATUS
 987 EFIAPI
 988 RootBridgeIoPciRead (
 989   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       *This,
 990   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
 991   IN     UINT64                                Address,
 992   IN     UINTN                                 Count,
 993   IN OUT VOID                                  *Buffer
 994   )
 995 {
 996   return RootBridgeIoPciAccess (This, TRUE, Width, Address, Count, Buffer);
 997 }
 998
 999 /**
1000   Allows write to PCI configuration space.
1001
1002   @param This     A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1003   @param Width    Signifies the width of the memory operation.
1004   @param Address  The address within the PCI configuration space
1005                   for the PCI controller.
1006   @param Count    The number of PCI configuration operations
1007                   to perform.
1008   @param Buffer   The source buffer to get the results.
1009
1010   @retval EFI_SUCCESS            The data was written to the PCI root bridge.
1011   @retval EFI_INVALID_PARAMETER  Invalid parameters found.
1012 **/
1013 EFI_STATUS
1014 EFIAPI
1015 RootBridgeIoPciWrite (
1016   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       *This,
1017   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
1018   IN     UINT64                                Address,
1019   IN     UINTN                                 Count,
1020   IN OUT VOID                                  *Buffer
1021   )
1022 {
1023   return RootBridgeIoPciAccess (This, FALSE, Width, Address, Count, Buffer);
1024 }
1025
1026 /**
1027   Provides the PCI controller-specific address needed to access
1028   system memory for DMA.
1029
1030   @param This           A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1031   @param Operation      Indicate if the bus master is going to read or write
1032                         to system memory.
1033   @param HostAddress    The system memory address to map on the PCI controller.
1034   @param NumberOfBytes  On input the number of bytes to map.
1035                         On output the number of bytes that were mapped.
1036   @param DeviceAddress  The resulting map address for the bus master PCI
1037                         controller to use to access the system memory's HostAddress.
1038   @param Mapping        The value to pass to Unmap() when the bus master DMA
1039                         operation is complete.
1040
1041   @retval EFI_SUCCESS            Success.
1042   @retval EFI_INVALID_PARAMETER  Invalid parameters found.
1043   @retval EFI_UNSUPPORTED        The HostAddress cannot be mapped as a common buffer.
1044   @retval EFI_DEVICE_ERROR       The System hardware could not map the requested address.
1045   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to lack of resources.
1046 **/
1047 EFI_STATUS
1048 EFIAPI
1049 RootBridgeIoMap (
1050   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL            *This,
1051   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  Operation,
1052   IN     VOID                                       *HostAddress,
1053   IN OUT UINTN                                      *NumberOfBytes,
1054   OUT    EFI_PHYSICAL_ADDRESS                       *DeviceAddress,
1055   OUT    VOID                                       **Mapping
1056   )
1057 {
1058   EFI_STATUS                                        Status;
1059   PCI_ROOT_BRIDGE_INSTANCE                          *RootBridge;
1060   EFI_PHYSICAL_ADDRESS                              PhysicalAddress;
1061   MAP_INFO                                          *MapInfo;
1062
1063   if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL ||
1064       Mapping == NULL) {
1065     return EFI_INVALID_PARAMETER;
1066   }
1067
1068   //
1069   // Make sure that Operation is valid
1070   //
1071   if ((UINT32) Operation >= EfiPciOperationMaximum) {
1072     return EFI_INVALID_PARAMETER;
1073   }
1074
1075   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1076
1077   if (mIoMmuProtocol != NULL) {
1078     if (!RootBridge->DmaAbove4G) {
1079       //
1080       // Clear 64bit support
1081       //
1082       if (Operation > EfiPciOperationBusMasterCommonBuffer) {
1083         Operation = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) (Operation - EfiPciOperationBusMasterRead64);
1084       }
1085     }
1086     Status = mIoMmuProtocol->Map (
1087                                mIoMmuProtocol,
1088                                Operation,
1089                                HostAddress,
1090                                NumberOfBytes,
1091                                DeviceAddress,
1092                                Mapping
1093                                );
1094     return Status;
1095   }
1096
1097   PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress;
1098   if ((!RootBridge->DmaAbove4G ||
1099        (Operation != EfiPciOperationBusMasterRead64 &&
1100         Operation != EfiPciOperationBusMasterWrite64 &&
1101         Operation != EfiPciOperationBusMasterCommonBuffer64)) &&
1102       ((PhysicalAddress + *NumberOfBytes) > SIZE_4GB)) {
1103
1104     //
1105     // If the root bridge or the device cannot handle performing DMA above
1106     // 4GB but any part of the DMA transfer being mapped is above 4GB, then
1107     // map the DMA transfer to a buffer below 4GB.
1108     //
1109
1110     if (Operation == EfiPciOperationBusMasterCommonBuffer ||
1111         Operation == EfiPciOperationBusMasterCommonBuffer64) {
1112       //
1113       // Common Buffer operations can not be remapped.  If the common buffer
1114       // if above 4GB, then it is not possible to generate a mapping, so return
1115       // an error.
1116       //
1117       return EFI_UNSUPPORTED;
1118     }
1119
1120     //
1121     // Allocate a MAP_INFO structure to remember the mapping when Unmap() is
1122     // called later.
1123     //
1124     MapInfo = AllocatePool (sizeof (MAP_INFO));
1125     if (MapInfo == NULL) {
1126       *NumberOfBytes = 0;
1127       return EFI_OUT_OF_RESOURCES;
1128     }
1129
1130     //
1131     // Initialize the MAP_INFO structure
1132     //
1133     MapInfo->Signature         = MAP_INFO_SIGNATURE;
1134     MapInfo->Operation         = Operation;
1135     MapInfo->NumberOfBytes     = *NumberOfBytes;
1136     MapInfo->NumberOfPages     = EFI_SIZE_TO_PAGES (MapInfo->NumberOfBytes);
1137     MapInfo->HostAddress       = PhysicalAddress;
1138     MapInfo->MappedHostAddress = SIZE_4GB - 1;
1139
1140     //
1141     // Allocate a buffer below 4GB to map the transfer to.
1142     //
1143     Status = gBS->AllocatePages (
1144                     AllocateMaxAddress,
1145                     EfiBootServicesData,
1146                     MapInfo->NumberOfPages,
1147                     &MapInfo->MappedHostAddress
1148                     );
1149     if (EFI_ERROR (Status)) {
1150       FreePool (MapInfo);
1151       *NumberOfBytes = 0;
1152       return Status;
1153     }
1154
1155     //
1156     // If this is a read operation from the Bus Master's point of view,
1157     // then copy the contents of the real buffer into the mapped buffer
1158     // so the Bus Master can read the contents of the real buffer.
1159     //
1160     if (Operation == EfiPciOperationBusMasterRead ||
1161         Operation == EfiPciOperationBusMasterRead64) {
1162       CopyMem (
1163         (VOID *) (UINTN) MapInfo->MappedHostAddress,
1164         (VOID *) (UINTN) MapInfo->HostAddress,
1165         MapInfo->NumberOfBytes
1166         );
1167     }
1168
1169     InsertTailList (&RootBridge->Maps, &MapInfo->Link);
1170
1171     //
1172     // The DeviceAddress is the address of the maped buffer below 4GB
1173     //
1174     *DeviceAddress = MapInfo->MappedHostAddress;
1175     //
1176     // Return a pointer to the MAP_INFO structure in Mapping
1177     //
1178     *Mapping       = MapInfo;
1179   } else {
1180     //
1181     // If the root bridge CAN handle performing DMA above 4GB or
1182     // the transfer is below 4GB, so the DeviceAddress is simply the
1183     // HostAddress
1184     //
1185     *DeviceAddress = PhysicalAddress;
1186     *Mapping       = NO_MAPPING;
1187   }
1188
1189   return EFI_SUCCESS;
1190 }
1191
1192 /**
1193   Completes the Map() operation and releases any corresponding resources.
1194
1195   The Unmap() function completes the Map() operation and releases any
1196   corresponding resources.
1197   If the operation was an EfiPciOperationBusMasterWrite or
1198   EfiPciOperationBusMasterWrite64, the data is committed to the target system
1199   memory.
1200   Any resources used for the mapping are freed.
1201
1202   @param[in] This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1203   @param[in] Mapping   The mapping value returned from Map().
1204
1205   @retval EFI_SUCCESS            The range was unmapped.
1206   @retval EFI_INVALID_PARAMETER  Mapping is not a value that was returned by Map().
1207   @retval EFI_DEVICE_ERROR       The data was not committed to the target system memory.
1208 **/
1209 EFI_STATUS
1210 EFIAPI
1211 RootBridgeIoUnmap (
1212   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
1213   IN VOID                             *Mapping
1214   )
1215 {
1216   MAP_INFO                 *MapInfo;
1217   LIST_ENTRY               *Link;
1218   PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
1219   EFI_STATUS                Status;
1220
1221   if (mIoMmuProtocol != NULL) {
1222     Status = mIoMmuProtocol->Unmap (
1223                                mIoMmuProtocol,
1224                                Mapping
1225                                );
1226     return Status;
1227   }
1228
1229   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1230
1231   //
1232   // See if the Map() operation associated with this Unmap() required a mapping
1233   // buffer. If a mapping buffer was not required, then this function simply
1234   // returns EFI_SUCCESS.
1235   //
1236   if (Mapping == NO_MAPPING) {
1237     return EFI_SUCCESS;
1238   }
1239
1240   MapInfo = NO_MAPPING;
1241   for (Link = GetFirstNode (&RootBridge->Maps)
1242        ; !IsNull (&RootBridge->Maps, Link)
1243        ; Link = GetNextNode (&RootBridge->Maps, Link)
1244        ) {
1245     MapInfo = MAP_INFO_FROM_LINK (Link);
1246     if (MapInfo == Mapping) {
1247       break;
1248     }
1249   }
1250   //
1251   // Mapping is not a valid value returned by Map()
1252   //
1253   if (MapInfo != Mapping) {
1254     return EFI_INVALID_PARAMETER;
1255   }
1256   RemoveEntryList (&MapInfo->Link);
1257
1258   //
1259   // If this is a write operation from the Bus Master's point of view,
1260   // then copy the contents of the mapped buffer into the real buffer
1261   // so the processor can read the contents of the real buffer.
1262   //
1263   if (MapInfo->Operation == EfiPciOperationBusMasterWrite ||
1264       MapInfo->Operation == EfiPciOperationBusMasterWrite64) {
1265     CopyMem (
1266       (VOID *) (UINTN) MapInfo->HostAddress,
1267       (VOID *) (UINTN) MapInfo->MappedHostAddress,
1268       MapInfo->NumberOfBytes
1269       );
1270   }
1271
1272   //
1273   // Free the mapped buffer and the MAP_INFO structure.
1274   //
1275   gBS->FreePages (MapInfo->MappedHostAddress, MapInfo->NumberOfPages);
1276   FreePool (Mapping);
1277   return EFI_SUCCESS;
1278 }
1279
1280 /**
1281   Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer
1282   or EfiPciOperationBusMasterCommonBuffer64 mapping.
1283
1284   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1285   @param Type        This parameter is not used and must be ignored.
1286   @param MemoryType  The type of memory to allocate, EfiBootServicesData or
1287                      EfiRuntimeServicesData.
1288   @param Pages       The number of pages to allocate.
1289   @param HostAddress A pointer to store the base system memory address of the
1290                      allocated range.
1291   @param Attributes  The requested bit mask of attributes for the allocated
1292                      range. Only the attributes
1293                      EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE,
1294                      EFI_PCI_ATTRIBUTE_MEMORY_CACHED, and
1295                      EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this
1296                      function.
1297
1298   @retval EFI_SUCCESS            The requested memory pages were allocated.
1299   @retval EFI_INVALID_PARAMETER  MemoryType is invalid.
1300   @retval EFI_INVALID_PARAMETER  HostAddress is NULL.
1301   @retval EFI_UNSUPPORTED        Attributes is unsupported. The only legal
1302                                  attribute bits are MEMORY_WRITE_COMBINE,
1303                                  MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
1304   @retval EFI_OUT_OF_RESOURCES   The memory pages could not be allocated.
1305 **/
1306 EFI_STATUS
1307 EFIAPI
1308 RootBridgeIoAllocateBuffer (
1309   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
1310   IN  EFI_ALLOCATE_TYPE                Type,
1311   IN  EFI_MEMORY_TYPE                  MemoryType,
1312   IN  UINTN                            Pages,
1313   OUT VOID                             **HostAddress,
1314   IN  UINT64                           Attributes
1315   )
1316 {
1317   EFI_STATUS                Status;
1318   EFI_PHYSICAL_ADDRESS      PhysicalAddress;
1319   PCI_ROOT_BRIDGE_INSTANCE  *RootBridge;
1320   EFI_ALLOCATE_TYPE         AllocateType;
1321
1322   //
1323   // Validate Attributes
1324   //
1325   if ((Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) != 0) {
1326     return EFI_UNSUPPORTED;
1327   }
1328
1329   //
1330   // Check for invalid inputs
1331   //
1332   if (HostAddress == NULL) {
1333     return EFI_INVALID_PARAMETER;
1334   }
1335
1336   //
1337   // The only valid memory types are EfiBootServicesData and
1338   // EfiRuntimeServicesData
1339   //
1340   if (MemoryType != EfiBootServicesData &&
1341       MemoryType != EfiRuntimeServicesData) {
1342     return EFI_INVALID_PARAMETER;
1343   }
1344
1345   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1346
1347   if (mIoMmuProtocol != NULL) {
1348     if (!RootBridge->DmaAbove4G) {
1349       //
1350       // Clear DUAL_ADDRESS_CYCLE
1351       //
1352       Attributes &= ~EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE;
1353     }
1354     Status = mIoMmuProtocol->AllocateBuffer (
1355                                mIoMmuProtocol,
1356                                Type,
1357                                MemoryType,
1358                                Pages,
1359                                HostAddress,
1360                                Attributes
1361                                );
1362     return Status;
1363   }
1364
1365   AllocateType = AllocateAnyPages;
1366   if (!RootBridge->DmaAbove4G ||
1367       (Attributes & EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE) == 0) {
1368     //
1369     // Limit allocations to memory below 4GB
1370     //
1371     AllocateType    = AllocateMaxAddress;
1372     PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (SIZE_4GB - 1);
1373   }
1374   Status = gBS->AllocatePages (
1375                   AllocateType,
1376                   MemoryType,
1377                   Pages,
1378                   &PhysicalAddress
1379                   );
1380   if (!EFI_ERROR (Status)) {
1381     *HostAddress = (VOID *) (UINTN) PhysicalAddress;
1382   }
1383
1384   return Status;
1385 }
1386
1387 /**
1388   Frees memory that was allocated with AllocateBuffer().
1389
1390   The FreeBuffer() function frees memory that was allocated with
1391   AllocateBuffer().
1392
1393   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1394   @param Pages       The number of pages to free.
1395   @param HostAddress The base system memory address of the allocated range.
1396
1397   @retval EFI_SUCCESS            The requested memory pages were freed.
1398   @retval EFI_INVALID_PARAMETER  The memory range specified by HostAddress and
1399                                  Pages was not allocated with AllocateBuffer().
1400 **/
1401 EFI_STATUS
1402 EFIAPI
1403 RootBridgeIoFreeBuffer (
1404   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
1405   IN  UINTN                            Pages,
1406   OUT VOID                             *HostAddress
1407   )
1408 {
1409   EFI_STATUS                Status;
1410
1411   if (mIoMmuProtocol != NULL) {
1412     Status = mIoMmuProtocol->FreeBuffer (
1413                                mIoMmuProtocol,
1414                                Pages,
1415                                HostAddress
1416                                );
1417     return Status;
1418   }
1419
1420   return gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress, Pages);
1421 }
1422
1423 /**
1424   Flushes all PCI posted write transactions from a PCI host bridge to system
1425   memory.
1426
1427   The Flush() function flushes any PCI posted write transactions from a PCI
1428   host bridge to system memory. Posted write transactions are generated by PCI
1429   bus masters when they perform write transactions to target addresses in
1430   system memory.
1431   This function does not flush posted write transactions from any PCI bridges.
1432   A PCI controller specific action must be taken to guarantee that the posted
1433   write transactions have been flushed from the PCI controller and from all the
1434   PCI bridges into the PCI host bridge. This is typically done with a PCI read
1435   transaction from the PCI controller prior to calling Flush().
1436
1437   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1438
1439   @retval EFI_SUCCESS        The PCI posted write transactions were flushed
1440                              from the PCI host bridge to system memory.
1441   @retval EFI_DEVICE_ERROR   The PCI posted write transactions were not flushed
1442                              from the PCI host bridge due to a hardware error.
1443 **/
1444 EFI_STATUS
1445 EFIAPI
1446 RootBridgeIoFlush (
1447   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *This
1448   )
1449 {
1450   return EFI_SUCCESS;
1451 }
1452
1453 /**
1454   Gets the attributes that a PCI root bridge supports setting with
1455   SetAttributes(), and the attributes that a PCI root bridge is currently
1456   using.
1457
1458   The GetAttributes() function returns the mask of attributes that this PCI
1459   root bridge supports and the mask of attributes that the PCI root bridge is
1460   currently using.
1461
1462   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1463   @param Supported   A pointer to the mask of attributes that this PCI root
1464                      bridge supports setting with SetAttributes().
1465   @param Attributes  A pointer to the mask of attributes that this PCI root
1466                      bridge is currently using.
1467
1468   @retval  EFI_SUCCESS           If Supports is not NULL, then the attributes
1469                                  that the PCI root bridge supports is returned
1470                                  in Supports. If Attributes is not NULL, then
1471                                  the attributes that the PCI root bridge is
1472                                  currently using is returned in Attributes.
1473   @retval  EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
1474 **/
1475 EFI_STATUS
1476 EFIAPI
1477 RootBridgeIoGetAttributes (
1478   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
1479   OUT UINT64                           *Supported,
1480   OUT UINT64                           *Attributes
1481   )
1482 {
1483   PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
1484
1485   if (Attributes == NULL && Supported == NULL) {
1486     return EFI_INVALID_PARAMETER;
1487   }
1488
1489   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1490   //
1491   // Set the return value for Supported and Attributes
1492   //
1493   if (Supported != NULL) {
1494     *Supported  = RootBridge->Supports;
1495   }
1496
1497   if (Attributes != NULL) {
1498     *Attributes = RootBridge->Attributes;
1499   }
1500
1501   return EFI_SUCCESS;
1502 }
1503
1504 /**
1505   Sets attributes for a resource range on a PCI root bridge.
1506
1507   The SetAttributes() function sets the attributes specified in Attributes for
1508   the PCI root bridge on the resource range specified by ResourceBase and
1509   ResourceLength. Since the granularity of setting these attributes may vary
1510   from resource type to resource type, and from platform to platform, the
1511   actual resource range and the one passed in by the caller may differ. As a
1512   result, this function may set the attributes specified by Attributes on a
1513   larger resource range than the caller requested. The actual range is returned
1514   in ResourceBase and ResourceLength. The caller is responsible for verifying
1515   that the actual range for which the attributes were set is acceptable.
1516
1517   @param This            A pointer to the
1518                          EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1519   @param Attributes      The mask of attributes to set. If the
1520                          attribute bit MEMORY_WRITE_COMBINE,
1521                          MEMORY_CACHED, or MEMORY_DISABLE is set,
1522                          then the resource range is specified by
1523                          ResourceBase and ResourceLength. If
1524                          MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
1525                          MEMORY_DISABLE are not set, then
1526                          ResourceBase and ResourceLength are ignored,
1527                          and may be NULL.
1528   @param ResourceBase    A pointer to the base address of the
1529                          resource range to be modified by the
1530                          attributes specified by Attributes.
1531   @param ResourceLength  A pointer to the length of the resource
1532                                    range to be modified by the attributes
1533                                    specified by Attributes.
1534
1535   @retval  EFI_SUCCESS           The current configuration of this PCI root bridge
1536                                  was returned in Resources.
1537   @retval  EFI_UNSUPPORTED       The current configuration of this PCI root bridge
1538                                  could not be retrieved.
1539 **/
1540 EFI_STATUS
1541 EFIAPI
1542 RootBridgeIoSetAttributes (
1543   IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,
1544   IN     UINT64                           Attributes,
1545   IN OUT UINT64                           *ResourceBase,
1546   IN OUT UINT64                           *ResourceLength
1547   )
1548 {
1549   PCI_ROOT_BRIDGE_INSTANCE            *RootBridge;
1550
1551   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1552
1553   if ((Attributes & (~RootBridge->Supports)) != 0) {
1554     return EFI_UNSUPPORTED;
1555   }
1556
1557   RootBridge->Attributes = Attributes;
1558   return EFI_SUCCESS;
1559 }
1560
1561 /**
1562   Retrieves the current resource settings of this PCI root bridge in the form
1563   of a set of ACPI 2.0 resource descriptors.
1564
1565   There are only two resource descriptor types from the ACPI Specification that
1566   may be used to describe the current resources allocated to a PCI root bridge.
1567   These are the QWORD Address Space Descriptor (ACPI 2.0 Section 6.4.3.5.1),
1568   and the End Tag (ACPI 2.0 Section 6.4.2.8). The QWORD Address Space
1569   Descriptor can describe memory, I/O, and bus number ranges for dynamic or
1570   fixed resources. The configuration of a PCI root bridge is described with one
1571   or more QWORD Address Space Descriptors followed by an End Tag.
1572
1573   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1574   @param[out]  Resources   A pointer to the ACPI 2.0 resource descriptors that
1575                            describe the current configuration of this PCI root
1576                            bridge. The storage for the ACPI 2.0 resource
1577                            descriptors is allocated by this function. The
1578                            caller must treat the return buffer as read-only
1579                            data, and the buffer must not be freed by the
1580                            caller.
1581
1582   @retval  EFI_SUCCESS     The current configuration of this PCI root bridge
1583                            was returned in Resources.
1584   @retval  EFI_UNSUPPORTED The current configuration of this PCI root bridge
1585                            could not be retrieved.
1586 **/
1587 EFI_STATUS
1588 EFIAPI
1589 RootBridgeIoConfiguration (
1590   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *This,
1591   OUT VOID                                **Resources
1592   )
1593 {
1594   PCI_RESOURCE_TYPE                 Index;
1595   PCI_ROOT_BRIDGE_INSTANCE          *RootBridge;
1596   PCI_RES_NODE                      *ResAllocNode;
1597   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
1598   EFI_ACPI_END_TAG_DESCRIPTOR       *End;
1599
1600   //
1601   // Get this instance of the Root Bridge.
1602   //
1603   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
1604   ZeroMem (
1605     RootBridge->ConfigBuffer,
1606     TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)
1607     );
1608   Descriptor = RootBridge->ConfigBuffer;
1609   for (Index = TypeIo; Index < TypeMax; Index++) {
1610
1611     ResAllocNode = &RootBridge->ResAllocNode[Index];
1612
1613     if (ResAllocNode->Status != ResAllocated) {
1614       continue;
1615     }
1616
1617     Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1618     Descriptor->Len  = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
1619     Descriptor->AddrRangeMin  = ResAllocNode->Base;
1620     Descriptor->AddrRangeMax  = ResAllocNode->Base + ResAllocNode->Length - 1;
1621     Descriptor->AddrLen       = ResAllocNode->Length;
1622     switch (ResAllocNode->Type) {
1623
1624     case TypeIo:
1625       Descriptor->ResType       = ACPI_ADDRESS_SPACE_TYPE_IO;
1626       break;
1627
1628     case TypePMem32:
1629       Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
1630     case TypeMem32:
1631       Descriptor->ResType               = ACPI_ADDRESS_SPACE_TYPE_MEM;
1632       Descriptor->AddrSpaceGranularity  = 32;
1633       break;
1634
1635     case TypePMem64:
1636       Descriptor->SpecificFlag = EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;
1637     case TypeMem64:
1638       Descriptor->ResType               = ACPI_ADDRESS_SPACE_TYPE_MEM;
1639       Descriptor->AddrSpaceGranularity  = 64;
1640       break;
1641
1642     case TypeBus:
1643       Descriptor->ResType       = ACPI_ADDRESS_SPACE_TYPE_BUS;
1644       break;
1645
1646     default:
1647       break;
1648     }
1649
1650     Descriptor++;
1651   }
1652   //
1653   // Terminate the entries.
1654   //
1655   End = (EFI_ACPI_END_TAG_DESCRIPTOR *) Descriptor;
1656   End->Desc     = ACPI_END_TAG_DESCRIPTOR;
1657   End->Checksum = 0x0;
1658
1659   *Resources = RootBridge->ConfigBuffer;
1660   return EFI_SUCCESS;
1661 }