2 This driver is used to manage SD/MMC PCI host controllers which are compliance
3 with SD Host Controller Simplified Specification version 3.00 plus the 64-bit
4 System Addressing support in SD Host Controller Simplified Specification version
7 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
9 Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
10 Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.<BR>
11 SPDX-License-Identifier: BSD-2-Clause-Patent
15 #include "SdMmcPciHcDxe.h"
18 Dump the content of SD/MMC host controller's Capability Register.
20 @param[in] Slot The slot number of the SD card to send the command to.
21 @param[in] Capability The buffer to store the capability data.
27 IN SD_MMC_HC_SLOT_CAP
*Capability
31 // Dump Capability Data
33 DEBUG ((DEBUG_INFO
, " == Slot [%d] Capability is 0x%x ==\n", Slot
, Capability
));
34 DEBUG ((DEBUG_INFO
, " Timeout Clk Freq %d%a\n", Capability
->TimeoutFreq
, (Capability
->TimeoutUnit
) ? "MHz" : "KHz"));
35 DEBUG ((DEBUG_INFO
, " Base Clk Freq %dMHz\n", Capability
->BaseClkFreq
));
36 DEBUG ((DEBUG_INFO
, " Max Blk Len %dbytes\n", 512 * (1 << Capability
->MaxBlkLen
)));
37 DEBUG ((DEBUG_INFO
, " 8-bit Support %a\n", Capability
->BusWidth8
? "TRUE" : "FALSE"));
38 DEBUG ((DEBUG_INFO
, " ADMA2 Support %a\n", Capability
->Adma2
? "TRUE" : "FALSE"));
39 DEBUG ((DEBUG_INFO
, " HighSpeed Support %a\n", Capability
->HighSpeed
? "TRUE" : "FALSE"));
40 DEBUG ((DEBUG_INFO
, " SDMA Support %a\n", Capability
->Sdma
? "TRUE" : "FALSE"));
41 DEBUG ((DEBUG_INFO
, " Suspend/Resume %a\n", Capability
->SuspRes
? "TRUE" : "FALSE"));
42 DEBUG ((DEBUG_INFO
, " Voltage 3.3 %a\n", Capability
->Voltage33
? "TRUE" : "FALSE"));
43 DEBUG ((DEBUG_INFO
, " Voltage 3.0 %a\n", Capability
->Voltage30
? "TRUE" : "FALSE"));
44 DEBUG ((DEBUG_INFO
, " Voltage 1.8 %a\n", Capability
->Voltage18
? "TRUE" : "FALSE"));
45 DEBUG ((DEBUG_INFO
, " V4 64-bit Sys Bus %a\n", Capability
->SysBus64V4
? "TRUE" : "FALSE"));
46 DEBUG ((DEBUG_INFO
, " V3 64-bit Sys Bus %a\n", Capability
->SysBus64V3
? "TRUE" : "FALSE"));
47 DEBUG ((DEBUG_INFO
, " Async Interrupt %a\n", Capability
->AsyncInt
? "TRUE" : "FALSE"));
48 DEBUG ((DEBUG_INFO
, " SlotType "));
49 if (Capability
->SlotType
== 0x00) {
50 DEBUG ((DEBUG_INFO
, "%a\n", "Removable Slot"));
51 } else if (Capability
->SlotType
== 0x01) {
52 DEBUG ((DEBUG_INFO
, "%a\n", "Embedded Slot"));
53 } else if (Capability
->SlotType
== 0x02) {
54 DEBUG ((DEBUG_INFO
, "%a\n", "Shared Bus Slot"));
56 DEBUG ((DEBUG_INFO
, "%a\n", "Reserved"));
58 DEBUG ((DEBUG_INFO
, " SDR50 Support %a\n", Capability
->Sdr50
? "TRUE" : "FALSE"));
59 DEBUG ((DEBUG_INFO
, " SDR104 Support %a\n", Capability
->Sdr104
? "TRUE" : "FALSE"));
60 DEBUG ((DEBUG_INFO
, " DDR50 Support %a\n", Capability
->Ddr50
? "TRUE" : "FALSE"));
61 DEBUG ((DEBUG_INFO
, " Driver Type A %a\n", Capability
->DriverTypeA
? "TRUE" : "FALSE"));
62 DEBUG ((DEBUG_INFO
, " Driver Type C %a\n", Capability
->DriverTypeC
? "TRUE" : "FALSE"));
63 DEBUG ((DEBUG_INFO
, " Driver Type D %a\n", Capability
->DriverTypeD
? "TRUE" : "FALSE"));
64 DEBUG ((DEBUG_INFO
, " Driver Type 4 %a\n", Capability
->DriverType4
? "TRUE" : "FALSE"));
65 if (Capability
->TimerCount
== 0) {
66 DEBUG ((DEBUG_INFO
, " Retuning TimerCnt Disabled\n", 2 * (Capability
->TimerCount
- 1)));
68 DEBUG ((DEBUG_INFO
, " Retuning TimerCnt %dseconds\n", 2 * (Capability
->TimerCount
- 1)));
70 DEBUG ((DEBUG_INFO
, " SDR50 Tuning %a\n", Capability
->TuningSDR50
? "TRUE" : "FALSE"));
71 DEBUG ((DEBUG_INFO
, " Retuning Mode Mode %d\n", Capability
->RetuningMod
+ 1));
72 DEBUG ((DEBUG_INFO
, " Clock Multiplier M = %d\n", Capability
->ClkMultiplier
+ 1));
73 DEBUG ((DEBUG_INFO
, " HS 400 %a\n", Capability
->Hs400
? "TRUE" : "FALSE"));
78 Read SlotInfo register from SD/MMC host controller pci config space.
80 @param[in] PciIo The PCI IO protocol instance.
81 @param[out] FirstBar The buffer to store the first BAR value.
82 @param[out] SlotNum The buffer to store the supported slot number.
84 @retval EFI_SUCCESS The operation succeeds.
85 @retval Others The operation fails.
91 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
97 SD_MMC_HC_SLOT_INFO SlotInfo
;
99 Status
= PciIo
->Pci
.Read (
102 SD_MMC_HC_SLOT_OFFSET
,
106 if (EFI_ERROR (Status
)) {
110 *FirstBar
= SlotInfo
.FirstBar
;
111 *SlotNum
= SlotInfo
.SlotNum
+ 1;
112 ASSERT ((*FirstBar
+ *SlotNum
) < SD_MMC_HC_MAX_SLOT
);
117 Read/Write specified SD/MMC host controller mmio register.
119 @param[in] PciIo The PCI IO protocol instance.
120 @param[in] BarIndex The BAR index of the standard PCI Configuration
121 header to use as the base address for the memory
122 operation to perform.
123 @param[in] Offset The offset within the selected BAR to start the
125 @param[in] Read A boolean to indicate it's read or write operation.
126 @param[in] Count The width of the mmio register in bytes.
127 Must be 1, 2 , 4 or 8 bytes.
128 @param[in, out] Data For read operations, the destination buffer to store
129 the results. For write operations, the source buffer
130 to write data from. The caller is responsible for
131 having ownership of the data buffer and ensuring its
132 size not less than Count bytes.
134 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
135 @retval EFI_SUCCESS The read/write operation succeeds.
136 @retval Others The read/write operation fails.
142 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
151 EFI_PCI_IO_PROTOCOL_WIDTH Width
;
153 if ((PciIo
== NULL
) || (Data
== NULL
)) {
154 return EFI_INVALID_PARAMETER
;
159 Width
= EfiPciIoWidthUint8
;
162 Width
= EfiPciIoWidthUint16
;
166 Width
= EfiPciIoWidthUint32
;
170 Width
= EfiPciIoWidthUint32
;
174 return EFI_INVALID_PARAMETER
;
178 Status
= PciIo
->Mem
.Read (
187 Status
= PciIo
->Mem
.Write (
201 Do OR operation with the value of the specified SD/MMC host controller mmio register.
203 @param[in] PciIo The PCI IO protocol instance.
204 @param[in] BarIndex The BAR index of the standard PCI Configuration
205 header to use as the base address for the memory
206 operation to perform.
207 @param[in] Offset The offset within the selected BAR to start the
209 @param[in] Count The width of the mmio register in bytes.
210 Must be 1, 2 , 4 or 8 bytes.
211 @param[in] OrData The pointer to the data used to do OR operation.
212 The caller is responsible for having ownership of
213 the data buffer and ensuring its size not less than
216 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
217 @retval EFI_SUCCESS The OR operation succeeds.
218 @retval Others The OR operation fails.
224 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
235 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Data
);
236 if (EFI_ERROR (Status
)) {
241 Or
= *(UINT8
*) OrData
;
242 } else if (Count
== 2) {
243 Or
= *(UINT16
*) OrData
;
244 } else if (Count
== 4) {
245 Or
= *(UINT32
*) OrData
;
246 } else if (Count
== 8) {
247 Or
= *(UINT64
*) OrData
;
249 return EFI_INVALID_PARAMETER
;
253 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, FALSE
, Count
, &Data
);
259 Do AND operation with the value of the specified SD/MMC host controller mmio register.
261 @param[in] PciIo The PCI IO protocol instance.
262 @param[in] BarIndex The BAR index of the standard PCI Configuration
263 header to use as the base address for the memory
264 operation to perform.
265 @param[in] Offset The offset within the selected BAR to start the
267 @param[in] Count The width of the mmio register in bytes.
268 Must be 1, 2 , 4 or 8 bytes.
269 @param[in] AndData The pointer to the data used to do AND operation.
270 The caller is responsible for having ownership of
271 the data buffer and ensuring its size not less than
274 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
275 @retval EFI_SUCCESS The AND operation succeeds.
276 @retval Others The AND operation fails.
282 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
293 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Data
);
294 if (EFI_ERROR (Status
)) {
299 And
= *(UINT8
*) AndData
;
300 } else if (Count
== 2) {
301 And
= *(UINT16
*) AndData
;
302 } else if (Count
== 4) {
303 And
= *(UINT32
*) AndData
;
304 } else if (Count
== 8) {
305 And
= *(UINT64
*) AndData
;
307 return EFI_INVALID_PARAMETER
;
311 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, FALSE
, Count
, &Data
);
317 Wait for the value of the specified MMIO register set to the test value.
319 @param[in] PciIo The PCI IO protocol instance.
320 @param[in] BarIndex The BAR index of the standard PCI Configuration
321 header to use as the base address for the memory
322 operation to perform.
323 @param[in] Offset The offset within the selected BAR to start the
325 @param[in] Count The width of the mmio register in bytes.
326 Must be 1, 2, 4 or 8 bytes.
327 @param[in] MaskValue The mask value of memory.
328 @param[in] TestValue The test value of memory.
330 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
331 @retval EFI_SUCCESS The MMIO register has expected value.
332 @retval Others The MMIO operation fails.
337 SdMmcHcCheckMmioSet (
338 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
350 // Access PCI MMIO space to see if the value is the tested one.
353 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Value
);
354 if (EFI_ERROR (Status
)) {
360 if (Value
== TestValue
) {
364 return EFI_NOT_READY
;
368 Wait for the value of the specified MMIO register set to the test value.
370 @param[in] PciIo The PCI IO protocol instance.
371 @param[in] BarIndex The BAR index of the standard PCI Configuration
372 header to use as the base address for the memory
373 operation to perform.
374 @param[in] Offset The offset within the selected BAR to start the
376 @param[in] Count The width of the mmio register in bytes.
377 Must be 1, 2, 4 or 8 bytes.
378 @param[in] MaskValue The mask value of memory.
379 @param[in] TestValue The test value of memory.
380 @param[in] Timeout The time out value for wait memory set, uses 1
381 microsecond as a unit.
383 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
385 @retval EFI_SUCCESS The MMIO register has expected value.
386 @retval Others The MMIO operation fails.
392 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
402 BOOLEAN InfiniteWait
;
407 InfiniteWait
= FALSE
;
410 while (InfiniteWait
|| (Timeout
> 0)) {
411 Status
= SdMmcHcCheckMmioSet (
419 if (Status
!= EFI_NOT_READY
) {
424 // Stall for 1 microsecond.
435 Get the controller version information from the specified slot.
437 @param[in] PciIo The PCI IO protocol instance.
438 @param[in] Slot The slot number of the SD card to send the command to.
439 @param[out] Version The buffer to store the version information.
441 @retval EFI_SUCCESS The operation executes successfully.
442 @retval Others The operation fails.
446 SdMmcHcGetControllerVersion (
447 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
454 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CTRL_VER
, TRUE
, sizeof (UINT16
), Version
);
455 if (EFI_ERROR (Status
)) {
465 Software reset the specified SD/MMC host controller and enable all interrupts.
467 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
468 @param[in] Slot The slot number of the SD card to send the command to.
470 @retval EFI_SUCCESS The software reset executes successfully.
471 @retval Others The software reset fails.
476 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
482 EFI_PCI_IO_PROTOCOL
*PciIo
;
485 // Notify the SD/MMC override protocol that we are about to reset
486 // the SD/MMC host controller.
488 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
489 Status
= mOverride
->NotifyPhase (
490 Private
->ControllerHandle
,
494 if (EFI_ERROR (Status
)) {
496 "%a: SD/MMC pre reset notifier callback failed - %r\n",
497 __FUNCTION__
, Status
));
502 PciIo
= Private
->PciIo
;
504 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_SW_RST
, sizeof (SwReset
), &SwReset
);
506 if (EFI_ERROR (Status
)) {
507 DEBUG ((DEBUG_ERROR
, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status
));
511 Status
= SdMmcHcWaitMmioSet (
518 SD_MMC_HC_GENERIC_TIMEOUT
520 if (EFI_ERROR (Status
)) {
521 DEBUG ((DEBUG_INFO
, "SdMmcHcReset: reset done with %r\n", Status
));
526 // Enable all interrupt after reset all.
528 Status
= SdMmcHcEnableInterrupt (PciIo
, Slot
);
529 if (EFI_ERROR (Status
)) {
530 DEBUG ((DEBUG_INFO
, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",
536 // Notify the SD/MMC override protocol that we have just reset
537 // the SD/MMC host controller.
539 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
540 Status
= mOverride
->NotifyPhase (
541 Private
->ControllerHandle
,
545 if (EFI_ERROR (Status
)) {
547 "%a: SD/MMC post reset notifier callback failed - %r\n",
548 __FUNCTION__
, Status
));
556 Set all interrupt status bits in Normal and Error Interrupt Status Enable
559 @param[in] PciIo The PCI IO protocol instance.
560 @param[in] Slot The slot number of the SD card to send the command to.
562 @retval EFI_SUCCESS The operation executes successfully.
563 @retval Others The operation fails.
567 SdMmcHcEnableInterrupt (
568 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
576 // Enable all bits in Error Interrupt Status Enable Register
579 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_ERR_INT_STS_EN
, FALSE
, sizeof (IntStatus
), &IntStatus
);
580 if (EFI_ERROR (Status
)) {
584 // Enable all bits in Normal Interrupt Status Enable Register
587 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS_EN
, FALSE
, sizeof (IntStatus
), &IntStatus
);
593 Get the capability data from the specified slot.
595 @param[in] PciIo The PCI IO protocol instance.
596 @param[in] Slot The slot number of the SD card to send the command to.
597 @param[out] Capability The buffer to store the capability data.
599 @retval EFI_SUCCESS The operation executes successfully.
600 @retval Others The operation fails.
604 SdMmcHcGetCapability (
605 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
607 OUT SD_MMC_HC_SLOT_CAP
*Capability
613 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CAP
, TRUE
, sizeof (Cap
), &Cap
);
614 if (EFI_ERROR (Status
)) {
618 CopyMem (Capability
, &Cap
, sizeof (Cap
));
624 Get the maximum current capability data from the specified slot.
626 @param[in] PciIo The PCI IO protocol instance.
627 @param[in] Slot The slot number of the SD card to send the command to.
628 @param[out] MaxCurrent The buffer to store the maximum current capability data.
630 @retval EFI_SUCCESS The operation executes successfully.
631 @retval Others The operation fails.
635 SdMmcHcGetMaxCurrent (
636 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
638 OUT UINT64
*MaxCurrent
643 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_MAX_CURRENT_CAP
, TRUE
, sizeof (UINT64
), MaxCurrent
);
649 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
652 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
654 @param[in] PciIo The PCI IO protocol instance.
655 @param[in] Slot The slot number of the SD card to send the command to.
656 @param[out] MediaPresent The pointer to the media present boolean value.
658 @retval EFI_SUCCESS There is no media change happened.
659 @retval EFI_MEDIA_CHANGED There is media change happened.
660 @retval Others The detection fails.
665 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
667 OUT BOOLEAN
*MediaPresent
675 // Check Present State Register to see if there is a card presented.
677 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_PRESENT_STATE
, TRUE
, sizeof (PresentState
), &PresentState
);
678 if (EFI_ERROR (Status
)) {
682 if ((PresentState
& BIT16
) != 0) {
683 *MediaPresent
= TRUE
;
685 *MediaPresent
= FALSE
;
689 // Check Normal Interrupt Status Register
691 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS
, TRUE
, sizeof (Data
), &Data
);
692 if (EFI_ERROR (Status
)) {
696 if ((Data
& (BIT6
| BIT7
)) != 0) {
698 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
701 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (Data
), &Data
);
702 if (EFI_ERROR (Status
)) {
706 return EFI_MEDIA_CHANGED
;
713 Stop SD/MMC card clock.
715 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
717 @param[in] PciIo The PCI IO protocol instance.
718 @param[in] Slot The slot number of the SD card to send the command to.
720 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.
721 @retval Others Fail to stop SD/MMC clock.
726 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
735 // Ensure no SD transactions are occurring on the SD Bus by
736 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
737 // in the Present State register to be 0.
739 Status
= SdMmcHcWaitMmioSet (
742 SD_MMC_HC_PRESENT_STATE
,
743 sizeof (PresentState
),
746 SD_MMC_HC_GENERIC_TIMEOUT
748 if (EFI_ERROR (Status
)) {
753 // Set SD Clock Enable in the Clock Control register to 0
755 ClockCtrl
= (UINT16
)~BIT2
;
756 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, sizeof (ClockCtrl
), &ClockCtrl
);
764 @param[in] PciIo The PCI IO protocol instance.
765 @param[in] Slot The slot number.
767 @retval EFI_SUCCESS Succeeded to start the SD clock.
768 @retval Others Failed to start the SD clock.
771 SdMmcHcStartSdClock (
772 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
779 // Set SD Clock Enable in the Clock Control register to 1
782 return SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, sizeof (ClockCtrl
), &ClockCtrl
);
786 SD/MMC card clock supply.
788 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
790 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
791 @param[in] Slot The slot number of the SD card to send the command to.
792 @param[in] BusTiming BusTiming at which the frequency change is done.
793 @param[in] FirstTimeSetup Flag to indicate whether the clock is being setup for the first time.
794 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
796 @retval EFI_SUCCESS The clock is supplied successfully.
797 @retval Others The clock isn't supplied successfully.
802 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
804 IN SD_MMC_BUS_MODE BusTiming
,
805 IN BOOLEAN FirstTimeSetup
,
815 UINT16 ControllerVer
;
816 EFI_PCI_IO_PROTOCOL
*PciIo
;
818 PciIo
= Private
->PciIo
;
819 BaseClkFreq
= Private
->BaseClkFreq
[Slot
];
820 ControllerVer
= Private
->ControllerVersion
[Slot
];
822 if (BaseClkFreq
== 0 || ClockFreq
== 0) {
823 return EFI_INVALID_PARAMETER
;
826 if (ClockFreq
> (BaseClkFreq
* 1000)) {
827 ClockFreq
= BaseClkFreq
* 1000;
831 // Calculate the divisor of base frequency.
834 SettingFreq
= BaseClkFreq
* 1000;
835 while (ClockFreq
< SettingFreq
) {
838 SettingFreq
= (BaseClkFreq
* 1000) / (2 * Divisor
);
839 Remainder
= (BaseClkFreq
* 1000) % (2 * Divisor
);
840 if ((ClockFreq
== SettingFreq
) && (Remainder
== 0)) {
843 if ((ClockFreq
== SettingFreq
) && (Remainder
!= 0)) {
848 DEBUG ((DEBUG_INFO
, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq
, Divisor
, ClockFreq
));
851 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
853 if ((ControllerVer
>= SD_MMC_HC_CTRL_VER_300
) &&
854 (ControllerVer
<= SD_MMC_HC_CTRL_VER_420
)) {
855 ASSERT (Divisor
<= 0x3FF);
856 ClockCtrl
= ((Divisor
& 0xFF) << 8) | ((Divisor
& 0x300) >> 2);
857 } else if ((ControllerVer
== SD_MMC_HC_CTRL_VER_100
) ||
858 (ControllerVer
== SD_MMC_HC_CTRL_VER_200
)) {
860 // Only the most significant bit can be used as divisor.
862 if (((Divisor
- 1) & Divisor
) != 0) {
863 Divisor
= 1 << (HighBitSet32 (Divisor
) + 1);
865 ASSERT (Divisor
<= 0x80);
866 ClockCtrl
= (Divisor
& 0xFF) << 8;
868 DEBUG ((DEBUG_ERROR
, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer
));
869 return EFI_UNSUPPORTED
;
873 // Stop bus clock at first
875 Status
= SdMmcHcStopClock (PciIo
, Slot
);
876 if (EFI_ERROR (Status
)) {
881 // Supply clock frequency with specified divisor
884 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, FALSE
, sizeof (ClockCtrl
), &ClockCtrl
);
885 if (EFI_ERROR (Status
)) {
886 DEBUG ((DEBUG_ERROR
, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
891 // Wait Internal Clock Stable in the Clock Control register to be 1
893 Status
= SdMmcHcWaitMmioSet (
896 SD_MMC_HC_CLOCK_CTRL
,
900 SD_MMC_HC_GENERIC_TIMEOUT
902 if (EFI_ERROR (Status
)) {
906 Status
= SdMmcHcStartSdClock (PciIo
, Slot
);
907 if (EFI_ERROR (Status
)) {
912 // We don't notify the platform on first time setup to avoid changing
913 // legacy behavior. During first time setup we also don't know what type
914 // of the card slot it is and which enum value of BusTiming applies.
916 if (!FirstTimeSetup
&& mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
917 Status
= mOverride
->NotifyPhase (
918 Private
->ControllerHandle
,
920 EdkiiSdMmcSwitchClockFreqPost
,
923 if (EFI_ERROR (Status
)) {
926 "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
934 Private
->Slot
[Slot
].CurrentFreq
= ClockFreq
;
940 SD/MMC bus power control.
942 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
944 @param[in] PciIo The PCI IO protocol instance.
945 @param[in] Slot The slot number of the SD card to send the command to.
946 @param[in] PowerCtrl The value setting to the power control register.
948 @retval TRUE There is a SD/MMC card attached.
949 @retval FALSE There is no a SD/MMC card attached.
953 SdMmcHcPowerControl (
954 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
964 PowerCtrl
&= (UINT8
)~BIT0
;
965 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_POWER_CTRL
, FALSE
, sizeof (PowerCtrl
), &PowerCtrl
);
966 if (EFI_ERROR (Status
)) {
971 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
974 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_POWER_CTRL
, FALSE
, sizeof (PowerCtrl
), &PowerCtrl
);
980 Set the SD/MMC bus width.
982 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
984 @param[in] PciIo The PCI IO protocol instance.
985 @param[in] Slot The slot number of the SD card to send the command to.
986 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
988 @retval EFI_SUCCESS The bus width is set successfully.
989 @retval Others The bus width isn't set successfully.
994 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1002 if (BusWidth
== 1) {
1003 HostCtrl1
= (UINT8
)~(BIT5
| BIT1
);
1004 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1005 } else if (BusWidth
== 4) {
1006 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, TRUE
, sizeof (HostCtrl1
), &HostCtrl1
);
1007 if (EFI_ERROR (Status
)) {
1011 HostCtrl1
&= (UINT8
)~BIT5
;
1012 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, FALSE
, sizeof (HostCtrl1
), &HostCtrl1
);
1013 } else if (BusWidth
== 8) {
1014 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, TRUE
, sizeof (HostCtrl1
), &HostCtrl1
);
1015 if (EFI_ERROR (Status
)) {
1018 HostCtrl1
&= (UINT8
)~BIT1
;
1020 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, FALSE
, sizeof (HostCtrl1
), &HostCtrl1
);
1023 return EFI_INVALID_PARAMETER
;
1030 Configure V4 controller enhancements at initialization.
1032 @param[in] PciIo The PCI IO protocol instance.
1033 @param[in] Slot The slot number of the SD card to send the command to.
1034 @param[in] Capability The capability of the slot.
1035 @param[in] ControllerVer The version of host controller.
1037 @retval EFI_SUCCESS The clock is supplied successfully.
1041 SdMmcHcInitV4Enhancements (
1042 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1044 IN SD_MMC_HC_SLOT_CAP Capability
,
1045 IN UINT16 ControllerVer
1052 // Check if controller version V4 or higher
1054 if (ControllerVer
>= SD_MMC_HC_CTRL_VER_400
) {
1055 HostCtrl2
= SD_MMC_HC_V4_EN
;
1057 // Check if controller version V4.0
1059 if (ControllerVer
== SD_MMC_HC_CTRL_VER_400
) {
1061 // Check if 64bit support is available
1063 if (Capability
.SysBus64V3
!= 0) {
1064 HostCtrl2
|= SD_MMC_HC_64_ADDR_EN
;
1065 DEBUG ((DEBUG_INFO
, "Enabled V4 64 bit system bus support\n"));
1069 // Check if controller version V4.10 or higher
1071 else if (ControllerVer
>= SD_MMC_HC_CTRL_VER_410
) {
1073 // Check if 64bit support is available
1075 if (Capability
.SysBus64V4
!= 0) {
1076 HostCtrl2
|= SD_MMC_HC_64_ADDR_EN
;
1077 DEBUG ((DEBUG_INFO
, "Enabled V4 64 bit system bus support\n"));
1079 HostCtrl2
|= SD_MMC_HC_26_DATA_LEN_ADMA_EN
;
1080 DEBUG ((DEBUG_INFO
, "Enabled V4 26 bit data length ADMA support\n"));
1082 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1083 if (EFI_ERROR (Status
)) {
1092 Supply SD/MMC card with maximum voltage at initialization.
1094 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
1096 @param[in] PciIo The PCI IO protocol instance.
1097 @param[in] Slot The slot number of the SD card to send the command to.
1098 @param[in] Capability The capability of the slot.
1100 @retval EFI_SUCCESS The voltage is supplied successfully.
1101 @retval Others The voltage isn't supplied successfully.
1105 SdMmcHcInitPowerVoltage (
1106 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1108 IN SD_MMC_HC_SLOT_CAP Capability
1116 // Calculate supported maximum voltage according to SD Bus Voltage Select
1118 if (Capability
.Voltage33
!= 0) {
1123 } else if (Capability
.Voltage30
!= 0) {
1128 } else if (Capability
.Voltage18
!= 0) {
1134 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1136 if (EFI_ERROR (Status
)) {
1141 return EFI_DEVICE_ERROR
;
1145 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
1147 Status
= SdMmcHcPowerControl (PciIo
, Slot
, MaxVoltage
);
1153 Initialize the Timeout Control register with most conservative value at initialization.
1155 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
1157 @param[in] PciIo The PCI IO protocol instance.
1158 @param[in] Slot The slot number of the SD card to send the command to.
1160 @retval EFI_SUCCESS The timeout control register is configured successfully.
1161 @retval Others The timeout control register isn't configured successfully.
1165 SdMmcHcInitTimeoutCtrl (
1166 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1174 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_TIMEOUT_CTRL
, FALSE
, sizeof (Timeout
), &Timeout
);
1180 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
1183 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1184 @param[in] Slot The slot number of the SD card to send the command to.
1186 @retval EFI_SUCCESS The host controller is initialized successfully.
1187 @retval Others The host controller isn't initialized successfully.
1192 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1197 EFI_PCI_IO_PROTOCOL
*PciIo
;
1198 SD_MMC_HC_SLOT_CAP Capability
;
1201 // Notify the SD/MMC override protocol that we are about to initialize
1202 // the SD/MMC host controller.
1204 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
1205 Status
= mOverride
->NotifyPhase (
1206 Private
->ControllerHandle
,
1208 EdkiiSdMmcInitHostPre
,
1210 if (EFI_ERROR (Status
)) {
1212 "%a: SD/MMC pre init notifier callback failed - %r\n",
1213 __FUNCTION__
, Status
));
1218 PciIo
= Private
->PciIo
;
1219 Capability
= Private
->Capability
[Slot
];
1221 Status
= SdMmcHcInitV4Enhancements (PciIo
, Slot
, Capability
, Private
->ControllerVersion
[Slot
]);
1222 if (EFI_ERROR (Status
)) {
1227 // Perform first time clock setup with 400 KHz frequency.
1228 // We send the 0 as the BusTiming value because at this time
1229 // we still do not know the slot type and which enum value will apply.
1230 // Since it is a first time setup SdMmcHcClockSupply won't notify
1231 // the platofrm driver anyway so it doesn't matter.
1233 Status
= SdMmcHcClockSupply (Private
, Slot
, 0, TRUE
, 400);
1234 if (EFI_ERROR (Status
)) {
1238 Status
= SdMmcHcInitPowerVoltage (PciIo
, Slot
, Capability
);
1239 if (EFI_ERROR (Status
)) {
1243 Status
= SdMmcHcInitTimeoutCtrl (PciIo
, Slot
);
1244 if (EFI_ERROR (Status
)) {
1249 // Notify the SD/MMC override protocol that we are have just initialized
1250 // the SD/MMC host controller.
1252 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
1253 Status
= mOverride
->NotifyPhase (
1254 Private
->ControllerHandle
,
1256 EdkiiSdMmcInitHostPost
,
1258 if (EFI_ERROR (Status
)) {
1260 "%a: SD/MMC post init notifier callback failed - %r\n",
1261 __FUNCTION__
, Status
));
1268 Set SD Host Controler control 2 registry according to selected speed.
1270 @param[in] ControllerHandle The handle of the controller.
1271 @param[in] PciIo The PCI IO protocol instance.
1272 @param[in] Slot The slot number of the SD card to send the command to.
1273 @param[in] Timing The timing to select.
1275 @retval EFI_SUCCESS The timing is set successfully.
1276 @retval Others The timing isn't set successfully.
1279 SdMmcHcUhsSignaling (
1280 IN EFI_HANDLE ControllerHandle
,
1281 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1283 IN SD_MMC_BUS_MODE Timing
1289 HostCtrl2
= (UINT8
)~SD_MMC_HC_CTRL_UHS_MASK
;
1290 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1291 if (EFI_ERROR (Status
)) {
1297 HostCtrl2
= SD_MMC_HC_CTRL_UHS_SDR12
;
1300 HostCtrl2
= SD_MMC_HC_CTRL_UHS_SDR25
;
1303 HostCtrl2
= SD_MMC_HC_CTRL_UHS_SDR50
;
1305 case SdMmcUhsSdr104
:
1306 HostCtrl2
= SD_MMC_HC_CTRL_UHS_SDR104
;
1309 HostCtrl2
= SD_MMC_HC_CTRL_UHS_DDR50
;
1311 case SdMmcMmcLegacy
:
1312 HostCtrl2
= SD_MMC_HC_CTRL_MMC_LEGACY
;
1315 HostCtrl2
= SD_MMC_HC_CTRL_MMC_HS_SDR
;
1318 HostCtrl2
= SD_MMC_HC_CTRL_MMC_HS_DDR
;
1321 HostCtrl2
= SD_MMC_HC_CTRL_MMC_HS200
;
1324 HostCtrl2
= SD_MMC_HC_CTRL_MMC_HS400
;
1330 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1331 if (EFI_ERROR (Status
)) {
1335 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
1336 Status
= mOverride
->NotifyPhase (
1339 EdkiiSdMmcUhsSignaling
,
1342 if (EFI_ERROR (Status
)) {
1345 "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
1357 Set driver strength in host controller.
1359 @param[in] PciIo The PCI IO protocol instance.
1360 @param[in] SlotIndex The slot index of the card.
1361 @param[in] DriverStrength DriverStrength to set in the controller.
1363 @retval EFI_SUCCESS Driver strength programmed successfully.
1364 @retval Others Failed to set driver strength.
1367 SdMmcSetDriverStrength (
1368 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1370 IN SD_DRIVER_STRENGTH_TYPE DriverStrength
1376 if (DriverStrength
== SdDriverStrengthIgnore
) {
1380 HostCtrl2
= (UINT16
)~SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK
;
1381 Status
= SdMmcHcAndMmio (PciIo
, SlotIndex
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1382 if (EFI_ERROR (Status
)) {
1386 HostCtrl2
= (DriverStrength
<< 4) & SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK
;
1387 return SdMmcHcOrMmio (PciIo
, SlotIndex
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1393 @param[in] PciIo The PCI IO protocol instance.
1394 @param[in] Slot The slot number of the SD card to send the command to.
1395 @param[in] On The boolean to turn on/off LED.
1397 @retval EFI_SUCCESS The LED is turned on/off successfully.
1398 @retval Others The LED isn't turned on/off successfully.
1403 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1413 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1415 HostCtrl1
= (UINT8
)~BIT0
;
1416 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1423 Build ADMA descriptor table for transfer.
1425 Refer to SD Host Controller Simplified spec 4.2 Section 1.13 for details.
1427 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1428 @param[in] ControllerVer The version of host controller.
1430 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
1431 @retval Others The ADMA descriptor table isn't created successfully.
1435 BuildAdmaDescTable (
1436 IN SD_MMC_HC_TRB
*Trb
,
1437 IN UINT16 ControllerVer
1440 EFI_PHYSICAL_ADDRESS Data
;
1447 EFI_PCI_IO_PROTOCOL
*PciIo
;
1450 UINT32 AdmaMaxDataPerLine
;
1454 AdmaMaxDataPerLine
= ADMA_MAX_DATA_PER_LINE_16B
;
1455 DescSize
= sizeof (SD_MMC_HC_ADMA_32_DESC_LINE
);
1458 Data
= Trb
->DataPhy
;
1459 DataLen
= Trb
->DataLen
;
1460 PciIo
= Trb
->Private
->PciIo
;
1463 // Check for valid ranges in 32bit ADMA Descriptor Table
1465 if ((Trb
->Mode
== SdMmcAdma32bMode
) &&
1466 ((Data
>= 0x100000000ul
) || ((Data
+ DataLen
) > 0x100000000ul
))) {
1467 return EFI_INVALID_PARAMETER
;
1470 // Check address field alignment
1472 if (Trb
->Mode
!= SdMmcAdma32bMode
) {
1474 // Address field shall be set on 64-bit boundary (Lower 3-bit is always set to 0)
1476 if ((Data
& (BIT0
| BIT1
| BIT2
)) != 0) {
1477 DEBUG ((DEBUG_INFO
, "The buffer [0x%x] to construct ADMA desc is not aligned to 8 bytes boundary!\n", Data
));
1481 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
1483 if ((Data
& (BIT0
| BIT1
)) != 0) {
1484 DEBUG ((DEBUG_INFO
, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data
));
1489 // Configure 64b ADMA.
1491 if (Trb
->Mode
== SdMmcAdma64bV3Mode
) {
1492 DescSize
= sizeof (SD_MMC_HC_ADMA_64_V3_DESC_LINE
);
1493 }else if (Trb
->Mode
== SdMmcAdma64bV4Mode
) {
1494 DescSize
= sizeof (SD_MMC_HC_ADMA_64_V4_DESC_LINE
);
1497 // Configure 26b data length.
1499 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1500 AdmaMaxDataPerLine
= ADMA_MAX_DATA_PER_LINE_26B
;
1503 Entries
= DivU64x32 ((DataLen
+ AdmaMaxDataPerLine
- 1), AdmaMaxDataPerLine
);
1504 TableSize
= (UINTN
)MultU64x32 (Entries
, DescSize
);
1505 Trb
->AdmaPages
= (UINT32
)EFI_SIZE_TO_PAGES (TableSize
);
1506 Status
= PciIo
->AllocateBuffer (
1509 EfiBootServicesData
,
1510 EFI_SIZE_TO_PAGES (TableSize
),
1514 if (EFI_ERROR (Status
)) {
1515 return EFI_OUT_OF_RESOURCES
;
1517 ZeroMem (AdmaDesc
, TableSize
);
1519 Status
= PciIo
->Map (
1521 EfiPciIoOperationBusMasterCommonBuffer
,
1528 if (EFI_ERROR (Status
) || (Bytes
!= TableSize
)) {
1530 // Map error or unable to map the whole RFis buffer into a contiguous region.
1534 EFI_SIZE_TO_PAGES (TableSize
),
1537 return EFI_OUT_OF_RESOURCES
;
1540 if ((Trb
->Mode
== SdMmcAdma32bMode
) &&
1541 (UINT64
)(UINTN
)Trb
->AdmaDescPhy
> 0x100000000ul
) {
1543 // The ADMA doesn't support 64bit addressing.
1549 Trb
->AdmaMap
= NULL
;
1553 EFI_SIZE_TO_PAGES (TableSize
),
1556 return EFI_DEVICE_ERROR
;
1559 Remaining
= DataLen
;
1561 if (Trb
->Mode
== SdMmcAdma32bMode
) {
1562 Trb
->Adma32Desc
= AdmaDesc
;
1563 } else if (Trb
->Mode
== SdMmcAdma64bV3Mode
) {
1564 Trb
->Adma64V3Desc
= AdmaDesc
;
1566 Trb
->Adma64V4Desc
= AdmaDesc
;
1569 for (Index
= 0; Index
< Entries
; Index
++) {
1570 if (Trb
->Mode
== SdMmcAdma32bMode
) {
1571 if (Remaining
<= AdmaMaxDataPerLine
) {
1572 Trb
->Adma32Desc
[Index
].Valid
= 1;
1573 Trb
->Adma32Desc
[Index
].Act
= 2;
1574 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1575 Trb
->Adma32Desc
[Index
].UpperLength
= (UINT16
)RShiftU64 (Remaining
, 16);
1577 Trb
->Adma32Desc
[Index
].LowerLength
= (UINT16
)(Remaining
& MAX_UINT16
);
1578 Trb
->Adma32Desc
[Index
].Address
= (UINT32
)Address
;
1581 Trb
->Adma32Desc
[Index
].Valid
= 1;
1582 Trb
->Adma32Desc
[Index
].Act
= 2;
1583 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1584 Trb
->Adma32Desc
[Index
].UpperLength
= 0;
1586 Trb
->Adma32Desc
[Index
].LowerLength
= 0;
1587 Trb
->Adma32Desc
[Index
].Address
= (UINT32
)Address
;
1589 } else if (Trb
->Mode
== SdMmcAdma64bV3Mode
) {
1590 if (Remaining
<= AdmaMaxDataPerLine
) {
1591 Trb
->Adma64V3Desc
[Index
].Valid
= 1;
1592 Trb
->Adma64V3Desc
[Index
].Act
= 2;
1593 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1594 Trb
->Adma64V3Desc
[Index
].UpperLength
= (UINT16
)RShiftU64 (Remaining
, 16);
1596 Trb
->Adma64V3Desc
[Index
].LowerLength
= (UINT16
)(Remaining
& MAX_UINT16
);
1597 Trb
->Adma64V3Desc
[Index
].LowerAddress
= (UINT32
)Address
;
1598 Trb
->Adma64V3Desc
[Index
].UpperAddress
= (UINT32
)RShiftU64 (Address
, 32);
1601 Trb
->Adma64V3Desc
[Index
].Valid
= 1;
1602 Trb
->Adma64V3Desc
[Index
].Act
= 2;
1603 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1604 Trb
->Adma64V3Desc
[Index
].UpperLength
= 0;
1606 Trb
->Adma64V3Desc
[Index
].LowerLength
= 0;
1607 Trb
->Adma64V3Desc
[Index
].LowerAddress
= (UINT32
)Address
;
1608 Trb
->Adma64V3Desc
[Index
].UpperAddress
= (UINT32
)RShiftU64 (Address
, 32);
1611 if (Remaining
<= AdmaMaxDataPerLine
) {
1612 Trb
->Adma64V4Desc
[Index
].Valid
= 1;
1613 Trb
->Adma64V4Desc
[Index
].Act
= 2;
1614 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1615 Trb
->Adma64V4Desc
[Index
].UpperLength
= (UINT16
)RShiftU64 (Remaining
, 16);
1617 Trb
->Adma64V4Desc
[Index
].LowerLength
= (UINT16
)(Remaining
& MAX_UINT16
);
1618 Trb
->Adma64V4Desc
[Index
].LowerAddress
= (UINT32
)Address
;
1619 Trb
->Adma64V4Desc
[Index
].UpperAddress
= (UINT32
)RShiftU64 (Address
, 32);
1622 Trb
->Adma64V4Desc
[Index
].Valid
= 1;
1623 Trb
->Adma64V4Desc
[Index
].Act
= 2;
1624 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1625 Trb
->Adma64V4Desc
[Index
].UpperLength
= 0;
1627 Trb
->Adma64V4Desc
[Index
].LowerLength
= 0;
1628 Trb
->Adma64V4Desc
[Index
].LowerAddress
= (UINT32
)Address
;
1629 Trb
->Adma64V4Desc
[Index
].UpperAddress
= (UINT32
)RShiftU64 (Address
, 32);
1633 Remaining
-= AdmaMaxDataPerLine
;
1634 Address
+= AdmaMaxDataPerLine
;
1638 // Set the last descriptor line as end of descriptor table
1640 if (Trb
->Mode
== SdMmcAdma32bMode
) {
1641 Trb
->Adma32Desc
[Index
].End
= 1;
1642 } else if (Trb
->Mode
== SdMmcAdma64bV3Mode
) {
1643 Trb
->Adma64V3Desc
[Index
].End
= 1;
1645 Trb
->Adma64V4Desc
[Index
].End
= 1;
1651 Prints the contents of the command packet to the debug port.
1653 @param[in] DebugLevel Debug level at which the packet should be printed.
1654 @param[in] Packet Pointer to packet to print.
1658 IN UINT32 DebugLevel
,
1659 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
1662 if (Packet
== NULL
) {
1666 DEBUG ((DebugLevel
, "Printing EFI_SD_MMC_PASS_THRU_COMMAND_PACKET\n"));
1667 if (Packet
->SdMmcCmdBlk
!= NULL
) {
1668 DEBUG ((DebugLevel
, "Command index: %d, argument: %X\n", Packet
->SdMmcCmdBlk
->CommandIndex
, Packet
->SdMmcCmdBlk
->CommandArgument
));
1669 DEBUG ((DebugLevel
, "Command type: %d, response type: %d\n", Packet
->SdMmcCmdBlk
->CommandType
, Packet
->SdMmcCmdBlk
->ResponseType
));
1671 if (Packet
->SdMmcStatusBlk
!= NULL
) {
1672 DEBUG ((DebugLevel
, "Response 0: %X, 1: %X, 2: %X, 3: %X\n",
1673 Packet
->SdMmcStatusBlk
->Resp0
,
1674 Packet
->SdMmcStatusBlk
->Resp1
,
1675 Packet
->SdMmcStatusBlk
->Resp2
,
1676 Packet
->SdMmcStatusBlk
->Resp3
1679 DEBUG ((DebugLevel
, "Timeout: %ld\n", Packet
->Timeout
));
1680 DEBUG ((DebugLevel
, "InDataBuffer: %p\n", Packet
->InDataBuffer
));
1681 DEBUG ((DebugLevel
, "OutDataBuffer: %p\n", Packet
->OutDataBuffer
));
1682 DEBUG ((DebugLevel
, "InTransferLength: %d\n", Packet
->InTransferLength
));
1683 DEBUG ((DebugLevel
, "OutTransferLength: %d\n", Packet
->OutTransferLength
));
1684 DEBUG ((DebugLevel
, "TransactionStatus: %r\n", Packet
->TransactionStatus
));
1688 Prints the contents of the TRB to the debug port.
1690 @param[in] DebugLevel Debug level at which the TRB should be printed.
1691 @param[in] Trb Pointer to the TRB structure.
1695 IN UINT32 DebugLevel
,
1696 IN SD_MMC_HC_TRB
*Trb
1703 DEBUG ((DebugLevel
, "Printing SD_MMC_HC_TRB\n"));
1704 DEBUG ((DebugLevel
, "Slot: %d\n", Trb
->Slot
));
1705 DEBUG ((DebugLevel
, "BlockSize: %d\n", Trb
->BlockSize
));
1706 DEBUG ((DebugLevel
, "Data: %p\n", Trb
->Data
));
1707 DEBUG ((DebugLevel
, "DataLen: %d\n", Trb
->DataLen
));
1708 DEBUG ((DebugLevel
, "Read: %d\n", Trb
->Read
));
1709 DEBUG ((DebugLevel
, "DataPhy: %lX\n", Trb
->DataPhy
));
1710 DEBUG ((DebugLevel
, "DataMap: %p\n", Trb
->DataMap
));
1711 DEBUG ((DebugLevel
, "Mode: %d\n", Trb
->Mode
));
1712 DEBUG ((DebugLevel
, "AdmaLengthMode: %d\n", Trb
->AdmaLengthMode
));
1713 DEBUG ((DebugLevel
, "Event: %p\n", Trb
->Event
));
1714 DEBUG ((DebugLevel
, "Started: %d\n", Trb
->Started
));
1715 DEBUG ((DebugLevel
, "CommandComplete: %d\n", Trb
->CommandComplete
));
1716 DEBUG ((DebugLevel
, "Timeout: %ld\n", Trb
->Timeout
));
1717 DEBUG ((DebugLevel
, "Retries: %d\n", Trb
->Retries
));
1718 DEBUG ((DebugLevel
, "Adma32Desc: %p\n", Trb
->Adma32Desc
));
1719 DEBUG ((DebugLevel
, "Adma64V3Desc: %p\n", Trb
->Adma64V3Desc
));
1720 DEBUG ((DebugLevel
, "Adma64V4Desc: %p\n", Trb
->Adma64V4Desc
));
1721 DEBUG ((DebugLevel
, "AdmaMap: %p\n", Trb
->AdmaMap
));
1722 DEBUG ((DebugLevel
, "AdmaPages: %X\n", Trb
->AdmaPages
));
1724 SdMmcPrintPacket (DebugLevel
, Trb
->Packet
);
1728 Create a new TRB for the SD/MMC cmd request.
1730 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1731 @param[in] Slot The slot number of the SD card to send the command to.
1732 @param[in] Packet A pointer to the SD command data structure.
1733 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
1734 not NULL, then nonblocking I/O is performed, and Event
1735 will be signaled when the Packet completes.
1737 @return Created Trb or NULL.
1742 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1744 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
,
1751 EFI_PCI_IO_PROTOCOL_OPERATION Flag
;
1752 EFI_PCI_IO_PROTOCOL
*PciIo
;
1755 Trb
= AllocateZeroPool (sizeof (SD_MMC_HC_TRB
));
1760 Trb
->Signature
= SD_MMC_HC_TRB_SIG
;
1762 Trb
->BlockSize
= 0x200;
1763 Trb
->Packet
= Packet
;
1765 Trb
->Started
= FALSE
;
1766 Trb
->CommandComplete
= FALSE
;
1767 Trb
->Timeout
= Packet
->Timeout
;
1768 Trb
->Retries
= SD_MMC_TRB_RETRIES
;
1769 Trb
->Private
= Private
;
1771 if ((Packet
->InTransferLength
!= 0) && (Packet
->InDataBuffer
!= NULL
)) {
1772 Trb
->Data
= Packet
->InDataBuffer
;
1773 Trb
->DataLen
= Packet
->InTransferLength
;
1775 } else if ((Packet
->OutTransferLength
!= 0) && (Packet
->OutDataBuffer
!= NULL
)) {
1776 Trb
->Data
= Packet
->OutDataBuffer
;
1777 Trb
->DataLen
= Packet
->OutTransferLength
;
1779 } else if ((Packet
->InTransferLength
== 0) && (Packet
->OutTransferLength
== 0)) {
1786 if ((Trb
->DataLen
!= 0) && (Trb
->DataLen
< Trb
->BlockSize
)) {
1787 Trb
->BlockSize
= (UINT16
)Trb
->DataLen
;
1790 if (((Private
->Slot
[Trb
->Slot
].CardType
== EmmcCardType
) &&
1791 (Packet
->SdMmcCmdBlk
->CommandIndex
== EMMC_SEND_TUNING_BLOCK
)) ||
1792 ((Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) &&
1793 (Packet
->SdMmcCmdBlk
->CommandIndex
== SD_SEND_TUNING_BLOCK
))) {
1794 Trb
->Mode
= SdMmcPioMode
;
1797 Flag
= EfiPciIoOperationBusMasterWrite
;
1799 Flag
= EfiPciIoOperationBusMasterRead
;
1802 PciIo
= Private
->PciIo
;
1803 if (Trb
->DataLen
!= 0) {
1804 MapLength
= Trb
->DataLen
;
1805 Status
= PciIo
->Map (
1813 if (EFI_ERROR (Status
) || (Trb
->DataLen
!= MapLength
)) {
1814 Status
= EFI_BAD_BUFFER_SIZE
;
1819 if (Trb
->DataLen
== 0) {
1820 Trb
->Mode
= SdMmcNoData
;
1821 } else if (Private
->Capability
[Slot
].Adma2
!= 0) {
1822 Trb
->Mode
= SdMmcAdma32bMode
;
1823 Trb
->AdmaLengthMode
= SdMmcAdmaLen16b
;
1824 if ((Private
->ControllerVersion
[Slot
] == SD_MMC_HC_CTRL_VER_300
) &&
1825 (Private
->Capability
[Slot
].SysBus64V3
== 1)) {
1826 Trb
->Mode
= SdMmcAdma64bV3Mode
;
1827 } else if (((Private
->ControllerVersion
[Slot
] == SD_MMC_HC_CTRL_VER_400
) &&
1828 (Private
->Capability
[Slot
].SysBus64V3
== 1)) ||
1829 ((Private
->ControllerVersion
[Slot
] >= SD_MMC_HC_CTRL_VER_410
) &&
1830 (Private
->Capability
[Slot
].SysBus64V4
== 1))) {
1831 Trb
->Mode
= SdMmcAdma64bV4Mode
;
1833 if (Private
->ControllerVersion
[Slot
] >= SD_MMC_HC_CTRL_VER_410
) {
1834 Trb
->AdmaLengthMode
= SdMmcAdmaLen26b
;
1836 Status
= BuildAdmaDescTable (Trb
, Private
->ControllerVersion
[Slot
]);
1837 if (EFI_ERROR (Status
)) {
1840 } else if (Private
->Capability
[Slot
].Sdma
!= 0) {
1841 Trb
->Mode
= SdMmcSdmaMode
;
1843 Trb
->Mode
= SdMmcPioMode
;
1847 if (Event
!= NULL
) {
1848 OldTpl
= gBS
->RaiseTPL (TPL_NOTIFY
);
1849 InsertTailList (&Private
->Queue
, &Trb
->TrbList
);
1850 gBS
->RestoreTPL (OldTpl
);
1861 Free the resource used by the TRB.
1863 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1868 IN SD_MMC_HC_TRB
*Trb
1871 EFI_PCI_IO_PROTOCOL
*PciIo
;
1873 PciIo
= Trb
->Private
->PciIo
;
1875 if (Trb
->AdmaMap
!= NULL
) {
1881 if (Trb
->Adma32Desc
!= NULL
) {
1888 if (Trb
->Adma64V3Desc
!= NULL
) {
1895 if (Trb
->Adma64V4Desc
!= NULL
) {
1902 if (Trb
->DataMap
!= NULL
) {
1913 Check if the env is ready for execute specified TRB.
1915 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1916 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1918 @retval EFI_SUCCESS The env is ready for TRB execution.
1919 @retval EFI_NOT_READY The env is not ready for TRB execution.
1920 @retval Others Some erros happen.
1925 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1926 IN SD_MMC_HC_TRB
*Trb
1930 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1931 EFI_PCI_IO_PROTOCOL
*PciIo
;
1932 UINT32 PresentState
;
1934 Packet
= Trb
->Packet
;
1936 if ((Packet
->SdMmcCmdBlk
->CommandType
== SdMmcCommandTypeAdtc
) ||
1937 (Packet
->SdMmcCmdBlk
->ResponseType
== SdMmcResponseTypeR1b
) ||
1938 (Packet
->SdMmcCmdBlk
->ResponseType
== SdMmcResponseTypeR5b
)) {
1940 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1941 // the Present State register to be 0
1943 PresentState
= BIT0
| BIT1
;
1946 // Wait Command Inhibit (CMD) in the Present State register
1949 PresentState
= BIT0
;
1952 PciIo
= Private
->PciIo
;
1953 Status
= SdMmcHcCheckMmioSet (
1956 SD_MMC_HC_PRESENT_STATE
,
1957 sizeof (PresentState
),
1966 Wait for the env to be ready for execute specified TRB.
1968 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1969 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1971 @retval EFI_SUCCESS The env is ready for TRB execution.
1972 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
1973 @retval Others Some erros happen.
1978 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1979 IN SD_MMC_HC_TRB
*Trb
1983 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1985 BOOLEAN InfiniteWait
;
1988 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1990 Packet
= Trb
->Packet
;
1991 Timeout
= Packet
->Timeout
;
1993 InfiniteWait
= TRUE
;
1995 InfiniteWait
= FALSE
;
1998 while (InfiniteWait
|| (Timeout
> 0)) {
2000 // Check Trb execution result by reading Normal Interrupt Status register.
2002 Status
= SdMmcCheckTrbEnv (Private
, Trb
);
2003 if (Status
!= EFI_NOT_READY
) {
2007 // Stall for 1 microsecond.
2018 Execute the specified TRB.
2020 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2021 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2023 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
2024 @retval Others Some erros happen when sending this request to the host controller.
2029 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2030 IN SD_MMC_HC_TRB
*Trb
2034 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
2035 EFI_PCI_IO_PROTOCOL
*PciIo
;
2045 BOOLEAN AddressingMode64
;
2047 AddressingMode64
= FALSE
;
2049 Packet
= Trb
->Packet
;
2050 PciIo
= Trb
->Private
->PciIo
;
2052 // Clear all bits in Error Interrupt Status Register
2055 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ERR_INT_STS
, FALSE
, sizeof (IntStatus
), &IntStatus
);
2056 if (EFI_ERROR (Status
)) {
2060 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
2063 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (IntStatus
), &IntStatus
);
2064 if (EFI_ERROR (Status
)) {
2068 if (Private
->ControllerVersion
[Trb
->Slot
] >= SD_MMC_HC_CTRL_VER_400
) {
2069 Status
= SdMmcHcCheckMmioSet(PciIo
, Trb
->Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof(UINT16
),
2070 SD_MMC_HC_64_ADDR_EN
, SD_MMC_HC_64_ADDR_EN
);
2071 if (!EFI_ERROR (Status
)) {
2072 AddressingMode64
= TRUE
;
2077 // Set Host Control 1 register DMA Select field
2079 if ((Trb
->Mode
== SdMmcAdma32bMode
) ||
2080 (Trb
->Mode
== SdMmcAdma64bV4Mode
)) {
2082 Status
= SdMmcHcOrMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
2083 if (EFI_ERROR (Status
)) {
2086 } else if (Trb
->Mode
== SdMmcAdma64bV3Mode
) {
2087 HostCtrl1
= BIT4
|BIT3
;
2088 Status
= SdMmcHcOrMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
2089 if (EFI_ERROR (Status
)) {
2094 SdMmcHcLedOnOff (PciIo
, Trb
->Slot
, TRUE
);
2096 if (Trb
->Mode
== SdMmcSdmaMode
) {
2097 if ((!AddressingMode64
) &&
2098 ((UINT64
)(UINTN
)Trb
->DataPhy
>= 0x100000000ul
)) {
2099 return EFI_INVALID_PARAMETER
;
2102 SdmaAddr
= (UINT64
)(UINTN
)Trb
->DataPhy
;
2104 if (Private
->ControllerVersion
[Trb
->Slot
] >= SD_MMC_HC_CTRL_VER_400
) {
2105 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ADMA_SYS_ADDR
, FALSE
, sizeof (UINT64
), &SdmaAddr
);
2107 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_SDMA_ADDR
, FALSE
, sizeof (UINT32
), &SdmaAddr
);
2110 if (EFI_ERROR (Status
)) {
2113 } else if ((Trb
->Mode
== SdMmcAdma32bMode
) ||
2114 (Trb
->Mode
== SdMmcAdma64bV3Mode
) ||
2115 (Trb
->Mode
== SdMmcAdma64bV4Mode
)) {
2116 AdmaAddr
= (UINT64
)(UINTN
)Trb
->AdmaDescPhy
;
2117 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ADMA_SYS_ADDR
, FALSE
, sizeof (AdmaAddr
), &AdmaAddr
);
2118 if (EFI_ERROR (Status
)) {
2123 BlkSize
= Trb
->BlockSize
;
2124 if (Trb
->Mode
== SdMmcSdmaMode
) {
2126 // Set SDMA boundary to be 512K bytes.
2131 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_BLK_SIZE
, FALSE
, sizeof (BlkSize
), &BlkSize
);
2132 if (EFI_ERROR (Status
)) {
2137 if (Trb
->Mode
!= SdMmcNoData
) {
2139 // Calcuate Block Count.
2141 BlkCount
= (Trb
->DataLen
/ Trb
->BlockSize
);
2143 if (Private
->ControllerVersion
[Trb
->Slot
] >= SD_MMC_HC_CTRL_VER_410
) {
2144 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_SDMA_ADDR
, FALSE
, sizeof (UINT32
), &BlkCount
);
2146 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_BLK_COUNT
, FALSE
, sizeof (UINT16
), &BlkCount
);
2148 if (EFI_ERROR (Status
)) {
2152 Argument
= Packet
->SdMmcCmdBlk
->CommandArgument
;
2153 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ARG1
, FALSE
, sizeof (Argument
), &Argument
);
2154 if (EFI_ERROR (Status
)) {
2159 if (Trb
->Mode
!= SdMmcNoData
) {
2160 if (Trb
->Mode
!= SdMmcPioMode
) {
2167 TransMode
|= BIT5
| BIT1
;
2170 // Only SD memory card needs to use AUTO CMD12 feature.
2172 if (Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) {
2179 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_TRANS_MOD
, FALSE
, sizeof (TransMode
), &TransMode
);
2180 if (EFI_ERROR (Status
)) {
2184 Cmd
= (UINT16
)LShiftU64(Packet
->SdMmcCmdBlk
->CommandIndex
, 8);
2185 if (Packet
->SdMmcCmdBlk
->CommandType
== SdMmcCommandTypeAdtc
) {
2189 // Convert ResponseType to value
2191 if (Packet
->SdMmcCmdBlk
->CommandType
!= SdMmcCommandTypeBc
) {
2192 switch (Packet
->SdMmcCmdBlk
->ResponseType
) {
2193 case SdMmcResponseTypeR1
:
2194 case SdMmcResponseTypeR5
:
2195 case SdMmcResponseTypeR6
:
2196 case SdMmcResponseTypeR7
:
2197 Cmd
|= (BIT1
| BIT3
| BIT4
);
2199 case SdMmcResponseTypeR2
:
2200 Cmd
|= (BIT0
| BIT3
);
2202 case SdMmcResponseTypeR3
:
2203 case SdMmcResponseTypeR4
:
2206 case SdMmcResponseTypeR1b
:
2207 case SdMmcResponseTypeR5b
:
2208 Cmd
|= (BIT0
| BIT1
| BIT3
| BIT4
);
2218 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_COMMAND
, FALSE
, sizeof (Cmd
), &Cmd
);
2223 Performs SW reset based on passed error status mask.
2225 @param[in] Private Pointer to driver private data.
2226 @param[in] Slot Index of the slot to reset.
2227 @param[in] ErrIntStatus Error interrupt status mask.
2229 @retval EFI_SUCCESS Software reset performed successfully.
2230 @retval Other Software reset failed.
2233 SdMmcSoftwareReset (
2234 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2236 IN UINT16 ErrIntStatus
2243 if ((ErrIntStatus
& 0x0F) != 0) {
2246 if ((ErrIntStatus
& 0x70) != 0) {
2250 Status
= SdMmcHcRwMmio (
2258 if (EFI_ERROR (Status
)) {
2262 Status
= SdMmcHcWaitMmioSet (
2269 SD_MMC_HC_GENERIC_TIMEOUT
2271 if (EFI_ERROR (Status
)) {
2279 Checks the error status in error status register
2280 and issues appropriate software reset as described in
2281 SD specification section 3.10.
2283 @param[in] Private Pointer to driver private data.
2284 @param[in] Slot Index of the slot for device.
2285 @param[in] IntStatus Normal interrupt status mask.
2287 @retval EFI_CRC_ERROR CRC error happened during CMD execution.
2288 @retval EFI_SUCCESS No error reported.
2289 @retval Others Some other error happened.
2293 SdMmcCheckAndRecoverErrors (
2294 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2299 UINT16 ErrIntStatus
;
2301 EFI_STATUS ErrorStatus
;
2303 if ((IntStatus
& BIT15
) == 0) {
2307 Status
= SdMmcHcRwMmio (
2310 SD_MMC_HC_ERR_INT_STS
,
2312 sizeof (ErrIntStatus
),
2315 if (EFI_ERROR (Status
)) {
2319 DEBUG ((DEBUG_ERROR
, "Error reported by SDHCI\n"));
2320 DEBUG ((DEBUG_ERROR
, "Interrupt status = %X\n", IntStatus
));
2321 DEBUG ((DEBUG_ERROR
, "Error interrupt status = %X\n", ErrIntStatus
));
2324 // If the data timeout error is reported
2325 // but data transfer is signaled as completed we
2326 // have to ignore data timeout. We also assume that no
2327 // other error is present on the link since data transfer
2328 // completed successfully. Error interrupt status
2329 // register is going to be reset when the next command
2332 if (((ErrIntStatus
& BIT4
) != 0) && ((IntStatus
& BIT1
) != 0)) {
2337 // We treat both CMD and DAT CRC errors and
2338 // end bits errors as EFI_CRC_ERROR. This will
2339 // let higher layer know that the error possibly
2340 // happened due to random bus condition and the
2341 // command can be retried.
2343 if ((ErrIntStatus
& (BIT1
| BIT2
| BIT5
| BIT6
)) != 0) {
2344 ErrorStatus
= EFI_CRC_ERROR
;
2346 ErrorStatus
= EFI_DEVICE_ERROR
;
2349 Status
= SdMmcSoftwareReset (Private
, Slot
, ErrIntStatus
);
2350 if (EFI_ERROR (Status
)) {
2358 Reads the response data into the TRB buffer.
2359 This function assumes that caller made sure that
2360 command has completed.
2362 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2363 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2365 @retval EFI_SUCCESS Response read successfully.
2366 @retval Others Failed to get response.
2370 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2371 IN SD_MMC_HC_TRB
*Trb
2374 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
2379 Packet
= Trb
->Packet
;
2381 if (Packet
->SdMmcCmdBlk
->CommandType
== SdMmcCommandTypeBc
) {
2385 for (Index
= 0; Index
< 4; Index
++) {
2386 Status
= SdMmcHcRwMmio (
2389 SD_MMC_HC_RESPONSE
+ Index
* 4,
2394 if (EFI_ERROR (Status
)) {
2398 CopyMem (Packet
->SdMmcStatusBlk
, Response
, sizeof (Response
));
2404 Checks if the command completed. If the command
2405 completed it gets the response and records the
2406 command completion in the TRB.
2408 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2409 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2410 @param[in] IntStatus Snapshot of the normal interrupt status register.
2412 @retval EFI_SUCCESS Command completed successfully.
2413 @retval EFI_NOT_READY Command completion still pending.
2414 @retval Others Command failed to complete.
2417 SdMmcCheckCommandComplete (
2418 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2419 IN SD_MMC_HC_TRB
*Trb
,
2426 if ((IntStatus
& BIT0
) != 0) {
2428 Status
= SdMmcHcRwMmio (
2431 SD_MMC_HC_NOR_INT_STS
,
2436 if (EFI_ERROR (Status
)) {
2439 Status
= SdMmcGetResponse (Private
, Trb
);
2440 if (EFI_ERROR (Status
)) {
2443 Trb
->CommandComplete
= TRUE
;
2447 return EFI_NOT_READY
;
2451 Check the TRB execution result.
2453 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2454 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2456 @retval EFI_SUCCESS The TRB is executed successfully.
2457 @retval EFI_NOT_READY The TRB is not completed for execution.
2458 @retval Others Some erros happen when executing this request.
2462 SdMmcCheckTrbResult (
2463 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2464 IN SD_MMC_HC_TRB
*Trb
2468 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
2473 Packet
= Trb
->Packet
;
2475 // Check Trb execution result by reading Normal Interrupt Status register.
2477 Status
= SdMmcHcRwMmio (
2480 SD_MMC_HC_NOR_INT_STS
,
2485 if (EFI_ERROR (Status
)) {
2490 // Check if there are any errors reported by host controller
2491 // and if neccessary recover the controller before next command is executed.
2493 Status
= SdMmcCheckAndRecoverErrors (Private
, Trb
->Slot
, IntStatus
);
2494 if (EFI_ERROR (Status
)) {
2499 // Tuning commands are the only ones that do not generate command
2500 // complete interrupt. Process them here before entering the code
2501 // that waits for command completion.
2503 if (((Private
->Slot
[Trb
->Slot
].CardType
== EmmcCardType
) &&
2504 (Packet
->SdMmcCmdBlk
->CommandIndex
== EMMC_SEND_TUNING_BLOCK
)) ||
2505 ((Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) &&
2506 (Packet
->SdMmcCmdBlk
->CommandIndex
== SD_SEND_TUNING_BLOCK
))) {
2508 // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,
2509 // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.
2510 // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.
2512 if ((IntStatus
& BIT5
) == BIT5
) {
2514 // Clear Buffer Read Ready interrupt at first.
2517 SdMmcHcRwMmio (Private
->PciIo
, Trb
->Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (IntStatus
), &IntStatus
);
2519 // Read data out from Buffer Port register
2521 for (PioLength
= 0; PioLength
< Trb
->DataLen
; PioLength
+= 4) {
2522 SdMmcHcRwMmio (Private
->PciIo
, Trb
->Slot
, SD_MMC_HC_BUF_DAT_PORT
, TRUE
, 4, (UINT8
*)Trb
->Data
+ PioLength
);
2524 Status
= EFI_SUCCESS
;
2529 if (!Trb
->CommandComplete
) {
2530 Status
= SdMmcCheckCommandComplete (Private
, Trb
, IntStatus
);
2531 if (EFI_ERROR (Status
)) {
2535 // If the command doesn't require data transfer skip the transfer
2536 // complete checking.
2538 if ((Packet
->SdMmcCmdBlk
->CommandType
!= SdMmcCommandTypeAdtc
) &&
2539 (Packet
->SdMmcCmdBlk
->ResponseType
!= SdMmcResponseTypeR1b
) &&
2540 (Packet
->SdMmcCmdBlk
->ResponseType
!= SdMmcResponseTypeR5b
)) {
2547 // Check Transfer Complete bit is set or not.
2549 if ((IntStatus
& BIT1
) == BIT1
) {
2554 // Check if DMA interrupt is signalled for the SDMA transfer.
2556 if ((Trb
->Mode
== SdMmcSdmaMode
) && ((IntStatus
& BIT3
) == BIT3
)) {
2558 // Clear DMA interrupt bit.
2561 Status
= SdMmcHcRwMmio (
2564 SD_MMC_HC_NOR_INT_STS
,
2569 if (EFI_ERROR (Status
)) {
2573 // Update SDMA Address register.
2575 SdmaAddr
= SD_MMC_SDMA_ROUND_UP ((UINTN
)Trb
->DataPhy
, SD_MMC_SDMA_BOUNDARY
);
2577 if (Private
->ControllerVersion
[Trb
->Slot
] >= SD_MMC_HC_CTRL_VER_400
) {
2578 Status
= SdMmcHcRwMmio (
2581 SD_MMC_HC_ADMA_SYS_ADDR
,
2587 Status
= SdMmcHcRwMmio (
2590 SD_MMC_HC_SDMA_ADDR
,
2597 if (EFI_ERROR (Status
)) {
2600 Trb
->DataPhy
= (UINT64
)(UINTN
)SdmaAddr
;
2604 Status
= EFI_NOT_READY
;
2607 if (Status
!= EFI_NOT_READY
) {
2608 SdMmcHcLedOnOff (Private
->PciIo
, Trb
->Slot
, FALSE
);
2609 if (EFI_ERROR (Status
)) {
2610 DEBUG ((DEBUG_ERROR
, "TRB failed with %r\n", Status
));
2611 SdMmcPrintTrb (DEBUG_ERROR
, Trb
);
2613 DEBUG ((DEBUG_VERBOSE
, "TRB success\n"));
2614 SdMmcPrintTrb (DEBUG_VERBOSE
, Trb
);
2622 Wait for the TRB execution result.
2624 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2625 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2627 @retval EFI_SUCCESS The TRB is executed successfully.
2628 @retval Others Some erros happen when executing this request.
2632 SdMmcWaitTrbResult (
2633 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2634 IN SD_MMC_HC_TRB
*Trb
2638 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
2640 BOOLEAN InfiniteWait
;
2642 Packet
= Trb
->Packet
;
2644 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
2646 Timeout
= Packet
->Timeout
;
2648 InfiniteWait
= TRUE
;
2650 InfiniteWait
= FALSE
;
2653 while (InfiniteWait
|| (Timeout
> 0)) {
2655 // Check Trb execution result by reading Normal Interrupt Status register.
2657 Status
= SdMmcCheckTrbResult (Private
, Trb
);
2658 if (Status
!= EFI_NOT_READY
) {
2662 // Stall for 1 microsecond.