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MdeModulePkg/SdMmcPciHcDxe: Update comment for spec compliance status
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcDxe / SdMmcPciHci.c
1 /** @file
2 This driver is used to manage SD/MMC PCI host controllers which are compliance
3 with SD Host Controller Simplified Specification version 3.00 plus the 64-bit
4 System Addressing support in SD Host Controller Simplified Specification version
5 4.20.
6
7 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
8
9 Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
10 Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
11 This program and the accompanying materials
12 are licensed and made available under the terms and conditions of the BSD License
13 which accompanies this distribution. The full text of the license may be found at
14 http://opensource.org/licenses/bsd-license.php
15
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18
19 **/
20
21 #include "SdMmcPciHcDxe.h"
22
23 /**
24 Dump the content of SD/MMC host controller's Capability Register.
25
26 @param[in] Slot The slot number of the SD card to send the command to.
27 @param[in] Capability The buffer to store the capability data.
28
29 **/
30 VOID
31 DumpCapabilityReg (
32 IN UINT8 Slot,
33 IN SD_MMC_HC_SLOT_CAP *Capability
34 )
35 {
36 //
37 // Dump Capability Data
38 //
39 DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));
40 DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));
41 DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkFreq));
42 DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));
43 DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));
44 DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));
45 DEBUG ((DEBUG_INFO, " HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));
46 DEBUG ((DEBUG_INFO, " SDMA Support %a\n", Capability->Sdma ? "TRUE" : "FALSE"));
47 DEBUG ((DEBUG_INFO, " Suspend/Resume %a\n", Capability->SuspRes ? "TRUE" : "FALSE"));
48 DEBUG ((DEBUG_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));
49 DEBUG ((DEBUG_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));
50 DEBUG ((DEBUG_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));
51 DEBUG ((DEBUG_INFO, " V4 64-bit Sys Bus %a\n", Capability->SysBus64V4 ? "TRUE" : "FALSE"));
52 DEBUG ((DEBUG_INFO, " V3 64-bit Sys Bus %a\n", Capability->SysBus64V3 ? "TRUE" : "FALSE"));
53 DEBUG ((DEBUG_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));
54 DEBUG ((DEBUG_INFO, " SlotType "));
55 if (Capability->SlotType == 0x00) {
56 DEBUG ((DEBUG_INFO, "%a\n", "Removable Slot"));
57 } else if (Capability->SlotType == 0x01) {
58 DEBUG ((DEBUG_INFO, "%a\n", "Embedded Slot"));
59 } else if (Capability->SlotType == 0x02) {
60 DEBUG ((DEBUG_INFO, "%a\n", "Shared Bus Slot"));
61 } else {
62 DEBUG ((DEBUG_INFO, "%a\n", "Reserved"));
63 }
64 DEBUG ((DEBUG_INFO, " SDR50 Support %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));
65 DEBUG ((DEBUG_INFO, " SDR104 Support %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));
66 DEBUG ((DEBUG_INFO, " DDR50 Support %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));
67 DEBUG ((DEBUG_INFO, " Driver Type A %a\n", Capability->DriverTypeA ? "TRUE" : "FALSE"));
68 DEBUG ((DEBUG_INFO, " Driver Type C %a\n", Capability->DriverTypeC ? "TRUE" : "FALSE"));
69 DEBUG ((DEBUG_INFO, " Driver Type D %a\n", Capability->DriverTypeD ? "TRUE" : "FALSE"));
70 DEBUG ((DEBUG_INFO, " Driver Type 4 %a\n", Capability->DriverType4 ? "TRUE" : "FALSE"));
71 if (Capability->TimerCount == 0) {
72 DEBUG ((DEBUG_INFO, " Retuning TimerCnt Disabled\n", 2 * (Capability->TimerCount - 1)));
73 } else {
74 DEBUG ((DEBUG_INFO, " Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));
75 }
76 DEBUG ((DEBUG_INFO, " SDR50 Tuning %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));
77 DEBUG ((DEBUG_INFO, " Retuning Mode Mode %d\n", Capability->RetuningMod + 1));
78 DEBUG ((DEBUG_INFO, " Clock Multiplier M = %d\n", Capability->ClkMultiplier + 1));
79 DEBUG ((DEBUG_INFO, " HS 400 %a\n", Capability->Hs400 ? "TRUE" : "FALSE"));
80 return;
81 }
82
83 /**
84 Read SlotInfo register from SD/MMC host controller pci config space.
85
86 @param[in] PciIo The PCI IO protocol instance.
87 @param[out] FirstBar The buffer to store the first BAR value.
88 @param[out] SlotNum The buffer to store the supported slot number.
89
90 @retval EFI_SUCCESS The operation succeeds.
91 @retval Others The operation fails.
92
93 **/
94 EFI_STATUS
95 EFIAPI
96 SdMmcHcGetSlotInfo (
97 IN EFI_PCI_IO_PROTOCOL *PciIo,
98 OUT UINT8 *FirstBar,
99 OUT UINT8 *SlotNum
100 )
101 {
102 EFI_STATUS Status;
103 SD_MMC_HC_SLOT_INFO SlotInfo;
104
105 Status = PciIo->Pci.Read (
106 PciIo,
107 EfiPciIoWidthUint8,
108 SD_MMC_HC_SLOT_OFFSET,
109 sizeof (SlotInfo),
110 &SlotInfo
111 );
112 if (EFI_ERROR (Status)) {
113 return Status;
114 }
115
116 *FirstBar = SlotInfo.FirstBar;
117 *SlotNum = SlotInfo.SlotNum + 1;
118 ASSERT ((*FirstBar + *SlotNum) < SD_MMC_HC_MAX_SLOT);
119 return EFI_SUCCESS;
120 }
121
122 /**
123 Read/Write specified SD/MMC host controller mmio register.
124
125 @param[in] PciIo The PCI IO protocol instance.
126 @param[in] BarIndex The BAR index of the standard PCI Configuration
127 header to use as the base address for the memory
128 operation to perform.
129 @param[in] Offset The offset within the selected BAR to start the
130 memory operation.
131 @param[in] Read A boolean to indicate it's read or write operation.
132 @param[in] Count The width of the mmio register in bytes.
133 Must be 1, 2 , 4 or 8 bytes.
134 @param[in, out] Data For read operations, the destination buffer to store
135 the results. For write operations, the source buffer
136 to write data from. The caller is responsible for
137 having ownership of the data buffer and ensuring its
138 size not less than Count bytes.
139
140 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
141 @retval EFI_SUCCESS The read/write operation succeeds.
142 @retval Others The read/write operation fails.
143
144 **/
145 EFI_STATUS
146 EFIAPI
147 SdMmcHcRwMmio (
148 IN EFI_PCI_IO_PROTOCOL *PciIo,
149 IN UINT8 BarIndex,
150 IN UINT32 Offset,
151 IN BOOLEAN Read,
152 IN UINT8 Count,
153 IN OUT VOID *Data
154 )
155 {
156 EFI_STATUS Status;
157
158 if ((PciIo == NULL) || (Data == NULL)) {
159 return EFI_INVALID_PARAMETER;
160 }
161
162 if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {
163 return EFI_INVALID_PARAMETER;
164 }
165
166 if (Read) {
167 Status = PciIo->Mem.Read (
168 PciIo,
169 EfiPciIoWidthUint8,
170 BarIndex,
171 (UINT64) Offset,
172 Count,
173 Data
174 );
175 } else {
176 Status = PciIo->Mem.Write (
177 PciIo,
178 EfiPciIoWidthUint8,
179 BarIndex,
180 (UINT64) Offset,
181 Count,
182 Data
183 );
184 }
185
186 return Status;
187 }
188
189 /**
190 Do OR operation with the value of the specified SD/MMC host controller mmio register.
191
192 @param[in] PciIo The PCI IO protocol instance.
193 @param[in] BarIndex The BAR index of the standard PCI Configuration
194 header to use as the base address for the memory
195 operation to perform.
196 @param[in] Offset The offset within the selected BAR to start the
197 memory operation.
198 @param[in] Count The width of the mmio register in bytes.
199 Must be 1, 2 , 4 or 8 bytes.
200 @param[in] OrData The pointer to the data used to do OR operation.
201 The caller is responsible for having ownership of
202 the data buffer and ensuring its size not less than
203 Count bytes.
204
205 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
206 @retval EFI_SUCCESS The OR operation succeeds.
207 @retval Others The OR operation fails.
208
209 **/
210 EFI_STATUS
211 EFIAPI
212 SdMmcHcOrMmio (
213 IN EFI_PCI_IO_PROTOCOL *PciIo,
214 IN UINT8 BarIndex,
215 IN UINT32 Offset,
216 IN UINT8 Count,
217 IN VOID *OrData
218 )
219 {
220 EFI_STATUS Status;
221 UINT64 Data;
222 UINT64 Or;
223
224 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
225 if (EFI_ERROR (Status)) {
226 return Status;
227 }
228
229 if (Count == 1) {
230 Or = *(UINT8*) OrData;
231 } else if (Count == 2) {
232 Or = *(UINT16*) OrData;
233 } else if (Count == 4) {
234 Or = *(UINT32*) OrData;
235 } else if (Count == 8) {
236 Or = *(UINT64*) OrData;
237 } else {
238 return EFI_INVALID_PARAMETER;
239 }
240
241 Data |= Or;
242 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
243
244 return Status;
245 }
246
247 /**
248 Do AND operation with the value of the specified SD/MMC host controller mmio register.
249
250 @param[in] PciIo The PCI IO protocol instance.
251 @param[in] BarIndex The BAR index of the standard PCI Configuration
252 header to use as the base address for the memory
253 operation to perform.
254 @param[in] Offset The offset within the selected BAR to start the
255 memory operation.
256 @param[in] Count The width of the mmio register in bytes.
257 Must be 1, 2 , 4 or 8 bytes.
258 @param[in] AndData The pointer to the data used to do AND operation.
259 The caller is responsible for having ownership of
260 the data buffer and ensuring its size not less than
261 Count bytes.
262
263 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
264 @retval EFI_SUCCESS The AND operation succeeds.
265 @retval Others The AND operation fails.
266
267 **/
268 EFI_STATUS
269 EFIAPI
270 SdMmcHcAndMmio (
271 IN EFI_PCI_IO_PROTOCOL *PciIo,
272 IN UINT8 BarIndex,
273 IN UINT32 Offset,
274 IN UINT8 Count,
275 IN VOID *AndData
276 )
277 {
278 EFI_STATUS Status;
279 UINT64 Data;
280 UINT64 And;
281
282 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
283 if (EFI_ERROR (Status)) {
284 return Status;
285 }
286
287 if (Count == 1) {
288 And = *(UINT8*) AndData;
289 } else if (Count == 2) {
290 And = *(UINT16*) AndData;
291 } else if (Count == 4) {
292 And = *(UINT32*) AndData;
293 } else if (Count == 8) {
294 And = *(UINT64*) AndData;
295 } else {
296 return EFI_INVALID_PARAMETER;
297 }
298
299 Data &= And;
300 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
301
302 return Status;
303 }
304
305 /**
306 Wait for the value of the specified MMIO register set to the test value.
307
308 @param[in] PciIo The PCI IO protocol instance.
309 @param[in] BarIndex The BAR index of the standard PCI Configuration
310 header to use as the base address for the memory
311 operation to perform.
312 @param[in] Offset The offset within the selected BAR to start the
313 memory operation.
314 @param[in] Count The width of the mmio register in bytes.
315 Must be 1, 2, 4 or 8 bytes.
316 @param[in] MaskValue The mask value of memory.
317 @param[in] TestValue The test value of memory.
318
319 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
320 @retval EFI_SUCCESS The MMIO register has expected value.
321 @retval Others The MMIO operation fails.
322
323 **/
324 EFI_STATUS
325 EFIAPI
326 SdMmcHcCheckMmioSet (
327 IN EFI_PCI_IO_PROTOCOL *PciIo,
328 IN UINT8 BarIndex,
329 IN UINT32 Offset,
330 IN UINT8 Count,
331 IN UINT64 MaskValue,
332 IN UINT64 TestValue
333 )
334 {
335 EFI_STATUS Status;
336 UINT64 Value;
337
338 //
339 // Access PCI MMIO space to see if the value is the tested one.
340 //
341 Value = 0;
342 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);
343 if (EFI_ERROR (Status)) {
344 return Status;
345 }
346
347 Value &= MaskValue;
348
349 if (Value == TestValue) {
350 return EFI_SUCCESS;
351 }
352
353 return EFI_NOT_READY;
354 }
355
356 /**
357 Wait for the value of the specified MMIO register set to the test value.
358
359 @param[in] PciIo The PCI IO protocol instance.
360 @param[in] BarIndex The BAR index of the standard PCI Configuration
361 header to use as the base address for the memory
362 operation to perform.
363 @param[in] Offset The offset within the selected BAR to start the
364 memory operation.
365 @param[in] Count The width of the mmio register in bytes.
366 Must be 1, 2, 4 or 8 bytes.
367 @param[in] MaskValue The mask value of memory.
368 @param[in] TestValue The test value of memory.
369 @param[in] Timeout The time out value for wait memory set, uses 1
370 microsecond as a unit.
371
372 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
373 range.
374 @retval EFI_SUCCESS The MMIO register has expected value.
375 @retval Others The MMIO operation fails.
376
377 **/
378 EFI_STATUS
379 EFIAPI
380 SdMmcHcWaitMmioSet (
381 IN EFI_PCI_IO_PROTOCOL *PciIo,
382 IN UINT8 BarIndex,
383 IN UINT32 Offset,
384 IN UINT8 Count,
385 IN UINT64 MaskValue,
386 IN UINT64 TestValue,
387 IN UINT64 Timeout
388 )
389 {
390 EFI_STATUS Status;
391 BOOLEAN InfiniteWait;
392
393 if (Timeout == 0) {
394 InfiniteWait = TRUE;
395 } else {
396 InfiniteWait = FALSE;
397 }
398
399 while (InfiniteWait || (Timeout > 0)) {
400 Status = SdMmcHcCheckMmioSet (
401 PciIo,
402 BarIndex,
403 Offset,
404 Count,
405 MaskValue,
406 TestValue
407 );
408 if (Status != EFI_NOT_READY) {
409 return Status;
410 }
411
412 //
413 // Stall for 1 microsecond.
414 //
415 gBS->Stall (1);
416
417 Timeout--;
418 }
419
420 return EFI_TIMEOUT;
421 }
422
423 /**
424 Get the controller version information from the specified slot.
425
426 @param[in] PciIo The PCI IO protocol instance.
427 @param[in] Slot The slot number of the SD card to send the command to.
428 @param[out] Version The buffer to store the version information.
429
430 @retval EFI_SUCCESS The operation executes successfully.
431 @retval Others The operation fails.
432
433 **/
434 EFI_STATUS
435 SdMmcHcGetControllerVersion (
436 IN EFI_PCI_IO_PROTOCOL *PciIo,
437 IN UINT8 Slot,
438 OUT UINT16 *Version
439 )
440 {
441 EFI_STATUS Status;
442
443 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (UINT16), Version);
444 if (EFI_ERROR (Status)) {
445 return Status;
446 }
447
448 *Version &= 0xFF;
449
450 return EFI_SUCCESS;
451 }
452
453 /**
454 Software reset the specified SD/MMC host controller and enable all interrupts.
455
456 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
457 @param[in] Slot The slot number of the SD card to send the command to.
458
459 @retval EFI_SUCCESS The software reset executes successfully.
460 @retval Others The software reset fails.
461
462 **/
463 EFI_STATUS
464 SdMmcHcReset (
465 IN SD_MMC_HC_PRIVATE_DATA *Private,
466 IN UINT8 Slot
467 )
468 {
469 EFI_STATUS Status;
470 UINT8 SwReset;
471 EFI_PCI_IO_PROTOCOL *PciIo;
472
473 //
474 // Notify the SD/MMC override protocol that we are about to reset
475 // the SD/MMC host controller.
476 //
477 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
478 Status = mOverride->NotifyPhase (
479 Private->ControllerHandle,
480 Slot,
481 EdkiiSdMmcResetPre,
482 NULL);
483 if (EFI_ERROR (Status)) {
484 DEBUG ((DEBUG_WARN,
485 "%a: SD/MMC pre reset notifier callback failed - %r\n",
486 __FUNCTION__, Status));
487 return Status;
488 }
489 }
490
491 PciIo = Private->PciIo;
492 SwReset = BIT0;
493 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_SW_RST, sizeof (SwReset), &SwReset);
494
495 if (EFI_ERROR (Status)) {
496 DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status));
497 return Status;
498 }
499
500 Status = SdMmcHcWaitMmioSet (
501 PciIo,
502 Slot,
503 SD_MMC_HC_SW_RST,
504 sizeof (SwReset),
505 BIT0,
506 0x00,
507 SD_MMC_HC_GENERIC_TIMEOUT
508 );
509 if (EFI_ERROR (Status)) {
510 DEBUG ((DEBUG_INFO, "SdMmcHcReset: reset done with %r\n", Status));
511 return Status;
512 }
513
514 //
515 // Enable all interrupt after reset all.
516 //
517 Status = SdMmcHcEnableInterrupt (PciIo, Slot);
518 if (EFI_ERROR (Status)) {
519 DEBUG ((DEBUG_INFO, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",
520 Status));
521 return Status;
522 }
523
524 //
525 // Notify the SD/MMC override protocol that we have just reset
526 // the SD/MMC host controller.
527 //
528 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
529 Status = mOverride->NotifyPhase (
530 Private->ControllerHandle,
531 Slot,
532 EdkiiSdMmcResetPost,
533 NULL);
534 if (EFI_ERROR (Status)) {
535 DEBUG ((DEBUG_WARN,
536 "%a: SD/MMC post reset notifier callback failed - %r\n",
537 __FUNCTION__, Status));
538 }
539 }
540
541 return Status;
542 }
543
544 /**
545 Set all interrupt status bits in Normal and Error Interrupt Status Enable
546 register.
547
548 @param[in] PciIo The PCI IO protocol instance.
549 @param[in] Slot The slot number of the SD card to send the command to.
550
551 @retval EFI_SUCCESS The operation executes successfully.
552 @retval Others The operation fails.
553
554 **/
555 EFI_STATUS
556 SdMmcHcEnableInterrupt (
557 IN EFI_PCI_IO_PROTOCOL *PciIo,
558 IN UINT8 Slot
559 )
560 {
561 EFI_STATUS Status;
562 UINT16 IntStatus;
563
564 //
565 // Enable all bits in Error Interrupt Status Enable Register
566 //
567 IntStatus = 0xFFFF;
568 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
569 if (EFI_ERROR (Status)) {
570 return Status;
571 }
572 //
573 // Enable all bits in Normal Interrupt Status Enable Register
574 //
575 IntStatus = 0xFFFF;
576 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
577
578 return Status;
579 }
580
581 /**
582 Get the capability data from the specified slot.
583
584 @param[in] PciIo The PCI IO protocol instance.
585 @param[in] Slot The slot number of the SD card to send the command to.
586 @param[out] Capability The buffer to store the capability data.
587
588 @retval EFI_SUCCESS The operation executes successfully.
589 @retval Others The operation fails.
590
591 **/
592 EFI_STATUS
593 SdMmcHcGetCapability (
594 IN EFI_PCI_IO_PROTOCOL *PciIo,
595 IN UINT8 Slot,
596 OUT SD_MMC_HC_SLOT_CAP *Capability
597 )
598 {
599 EFI_STATUS Status;
600 UINT64 Cap;
601
602 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);
603 if (EFI_ERROR (Status)) {
604 return Status;
605 }
606
607 CopyMem (Capability, &Cap, sizeof (Cap));
608
609 return EFI_SUCCESS;
610 }
611
612 /**
613 Get the maximum current capability data from the specified slot.
614
615 @param[in] PciIo The PCI IO protocol instance.
616 @param[in] Slot The slot number of the SD card to send the command to.
617 @param[out] MaxCurrent The buffer to store the maximum current capability data.
618
619 @retval EFI_SUCCESS The operation executes successfully.
620 @retval Others The operation fails.
621
622 **/
623 EFI_STATUS
624 SdMmcHcGetMaxCurrent (
625 IN EFI_PCI_IO_PROTOCOL *PciIo,
626 IN UINT8 Slot,
627 OUT UINT64 *MaxCurrent
628 )
629 {
630 EFI_STATUS Status;
631
632 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);
633
634 return Status;
635 }
636
637 /**
638 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
639 slot.
640
641 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
642
643 @param[in] PciIo The PCI IO protocol instance.
644 @param[in] Slot The slot number of the SD card to send the command to.
645 @param[out] MediaPresent The pointer to the media present boolean value.
646
647 @retval EFI_SUCCESS There is no media change happened.
648 @retval EFI_MEDIA_CHANGED There is media change happened.
649 @retval Others The detection fails.
650
651 **/
652 EFI_STATUS
653 SdMmcHcCardDetect (
654 IN EFI_PCI_IO_PROTOCOL *PciIo,
655 IN UINT8 Slot,
656 OUT BOOLEAN *MediaPresent
657 )
658 {
659 EFI_STATUS Status;
660 UINT16 Data;
661 UINT32 PresentState;
662
663 //
664 // Check Present State Register to see if there is a card presented.
665 //
666 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
667 if (EFI_ERROR (Status)) {
668 return Status;
669 }
670
671 if ((PresentState & BIT16) != 0) {
672 *MediaPresent = TRUE;
673 } else {
674 *MediaPresent = FALSE;
675 }
676
677 //
678 // Check Normal Interrupt Status Register
679 //
680 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);
681 if (EFI_ERROR (Status)) {
682 return Status;
683 }
684
685 if ((Data & (BIT6 | BIT7)) != 0) {
686 //
687 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
688 //
689 Data &= BIT6 | BIT7;
690 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);
691 if (EFI_ERROR (Status)) {
692 return Status;
693 }
694
695 return EFI_MEDIA_CHANGED;
696 }
697
698 return EFI_SUCCESS;
699 }
700
701 /**
702 Stop SD/MMC card clock.
703
704 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
705
706 @param[in] PciIo The PCI IO protocol instance.
707 @param[in] Slot The slot number of the SD card to send the command to.
708
709 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.
710 @retval Others Fail to stop SD/MMC clock.
711
712 **/
713 EFI_STATUS
714 SdMmcHcStopClock (
715 IN EFI_PCI_IO_PROTOCOL *PciIo,
716 IN UINT8 Slot
717 )
718 {
719 EFI_STATUS Status;
720 UINT32 PresentState;
721 UINT16 ClockCtrl;
722
723 //
724 // Ensure no SD transactions are occurring on the SD Bus by
725 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
726 // in the Present State register to be 0.
727 //
728 Status = SdMmcHcWaitMmioSet (
729 PciIo,
730 Slot,
731 SD_MMC_HC_PRESENT_STATE,
732 sizeof (PresentState),
733 BIT0 | BIT1,
734 0,
735 SD_MMC_HC_GENERIC_TIMEOUT
736 );
737 if (EFI_ERROR (Status)) {
738 return Status;
739 }
740
741 //
742 // Set SD Clock Enable in the Clock Control register to 0
743 //
744 ClockCtrl = (UINT16)~BIT2;
745 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
746
747 return Status;
748 }
749
750 /**
751 SD/MMC card clock supply.
752
753 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
754
755 @param[in] PciIo The PCI IO protocol instance.
756 @param[in] Slot The slot number of the SD card to send the command to.
757 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
758 @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
759 @param[in] ControllerVer The version of host controller.
760
761 @retval EFI_SUCCESS The clock is supplied successfully.
762 @retval Others The clock isn't supplied successfully.
763
764 **/
765 EFI_STATUS
766 SdMmcHcClockSupply (
767 IN EFI_PCI_IO_PROTOCOL *PciIo,
768 IN UINT8 Slot,
769 IN UINT64 ClockFreq,
770 IN UINT32 BaseClkFreq,
771 IN UINT16 ControllerVer
772 )
773 {
774 EFI_STATUS Status;
775 UINT32 SettingFreq;
776 UINT32 Divisor;
777 UINT32 Remainder;
778 UINT16 ClockCtrl;
779
780 //
781 // Calculate a divisor for SD clock frequency
782 //
783 ASSERT (BaseClkFreq != 0);
784
785 if (ClockFreq == 0) {
786 return EFI_INVALID_PARAMETER;
787 }
788
789 if (ClockFreq > (BaseClkFreq * 1000)) {
790 ClockFreq = BaseClkFreq * 1000;
791 }
792
793 //
794 // Calculate the divisor of base frequency.
795 //
796 Divisor = 0;
797 SettingFreq = BaseClkFreq * 1000;
798 while (ClockFreq < SettingFreq) {
799 Divisor++;
800
801 SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);
802 Remainder = (BaseClkFreq * 1000) % (2 * Divisor);
803 if ((ClockFreq == SettingFreq) && (Remainder == 0)) {
804 break;
805 }
806 if ((ClockFreq == SettingFreq) && (Remainder != 0)) {
807 SettingFreq ++;
808 }
809 }
810
811 DEBUG ((DEBUG_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));
812
813 //
814 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
815 //
816 if ((ControllerVer >= SD_MMC_HC_CTRL_VER_300) &&
817 (ControllerVer <= SD_MMC_HC_CTRL_VER_420)) {
818 ASSERT (Divisor <= 0x3FF);
819 ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);
820 } else if ((ControllerVer == SD_MMC_HC_CTRL_VER_100) ||
821 (ControllerVer == SD_MMC_HC_CTRL_VER_200)) {
822 //
823 // Only the most significant bit can be used as divisor.
824 //
825 if (((Divisor - 1) & Divisor) != 0) {
826 Divisor = 1 << (HighBitSet32 (Divisor) + 1);
827 }
828 ASSERT (Divisor <= 0x80);
829 ClockCtrl = (Divisor & 0xFF) << 8;
830 } else {
831 DEBUG ((DEBUG_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));
832 return EFI_UNSUPPORTED;
833 }
834
835 //
836 // Stop bus clock at first
837 //
838 Status = SdMmcHcStopClock (PciIo, Slot);
839 if (EFI_ERROR (Status)) {
840 return Status;
841 }
842
843 //
844 // Supply clock frequency with specified divisor
845 //
846 ClockCtrl |= BIT0;
847 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);
848 if (EFI_ERROR (Status)) {
849 DEBUG ((DEBUG_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
850 return Status;
851 }
852
853 //
854 // Wait Internal Clock Stable in the Clock Control register to be 1
855 //
856 Status = SdMmcHcWaitMmioSet (
857 PciIo,
858 Slot,
859 SD_MMC_HC_CLOCK_CTRL,
860 sizeof (ClockCtrl),
861 BIT1,
862 BIT1,
863 SD_MMC_HC_GENERIC_TIMEOUT
864 );
865 if (EFI_ERROR (Status)) {
866 return Status;
867 }
868
869 //
870 // Set SD Clock Enable in the Clock Control register to 1
871 //
872 ClockCtrl = BIT2;
873 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
874
875 return Status;
876 }
877
878 /**
879 SD/MMC bus power control.
880
881 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
882
883 @param[in] PciIo The PCI IO protocol instance.
884 @param[in] Slot The slot number of the SD card to send the command to.
885 @param[in] PowerCtrl The value setting to the power control register.
886
887 @retval TRUE There is a SD/MMC card attached.
888 @retval FALSE There is no a SD/MMC card attached.
889
890 **/
891 EFI_STATUS
892 SdMmcHcPowerControl (
893 IN EFI_PCI_IO_PROTOCOL *PciIo,
894 IN UINT8 Slot,
895 IN UINT8 PowerCtrl
896 )
897 {
898 EFI_STATUS Status;
899
900 //
901 // Clr SD Bus Power
902 //
903 PowerCtrl &= (UINT8)~BIT0;
904 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
905 if (EFI_ERROR (Status)) {
906 return Status;
907 }
908
909 //
910 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
911 //
912 PowerCtrl |= BIT0;
913 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
914
915 return Status;
916 }
917
918 /**
919 Set the SD/MMC bus width.
920
921 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
922
923 @param[in] PciIo The PCI IO protocol instance.
924 @param[in] Slot The slot number of the SD card to send the command to.
925 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
926
927 @retval EFI_SUCCESS The bus width is set successfully.
928 @retval Others The bus width isn't set successfully.
929
930 **/
931 EFI_STATUS
932 SdMmcHcSetBusWidth (
933 IN EFI_PCI_IO_PROTOCOL *PciIo,
934 IN UINT8 Slot,
935 IN UINT16 BusWidth
936 )
937 {
938 EFI_STATUS Status;
939 UINT8 HostCtrl1;
940
941 if (BusWidth == 1) {
942 HostCtrl1 = (UINT8)~(BIT5 | BIT1);
943 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
944 } else if (BusWidth == 4) {
945 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
946 if (EFI_ERROR (Status)) {
947 return Status;
948 }
949 HostCtrl1 |= BIT1;
950 HostCtrl1 &= (UINT8)~BIT5;
951 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
952 } else if (BusWidth == 8) {
953 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
954 if (EFI_ERROR (Status)) {
955 return Status;
956 }
957 HostCtrl1 &= (UINT8)~BIT1;
958 HostCtrl1 |= BIT5;
959 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
960 } else {
961 ASSERT (FALSE);
962 return EFI_INVALID_PARAMETER;
963 }
964
965 return Status;
966 }
967
968 /**
969 Configure V4 controller enhancements at initialization.
970
971 @param[in] PciIo The PCI IO protocol instance.
972 @param[in] Slot The slot number of the SD card to send the command to.
973 @param[in] Capability The capability of the slot.
974 @param[in] ControllerVer The version of host controller.
975
976 @retval EFI_SUCCESS The clock is supplied successfully.
977
978 **/
979 EFI_STATUS
980 SdMmcHcInitV4Enhancements (
981 IN EFI_PCI_IO_PROTOCOL *PciIo,
982 IN UINT8 Slot,
983 IN SD_MMC_HC_SLOT_CAP Capability,
984 IN UINT16 ControllerVer
985 )
986 {
987 EFI_STATUS Status;
988 UINT16 HostCtrl2;
989
990 //
991 // Check if controller version V4 or higher
992 //
993 if (ControllerVer >= SD_MMC_HC_CTRL_VER_400) {
994 HostCtrl2 = SD_MMC_HC_V4_EN;
995 //
996 // Check if V4 64bit support is available
997 //
998 if (Capability.SysBus64V4 != 0) {
999 HostCtrl2 |= SD_MMC_HC_64_ADDR_EN;
1000 DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"));
1001 }
1002 //
1003 // Check if controller version V4.10 or higher
1004 //
1005 if (ControllerVer >= SD_MMC_HC_CTRL_VER_410) {
1006 HostCtrl2 |= SD_MMC_HC_26_DATA_LEN_ADMA_EN;
1007 DEBUG ((DEBUG_INFO, "Enabled V4 26 bit data length ADMA support\n"));
1008 }
1009 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1010 if (EFI_ERROR (Status)) {
1011 return Status;
1012 }
1013 }
1014
1015 return EFI_SUCCESS;
1016 }
1017
1018 /**
1019 Supply SD/MMC card with lowest clock frequency at initialization.
1020
1021 @param[in] PciIo The PCI IO protocol instance.
1022 @param[in] Slot The slot number of the SD card to send the command to.
1023 @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
1024 @param[in] ControllerVer The version of host controller.
1025
1026 @retval EFI_SUCCESS The clock is supplied successfully.
1027 @retval Others The clock isn't supplied successfully.
1028
1029 **/
1030 EFI_STATUS
1031 SdMmcHcInitClockFreq (
1032 IN EFI_PCI_IO_PROTOCOL *PciIo,
1033 IN UINT8 Slot,
1034 IN UINT32 BaseClkFreq,
1035 IN UINT16 ControllerVer
1036 )
1037 {
1038 EFI_STATUS Status;
1039 UINT32 InitFreq;
1040
1041 //
1042 // According to SDHCI specification ver. 4.2, BaseClkFreq field value of
1043 // the Capability Register 1 can be zero, which means a need for obtaining
1044 // the clock frequency via another method. Fail in case it is not updated
1045 // by SW at this point.
1046 //
1047 if (BaseClkFreq == 0) {
1048 //
1049 // Don't support get Base Clock Frequency information via another method
1050 //
1051 return EFI_UNSUPPORTED;
1052 }
1053 //
1054 // Supply 400KHz clock frequency at initialization phase.
1055 //
1056 InitFreq = 400;
1057 Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, BaseClkFreq, ControllerVer);
1058 return Status;
1059 }
1060
1061 /**
1062 Supply SD/MMC card with maximum voltage at initialization.
1063
1064 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
1065
1066 @param[in] PciIo The PCI IO protocol instance.
1067 @param[in] Slot The slot number of the SD card to send the command to.
1068 @param[in] Capability The capability of the slot.
1069
1070 @retval EFI_SUCCESS The voltage is supplied successfully.
1071 @retval Others The voltage isn't supplied successfully.
1072
1073 **/
1074 EFI_STATUS
1075 SdMmcHcInitPowerVoltage (
1076 IN EFI_PCI_IO_PROTOCOL *PciIo,
1077 IN UINT8 Slot,
1078 IN SD_MMC_HC_SLOT_CAP Capability
1079 )
1080 {
1081 EFI_STATUS Status;
1082 UINT8 MaxVoltage;
1083 UINT8 HostCtrl2;
1084
1085 //
1086 // Calculate supported maximum voltage according to SD Bus Voltage Select
1087 //
1088 if (Capability.Voltage33 != 0) {
1089 //
1090 // Support 3.3V
1091 //
1092 MaxVoltage = 0x0E;
1093 } else if (Capability.Voltage30 != 0) {
1094 //
1095 // Support 3.0V
1096 //
1097 MaxVoltage = 0x0C;
1098 } else if (Capability.Voltage18 != 0) {
1099 //
1100 // Support 1.8V
1101 //
1102 MaxVoltage = 0x0A;
1103 HostCtrl2 = BIT3;
1104 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1105 gBS->Stall (5000);
1106 if (EFI_ERROR (Status)) {
1107 return Status;
1108 }
1109 } else {
1110 ASSERT (FALSE);
1111 return EFI_DEVICE_ERROR;
1112 }
1113
1114 //
1115 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
1116 //
1117 Status = SdMmcHcPowerControl (PciIo, Slot, MaxVoltage);
1118
1119 return Status;
1120 }
1121
1122 /**
1123 Initialize the Timeout Control register with most conservative value at initialization.
1124
1125 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
1126
1127 @param[in] PciIo The PCI IO protocol instance.
1128 @param[in] Slot The slot number of the SD card to send the command to.
1129
1130 @retval EFI_SUCCESS The timeout control register is configured successfully.
1131 @retval Others The timeout control register isn't configured successfully.
1132
1133 **/
1134 EFI_STATUS
1135 SdMmcHcInitTimeoutCtrl (
1136 IN EFI_PCI_IO_PROTOCOL *PciIo,
1137 IN UINT8 Slot
1138 )
1139 {
1140 EFI_STATUS Status;
1141 UINT8 Timeout;
1142
1143 Timeout = 0x0E;
1144 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);
1145
1146 return Status;
1147 }
1148
1149 /**
1150 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
1151 at initialization.
1152
1153 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1154 @param[in] Slot The slot number of the SD card to send the command to.
1155
1156 @retval EFI_SUCCESS The host controller is initialized successfully.
1157 @retval Others The host controller isn't initialized successfully.
1158
1159 **/
1160 EFI_STATUS
1161 SdMmcHcInitHost (
1162 IN SD_MMC_HC_PRIVATE_DATA *Private,
1163 IN UINT8 Slot
1164 )
1165 {
1166 EFI_STATUS Status;
1167 EFI_PCI_IO_PROTOCOL *PciIo;
1168 SD_MMC_HC_SLOT_CAP Capability;
1169
1170 //
1171 // Notify the SD/MMC override protocol that we are about to initialize
1172 // the SD/MMC host controller.
1173 //
1174 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1175 Status = mOverride->NotifyPhase (
1176 Private->ControllerHandle,
1177 Slot,
1178 EdkiiSdMmcInitHostPre,
1179 NULL);
1180 if (EFI_ERROR (Status)) {
1181 DEBUG ((DEBUG_WARN,
1182 "%a: SD/MMC pre init notifier callback failed - %r\n",
1183 __FUNCTION__, Status));
1184 return Status;
1185 }
1186 }
1187
1188 PciIo = Private->PciIo;
1189 Capability = Private->Capability[Slot];
1190
1191 Status = SdMmcHcInitV4Enhancements (PciIo, Slot, Capability, Private->ControllerVersion[Slot]);
1192 if (EFI_ERROR (Status)) {
1193 return Status;
1194 }
1195
1196 Status = SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot], Private->ControllerVersion[Slot]);
1197 if (EFI_ERROR (Status)) {
1198 return Status;
1199 }
1200
1201 Status = SdMmcHcInitPowerVoltage (PciIo, Slot, Capability);
1202 if (EFI_ERROR (Status)) {
1203 return Status;
1204 }
1205
1206 Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);
1207 if (EFI_ERROR (Status)) {
1208 return Status;
1209 }
1210
1211 //
1212 // Notify the SD/MMC override protocol that we are have just initialized
1213 // the SD/MMC host controller.
1214 //
1215 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1216 Status = mOverride->NotifyPhase (
1217 Private->ControllerHandle,
1218 Slot,
1219 EdkiiSdMmcInitHostPost,
1220 NULL);
1221 if (EFI_ERROR (Status)) {
1222 DEBUG ((DEBUG_WARN,
1223 "%a: SD/MMC post init notifier callback failed - %r\n",
1224 __FUNCTION__, Status));
1225 }
1226 }
1227 return Status;
1228 }
1229
1230 /**
1231 Set SD Host Controler control 2 registry according to selected speed.
1232
1233 @param[in] ControllerHandle The handle of the controller.
1234 @param[in] PciIo The PCI IO protocol instance.
1235 @param[in] Slot The slot number of the SD card to send the command to.
1236 @param[in] Timing The timing to select.
1237
1238 @retval EFI_SUCCESS The timing is set successfully.
1239 @retval Others The timing isn't set successfully.
1240 **/
1241 EFI_STATUS
1242 SdMmcHcUhsSignaling (
1243 IN EFI_HANDLE ControllerHandle,
1244 IN EFI_PCI_IO_PROTOCOL *PciIo,
1245 IN UINT8 Slot,
1246 IN SD_MMC_BUS_MODE Timing
1247 )
1248 {
1249 EFI_STATUS Status;
1250 UINT8 HostCtrl2;
1251
1252 HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;
1253 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1254 if (EFI_ERROR (Status)) {
1255 return Status;
1256 }
1257
1258 switch (Timing) {
1259 case SdMmcUhsSdr12:
1260 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;
1261 break;
1262 case SdMmcUhsSdr25:
1263 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;
1264 break;
1265 case SdMmcUhsSdr50:
1266 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;
1267 break;
1268 case SdMmcUhsSdr104:
1269 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;
1270 break;
1271 case SdMmcUhsDdr50:
1272 HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;
1273 break;
1274 case SdMmcMmcLegacy:
1275 HostCtrl2 = SD_MMC_HC_CTRL_MMC_LEGACY;
1276 break;
1277 case SdMmcMmcHsSdr:
1278 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_SDR;
1279 break;
1280 case SdMmcMmcHsDdr:
1281 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_DDR;
1282 break;
1283 case SdMmcMmcHs200:
1284 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS200;
1285 break;
1286 case SdMmcMmcHs400:
1287 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS400;
1288 break;
1289 default:
1290 HostCtrl2 = 0;
1291 break;
1292 }
1293 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1294 if (EFI_ERROR (Status)) {
1295 return Status;
1296 }
1297
1298 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1299 Status = mOverride->NotifyPhase (
1300 ControllerHandle,
1301 Slot,
1302 EdkiiSdMmcUhsSignaling,
1303 &Timing
1304 );
1305 if (EFI_ERROR (Status)) {
1306 DEBUG ((
1307 DEBUG_ERROR,
1308 "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
1309 __FUNCTION__,
1310 Status
1311 ));
1312 return Status;
1313 }
1314 }
1315
1316 return EFI_SUCCESS;
1317 }
1318
1319 /**
1320 Turn on/off LED.
1321
1322 @param[in] PciIo The PCI IO protocol instance.
1323 @param[in] Slot The slot number of the SD card to send the command to.
1324 @param[in] On The boolean to turn on/off LED.
1325
1326 @retval EFI_SUCCESS The LED is turned on/off successfully.
1327 @retval Others The LED isn't turned on/off successfully.
1328
1329 **/
1330 EFI_STATUS
1331 SdMmcHcLedOnOff (
1332 IN EFI_PCI_IO_PROTOCOL *PciIo,
1333 IN UINT8 Slot,
1334 IN BOOLEAN On
1335 )
1336 {
1337 EFI_STATUS Status;
1338 UINT8 HostCtrl1;
1339
1340 if (On) {
1341 HostCtrl1 = BIT0;
1342 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1343 } else {
1344 HostCtrl1 = (UINT8)~BIT0;
1345 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1346 }
1347
1348 return Status;
1349 }
1350
1351 /**
1352 Build ADMA descriptor table for transfer.
1353
1354 Refer to SD Host Controller Simplified spec 4.2 Section 1.13 for details.
1355
1356 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1357 @param[in] ControllerVer The version of host controller.
1358
1359 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
1360 @retval Others The ADMA descriptor table isn't created successfully.
1361
1362 **/
1363 EFI_STATUS
1364 BuildAdmaDescTable (
1365 IN SD_MMC_HC_TRB *Trb,
1366 IN UINT16 ControllerVer
1367 )
1368 {
1369 EFI_PHYSICAL_ADDRESS Data;
1370 UINT64 DataLen;
1371 UINT64 Entries;
1372 UINT32 Index;
1373 UINT64 Remaining;
1374 UINT64 Address;
1375 UINTN TableSize;
1376 EFI_PCI_IO_PROTOCOL *PciIo;
1377 EFI_STATUS Status;
1378 UINTN Bytes;
1379 BOOLEAN AddressingMode64;
1380 BOOLEAN DataLength26;
1381 UINT32 AdmaMaxDataPerLine;
1382 UINT32 DescSize;
1383 VOID *AdmaDesc;
1384
1385 AddressingMode64 = FALSE;
1386 DataLength26 = FALSE;
1387 AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_16B;
1388 DescSize = sizeof (SD_MMC_HC_ADMA_32_DESC_LINE);
1389 AdmaDesc = NULL;
1390
1391 Data = Trb->DataPhy;
1392 DataLen = Trb->DataLen;
1393 PciIo = Trb->Private->PciIo;
1394
1395 //
1396 // Detect whether 64bit addressing is supported.
1397 //
1398 if (ControllerVer >= SD_MMC_HC_CTRL_VER_400) {
1399 Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),
1400 SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN, SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN);
1401 if (!EFI_ERROR (Status)) {
1402 AddressingMode64 = TRUE;
1403 DescSize = sizeof (SD_MMC_HC_ADMA_64_DESC_LINE);
1404 }
1405 }
1406 //
1407 // Check for valid ranges in 32bit ADMA Descriptor Table
1408 //
1409 if (!AddressingMode64 &&
1410 ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul))) {
1411 return EFI_INVALID_PARAMETER;
1412 }
1413 //
1414 // Check address field alignment
1415 //
1416 if (AddressingMode64) {
1417 //
1418 // Address field shall be set on 64-bit boundary (Lower 3-bit is always set to 0)
1419 //
1420 if ((Data & (BIT0 | BIT1 | BIT2)) != 0) {
1421 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 8 bytes boundary!\n", Data));
1422 }
1423 } else {
1424 //
1425 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
1426 //
1427 if ((Data & (BIT0 | BIT1)) != 0) {
1428 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));
1429 }
1430 }
1431 //
1432 // Detect whether 26bit data length is supported.
1433 //
1434 Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),
1435 SD_MMC_HC_26_DATA_LEN_ADMA_EN, SD_MMC_HC_26_DATA_LEN_ADMA_EN);
1436 if (!EFI_ERROR (Status)) {
1437 DataLength26 = TRUE;
1438 AdmaMaxDataPerLine = ADMA_MAX_DATA_PER_LINE_26B;
1439 }
1440
1441 Entries = DivU64x32 ((DataLen + AdmaMaxDataPerLine - 1), AdmaMaxDataPerLine);
1442 TableSize = (UINTN)MultU64x32 (Entries, DescSize);
1443 Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);
1444 Status = PciIo->AllocateBuffer (
1445 PciIo,
1446 AllocateAnyPages,
1447 EfiBootServicesData,
1448 EFI_SIZE_TO_PAGES (TableSize),
1449 (VOID **)&AdmaDesc,
1450 0
1451 );
1452 if (EFI_ERROR (Status)) {
1453 return EFI_OUT_OF_RESOURCES;
1454 }
1455 ZeroMem (AdmaDesc, TableSize);
1456 Bytes = TableSize;
1457 Status = PciIo->Map (
1458 PciIo,
1459 EfiPciIoOperationBusMasterCommonBuffer,
1460 AdmaDesc,
1461 &Bytes,
1462 &Trb->AdmaDescPhy,
1463 &Trb->AdmaMap
1464 );
1465
1466 if (EFI_ERROR (Status) || (Bytes != TableSize)) {
1467 //
1468 // Map error or unable to map the whole RFis buffer into a contiguous region.
1469 //
1470 PciIo->FreeBuffer (
1471 PciIo,
1472 EFI_SIZE_TO_PAGES (TableSize),
1473 AdmaDesc
1474 );
1475 return EFI_OUT_OF_RESOURCES;
1476 }
1477
1478 if ((!AddressingMode64) &&
1479 (UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {
1480 //
1481 // The ADMA doesn't support 64bit addressing.
1482 //
1483 PciIo->Unmap (
1484 PciIo,
1485 Trb->AdmaMap
1486 );
1487 PciIo->FreeBuffer (
1488 PciIo,
1489 EFI_SIZE_TO_PAGES (TableSize),
1490 AdmaDesc
1491 );
1492 return EFI_DEVICE_ERROR;
1493 }
1494
1495 Remaining = DataLen;
1496 Address = Data;
1497 if (!AddressingMode64) {
1498 Trb->Adma32Desc = AdmaDesc;
1499 Trb->Adma64Desc = NULL;
1500 } else {
1501 Trb->Adma64Desc = AdmaDesc;
1502 Trb->Adma32Desc = NULL;
1503 }
1504 for (Index = 0; Index < Entries; Index++) {
1505 if (!AddressingMode64) {
1506 if (Remaining <= AdmaMaxDataPerLine) {
1507 Trb->Adma32Desc[Index].Valid = 1;
1508 Trb->Adma32Desc[Index].Act = 2;
1509 if (DataLength26) {
1510 Trb->Adma32Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
1511 }
1512 Trb->Adma32Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
1513 Trb->Adma32Desc[Index].Address = (UINT32)Address;
1514 break;
1515 } else {
1516 Trb->Adma32Desc[Index].Valid = 1;
1517 Trb->Adma32Desc[Index].Act = 2;
1518 if (DataLength26) {
1519 Trb->Adma32Desc[Index].UpperLength = 0;
1520 }
1521 Trb->Adma32Desc[Index].LowerLength = 0;
1522 Trb->Adma32Desc[Index].Address = (UINT32)Address;
1523 }
1524 } else {
1525 if (Remaining <= AdmaMaxDataPerLine) {
1526 Trb->Adma64Desc[Index].Valid = 1;
1527 Trb->Adma64Desc[Index].Act = 2;
1528 if (DataLength26) {
1529 Trb->Adma64Desc[Index].UpperLength = (UINT16)RShiftU64 (Remaining, 16);
1530 }
1531 Trb->Adma64Desc[Index].LowerLength = (UINT16)(Remaining & MAX_UINT16);
1532 Trb->Adma64Desc[Index].LowerAddress = (UINT32)Address;
1533 Trb->Adma64Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1534 break;
1535 } else {
1536 Trb->Adma64Desc[Index].Valid = 1;
1537 Trb->Adma64Desc[Index].Act = 2;
1538 if (DataLength26) {
1539 Trb->Adma64Desc[Index].UpperLength = 0;
1540 }
1541 Trb->Adma64Desc[Index].LowerLength = 0;
1542 Trb->Adma64Desc[Index].LowerAddress = (UINT32)Address;
1543 Trb->Adma64Desc[Index].UpperAddress = (UINT32)RShiftU64 (Address, 32);
1544 }
1545 }
1546
1547 Remaining -= AdmaMaxDataPerLine;
1548 Address += AdmaMaxDataPerLine;
1549 }
1550
1551 //
1552 // Set the last descriptor line as end of descriptor table
1553 //
1554 AddressingMode64 ? (Trb->Adma64Desc[Index].End = 1) : (Trb->Adma32Desc[Index].End = 1);
1555 return EFI_SUCCESS;
1556 }
1557
1558 /**
1559 Create a new TRB for the SD/MMC cmd request.
1560
1561 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1562 @param[in] Slot The slot number of the SD card to send the command to.
1563 @param[in] Packet A pointer to the SD command data structure.
1564 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
1565 not NULL, then nonblocking I/O is performed, and Event
1566 will be signaled when the Packet completes.
1567
1568 @return Created Trb or NULL.
1569
1570 **/
1571 SD_MMC_HC_TRB *
1572 SdMmcCreateTrb (
1573 IN SD_MMC_HC_PRIVATE_DATA *Private,
1574 IN UINT8 Slot,
1575 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
1576 IN EFI_EVENT Event
1577 )
1578 {
1579 SD_MMC_HC_TRB *Trb;
1580 EFI_STATUS Status;
1581 EFI_TPL OldTpl;
1582 EFI_PCI_IO_PROTOCOL_OPERATION Flag;
1583 EFI_PCI_IO_PROTOCOL *PciIo;
1584 UINTN MapLength;
1585
1586 Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));
1587 if (Trb == NULL) {
1588 return NULL;
1589 }
1590
1591 Trb->Signature = SD_MMC_HC_TRB_SIG;
1592 Trb->Slot = Slot;
1593 Trb->BlockSize = 0x200;
1594 Trb->Packet = Packet;
1595 Trb->Event = Event;
1596 Trb->Started = FALSE;
1597 Trb->Timeout = Packet->Timeout;
1598 Trb->Private = Private;
1599
1600 if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
1601 Trb->Data = Packet->InDataBuffer;
1602 Trb->DataLen = Packet->InTransferLength;
1603 Trb->Read = TRUE;
1604 } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
1605 Trb->Data = Packet->OutDataBuffer;
1606 Trb->DataLen = Packet->OutTransferLength;
1607 Trb->Read = FALSE;
1608 } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {
1609 Trb->Data = NULL;
1610 Trb->DataLen = 0;
1611 } else {
1612 goto Error;
1613 }
1614
1615 if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {
1616 Trb->BlockSize = (UINT16)Trb->DataLen;
1617 }
1618
1619 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
1620 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
1621 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
1622 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
1623 Trb->Mode = SdMmcPioMode;
1624 } else {
1625 if (Trb->Read) {
1626 Flag = EfiPciIoOperationBusMasterWrite;
1627 } else {
1628 Flag = EfiPciIoOperationBusMasterRead;
1629 }
1630
1631 PciIo = Private->PciIo;
1632 if (Trb->DataLen != 0) {
1633 MapLength = Trb->DataLen;
1634 Status = PciIo->Map (
1635 PciIo,
1636 Flag,
1637 Trb->Data,
1638 &MapLength,
1639 &Trb->DataPhy,
1640 &Trb->DataMap
1641 );
1642 if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {
1643 Status = EFI_BAD_BUFFER_SIZE;
1644 goto Error;
1645 }
1646 }
1647
1648 if (Trb->DataLen == 0) {
1649 Trb->Mode = SdMmcNoData;
1650 } else if (Private->Capability[Slot].Adma2 != 0) {
1651 Trb->Mode = SdMmcAdmaMode;
1652 Status = BuildAdmaDescTable (Trb, Private->ControllerVersion[Slot]);
1653 if (EFI_ERROR (Status)) {
1654 PciIo->Unmap (PciIo, Trb->DataMap);
1655 goto Error;
1656 }
1657 } else if (Private->Capability[Slot].Sdma != 0) {
1658 Trb->Mode = SdMmcSdmaMode;
1659 } else {
1660 Trb->Mode = SdMmcPioMode;
1661 }
1662 }
1663
1664 if (Event != NULL) {
1665 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
1666 InsertTailList (&Private->Queue, &Trb->TrbList);
1667 gBS->RestoreTPL (OldTpl);
1668 }
1669
1670 return Trb;
1671
1672 Error:
1673 SdMmcFreeTrb (Trb);
1674 return NULL;
1675 }
1676
1677 /**
1678 Free the resource used by the TRB.
1679
1680 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1681
1682 **/
1683 VOID
1684 SdMmcFreeTrb (
1685 IN SD_MMC_HC_TRB *Trb
1686 )
1687 {
1688 EFI_PCI_IO_PROTOCOL *PciIo;
1689
1690 PciIo = Trb->Private->PciIo;
1691
1692 if (Trb->AdmaMap != NULL) {
1693 PciIo->Unmap (
1694 PciIo,
1695 Trb->AdmaMap
1696 );
1697 }
1698 if (Trb->Adma32Desc != NULL) {
1699 PciIo->FreeBuffer (
1700 PciIo,
1701 Trb->AdmaPages,
1702 Trb->Adma32Desc
1703 );
1704 }
1705 if (Trb->Adma64Desc != NULL) {
1706 PciIo->FreeBuffer (
1707 PciIo,
1708 Trb->AdmaPages,
1709 Trb->Adma64Desc
1710 );
1711 }
1712 if (Trb->DataMap != NULL) {
1713 PciIo->Unmap (
1714 PciIo,
1715 Trb->DataMap
1716 );
1717 }
1718 FreePool (Trb);
1719 return;
1720 }
1721
1722 /**
1723 Check if the env is ready for execute specified TRB.
1724
1725 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1726 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1727
1728 @retval EFI_SUCCESS The env is ready for TRB execution.
1729 @retval EFI_NOT_READY The env is not ready for TRB execution.
1730 @retval Others Some erros happen.
1731
1732 **/
1733 EFI_STATUS
1734 SdMmcCheckTrbEnv (
1735 IN SD_MMC_HC_PRIVATE_DATA *Private,
1736 IN SD_MMC_HC_TRB *Trb
1737 )
1738 {
1739 EFI_STATUS Status;
1740 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1741 EFI_PCI_IO_PROTOCOL *PciIo;
1742 UINT32 PresentState;
1743
1744 Packet = Trb->Packet;
1745
1746 if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||
1747 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||
1748 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b)) {
1749 //
1750 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1751 // the Present State register to be 0
1752 //
1753 PresentState = BIT0 | BIT1;
1754 } else {
1755 //
1756 // Wait Command Inhibit (CMD) in the Present State register
1757 // to be 0
1758 //
1759 PresentState = BIT0;
1760 }
1761
1762 PciIo = Private->PciIo;
1763 Status = SdMmcHcCheckMmioSet (
1764 PciIo,
1765 Trb->Slot,
1766 SD_MMC_HC_PRESENT_STATE,
1767 sizeof (PresentState),
1768 PresentState,
1769 0
1770 );
1771
1772 return Status;
1773 }
1774
1775 /**
1776 Wait for the env to be ready for execute specified TRB.
1777
1778 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1779 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1780
1781 @retval EFI_SUCCESS The env is ready for TRB execution.
1782 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
1783 @retval Others Some erros happen.
1784
1785 **/
1786 EFI_STATUS
1787 SdMmcWaitTrbEnv (
1788 IN SD_MMC_HC_PRIVATE_DATA *Private,
1789 IN SD_MMC_HC_TRB *Trb
1790 )
1791 {
1792 EFI_STATUS Status;
1793 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1794 UINT64 Timeout;
1795 BOOLEAN InfiniteWait;
1796
1797 //
1798 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1799 //
1800 Packet = Trb->Packet;
1801 Timeout = Packet->Timeout;
1802 if (Timeout == 0) {
1803 InfiniteWait = TRUE;
1804 } else {
1805 InfiniteWait = FALSE;
1806 }
1807
1808 while (InfiniteWait || (Timeout > 0)) {
1809 //
1810 // Check Trb execution result by reading Normal Interrupt Status register.
1811 //
1812 Status = SdMmcCheckTrbEnv (Private, Trb);
1813 if (Status != EFI_NOT_READY) {
1814 return Status;
1815 }
1816 //
1817 // Stall for 1 microsecond.
1818 //
1819 gBS->Stall (1);
1820
1821 Timeout--;
1822 }
1823
1824 return EFI_TIMEOUT;
1825 }
1826
1827 /**
1828 Execute the specified TRB.
1829
1830 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1831 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1832
1833 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
1834 @retval Others Some erros happen when sending this request to the host controller.
1835
1836 **/
1837 EFI_STATUS
1838 SdMmcExecTrb (
1839 IN SD_MMC_HC_PRIVATE_DATA *Private,
1840 IN SD_MMC_HC_TRB *Trb
1841 )
1842 {
1843 EFI_STATUS Status;
1844 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1845 EFI_PCI_IO_PROTOCOL *PciIo;
1846 UINT16 Cmd;
1847 UINT16 IntStatus;
1848 UINT32 Argument;
1849 UINT32 BlkCount;
1850 UINT16 BlkSize;
1851 UINT16 TransMode;
1852 UINT8 HostCtrl1;
1853 UINT64 SdmaAddr;
1854 UINT64 AdmaAddr;
1855 BOOLEAN AddressingMode64;
1856
1857 AddressingMode64 = FALSE;
1858
1859 Packet = Trb->Packet;
1860 PciIo = Trb->Private->PciIo;
1861 //
1862 // Clear all bits in Error Interrupt Status Register
1863 //
1864 IntStatus = 0xFFFF;
1865 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1866 if (EFI_ERROR (Status)) {
1867 return Status;
1868 }
1869 //
1870 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
1871 //
1872 IntStatus = 0xFF3F;
1873 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1874 if (EFI_ERROR (Status)) {
1875 return Status;
1876 }
1877 //
1878 // Set Host Control 1 register DMA Select field
1879 //
1880 if (Trb->Mode == SdMmcAdmaMode) {
1881 HostCtrl1 = BIT4;
1882 Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1883 if (EFI_ERROR (Status)) {
1884 return Status;
1885 }
1886 }
1887
1888 SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);
1889
1890 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
1891 Status = SdMmcHcCheckMmioSet(PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL2, sizeof(UINT16),
1892 SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN, SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN);
1893 if (!EFI_ERROR (Status)) {
1894 AddressingMode64 = TRUE;
1895 }
1896 }
1897
1898 if (Trb->Mode == SdMmcSdmaMode) {
1899 if ((!AddressingMode64) &&
1900 ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul)) {
1901 return EFI_INVALID_PARAMETER;
1902 }
1903
1904 SdmaAddr = (UINT64)(UINTN)Trb->DataPhy;
1905
1906 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
1907 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (UINT64), &SdmaAddr);
1908 } else {
1909 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &SdmaAddr);
1910 }
1911
1912 if (EFI_ERROR (Status)) {
1913 return Status;
1914 }
1915 } else if (Trb->Mode == SdMmcAdmaMode) {
1916 AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;
1917 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);
1918 if (EFI_ERROR (Status)) {
1919 return Status;
1920 }
1921 }
1922
1923 BlkSize = Trb->BlockSize;
1924 if (Trb->Mode == SdMmcSdmaMode) {
1925 //
1926 // Set SDMA boundary to be 512K bytes.
1927 //
1928 BlkSize |= 0x7000;
1929 }
1930
1931 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);
1932 if (EFI_ERROR (Status)) {
1933 return Status;
1934 }
1935
1936 BlkCount = 0;
1937 if (Trb->Mode != SdMmcNoData) {
1938 //
1939 // Calcuate Block Count.
1940 //
1941 BlkCount = (Trb->DataLen / Trb->BlockSize);
1942 }
1943 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_410) {
1944 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (UINT32), &BlkCount);
1945 } else {
1946 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (UINT16), &BlkCount);
1947 }
1948 if (EFI_ERROR (Status)) {
1949 return Status;
1950 }
1951
1952 Argument = Packet->SdMmcCmdBlk->CommandArgument;
1953 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);
1954 if (EFI_ERROR (Status)) {
1955 return Status;
1956 }
1957
1958 TransMode = 0;
1959 if (Trb->Mode != SdMmcNoData) {
1960 if (Trb->Mode != SdMmcPioMode) {
1961 TransMode |= BIT0;
1962 }
1963 if (Trb->Read) {
1964 TransMode |= BIT4;
1965 }
1966 if (BlkCount > 1) {
1967 TransMode |= BIT5 | BIT1;
1968 }
1969 //
1970 // Only SD memory card needs to use AUTO CMD12 feature.
1971 //
1972 if (Private->Slot[Trb->Slot].CardType == SdCardType) {
1973 if (BlkCount > 1) {
1974 TransMode |= BIT2;
1975 }
1976 }
1977 }
1978
1979 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);
1980 if (EFI_ERROR (Status)) {
1981 return Status;
1982 }
1983
1984 Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);
1985 if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {
1986 Cmd |= BIT5;
1987 }
1988 //
1989 // Convert ResponseType to value
1990 //
1991 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
1992 switch (Packet->SdMmcCmdBlk->ResponseType) {
1993 case SdMmcResponseTypeR1:
1994 case SdMmcResponseTypeR5:
1995 case SdMmcResponseTypeR6:
1996 case SdMmcResponseTypeR7:
1997 Cmd |= (BIT1 | BIT3 | BIT4);
1998 break;
1999 case SdMmcResponseTypeR2:
2000 Cmd |= (BIT0 | BIT3);
2001 break;
2002 case SdMmcResponseTypeR3:
2003 case SdMmcResponseTypeR4:
2004 Cmd |= BIT1;
2005 break;
2006 case SdMmcResponseTypeR1b:
2007 case SdMmcResponseTypeR5b:
2008 Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);
2009 break;
2010 default:
2011 ASSERT (FALSE);
2012 break;
2013 }
2014 }
2015 //
2016 // Execute cmd
2017 //
2018 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);
2019 return Status;
2020 }
2021
2022 /**
2023 Check the TRB execution result.
2024
2025 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2026 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2027
2028 @retval EFI_SUCCESS The TRB is executed successfully.
2029 @retval EFI_NOT_READY The TRB is not completed for execution.
2030 @retval Others Some erros happen when executing this request.
2031
2032 **/
2033 EFI_STATUS
2034 SdMmcCheckTrbResult (
2035 IN SD_MMC_HC_PRIVATE_DATA *Private,
2036 IN SD_MMC_HC_TRB *Trb
2037 )
2038 {
2039 EFI_STATUS Status;
2040 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2041 UINT16 IntStatus;
2042 UINT32 Response[4];
2043 UINT64 SdmaAddr;
2044 UINT8 Index;
2045 UINT8 SwReset;
2046 UINT32 PioLength;
2047
2048 SwReset = 0;
2049 Packet = Trb->Packet;
2050 //
2051 // Check Trb execution result by reading Normal Interrupt Status register.
2052 //
2053 Status = SdMmcHcRwMmio (
2054 Private->PciIo,
2055 Trb->Slot,
2056 SD_MMC_HC_NOR_INT_STS,
2057 TRUE,
2058 sizeof (IntStatus),
2059 &IntStatus
2060 );
2061 if (EFI_ERROR (Status)) {
2062 goto Done;
2063 }
2064 //
2065 // Check Transfer Complete bit is set or not.
2066 //
2067 if ((IntStatus & BIT1) == BIT1) {
2068 if ((IntStatus & BIT15) == BIT15) {
2069 //
2070 // Read Error Interrupt Status register to check if the error is
2071 // Data Timeout Error.
2072 // If yes, treat it as success as Transfer Complete has higher
2073 // priority than Data Timeout Error.
2074 //
2075 Status = SdMmcHcRwMmio (
2076 Private->PciIo,
2077 Trb->Slot,
2078 SD_MMC_HC_ERR_INT_STS,
2079 TRUE,
2080 sizeof (IntStatus),
2081 &IntStatus
2082 );
2083 if (!EFI_ERROR (Status)) {
2084 if ((IntStatus & BIT4) == BIT4) {
2085 Status = EFI_SUCCESS;
2086 } else {
2087 Status = EFI_DEVICE_ERROR;
2088 }
2089 }
2090 }
2091
2092 goto Done;
2093 }
2094 //
2095 // Check if there is a error happened during cmd execution.
2096 // If yes, then do error recovery procedure to follow SD Host Controller
2097 // Simplified Spec 3.0 section 3.10.1.
2098 //
2099 if ((IntStatus & BIT15) == BIT15) {
2100 Status = SdMmcHcRwMmio (
2101 Private->PciIo,
2102 Trb->Slot,
2103 SD_MMC_HC_ERR_INT_STS,
2104 TRUE,
2105 sizeof (IntStatus),
2106 &IntStatus
2107 );
2108 if (EFI_ERROR (Status)) {
2109 goto Done;
2110 }
2111 if ((IntStatus & 0x0F) != 0) {
2112 SwReset |= BIT1;
2113 }
2114 if ((IntStatus & 0xF0) != 0) {
2115 SwReset |= BIT2;
2116 }
2117
2118 Status = SdMmcHcRwMmio (
2119 Private->PciIo,
2120 Trb->Slot,
2121 SD_MMC_HC_SW_RST,
2122 FALSE,
2123 sizeof (SwReset),
2124 &SwReset
2125 );
2126 if (EFI_ERROR (Status)) {
2127 goto Done;
2128 }
2129 Status = SdMmcHcWaitMmioSet (
2130 Private->PciIo,
2131 Trb->Slot,
2132 SD_MMC_HC_SW_RST,
2133 sizeof (SwReset),
2134 0xFF,
2135 0,
2136 SD_MMC_HC_GENERIC_TIMEOUT
2137 );
2138 if (EFI_ERROR (Status)) {
2139 goto Done;
2140 }
2141
2142 Status = EFI_DEVICE_ERROR;
2143 goto Done;
2144 }
2145 //
2146 // Check if DMA interrupt is signalled for the SDMA transfer.
2147 //
2148 if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {
2149 //
2150 // Clear DMA interrupt bit.
2151 //
2152 IntStatus = BIT3;
2153 Status = SdMmcHcRwMmio (
2154 Private->PciIo,
2155 Trb->Slot,
2156 SD_MMC_HC_NOR_INT_STS,
2157 FALSE,
2158 sizeof (IntStatus),
2159 &IntStatus
2160 );
2161 if (EFI_ERROR (Status)) {
2162 goto Done;
2163 }
2164 //
2165 // Update SDMA Address register.
2166 //
2167 SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);
2168
2169 if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
2170 Status = SdMmcHcRwMmio (
2171 Private->PciIo,
2172 Trb->Slot,
2173 SD_MMC_HC_ADMA_SYS_ADDR,
2174 FALSE,
2175 sizeof (UINT64),
2176 &SdmaAddr
2177 );
2178 } else {
2179 Status = SdMmcHcRwMmio (
2180 Private->PciIo,
2181 Trb->Slot,
2182 SD_MMC_HC_SDMA_ADDR,
2183 FALSE,
2184 sizeof (UINT32),
2185 &SdmaAddr
2186 );
2187 }
2188
2189 if (EFI_ERROR (Status)) {
2190 goto Done;
2191 }
2192 Trb->DataPhy = (UINT64)(UINTN)SdmaAddr;
2193 }
2194
2195 if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&
2196 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR1b) &&
2197 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR5b)) {
2198 if ((IntStatus & BIT0) == BIT0) {
2199 Status = EFI_SUCCESS;
2200 goto Done;
2201 }
2202 }
2203
2204 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
2205 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
2206 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
2207 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
2208 //
2209 // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,
2210 // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.
2211 // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.
2212 //
2213 if ((IntStatus & BIT5) == BIT5) {
2214 //
2215 // Clear Buffer Read Ready interrupt at first.
2216 //
2217 IntStatus = BIT5;
2218 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
2219 //
2220 // Read data out from Buffer Port register
2221 //
2222 for (PioLength = 0; PioLength < Trb->DataLen; PioLength += 4) {
2223 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength);
2224 }
2225 Status = EFI_SUCCESS;
2226 goto Done;
2227 }
2228 }
2229
2230 Status = EFI_NOT_READY;
2231 Done:
2232 //
2233 // Get response data when the cmd is executed successfully.
2234 //
2235 if (!EFI_ERROR (Status)) {
2236 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
2237 for (Index = 0; Index < 4; Index++) {
2238 Status = SdMmcHcRwMmio (
2239 Private->PciIo,
2240 Trb->Slot,
2241 SD_MMC_HC_RESPONSE + Index * 4,
2242 TRUE,
2243 sizeof (UINT32),
2244 &Response[Index]
2245 );
2246 if (EFI_ERROR (Status)) {
2247 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
2248 return Status;
2249 }
2250 }
2251 CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));
2252 }
2253 }
2254
2255 if (Status != EFI_NOT_READY) {
2256 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
2257 }
2258
2259 return Status;
2260 }
2261
2262 /**
2263 Wait for the TRB execution result.
2264
2265 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2266 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2267
2268 @retval EFI_SUCCESS The TRB is executed successfully.
2269 @retval Others Some erros happen when executing this request.
2270
2271 **/
2272 EFI_STATUS
2273 SdMmcWaitTrbResult (
2274 IN SD_MMC_HC_PRIVATE_DATA *Private,
2275 IN SD_MMC_HC_TRB *Trb
2276 )
2277 {
2278 EFI_STATUS Status;
2279 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2280 UINT64 Timeout;
2281 BOOLEAN InfiniteWait;
2282
2283 Packet = Trb->Packet;
2284 //
2285 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
2286 //
2287 Timeout = Packet->Timeout;
2288 if (Timeout == 0) {
2289 InfiniteWait = TRUE;
2290 } else {
2291 InfiniteWait = FALSE;
2292 }
2293
2294 while (InfiniteWait || (Timeout > 0)) {
2295 //
2296 // Check Trb execution result by reading Normal Interrupt Status register.
2297 //
2298 Status = SdMmcCheckTrbResult (Private, Trb);
2299 if (Status != EFI_NOT_READY) {
2300 return Status;
2301 }
2302 //
2303 // Stall for 1 microsecond.
2304 //
2305 gBS->Stall (1);
2306
2307 Timeout--;
2308 }
2309
2310 return EFI_TIMEOUT;
2311 }
2312
EFI Development Kit II mirror for PVE