2 This driver is used to manage SD/MMC PCI host controllers which are compliance
3 with SD Host Controller Simplified Specification version 3.00 plus the 64-bit
4 System Addressing support in SD Host Controller Simplified Specification version
7 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
9 Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
10 Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
11 SPDX-License-Identifier: BSD-2-Clause-Patent
15 #include "SdMmcPciHcDxe.h"
18 Dump the content of SD/MMC host controller's Capability Register.
20 @param[in] Slot The slot number of the SD card to send the command to.
21 @param[in] Capability The buffer to store the capability data.
27 IN SD_MMC_HC_SLOT_CAP
*Capability
31 // Dump Capability Data
33 DEBUG ((DEBUG_INFO
, " == Slot [%d] Capability is 0x%x ==\n", Slot
, Capability
));
34 DEBUG ((DEBUG_INFO
, " Timeout Clk Freq %d%a\n", Capability
->TimeoutFreq
, (Capability
->TimeoutUnit
) ? "MHz" : "KHz"));
35 DEBUG ((DEBUG_INFO
, " Base Clk Freq %dMHz\n", Capability
->BaseClkFreq
));
36 DEBUG ((DEBUG_INFO
, " Max Blk Len %dbytes\n", 512 * (1 << Capability
->MaxBlkLen
)));
37 DEBUG ((DEBUG_INFO
, " 8-bit Support %a\n", Capability
->BusWidth8
? "TRUE" : "FALSE"));
38 DEBUG ((DEBUG_INFO
, " ADMA2 Support %a\n", Capability
->Adma2
? "TRUE" : "FALSE"));
39 DEBUG ((DEBUG_INFO
, " HighSpeed Support %a\n", Capability
->HighSpeed
? "TRUE" : "FALSE"));
40 DEBUG ((DEBUG_INFO
, " SDMA Support %a\n", Capability
->Sdma
? "TRUE" : "FALSE"));
41 DEBUG ((DEBUG_INFO
, " Suspend/Resume %a\n", Capability
->SuspRes
? "TRUE" : "FALSE"));
42 DEBUG ((DEBUG_INFO
, " Voltage 3.3 %a\n", Capability
->Voltage33
? "TRUE" : "FALSE"));
43 DEBUG ((DEBUG_INFO
, " Voltage 3.0 %a\n", Capability
->Voltage30
? "TRUE" : "FALSE"));
44 DEBUG ((DEBUG_INFO
, " Voltage 1.8 %a\n", Capability
->Voltage18
? "TRUE" : "FALSE"));
45 DEBUG ((DEBUG_INFO
, " V4 64-bit Sys Bus %a\n", Capability
->SysBus64V4
? "TRUE" : "FALSE"));
46 DEBUG ((DEBUG_INFO
, " V3 64-bit Sys Bus %a\n", Capability
->SysBus64V3
? "TRUE" : "FALSE"));
47 DEBUG ((DEBUG_INFO
, " Async Interrupt %a\n", Capability
->AsyncInt
? "TRUE" : "FALSE"));
48 DEBUG ((DEBUG_INFO
, " SlotType "));
49 if (Capability
->SlotType
== 0x00) {
50 DEBUG ((DEBUG_INFO
, "%a\n", "Removable Slot"));
51 } else if (Capability
->SlotType
== 0x01) {
52 DEBUG ((DEBUG_INFO
, "%a\n", "Embedded Slot"));
53 } else if (Capability
->SlotType
== 0x02) {
54 DEBUG ((DEBUG_INFO
, "%a\n", "Shared Bus Slot"));
56 DEBUG ((DEBUG_INFO
, "%a\n", "Reserved"));
58 DEBUG ((DEBUG_INFO
, " SDR50 Support %a\n", Capability
->Sdr50
? "TRUE" : "FALSE"));
59 DEBUG ((DEBUG_INFO
, " SDR104 Support %a\n", Capability
->Sdr104
? "TRUE" : "FALSE"));
60 DEBUG ((DEBUG_INFO
, " DDR50 Support %a\n", Capability
->Ddr50
? "TRUE" : "FALSE"));
61 DEBUG ((DEBUG_INFO
, " Driver Type A %a\n", Capability
->DriverTypeA
? "TRUE" : "FALSE"));
62 DEBUG ((DEBUG_INFO
, " Driver Type C %a\n", Capability
->DriverTypeC
? "TRUE" : "FALSE"));
63 DEBUG ((DEBUG_INFO
, " Driver Type D %a\n", Capability
->DriverTypeD
? "TRUE" : "FALSE"));
64 DEBUG ((DEBUG_INFO
, " Driver Type 4 %a\n", Capability
->DriverType4
? "TRUE" : "FALSE"));
65 if (Capability
->TimerCount
== 0) {
66 DEBUG ((DEBUG_INFO
, " Retuning TimerCnt Disabled\n", 2 * (Capability
->TimerCount
- 1)));
68 DEBUG ((DEBUG_INFO
, " Retuning TimerCnt %dseconds\n", 2 * (Capability
->TimerCount
- 1)));
70 DEBUG ((DEBUG_INFO
, " SDR50 Tuning %a\n", Capability
->TuningSDR50
? "TRUE" : "FALSE"));
71 DEBUG ((DEBUG_INFO
, " Retuning Mode Mode %d\n", Capability
->RetuningMod
+ 1));
72 DEBUG ((DEBUG_INFO
, " Clock Multiplier M = %d\n", Capability
->ClkMultiplier
+ 1));
73 DEBUG ((DEBUG_INFO
, " HS 400 %a\n", Capability
->Hs400
? "TRUE" : "FALSE"));
78 Read SlotInfo register from SD/MMC host controller pci config space.
80 @param[in] PciIo The PCI IO protocol instance.
81 @param[out] FirstBar The buffer to store the first BAR value.
82 @param[out] SlotNum The buffer to store the supported slot number.
84 @retval EFI_SUCCESS The operation succeeds.
85 @retval Others The operation fails.
91 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
97 SD_MMC_HC_SLOT_INFO SlotInfo
;
99 Status
= PciIo
->Pci
.Read (
102 SD_MMC_HC_SLOT_OFFSET
,
106 if (EFI_ERROR (Status
)) {
110 *FirstBar
= SlotInfo
.FirstBar
;
111 *SlotNum
= SlotInfo
.SlotNum
+ 1;
112 ASSERT ((*FirstBar
+ *SlotNum
) < SD_MMC_HC_MAX_SLOT
);
117 Read/Write specified SD/MMC host controller mmio register.
119 @param[in] PciIo The PCI IO protocol instance.
120 @param[in] BarIndex The BAR index of the standard PCI Configuration
121 header to use as the base address for the memory
122 operation to perform.
123 @param[in] Offset The offset within the selected BAR to start the
125 @param[in] Read A boolean to indicate it's read or write operation.
126 @param[in] Count The width of the mmio register in bytes.
127 Must be 1, 2 , 4 or 8 bytes.
128 @param[in, out] Data For read operations, the destination buffer to store
129 the results. For write operations, the source buffer
130 to write data from. The caller is responsible for
131 having ownership of the data buffer and ensuring its
132 size not less than Count bytes.
134 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
135 @retval EFI_SUCCESS The read/write operation succeeds.
136 @retval Others The read/write operation fails.
142 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
151 EFI_PCI_IO_PROTOCOL_WIDTH Width
;
153 if ((PciIo
== NULL
) || (Data
== NULL
)) {
154 return EFI_INVALID_PARAMETER
;
159 Width
= EfiPciIoWidthUint8
;
162 Width
= EfiPciIoWidthUint16
;
166 Width
= EfiPciIoWidthUint32
;
170 Width
= EfiPciIoWidthUint32
;
174 return EFI_INVALID_PARAMETER
;
178 Status
= PciIo
->Mem
.Read (
187 Status
= PciIo
->Mem
.Write (
201 Do OR operation with the value of the specified SD/MMC host controller mmio register.
203 @param[in] PciIo The PCI IO protocol instance.
204 @param[in] BarIndex The BAR index of the standard PCI Configuration
205 header to use as the base address for the memory
206 operation to perform.
207 @param[in] Offset The offset within the selected BAR to start the
209 @param[in] Count The width of the mmio register in bytes.
210 Must be 1, 2 , 4 or 8 bytes.
211 @param[in] OrData The pointer to the data used to do OR operation.
212 The caller is responsible for having ownership of
213 the data buffer and ensuring its size not less than
216 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
217 @retval EFI_SUCCESS The OR operation succeeds.
218 @retval Others The OR operation fails.
224 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
235 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Data
);
236 if (EFI_ERROR (Status
)) {
241 Or
= *(UINT8
*) OrData
;
242 } else if (Count
== 2) {
243 Or
= *(UINT16
*) OrData
;
244 } else if (Count
== 4) {
245 Or
= *(UINT32
*) OrData
;
246 } else if (Count
== 8) {
247 Or
= *(UINT64
*) OrData
;
249 return EFI_INVALID_PARAMETER
;
253 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, FALSE
, Count
, &Data
);
259 Do AND operation with the value of the specified SD/MMC host controller mmio register.
261 @param[in] PciIo The PCI IO protocol instance.
262 @param[in] BarIndex The BAR index of the standard PCI Configuration
263 header to use as the base address for the memory
264 operation to perform.
265 @param[in] Offset The offset within the selected BAR to start the
267 @param[in] Count The width of the mmio register in bytes.
268 Must be 1, 2 , 4 or 8 bytes.
269 @param[in] AndData The pointer to the data used to do AND operation.
270 The caller is responsible for having ownership of
271 the data buffer and ensuring its size not less than
274 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
275 @retval EFI_SUCCESS The AND operation succeeds.
276 @retval Others The AND operation fails.
282 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
293 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Data
);
294 if (EFI_ERROR (Status
)) {
299 And
= *(UINT8
*) AndData
;
300 } else if (Count
== 2) {
301 And
= *(UINT16
*) AndData
;
302 } else if (Count
== 4) {
303 And
= *(UINT32
*) AndData
;
304 } else if (Count
== 8) {
305 And
= *(UINT64
*) AndData
;
307 return EFI_INVALID_PARAMETER
;
311 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, FALSE
, Count
, &Data
);
317 Wait for the value of the specified MMIO register set to the test value.
319 @param[in] PciIo The PCI IO protocol instance.
320 @param[in] BarIndex The BAR index of the standard PCI Configuration
321 header to use as the base address for the memory
322 operation to perform.
323 @param[in] Offset The offset within the selected BAR to start the
325 @param[in] Count The width of the mmio register in bytes.
326 Must be 1, 2, 4 or 8 bytes.
327 @param[in] MaskValue The mask value of memory.
328 @param[in] TestValue The test value of memory.
330 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
331 @retval EFI_SUCCESS The MMIO register has expected value.
332 @retval Others The MMIO operation fails.
337 SdMmcHcCheckMmioSet (
338 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
350 // Access PCI MMIO space to see if the value is the tested one.
353 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Value
);
354 if (EFI_ERROR (Status
)) {
360 if (Value
== TestValue
) {
364 return EFI_NOT_READY
;
368 Wait for the value of the specified MMIO register set to the test value.
370 @param[in] PciIo The PCI IO protocol instance.
371 @param[in] BarIndex The BAR index of the standard PCI Configuration
372 header to use as the base address for the memory
373 operation to perform.
374 @param[in] Offset The offset within the selected BAR to start the
376 @param[in] Count The width of the mmio register in bytes.
377 Must be 1, 2, 4 or 8 bytes.
378 @param[in] MaskValue The mask value of memory.
379 @param[in] TestValue The test value of memory.
380 @param[in] Timeout The time out value for wait memory set, uses 1
381 microsecond as a unit.
383 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
385 @retval EFI_SUCCESS The MMIO register has expected value.
386 @retval Others The MMIO operation fails.
392 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
402 BOOLEAN InfiniteWait
;
407 InfiniteWait
= FALSE
;
410 while (InfiniteWait
|| (Timeout
> 0)) {
411 Status
= SdMmcHcCheckMmioSet (
419 if (Status
!= EFI_NOT_READY
) {
424 // Stall for 1 microsecond.
435 Get the controller version information from the specified slot.
437 @param[in] PciIo The PCI IO protocol instance.
438 @param[in] Slot The slot number of the SD card to send the command to.
439 @param[out] Version The buffer to store the version information.
441 @retval EFI_SUCCESS The operation executes successfully.
442 @retval Others The operation fails.
446 SdMmcHcGetControllerVersion (
447 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
454 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CTRL_VER
, TRUE
, sizeof (UINT16
), Version
);
455 if (EFI_ERROR (Status
)) {
465 Software reset the specified SD/MMC host controller and enable all interrupts.
467 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
468 @param[in] Slot The slot number of the SD card to send the command to.
470 @retval EFI_SUCCESS The software reset executes successfully.
471 @retval Others The software reset fails.
476 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
482 EFI_PCI_IO_PROTOCOL
*PciIo
;
485 // Notify the SD/MMC override protocol that we are about to reset
486 // the SD/MMC host controller.
488 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
489 Status
= mOverride
->NotifyPhase (
490 Private
->ControllerHandle
,
494 if (EFI_ERROR (Status
)) {
496 "%a: SD/MMC pre reset notifier callback failed - %r\n",
497 __FUNCTION__
, Status
));
502 PciIo
= Private
->PciIo
;
504 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_SW_RST
, sizeof (SwReset
), &SwReset
);
506 if (EFI_ERROR (Status
)) {
507 DEBUG ((DEBUG_ERROR
, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status
));
511 Status
= SdMmcHcWaitMmioSet (
518 SD_MMC_HC_GENERIC_TIMEOUT
520 if (EFI_ERROR (Status
)) {
521 DEBUG ((DEBUG_INFO
, "SdMmcHcReset: reset done with %r\n", Status
));
526 // Enable all interrupt after reset all.
528 Status
= SdMmcHcEnableInterrupt (PciIo
, Slot
);
529 if (EFI_ERROR (Status
)) {
530 DEBUG ((DEBUG_INFO
, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",
536 // Notify the SD/MMC override protocol that we have just reset
537 // the SD/MMC host controller.
539 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
540 Status
= mOverride
->NotifyPhase (
541 Private
->ControllerHandle
,
545 if (EFI_ERROR (Status
)) {
547 "%a: SD/MMC post reset notifier callback failed - %r\n",
548 __FUNCTION__
, Status
));
556 Set all interrupt status bits in Normal and Error Interrupt Status Enable
559 @param[in] PciIo The PCI IO protocol instance.
560 @param[in] Slot The slot number of the SD card to send the command to.
562 @retval EFI_SUCCESS The operation executes successfully.
563 @retval Others The operation fails.
567 SdMmcHcEnableInterrupt (
568 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
576 // Enable all bits in Error Interrupt Status Enable Register
579 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_ERR_INT_STS_EN
, FALSE
, sizeof (IntStatus
), &IntStatus
);
580 if (EFI_ERROR (Status
)) {
584 // Enable all bits in Normal Interrupt Status Enable Register
587 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS_EN
, FALSE
, sizeof (IntStatus
), &IntStatus
);
593 Get the capability data from the specified slot.
595 @param[in] PciIo The PCI IO protocol instance.
596 @param[in] Slot The slot number of the SD card to send the command to.
597 @param[out] Capability The buffer to store the capability data.
599 @retval EFI_SUCCESS The operation executes successfully.
600 @retval Others The operation fails.
604 SdMmcHcGetCapability (
605 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
607 OUT SD_MMC_HC_SLOT_CAP
*Capability
613 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CAP
, TRUE
, sizeof (Cap
), &Cap
);
614 if (EFI_ERROR (Status
)) {
618 CopyMem (Capability
, &Cap
, sizeof (Cap
));
624 Get the maximum current capability data from the specified slot.
626 @param[in] PciIo The PCI IO protocol instance.
627 @param[in] Slot The slot number of the SD card to send the command to.
628 @param[out] MaxCurrent The buffer to store the maximum current capability data.
630 @retval EFI_SUCCESS The operation executes successfully.
631 @retval Others The operation fails.
635 SdMmcHcGetMaxCurrent (
636 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
638 OUT UINT64
*MaxCurrent
643 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_MAX_CURRENT_CAP
, TRUE
, sizeof (UINT64
), MaxCurrent
);
649 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
652 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
654 @param[in] PciIo The PCI IO protocol instance.
655 @param[in] Slot The slot number of the SD card to send the command to.
656 @param[out] MediaPresent The pointer to the media present boolean value.
658 @retval EFI_SUCCESS There is no media change happened.
659 @retval EFI_MEDIA_CHANGED There is media change happened.
660 @retval Others The detection fails.
665 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
667 OUT BOOLEAN
*MediaPresent
675 // Check Present State Register to see if there is a card presented.
677 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_PRESENT_STATE
, TRUE
, sizeof (PresentState
), &PresentState
);
678 if (EFI_ERROR (Status
)) {
682 if ((PresentState
& BIT16
) != 0) {
683 *MediaPresent
= TRUE
;
685 *MediaPresent
= FALSE
;
689 // Check Normal Interrupt Status Register
691 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS
, TRUE
, sizeof (Data
), &Data
);
692 if (EFI_ERROR (Status
)) {
696 if ((Data
& (BIT6
| BIT7
)) != 0) {
698 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
701 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (Data
), &Data
);
702 if (EFI_ERROR (Status
)) {
706 return EFI_MEDIA_CHANGED
;
713 Stop SD/MMC card clock.
715 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
717 @param[in] PciIo The PCI IO protocol instance.
718 @param[in] Slot The slot number of the SD card to send the command to.
720 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.
721 @retval Others Fail to stop SD/MMC clock.
726 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
735 // Ensure no SD transactions are occurring on the SD Bus by
736 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
737 // in the Present State register to be 0.
739 Status
= SdMmcHcWaitMmioSet (
742 SD_MMC_HC_PRESENT_STATE
,
743 sizeof (PresentState
),
746 SD_MMC_HC_GENERIC_TIMEOUT
748 if (EFI_ERROR (Status
)) {
753 // Set SD Clock Enable in the Clock Control register to 0
755 ClockCtrl
= (UINT16
)~BIT2
;
756 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, sizeof (ClockCtrl
), &ClockCtrl
);
762 SD/MMC card clock supply.
764 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
766 @param[in] PciIo The PCI IO protocol instance.
767 @param[in] Slot The slot number of the SD card to send the command to.
768 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
769 @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
770 @param[in] ControllerVer The version of host controller.
772 @retval EFI_SUCCESS The clock is supplied successfully.
773 @retval Others The clock isn't supplied successfully.
778 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
781 IN UINT32 BaseClkFreq
,
782 IN UINT16 ControllerVer
792 // Calculate a divisor for SD clock frequency
794 ASSERT (BaseClkFreq
!= 0);
796 if (ClockFreq
== 0) {
797 return EFI_INVALID_PARAMETER
;
800 if (ClockFreq
> (BaseClkFreq
* 1000)) {
801 ClockFreq
= BaseClkFreq
* 1000;
805 // Calculate the divisor of base frequency.
808 SettingFreq
= BaseClkFreq
* 1000;
809 while (ClockFreq
< SettingFreq
) {
812 SettingFreq
= (BaseClkFreq
* 1000) / (2 * Divisor
);
813 Remainder
= (BaseClkFreq
* 1000) % (2 * Divisor
);
814 if ((ClockFreq
== SettingFreq
) && (Remainder
== 0)) {
817 if ((ClockFreq
== SettingFreq
) && (Remainder
!= 0)) {
822 DEBUG ((DEBUG_INFO
, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq
, Divisor
, ClockFreq
));
825 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
827 if ((ControllerVer
>= SD_MMC_HC_CTRL_VER_300
) &&
828 (ControllerVer
<= SD_MMC_HC_CTRL_VER_420
)) {
829 ASSERT (Divisor
<= 0x3FF);
830 ClockCtrl
= ((Divisor
& 0xFF) << 8) | ((Divisor
& 0x300) >> 2);
831 } else if ((ControllerVer
== SD_MMC_HC_CTRL_VER_100
) ||
832 (ControllerVer
== SD_MMC_HC_CTRL_VER_200
)) {
834 // Only the most significant bit can be used as divisor.
836 if (((Divisor
- 1) & Divisor
) != 0) {
837 Divisor
= 1 << (HighBitSet32 (Divisor
) + 1);
839 ASSERT (Divisor
<= 0x80);
840 ClockCtrl
= (Divisor
& 0xFF) << 8;
842 DEBUG ((DEBUG_ERROR
, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer
));
843 return EFI_UNSUPPORTED
;
847 // Stop bus clock at first
849 Status
= SdMmcHcStopClock (PciIo
, Slot
);
850 if (EFI_ERROR (Status
)) {
855 // Supply clock frequency with specified divisor
858 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, FALSE
, sizeof (ClockCtrl
), &ClockCtrl
);
859 if (EFI_ERROR (Status
)) {
860 DEBUG ((DEBUG_ERROR
, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
865 // Wait Internal Clock Stable in the Clock Control register to be 1
867 Status
= SdMmcHcWaitMmioSet (
870 SD_MMC_HC_CLOCK_CTRL
,
874 SD_MMC_HC_GENERIC_TIMEOUT
876 if (EFI_ERROR (Status
)) {
881 // Set SD Clock Enable in the Clock Control register to 1
884 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, sizeof (ClockCtrl
), &ClockCtrl
);
890 SD/MMC bus power control.
892 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
894 @param[in] PciIo The PCI IO protocol instance.
895 @param[in] Slot The slot number of the SD card to send the command to.
896 @param[in] PowerCtrl The value setting to the power control register.
898 @retval TRUE There is a SD/MMC card attached.
899 @retval FALSE There is no a SD/MMC card attached.
903 SdMmcHcPowerControl (
904 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
914 PowerCtrl
&= (UINT8
)~BIT0
;
915 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_POWER_CTRL
, FALSE
, sizeof (PowerCtrl
), &PowerCtrl
);
916 if (EFI_ERROR (Status
)) {
921 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
924 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_POWER_CTRL
, FALSE
, sizeof (PowerCtrl
), &PowerCtrl
);
930 Set the SD/MMC bus width.
932 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
934 @param[in] PciIo The PCI IO protocol instance.
935 @param[in] Slot The slot number of the SD card to send the command to.
936 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
938 @retval EFI_SUCCESS The bus width is set successfully.
939 @retval Others The bus width isn't set successfully.
944 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
953 HostCtrl1
= (UINT8
)~(BIT5
| BIT1
);
954 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
955 } else if (BusWidth
== 4) {
956 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, TRUE
, sizeof (HostCtrl1
), &HostCtrl1
);
957 if (EFI_ERROR (Status
)) {
961 HostCtrl1
&= (UINT8
)~BIT5
;
962 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, FALSE
, sizeof (HostCtrl1
), &HostCtrl1
);
963 } else if (BusWidth
== 8) {
964 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, TRUE
, sizeof (HostCtrl1
), &HostCtrl1
);
965 if (EFI_ERROR (Status
)) {
968 HostCtrl1
&= (UINT8
)~BIT1
;
970 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, FALSE
, sizeof (HostCtrl1
), &HostCtrl1
);
973 return EFI_INVALID_PARAMETER
;
980 Configure V4 controller enhancements at initialization.
982 @param[in] PciIo The PCI IO protocol instance.
983 @param[in] Slot The slot number of the SD card to send the command to.
984 @param[in] Capability The capability of the slot.
985 @param[in] ControllerVer The version of host controller.
987 @retval EFI_SUCCESS The clock is supplied successfully.
991 SdMmcHcInitV4Enhancements (
992 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
994 IN SD_MMC_HC_SLOT_CAP Capability
,
995 IN UINT16 ControllerVer
1002 // Check if controller version V4 or higher
1004 if (ControllerVer
>= SD_MMC_HC_CTRL_VER_400
) {
1005 HostCtrl2
= SD_MMC_HC_V4_EN
;
1007 // Check if controller version V4.0
1009 if (ControllerVer
== SD_MMC_HC_CTRL_VER_400
) {
1011 // Check if 64bit support is available
1013 if (Capability
.SysBus64V3
!= 0) {
1014 HostCtrl2
|= SD_MMC_HC_64_ADDR_EN
;
1015 DEBUG ((DEBUG_INFO
, "Enabled V4 64 bit system bus support\n"));
1019 // Check if controller version V4.10 or higher
1021 else if (ControllerVer
>= SD_MMC_HC_CTRL_VER_410
) {
1023 // Check if 64bit support is available
1025 if (Capability
.SysBus64V4
!= 0) {
1026 HostCtrl2
|= SD_MMC_HC_64_ADDR_EN
;
1027 DEBUG ((DEBUG_INFO
, "Enabled V4 64 bit system bus support\n"));
1029 HostCtrl2
|= SD_MMC_HC_26_DATA_LEN_ADMA_EN
;
1030 DEBUG ((DEBUG_INFO
, "Enabled V4 26 bit data length ADMA support\n"));
1032 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1033 if (EFI_ERROR (Status
)) {
1042 Supply SD/MMC card with lowest clock frequency at initialization.
1044 @param[in] PciIo The PCI IO protocol instance.
1045 @param[in] Slot The slot number of the SD card to send the command to.
1046 @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
1047 @param[in] ControllerVer The version of host controller.
1049 @retval EFI_SUCCESS The clock is supplied successfully.
1050 @retval Others The clock isn't supplied successfully.
1054 SdMmcHcInitClockFreq (
1055 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1057 IN UINT32 BaseClkFreq
,
1058 IN UINT16 ControllerVer
1065 // According to SDHCI specification ver. 4.2, BaseClkFreq field value of
1066 // the Capability Register 1 can be zero, which means a need for obtaining
1067 // the clock frequency via another method. Fail in case it is not updated
1068 // by SW at this point.
1070 if (BaseClkFreq
== 0) {
1072 // Don't support get Base Clock Frequency information via another method
1074 return EFI_UNSUPPORTED
;
1077 // Supply 400KHz clock frequency at initialization phase.
1080 Status
= SdMmcHcClockSupply (PciIo
, Slot
, InitFreq
, BaseClkFreq
, ControllerVer
);
1085 Supply SD/MMC card with maximum voltage at initialization.
1087 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
1089 @param[in] PciIo The PCI IO protocol instance.
1090 @param[in] Slot The slot number of the SD card to send the command to.
1091 @param[in] Capability The capability of the slot.
1093 @retval EFI_SUCCESS The voltage is supplied successfully.
1094 @retval Others The voltage isn't supplied successfully.
1098 SdMmcHcInitPowerVoltage (
1099 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1101 IN SD_MMC_HC_SLOT_CAP Capability
1109 // Calculate supported maximum voltage according to SD Bus Voltage Select
1111 if (Capability
.Voltage33
!= 0) {
1116 } else if (Capability
.Voltage30
!= 0) {
1121 } else if (Capability
.Voltage18
!= 0) {
1127 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1129 if (EFI_ERROR (Status
)) {
1134 return EFI_DEVICE_ERROR
;
1138 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
1140 Status
= SdMmcHcPowerControl (PciIo
, Slot
, MaxVoltage
);
1146 Initialize the Timeout Control register with most conservative value at initialization.
1148 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
1150 @param[in] PciIo The PCI IO protocol instance.
1151 @param[in] Slot The slot number of the SD card to send the command to.
1153 @retval EFI_SUCCESS The timeout control register is configured successfully.
1154 @retval Others The timeout control register isn't configured successfully.
1158 SdMmcHcInitTimeoutCtrl (
1159 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1167 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_TIMEOUT_CTRL
, FALSE
, sizeof (Timeout
), &Timeout
);
1173 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
1176 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1177 @param[in] Slot The slot number of the SD card to send the command to.
1179 @retval EFI_SUCCESS The host controller is initialized successfully.
1180 @retval Others The host controller isn't initialized successfully.
1185 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1190 EFI_PCI_IO_PROTOCOL
*PciIo
;
1191 SD_MMC_HC_SLOT_CAP Capability
;
1194 // Notify the SD/MMC override protocol that we are about to initialize
1195 // the SD/MMC host controller.
1197 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
1198 Status
= mOverride
->NotifyPhase (
1199 Private
->ControllerHandle
,
1201 EdkiiSdMmcInitHostPre
,
1203 if (EFI_ERROR (Status
)) {
1205 "%a: SD/MMC pre init notifier callback failed - %r\n",
1206 __FUNCTION__
, Status
));
1211 PciIo
= Private
->PciIo
;
1212 Capability
= Private
->Capability
[Slot
];
1214 Status
= SdMmcHcInitV4Enhancements (PciIo
, Slot
, Capability
, Private
->ControllerVersion
[Slot
]);
1215 if (EFI_ERROR (Status
)) {
1219 Status
= SdMmcHcInitClockFreq (PciIo
, Slot
, Private
->BaseClkFreq
[Slot
], Private
->ControllerVersion
[Slot
]);
1220 if (EFI_ERROR (Status
)) {
1224 Status
= SdMmcHcInitPowerVoltage (PciIo
, Slot
, Capability
);
1225 if (EFI_ERROR (Status
)) {
1229 Status
= SdMmcHcInitTimeoutCtrl (PciIo
, Slot
);
1230 if (EFI_ERROR (Status
)) {
1235 // Notify the SD/MMC override protocol that we are have just initialized
1236 // the SD/MMC host controller.
1238 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
1239 Status
= mOverride
->NotifyPhase (
1240 Private
->ControllerHandle
,
1242 EdkiiSdMmcInitHostPost
,
1244 if (EFI_ERROR (Status
)) {
1246 "%a: SD/MMC post init notifier callback failed - %r\n",
1247 __FUNCTION__
, Status
));
1254 Set SD Host Controler control 2 registry according to selected speed.
1256 @param[in] ControllerHandle The handle of the controller.
1257 @param[in] PciIo The PCI IO protocol instance.
1258 @param[in] Slot The slot number of the SD card to send the command to.
1259 @param[in] Timing The timing to select.
1261 @retval EFI_SUCCESS The timing is set successfully.
1262 @retval Others The timing isn't set successfully.
1265 SdMmcHcUhsSignaling (
1266 IN EFI_HANDLE ControllerHandle
,
1267 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1269 IN SD_MMC_BUS_MODE Timing
1275 HostCtrl2
= (UINT8
)~SD_MMC_HC_CTRL_UHS_MASK
;
1276 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1277 if (EFI_ERROR (Status
)) {
1283 HostCtrl2
= SD_MMC_HC_CTRL_UHS_SDR12
;
1286 HostCtrl2
= SD_MMC_HC_CTRL_UHS_SDR25
;
1289 HostCtrl2
= SD_MMC_HC_CTRL_UHS_SDR50
;
1291 case SdMmcUhsSdr104
:
1292 HostCtrl2
= SD_MMC_HC_CTRL_UHS_SDR104
;
1295 HostCtrl2
= SD_MMC_HC_CTRL_UHS_DDR50
;
1297 case SdMmcMmcLegacy
:
1298 HostCtrl2
= SD_MMC_HC_CTRL_MMC_LEGACY
;
1301 HostCtrl2
= SD_MMC_HC_CTRL_MMC_HS_SDR
;
1304 HostCtrl2
= SD_MMC_HC_CTRL_MMC_HS_DDR
;
1307 HostCtrl2
= SD_MMC_HC_CTRL_MMC_HS200
;
1310 HostCtrl2
= SD_MMC_HC_CTRL_MMC_HS400
;
1316 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1317 if (EFI_ERROR (Status
)) {
1321 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
1322 Status
= mOverride
->NotifyPhase (
1325 EdkiiSdMmcUhsSignaling
,
1328 if (EFI_ERROR (Status
)) {
1331 "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
1345 @param[in] PciIo The PCI IO protocol instance.
1346 @param[in] Slot The slot number of the SD card to send the command to.
1347 @param[in] On The boolean to turn on/off LED.
1349 @retval EFI_SUCCESS The LED is turned on/off successfully.
1350 @retval Others The LED isn't turned on/off successfully.
1355 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1365 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1367 HostCtrl1
= (UINT8
)~BIT0
;
1368 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1375 Build ADMA descriptor table for transfer.
1377 Refer to SD Host Controller Simplified spec 4.2 Section 1.13 for details.
1379 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1380 @param[in] ControllerVer The version of host controller.
1382 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
1383 @retval Others The ADMA descriptor table isn't created successfully.
1387 BuildAdmaDescTable (
1388 IN SD_MMC_HC_TRB
*Trb
,
1389 IN UINT16 ControllerVer
1392 EFI_PHYSICAL_ADDRESS Data
;
1399 EFI_PCI_IO_PROTOCOL
*PciIo
;
1402 UINT32 AdmaMaxDataPerLine
;
1406 AdmaMaxDataPerLine
= ADMA_MAX_DATA_PER_LINE_16B
;
1407 DescSize
= sizeof (SD_MMC_HC_ADMA_32_DESC_LINE
);
1410 Data
= Trb
->DataPhy
;
1411 DataLen
= Trb
->DataLen
;
1412 PciIo
= Trb
->Private
->PciIo
;
1415 // Check for valid ranges in 32bit ADMA Descriptor Table
1417 if ((Trb
->Mode
== SdMmcAdma32bMode
) &&
1418 ((Data
>= 0x100000000ul
) || ((Data
+ DataLen
) > 0x100000000ul
))) {
1419 return EFI_INVALID_PARAMETER
;
1422 // Check address field alignment
1424 if (Trb
->Mode
!= SdMmcAdma32bMode
) {
1426 // Address field shall be set on 64-bit boundary (Lower 3-bit is always set to 0)
1428 if ((Data
& (BIT0
| BIT1
| BIT2
)) != 0) {
1429 DEBUG ((DEBUG_INFO
, "The buffer [0x%x] to construct ADMA desc is not aligned to 8 bytes boundary!\n", Data
));
1433 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
1435 if ((Data
& (BIT0
| BIT1
)) != 0) {
1436 DEBUG ((DEBUG_INFO
, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data
));
1441 // Configure 64b ADMA.
1443 if (Trb
->Mode
== SdMmcAdma64bV3Mode
) {
1444 DescSize
= sizeof (SD_MMC_HC_ADMA_64_V3_DESC_LINE
);
1445 }else if (Trb
->Mode
== SdMmcAdma64bV4Mode
) {
1446 DescSize
= sizeof (SD_MMC_HC_ADMA_64_V4_DESC_LINE
);
1449 // Configure 26b data length.
1451 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1452 AdmaMaxDataPerLine
= ADMA_MAX_DATA_PER_LINE_26B
;
1455 Entries
= DivU64x32 ((DataLen
+ AdmaMaxDataPerLine
- 1), AdmaMaxDataPerLine
);
1456 TableSize
= (UINTN
)MultU64x32 (Entries
, DescSize
);
1457 Trb
->AdmaPages
= (UINT32
)EFI_SIZE_TO_PAGES (TableSize
);
1458 Status
= PciIo
->AllocateBuffer (
1461 EfiBootServicesData
,
1462 EFI_SIZE_TO_PAGES (TableSize
),
1466 if (EFI_ERROR (Status
)) {
1467 return EFI_OUT_OF_RESOURCES
;
1469 ZeroMem (AdmaDesc
, TableSize
);
1471 Status
= PciIo
->Map (
1473 EfiPciIoOperationBusMasterCommonBuffer
,
1480 if (EFI_ERROR (Status
) || (Bytes
!= TableSize
)) {
1482 // Map error or unable to map the whole RFis buffer into a contiguous region.
1486 EFI_SIZE_TO_PAGES (TableSize
),
1489 return EFI_OUT_OF_RESOURCES
;
1492 if ((Trb
->Mode
== SdMmcAdma32bMode
) &&
1493 (UINT64
)(UINTN
)Trb
->AdmaDescPhy
> 0x100000000ul
) {
1495 // The ADMA doesn't support 64bit addressing.
1503 EFI_SIZE_TO_PAGES (TableSize
),
1506 return EFI_DEVICE_ERROR
;
1509 Remaining
= DataLen
;
1511 if (Trb
->Mode
== SdMmcAdma32bMode
) {
1512 Trb
->Adma32Desc
= AdmaDesc
;
1513 } else if (Trb
->Mode
== SdMmcAdma64bV3Mode
) {
1514 Trb
->Adma64V3Desc
= AdmaDesc
;
1516 Trb
->Adma64V4Desc
= AdmaDesc
;
1519 for (Index
= 0; Index
< Entries
; Index
++) {
1520 if (Trb
->Mode
== SdMmcAdma32bMode
) {
1521 if (Remaining
<= AdmaMaxDataPerLine
) {
1522 Trb
->Adma32Desc
[Index
].Valid
= 1;
1523 Trb
->Adma32Desc
[Index
].Act
= 2;
1524 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1525 Trb
->Adma32Desc
[Index
].UpperLength
= (UINT16
)RShiftU64 (Remaining
, 16);
1527 Trb
->Adma32Desc
[Index
].LowerLength
= (UINT16
)(Remaining
& MAX_UINT16
);
1528 Trb
->Adma32Desc
[Index
].Address
= (UINT32
)Address
;
1531 Trb
->Adma32Desc
[Index
].Valid
= 1;
1532 Trb
->Adma32Desc
[Index
].Act
= 2;
1533 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1534 Trb
->Adma32Desc
[Index
].UpperLength
= 0;
1536 Trb
->Adma32Desc
[Index
].LowerLength
= 0;
1537 Trb
->Adma32Desc
[Index
].Address
= (UINT32
)Address
;
1539 } else if (Trb
->Mode
== SdMmcAdma64bV3Mode
) {
1540 if (Remaining
<= AdmaMaxDataPerLine
) {
1541 Trb
->Adma64V3Desc
[Index
].Valid
= 1;
1542 Trb
->Adma64V3Desc
[Index
].Act
= 2;
1543 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1544 Trb
->Adma64V3Desc
[Index
].UpperLength
= (UINT16
)RShiftU64 (Remaining
, 16);
1546 Trb
->Adma64V3Desc
[Index
].LowerLength
= (UINT16
)(Remaining
& MAX_UINT16
);
1547 Trb
->Adma64V3Desc
[Index
].LowerAddress
= (UINT32
)Address
;
1548 Trb
->Adma64V3Desc
[Index
].UpperAddress
= (UINT32
)RShiftU64 (Address
, 32);
1551 Trb
->Adma64V3Desc
[Index
].Valid
= 1;
1552 Trb
->Adma64V3Desc
[Index
].Act
= 2;
1553 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1554 Trb
->Adma64V3Desc
[Index
].UpperLength
= 0;
1556 Trb
->Adma64V3Desc
[Index
].LowerLength
= 0;
1557 Trb
->Adma64V3Desc
[Index
].LowerAddress
= (UINT32
)Address
;
1558 Trb
->Adma64V3Desc
[Index
].UpperAddress
= (UINT32
)RShiftU64 (Address
, 32);
1561 if (Remaining
<= AdmaMaxDataPerLine
) {
1562 Trb
->Adma64V4Desc
[Index
].Valid
= 1;
1563 Trb
->Adma64V4Desc
[Index
].Act
= 2;
1564 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1565 Trb
->Adma64V4Desc
[Index
].UpperLength
= (UINT16
)RShiftU64 (Remaining
, 16);
1567 Trb
->Adma64V4Desc
[Index
].LowerLength
= (UINT16
)(Remaining
& MAX_UINT16
);
1568 Trb
->Adma64V4Desc
[Index
].LowerAddress
= (UINT32
)Address
;
1569 Trb
->Adma64V4Desc
[Index
].UpperAddress
= (UINT32
)RShiftU64 (Address
, 32);
1572 Trb
->Adma64V4Desc
[Index
].Valid
= 1;
1573 Trb
->Adma64V4Desc
[Index
].Act
= 2;
1574 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1575 Trb
->Adma64V4Desc
[Index
].UpperLength
= 0;
1577 Trb
->Adma64V4Desc
[Index
].LowerLength
= 0;
1578 Trb
->Adma64V4Desc
[Index
].LowerAddress
= (UINT32
)Address
;
1579 Trb
->Adma64V4Desc
[Index
].UpperAddress
= (UINT32
)RShiftU64 (Address
, 32);
1583 Remaining
-= AdmaMaxDataPerLine
;
1584 Address
+= AdmaMaxDataPerLine
;
1588 // Set the last descriptor line as end of descriptor table
1590 if (Trb
->Mode
== SdMmcAdma32bMode
) {
1591 Trb
->Adma32Desc
[Index
].End
= 1;
1592 } else if (Trb
->Mode
== SdMmcAdma64bV3Mode
) {
1593 Trb
->Adma64V3Desc
[Index
].End
= 1;
1595 Trb
->Adma64V4Desc
[Index
].End
= 1;
1601 Create a new TRB for the SD/MMC cmd request.
1603 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1604 @param[in] Slot The slot number of the SD card to send the command to.
1605 @param[in] Packet A pointer to the SD command data structure.
1606 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
1607 not NULL, then nonblocking I/O is performed, and Event
1608 will be signaled when the Packet completes.
1610 @return Created Trb or NULL.
1615 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1617 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
,
1624 EFI_PCI_IO_PROTOCOL_OPERATION Flag
;
1625 EFI_PCI_IO_PROTOCOL
*PciIo
;
1628 Trb
= AllocateZeroPool (sizeof (SD_MMC_HC_TRB
));
1633 Trb
->Signature
= SD_MMC_HC_TRB_SIG
;
1635 Trb
->BlockSize
= 0x200;
1636 Trb
->Packet
= Packet
;
1638 Trb
->Started
= FALSE
;
1639 Trb
->Timeout
= Packet
->Timeout
;
1640 Trb
->Private
= Private
;
1642 if ((Packet
->InTransferLength
!= 0) && (Packet
->InDataBuffer
!= NULL
)) {
1643 Trb
->Data
= Packet
->InDataBuffer
;
1644 Trb
->DataLen
= Packet
->InTransferLength
;
1646 } else if ((Packet
->OutTransferLength
!= 0) && (Packet
->OutDataBuffer
!= NULL
)) {
1647 Trb
->Data
= Packet
->OutDataBuffer
;
1648 Trb
->DataLen
= Packet
->OutTransferLength
;
1650 } else if ((Packet
->InTransferLength
== 0) && (Packet
->OutTransferLength
== 0)) {
1657 if ((Trb
->DataLen
!= 0) && (Trb
->DataLen
< Trb
->BlockSize
)) {
1658 Trb
->BlockSize
= (UINT16
)Trb
->DataLen
;
1661 if (((Private
->Slot
[Trb
->Slot
].CardType
== EmmcCardType
) &&
1662 (Packet
->SdMmcCmdBlk
->CommandIndex
== EMMC_SEND_TUNING_BLOCK
)) ||
1663 ((Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) &&
1664 (Packet
->SdMmcCmdBlk
->CommandIndex
== SD_SEND_TUNING_BLOCK
))) {
1665 Trb
->Mode
= SdMmcPioMode
;
1668 Flag
= EfiPciIoOperationBusMasterWrite
;
1670 Flag
= EfiPciIoOperationBusMasterRead
;
1673 PciIo
= Private
->PciIo
;
1674 if (Trb
->DataLen
!= 0) {
1675 MapLength
= Trb
->DataLen
;
1676 Status
= PciIo
->Map (
1684 if (EFI_ERROR (Status
) || (Trb
->DataLen
!= MapLength
)) {
1685 Status
= EFI_BAD_BUFFER_SIZE
;
1690 if (Trb
->DataLen
== 0) {
1691 Trb
->Mode
= SdMmcNoData
;
1692 } else if (Private
->Capability
[Slot
].Adma2
!= 0) {
1693 Trb
->Mode
= SdMmcAdma32bMode
;
1694 Trb
->AdmaLengthMode
= SdMmcAdmaLen16b
;
1695 if ((Private
->ControllerVersion
[Slot
] == SD_MMC_HC_CTRL_VER_300
) &&
1696 (Private
->Capability
[Slot
].SysBus64V3
== 1)) {
1697 Trb
->Mode
= SdMmcAdma64bV3Mode
;
1698 } else if (((Private
->ControllerVersion
[Slot
] == SD_MMC_HC_CTRL_VER_400
) &&
1699 (Private
->Capability
[Slot
].SysBus64V3
== 1)) ||
1700 ((Private
->ControllerVersion
[Slot
] >= SD_MMC_HC_CTRL_VER_410
) &&
1701 (Private
->Capability
[Slot
].SysBus64V4
== 1))) {
1702 Trb
->Mode
= SdMmcAdma64bV4Mode
;
1704 if (Private
->ControllerVersion
[Slot
] >= SD_MMC_HC_CTRL_VER_410
) {
1705 Trb
->AdmaLengthMode
= SdMmcAdmaLen26b
;
1707 Status
= BuildAdmaDescTable (Trb
, Private
->ControllerVersion
[Slot
]);
1708 if (EFI_ERROR (Status
)) {
1709 PciIo
->Unmap (PciIo
, Trb
->DataMap
);
1712 } else if (Private
->Capability
[Slot
].Sdma
!= 0) {
1713 Trb
->Mode
= SdMmcSdmaMode
;
1715 Trb
->Mode
= SdMmcPioMode
;
1719 if (Event
!= NULL
) {
1720 OldTpl
= gBS
->RaiseTPL (TPL_NOTIFY
);
1721 InsertTailList (&Private
->Queue
, &Trb
->TrbList
);
1722 gBS
->RestoreTPL (OldTpl
);
1733 Free the resource used by the TRB.
1735 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1740 IN SD_MMC_HC_TRB
*Trb
1743 EFI_PCI_IO_PROTOCOL
*PciIo
;
1745 PciIo
= Trb
->Private
->PciIo
;
1747 if (Trb
->AdmaMap
!= NULL
) {
1753 if (Trb
->Adma32Desc
!= NULL
) {
1760 if (Trb
->Adma64V3Desc
!= NULL
) {
1767 if (Trb
->Adma64V4Desc
!= NULL
) {
1774 if (Trb
->DataMap
!= NULL
) {
1785 Check if the env is ready for execute specified TRB.
1787 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1788 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1790 @retval EFI_SUCCESS The env is ready for TRB execution.
1791 @retval EFI_NOT_READY The env is not ready for TRB execution.
1792 @retval Others Some erros happen.
1797 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1798 IN SD_MMC_HC_TRB
*Trb
1802 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1803 EFI_PCI_IO_PROTOCOL
*PciIo
;
1804 UINT32 PresentState
;
1806 Packet
= Trb
->Packet
;
1808 if ((Packet
->SdMmcCmdBlk
->CommandType
== SdMmcCommandTypeAdtc
) ||
1809 (Packet
->SdMmcCmdBlk
->ResponseType
== SdMmcResponseTypeR1b
) ||
1810 (Packet
->SdMmcCmdBlk
->ResponseType
== SdMmcResponseTypeR5b
)) {
1812 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1813 // the Present State register to be 0
1815 PresentState
= BIT0
| BIT1
;
1818 // Wait Command Inhibit (CMD) in the Present State register
1821 PresentState
= BIT0
;
1824 PciIo
= Private
->PciIo
;
1825 Status
= SdMmcHcCheckMmioSet (
1828 SD_MMC_HC_PRESENT_STATE
,
1829 sizeof (PresentState
),
1838 Wait for the env to be ready for execute specified TRB.
1840 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1841 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1843 @retval EFI_SUCCESS The env is ready for TRB execution.
1844 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
1845 @retval Others Some erros happen.
1850 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1851 IN SD_MMC_HC_TRB
*Trb
1855 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1857 BOOLEAN InfiniteWait
;
1860 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1862 Packet
= Trb
->Packet
;
1863 Timeout
= Packet
->Timeout
;
1865 InfiniteWait
= TRUE
;
1867 InfiniteWait
= FALSE
;
1870 while (InfiniteWait
|| (Timeout
> 0)) {
1872 // Check Trb execution result by reading Normal Interrupt Status register.
1874 Status
= SdMmcCheckTrbEnv (Private
, Trb
);
1875 if (Status
!= EFI_NOT_READY
) {
1879 // Stall for 1 microsecond.
1890 Execute the specified TRB.
1892 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1893 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1895 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
1896 @retval Others Some erros happen when sending this request to the host controller.
1901 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1902 IN SD_MMC_HC_TRB
*Trb
1906 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1907 EFI_PCI_IO_PROTOCOL
*PciIo
;
1917 BOOLEAN AddressingMode64
;
1919 AddressingMode64
= FALSE
;
1921 Packet
= Trb
->Packet
;
1922 PciIo
= Trb
->Private
->PciIo
;
1924 // Clear all bits in Error Interrupt Status Register
1927 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ERR_INT_STS
, FALSE
, sizeof (IntStatus
), &IntStatus
);
1928 if (EFI_ERROR (Status
)) {
1932 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
1935 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (IntStatus
), &IntStatus
);
1936 if (EFI_ERROR (Status
)) {
1940 if (Private
->ControllerVersion
[Trb
->Slot
] >= SD_MMC_HC_CTRL_VER_400
) {
1941 Status
= SdMmcHcCheckMmioSet(PciIo
, Trb
->Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof(UINT16
),
1942 SD_MMC_HC_64_ADDR_EN
, SD_MMC_HC_64_ADDR_EN
);
1943 if (!EFI_ERROR (Status
)) {
1944 AddressingMode64
= TRUE
;
1949 // Set Host Control 1 register DMA Select field
1951 if ((Trb
->Mode
== SdMmcAdma32bMode
) ||
1952 (Trb
->Mode
== SdMmcAdma64bV4Mode
)) {
1954 Status
= SdMmcHcOrMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1955 if (EFI_ERROR (Status
)) {
1958 } else if (Trb
->Mode
== SdMmcAdma64bV3Mode
) {
1959 HostCtrl1
= BIT4
|BIT3
;
1960 Status
= SdMmcHcOrMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1961 if (EFI_ERROR (Status
)) {
1966 SdMmcHcLedOnOff (PciIo
, Trb
->Slot
, TRUE
);
1968 if (Trb
->Mode
== SdMmcSdmaMode
) {
1969 if ((!AddressingMode64
) &&
1970 ((UINT64
)(UINTN
)Trb
->DataPhy
>= 0x100000000ul
)) {
1971 return EFI_INVALID_PARAMETER
;
1974 SdmaAddr
= (UINT64
)(UINTN
)Trb
->DataPhy
;
1976 if (Private
->ControllerVersion
[Trb
->Slot
] >= SD_MMC_HC_CTRL_VER_400
) {
1977 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ADMA_SYS_ADDR
, FALSE
, sizeof (UINT64
), &SdmaAddr
);
1979 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_SDMA_ADDR
, FALSE
, sizeof (UINT32
), &SdmaAddr
);
1982 if (EFI_ERROR (Status
)) {
1985 } else if ((Trb
->Mode
== SdMmcAdma32bMode
) ||
1986 (Trb
->Mode
== SdMmcAdma64bV3Mode
) ||
1987 (Trb
->Mode
== SdMmcAdma64bV4Mode
)) {
1988 AdmaAddr
= (UINT64
)(UINTN
)Trb
->AdmaDescPhy
;
1989 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ADMA_SYS_ADDR
, FALSE
, sizeof (AdmaAddr
), &AdmaAddr
);
1990 if (EFI_ERROR (Status
)) {
1995 BlkSize
= Trb
->BlockSize
;
1996 if (Trb
->Mode
== SdMmcSdmaMode
) {
1998 // Set SDMA boundary to be 512K bytes.
2003 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_BLK_SIZE
, FALSE
, sizeof (BlkSize
), &BlkSize
);
2004 if (EFI_ERROR (Status
)) {
2009 if (Trb
->Mode
!= SdMmcNoData
) {
2011 // Calcuate Block Count.
2013 BlkCount
= (Trb
->DataLen
/ Trb
->BlockSize
);
2015 if (Private
->ControllerVersion
[Trb
->Slot
] >= SD_MMC_HC_CTRL_VER_410
) {
2016 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_SDMA_ADDR
, FALSE
, sizeof (UINT32
), &BlkCount
);
2018 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_BLK_COUNT
, FALSE
, sizeof (UINT16
), &BlkCount
);
2020 if (EFI_ERROR (Status
)) {
2024 Argument
= Packet
->SdMmcCmdBlk
->CommandArgument
;
2025 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ARG1
, FALSE
, sizeof (Argument
), &Argument
);
2026 if (EFI_ERROR (Status
)) {
2031 if (Trb
->Mode
!= SdMmcNoData
) {
2032 if (Trb
->Mode
!= SdMmcPioMode
) {
2039 TransMode
|= BIT5
| BIT1
;
2042 // Only SD memory card needs to use AUTO CMD12 feature.
2044 if (Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) {
2051 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_TRANS_MOD
, FALSE
, sizeof (TransMode
), &TransMode
);
2052 if (EFI_ERROR (Status
)) {
2056 Cmd
= (UINT16
)LShiftU64(Packet
->SdMmcCmdBlk
->CommandIndex
, 8);
2057 if (Packet
->SdMmcCmdBlk
->CommandType
== SdMmcCommandTypeAdtc
) {
2061 // Convert ResponseType to value
2063 if (Packet
->SdMmcCmdBlk
->CommandType
!= SdMmcCommandTypeBc
) {
2064 switch (Packet
->SdMmcCmdBlk
->ResponseType
) {
2065 case SdMmcResponseTypeR1
:
2066 case SdMmcResponseTypeR5
:
2067 case SdMmcResponseTypeR6
:
2068 case SdMmcResponseTypeR7
:
2069 Cmd
|= (BIT1
| BIT3
| BIT4
);
2071 case SdMmcResponseTypeR2
:
2072 Cmd
|= (BIT0
| BIT3
);
2074 case SdMmcResponseTypeR3
:
2075 case SdMmcResponseTypeR4
:
2078 case SdMmcResponseTypeR1b
:
2079 case SdMmcResponseTypeR5b
:
2080 Cmd
|= (BIT0
| BIT1
| BIT3
| BIT4
);
2090 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_COMMAND
, FALSE
, sizeof (Cmd
), &Cmd
);
2095 Check the TRB execution result.
2097 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2098 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2100 @retval EFI_SUCCESS The TRB is executed successfully.
2101 @retval EFI_NOT_READY The TRB is not completed for execution.
2102 @retval Others Some erros happen when executing this request.
2106 SdMmcCheckTrbResult (
2107 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2108 IN SD_MMC_HC_TRB
*Trb
2112 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
2121 Packet
= Trb
->Packet
;
2123 // Check Trb execution result by reading Normal Interrupt Status register.
2125 Status
= SdMmcHcRwMmio (
2128 SD_MMC_HC_NOR_INT_STS
,
2133 if (EFI_ERROR (Status
)) {
2137 // Check Transfer Complete bit is set or not.
2139 if ((IntStatus
& BIT1
) == BIT1
) {
2140 if ((IntStatus
& BIT15
) == BIT15
) {
2142 // Read Error Interrupt Status register to check if the error is
2143 // Data Timeout Error.
2144 // If yes, treat it as success as Transfer Complete has higher
2145 // priority than Data Timeout Error.
2147 Status
= SdMmcHcRwMmio (
2150 SD_MMC_HC_ERR_INT_STS
,
2155 if (!EFI_ERROR (Status
)) {
2156 if ((IntStatus
& BIT4
) == BIT4
) {
2157 Status
= EFI_SUCCESS
;
2159 Status
= EFI_DEVICE_ERROR
;
2167 // Check if there is a error happened during cmd execution.
2168 // If yes, then do error recovery procedure to follow SD Host Controller
2169 // Simplified Spec 3.0 section 3.10.1.
2171 if ((IntStatus
& BIT15
) == BIT15
) {
2172 Status
= SdMmcHcRwMmio (
2175 SD_MMC_HC_ERR_INT_STS
,
2180 if (EFI_ERROR (Status
)) {
2183 if ((IntStatus
& 0x0F) != 0) {
2186 if ((IntStatus
& 0xF0) != 0) {
2190 Status
= SdMmcHcRwMmio (
2198 if (EFI_ERROR (Status
)) {
2201 Status
= SdMmcHcWaitMmioSet (
2208 SD_MMC_HC_GENERIC_TIMEOUT
2210 if (EFI_ERROR (Status
)) {
2214 Status
= EFI_DEVICE_ERROR
;
2218 // Check if DMA interrupt is signalled for the SDMA transfer.
2220 if ((Trb
->Mode
== SdMmcSdmaMode
) && ((IntStatus
& BIT3
) == BIT3
)) {
2222 // Clear DMA interrupt bit.
2225 Status
= SdMmcHcRwMmio (
2228 SD_MMC_HC_NOR_INT_STS
,
2233 if (EFI_ERROR (Status
)) {
2237 // Update SDMA Address register.
2239 SdmaAddr
= SD_MMC_SDMA_ROUND_UP ((UINTN
)Trb
->DataPhy
, SD_MMC_SDMA_BOUNDARY
);
2241 if (Private
->ControllerVersion
[Trb
->Slot
] >= SD_MMC_HC_CTRL_VER_400
) {
2242 Status
= SdMmcHcRwMmio (
2245 SD_MMC_HC_ADMA_SYS_ADDR
,
2251 Status
= SdMmcHcRwMmio (
2254 SD_MMC_HC_SDMA_ADDR
,
2261 if (EFI_ERROR (Status
)) {
2264 Trb
->DataPhy
= (UINT64
)(UINTN
)SdmaAddr
;
2267 if ((Packet
->SdMmcCmdBlk
->CommandType
!= SdMmcCommandTypeAdtc
) &&
2268 (Packet
->SdMmcCmdBlk
->ResponseType
!= SdMmcResponseTypeR1b
) &&
2269 (Packet
->SdMmcCmdBlk
->ResponseType
!= SdMmcResponseTypeR5b
)) {
2270 if ((IntStatus
& BIT0
) == BIT0
) {
2271 Status
= EFI_SUCCESS
;
2276 if (((Private
->Slot
[Trb
->Slot
].CardType
== EmmcCardType
) &&
2277 (Packet
->SdMmcCmdBlk
->CommandIndex
== EMMC_SEND_TUNING_BLOCK
)) ||
2278 ((Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) &&
2279 (Packet
->SdMmcCmdBlk
->CommandIndex
== SD_SEND_TUNING_BLOCK
))) {
2281 // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,
2282 // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.
2283 // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.
2285 if ((IntStatus
& BIT5
) == BIT5
) {
2287 // Clear Buffer Read Ready interrupt at first.
2290 SdMmcHcRwMmio (Private
->PciIo
, Trb
->Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (IntStatus
), &IntStatus
);
2292 // Read data out from Buffer Port register
2294 for (PioLength
= 0; PioLength
< Trb
->DataLen
; PioLength
+= 4) {
2295 SdMmcHcRwMmio (Private
->PciIo
, Trb
->Slot
, SD_MMC_HC_BUF_DAT_PORT
, TRUE
, 4, (UINT8
*)Trb
->Data
+ PioLength
);
2297 Status
= EFI_SUCCESS
;
2302 Status
= EFI_NOT_READY
;
2305 // Get response data when the cmd is executed successfully.
2307 if (!EFI_ERROR (Status
)) {
2308 if (Packet
->SdMmcCmdBlk
->CommandType
!= SdMmcCommandTypeBc
) {
2309 for (Index
= 0; Index
< 4; Index
++) {
2310 Status
= SdMmcHcRwMmio (
2313 SD_MMC_HC_RESPONSE
+ Index
* 4,
2318 if (EFI_ERROR (Status
)) {
2319 SdMmcHcLedOnOff (Private
->PciIo
, Trb
->Slot
, FALSE
);
2323 CopyMem (Packet
->SdMmcStatusBlk
, Response
, sizeof (Response
));
2327 if (Status
!= EFI_NOT_READY
) {
2328 SdMmcHcLedOnOff (Private
->PciIo
, Trb
->Slot
, FALSE
);
2335 Wait for the TRB execution result.
2337 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2338 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2340 @retval EFI_SUCCESS The TRB is executed successfully.
2341 @retval Others Some erros happen when executing this request.
2345 SdMmcWaitTrbResult (
2346 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2347 IN SD_MMC_HC_TRB
*Trb
2351 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
2353 BOOLEAN InfiniteWait
;
2355 Packet
= Trb
->Packet
;
2357 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
2359 Timeout
= Packet
->Timeout
;
2361 InfiniteWait
= TRUE
;
2363 InfiniteWait
= FALSE
;
2366 while (InfiniteWait
|| (Timeout
> 0)) {
2368 // Check Trb execution result by reading Normal Interrupt Status register.
2370 Status
= SdMmcCheckTrbResult (Private
, Trb
);
2371 if (Status
!= EFI_NOT_READY
) {
2375 // Stall for 1 microsecond.