2 This driver is used to manage SD/MMC PCI host controllers which are compliance
3 with SD Host Controller Simplified Specification version 3.00 plus the 64-bit
4 System Addressing support in SD Host Controller Simplified Specification version
7 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
9 Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
10 Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.<BR>
11 SPDX-License-Identifier: BSD-2-Clause-Patent
15 #include "SdMmcPciHcDxe.h"
18 Dump the content of SD/MMC host controller's Capability Register.
20 @param[in] Slot The slot number of the SD card to send the command to.
21 @param[in] Capability The buffer to store the capability data.
27 IN SD_MMC_HC_SLOT_CAP
*Capability
31 // Dump Capability Data
33 DEBUG ((DEBUG_INFO
, " == Slot [%d] Capability is 0x%x ==\n", Slot
, Capability
));
34 DEBUG ((DEBUG_INFO
, " Timeout Clk Freq %d%a\n", Capability
->TimeoutFreq
, (Capability
->TimeoutUnit
) ? "MHz" : "KHz"));
35 DEBUG ((DEBUG_INFO
, " Base Clk Freq %dMHz\n", Capability
->BaseClkFreq
));
36 DEBUG ((DEBUG_INFO
, " Max Blk Len %dbytes\n", 512 * (1 << Capability
->MaxBlkLen
)));
37 DEBUG ((DEBUG_INFO
, " 8-bit Support %a\n", Capability
->BusWidth8
? "TRUE" : "FALSE"));
38 DEBUG ((DEBUG_INFO
, " ADMA2 Support %a\n", Capability
->Adma2
? "TRUE" : "FALSE"));
39 DEBUG ((DEBUG_INFO
, " HighSpeed Support %a\n", Capability
->HighSpeed
? "TRUE" : "FALSE"));
40 DEBUG ((DEBUG_INFO
, " SDMA Support %a\n", Capability
->Sdma
? "TRUE" : "FALSE"));
41 DEBUG ((DEBUG_INFO
, " Suspend/Resume %a\n", Capability
->SuspRes
? "TRUE" : "FALSE"));
42 DEBUG ((DEBUG_INFO
, " Voltage 3.3 %a\n", Capability
->Voltage33
? "TRUE" : "FALSE"));
43 DEBUG ((DEBUG_INFO
, " Voltage 3.0 %a\n", Capability
->Voltage30
? "TRUE" : "FALSE"));
44 DEBUG ((DEBUG_INFO
, " Voltage 1.8 %a\n", Capability
->Voltage18
? "TRUE" : "FALSE"));
45 DEBUG ((DEBUG_INFO
, " V4 64-bit Sys Bus %a\n", Capability
->SysBus64V4
? "TRUE" : "FALSE"));
46 DEBUG ((DEBUG_INFO
, " V3 64-bit Sys Bus %a\n", Capability
->SysBus64V3
? "TRUE" : "FALSE"));
47 DEBUG ((DEBUG_INFO
, " Async Interrupt %a\n", Capability
->AsyncInt
? "TRUE" : "FALSE"));
48 DEBUG ((DEBUG_INFO
, " SlotType "));
49 if (Capability
->SlotType
== 0x00) {
50 DEBUG ((DEBUG_INFO
, "%a\n", "Removable Slot"));
51 } else if (Capability
->SlotType
== 0x01) {
52 DEBUG ((DEBUG_INFO
, "%a\n", "Embedded Slot"));
53 } else if (Capability
->SlotType
== 0x02) {
54 DEBUG ((DEBUG_INFO
, "%a\n", "Shared Bus Slot"));
56 DEBUG ((DEBUG_INFO
, "%a\n", "Reserved"));
58 DEBUG ((DEBUG_INFO
, " SDR50 Support %a\n", Capability
->Sdr50
? "TRUE" : "FALSE"));
59 DEBUG ((DEBUG_INFO
, " SDR104 Support %a\n", Capability
->Sdr104
? "TRUE" : "FALSE"));
60 DEBUG ((DEBUG_INFO
, " DDR50 Support %a\n", Capability
->Ddr50
? "TRUE" : "FALSE"));
61 DEBUG ((DEBUG_INFO
, " Driver Type A %a\n", Capability
->DriverTypeA
? "TRUE" : "FALSE"));
62 DEBUG ((DEBUG_INFO
, " Driver Type C %a\n", Capability
->DriverTypeC
? "TRUE" : "FALSE"));
63 DEBUG ((DEBUG_INFO
, " Driver Type D %a\n", Capability
->DriverTypeD
? "TRUE" : "FALSE"));
64 DEBUG ((DEBUG_INFO
, " Driver Type 4 %a\n", Capability
->DriverType4
? "TRUE" : "FALSE"));
65 if (Capability
->TimerCount
== 0) {
66 DEBUG ((DEBUG_INFO
, " Retuning TimerCnt Disabled\n", 2 * (Capability
->TimerCount
- 1)));
68 DEBUG ((DEBUG_INFO
, " Retuning TimerCnt %dseconds\n", 2 * (Capability
->TimerCount
- 1)));
70 DEBUG ((DEBUG_INFO
, " SDR50 Tuning %a\n", Capability
->TuningSDR50
? "TRUE" : "FALSE"));
71 DEBUG ((DEBUG_INFO
, " Retuning Mode Mode %d\n", Capability
->RetuningMod
+ 1));
72 DEBUG ((DEBUG_INFO
, " Clock Multiplier M = %d\n", Capability
->ClkMultiplier
+ 1));
73 DEBUG ((DEBUG_INFO
, " HS 400 %a\n", Capability
->Hs400
? "TRUE" : "FALSE"));
78 Read SlotInfo register from SD/MMC host controller pci config space.
80 @param[in] PciIo The PCI IO protocol instance.
81 @param[out] FirstBar The buffer to store the first BAR value.
82 @param[out] SlotNum The buffer to store the supported slot number.
84 @retval EFI_SUCCESS The operation succeeds.
85 @retval Others The operation fails.
91 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
97 SD_MMC_HC_SLOT_INFO SlotInfo
;
99 Status
= PciIo
->Pci
.Read (
102 SD_MMC_HC_SLOT_OFFSET
,
106 if (EFI_ERROR (Status
)) {
110 *FirstBar
= SlotInfo
.FirstBar
;
111 *SlotNum
= SlotInfo
.SlotNum
+ 1;
112 ASSERT ((*FirstBar
+ *SlotNum
) < SD_MMC_HC_MAX_SLOT
);
117 Read/Write specified SD/MMC host controller mmio register.
119 @param[in] PciIo The PCI IO protocol instance.
120 @param[in] BarIndex The BAR index of the standard PCI Configuration
121 header to use as the base address for the memory
122 operation to perform.
123 @param[in] Offset The offset within the selected BAR to start the
125 @param[in] Read A boolean to indicate it's read or write operation.
126 @param[in] Count The width of the mmio register in bytes.
127 Must be 1, 2 , 4 or 8 bytes.
128 @param[in, out] Data For read operations, the destination buffer to store
129 the results. For write operations, the source buffer
130 to write data from. The caller is responsible for
131 having ownership of the data buffer and ensuring its
132 size not less than Count bytes.
134 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
135 @retval EFI_SUCCESS The read/write operation succeeds.
136 @retval Others The read/write operation fails.
142 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
151 EFI_PCI_IO_PROTOCOL_WIDTH Width
;
153 if ((PciIo
== NULL
) || (Data
== NULL
)) {
154 return EFI_INVALID_PARAMETER
;
159 Width
= EfiPciIoWidthUint8
;
162 Width
= EfiPciIoWidthUint16
;
166 Width
= EfiPciIoWidthUint32
;
170 Width
= EfiPciIoWidthUint32
;
174 return EFI_INVALID_PARAMETER
;
178 Status
= PciIo
->Mem
.Read (
187 Status
= PciIo
->Mem
.Write (
201 Do OR operation with the value of the specified SD/MMC host controller mmio register.
203 @param[in] PciIo The PCI IO protocol instance.
204 @param[in] BarIndex The BAR index of the standard PCI Configuration
205 header to use as the base address for the memory
206 operation to perform.
207 @param[in] Offset The offset within the selected BAR to start the
209 @param[in] Count The width of the mmio register in bytes.
210 Must be 1, 2 , 4 or 8 bytes.
211 @param[in] OrData The pointer to the data used to do OR operation.
212 The caller is responsible for having ownership of
213 the data buffer and ensuring its size not less than
216 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
217 @retval EFI_SUCCESS The OR operation succeeds.
218 @retval Others The OR operation fails.
224 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
235 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Data
);
236 if (EFI_ERROR (Status
)) {
241 Or
= *(UINT8
*) OrData
;
242 } else if (Count
== 2) {
243 Or
= *(UINT16
*) OrData
;
244 } else if (Count
== 4) {
245 Or
= *(UINT32
*) OrData
;
246 } else if (Count
== 8) {
247 Or
= *(UINT64
*) OrData
;
249 return EFI_INVALID_PARAMETER
;
253 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, FALSE
, Count
, &Data
);
259 Do AND operation with the value of the specified SD/MMC host controller mmio register.
261 @param[in] PciIo The PCI IO protocol instance.
262 @param[in] BarIndex The BAR index of the standard PCI Configuration
263 header to use as the base address for the memory
264 operation to perform.
265 @param[in] Offset The offset within the selected BAR to start the
267 @param[in] Count The width of the mmio register in bytes.
268 Must be 1, 2 , 4 or 8 bytes.
269 @param[in] AndData The pointer to the data used to do AND operation.
270 The caller is responsible for having ownership of
271 the data buffer and ensuring its size not less than
274 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
275 @retval EFI_SUCCESS The AND operation succeeds.
276 @retval Others The AND operation fails.
282 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
293 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Data
);
294 if (EFI_ERROR (Status
)) {
299 And
= *(UINT8
*) AndData
;
300 } else if (Count
== 2) {
301 And
= *(UINT16
*) AndData
;
302 } else if (Count
== 4) {
303 And
= *(UINT32
*) AndData
;
304 } else if (Count
== 8) {
305 And
= *(UINT64
*) AndData
;
307 return EFI_INVALID_PARAMETER
;
311 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, FALSE
, Count
, &Data
);
317 Wait for the value of the specified MMIO register set to the test value.
319 @param[in] PciIo The PCI IO protocol instance.
320 @param[in] BarIndex The BAR index of the standard PCI Configuration
321 header to use as the base address for the memory
322 operation to perform.
323 @param[in] Offset The offset within the selected BAR to start the
325 @param[in] Count The width of the mmio register in bytes.
326 Must be 1, 2, 4 or 8 bytes.
327 @param[in] MaskValue The mask value of memory.
328 @param[in] TestValue The test value of memory.
330 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
331 @retval EFI_SUCCESS The MMIO register has expected value.
332 @retval Others The MMIO operation fails.
337 SdMmcHcCheckMmioSet (
338 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
350 // Access PCI MMIO space to see if the value is the tested one.
353 Status
= SdMmcHcRwMmio (PciIo
, BarIndex
, Offset
, TRUE
, Count
, &Value
);
354 if (EFI_ERROR (Status
)) {
360 if (Value
== TestValue
) {
364 return EFI_NOT_READY
;
368 Wait for the value of the specified MMIO register set to the test value.
370 @param[in] PciIo The PCI IO protocol instance.
371 @param[in] BarIndex The BAR index of the standard PCI Configuration
372 header to use as the base address for the memory
373 operation to perform.
374 @param[in] Offset The offset within the selected BAR to start the
376 @param[in] Count The width of the mmio register in bytes.
377 Must be 1, 2, 4 or 8 bytes.
378 @param[in] MaskValue The mask value of memory.
379 @param[in] TestValue The test value of memory.
380 @param[in] Timeout The time out value for wait memory set, uses 1
381 microsecond as a unit.
383 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
385 @retval EFI_SUCCESS The MMIO register has expected value.
386 @retval Others The MMIO operation fails.
392 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
402 BOOLEAN InfiniteWait
;
407 InfiniteWait
= FALSE
;
410 while (InfiniteWait
|| (Timeout
> 0)) {
411 Status
= SdMmcHcCheckMmioSet (
419 if (Status
!= EFI_NOT_READY
) {
424 // Stall for 1 microsecond.
435 Get the controller version information from the specified slot.
437 @param[in] PciIo The PCI IO protocol instance.
438 @param[in] Slot The slot number of the SD card to send the command to.
439 @param[out] Version The buffer to store the version information.
441 @retval EFI_SUCCESS The operation executes successfully.
442 @retval Others The operation fails.
446 SdMmcHcGetControllerVersion (
447 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
454 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CTRL_VER
, TRUE
, sizeof (UINT16
), Version
);
455 if (EFI_ERROR (Status
)) {
465 Software reset the specified SD/MMC host controller and enable all interrupts.
467 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
468 @param[in] Slot The slot number of the SD card to send the command to.
470 @retval EFI_SUCCESS The software reset executes successfully.
471 @retval Others The software reset fails.
476 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
482 EFI_PCI_IO_PROTOCOL
*PciIo
;
485 // Notify the SD/MMC override protocol that we are about to reset
486 // the SD/MMC host controller.
488 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
489 Status
= mOverride
->NotifyPhase (
490 Private
->ControllerHandle
,
494 if (EFI_ERROR (Status
)) {
496 "%a: SD/MMC pre reset notifier callback failed - %r\n",
497 __FUNCTION__
, Status
));
502 PciIo
= Private
->PciIo
;
504 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_SW_RST
, sizeof (SwReset
), &SwReset
);
506 if (EFI_ERROR (Status
)) {
507 DEBUG ((DEBUG_ERROR
, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status
));
511 Status
= SdMmcHcWaitMmioSet (
518 SD_MMC_HC_GENERIC_TIMEOUT
520 if (EFI_ERROR (Status
)) {
521 DEBUG ((DEBUG_INFO
, "SdMmcHcReset: reset done with %r\n", Status
));
526 // Enable all interrupt after reset all.
528 Status
= SdMmcHcEnableInterrupt (PciIo
, Slot
);
529 if (EFI_ERROR (Status
)) {
530 DEBUG ((DEBUG_INFO
, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",
536 // Notify the SD/MMC override protocol that we have just reset
537 // the SD/MMC host controller.
539 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
540 Status
= mOverride
->NotifyPhase (
541 Private
->ControllerHandle
,
545 if (EFI_ERROR (Status
)) {
547 "%a: SD/MMC post reset notifier callback failed - %r\n",
548 __FUNCTION__
, Status
));
556 Set all interrupt status bits in Normal and Error Interrupt Status Enable
559 @param[in] PciIo The PCI IO protocol instance.
560 @param[in] Slot The slot number of the SD card to send the command to.
562 @retval EFI_SUCCESS The operation executes successfully.
563 @retval Others The operation fails.
567 SdMmcHcEnableInterrupt (
568 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
576 // Enable all bits in Error Interrupt Status Enable Register
579 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_ERR_INT_STS_EN
, FALSE
, sizeof (IntStatus
), &IntStatus
);
580 if (EFI_ERROR (Status
)) {
584 // Enable all bits in Normal Interrupt Status Enable Register
587 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS_EN
, FALSE
, sizeof (IntStatus
), &IntStatus
);
593 Get the capability data from the specified slot.
595 @param[in] PciIo The PCI IO protocol instance.
596 @param[in] Slot The slot number of the SD card to send the command to.
597 @param[out] Capability The buffer to store the capability data.
599 @retval EFI_SUCCESS The operation executes successfully.
600 @retval Others The operation fails.
604 SdMmcHcGetCapability (
605 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
607 OUT SD_MMC_HC_SLOT_CAP
*Capability
613 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CAP
, TRUE
, sizeof (Cap
), &Cap
);
614 if (EFI_ERROR (Status
)) {
618 CopyMem (Capability
, &Cap
, sizeof (Cap
));
624 Get the maximum current capability data from the specified slot.
626 @param[in] PciIo The PCI IO protocol instance.
627 @param[in] Slot The slot number of the SD card to send the command to.
628 @param[out] MaxCurrent The buffer to store the maximum current capability data.
630 @retval EFI_SUCCESS The operation executes successfully.
631 @retval Others The operation fails.
635 SdMmcHcGetMaxCurrent (
636 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
638 OUT UINT64
*MaxCurrent
643 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_MAX_CURRENT_CAP
, TRUE
, sizeof (UINT64
), MaxCurrent
);
649 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
652 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
654 @param[in] PciIo The PCI IO protocol instance.
655 @param[in] Slot The slot number of the SD card to send the command to.
656 @param[out] MediaPresent The pointer to the media present boolean value.
658 @retval EFI_SUCCESS There is no media change happened.
659 @retval EFI_MEDIA_CHANGED There is media change happened.
660 @retval Others The detection fails.
665 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
667 OUT BOOLEAN
*MediaPresent
675 // Check Present State Register to see if there is a card presented.
677 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_PRESENT_STATE
, TRUE
, sizeof (PresentState
), &PresentState
);
678 if (EFI_ERROR (Status
)) {
682 if ((PresentState
& BIT16
) != 0) {
683 *MediaPresent
= TRUE
;
685 *MediaPresent
= FALSE
;
689 // Check Normal Interrupt Status Register
691 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS
, TRUE
, sizeof (Data
), &Data
);
692 if (EFI_ERROR (Status
)) {
696 if ((Data
& (BIT6
| BIT7
)) != 0) {
698 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
701 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (Data
), &Data
);
702 if (EFI_ERROR (Status
)) {
706 return EFI_MEDIA_CHANGED
;
713 Stop SD/MMC card clock.
715 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
717 @param[in] PciIo The PCI IO protocol instance.
718 @param[in] Slot The slot number of the SD card to send the command to.
720 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.
721 @retval Others Fail to stop SD/MMC clock.
726 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
735 // Ensure no SD transactions are occurring on the SD Bus by
736 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
737 // in the Present State register to be 0.
739 Status
= SdMmcHcWaitMmioSet (
742 SD_MMC_HC_PRESENT_STATE
,
743 sizeof (PresentState
),
746 SD_MMC_HC_GENERIC_TIMEOUT
748 if (EFI_ERROR (Status
)) {
753 // Set SD Clock Enable in the Clock Control register to 0
755 ClockCtrl
= (UINT16
)~BIT2
;
756 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, sizeof (ClockCtrl
), &ClockCtrl
);
764 @param[in] PciIo The PCI IO protocol instance.
765 @param[in] Slot The slot number.
767 @retval EFI_SUCCESS Succeeded to start the SD clock.
768 @retval Others Failed to start the SD clock.
771 SdMmcHcStartSdClock (
772 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
779 // Set SD Clock Enable in the Clock Control register to 1
782 return SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, sizeof (ClockCtrl
), &ClockCtrl
);
786 SD/MMC card clock supply.
788 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
790 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
791 @param[in] Slot The slot number of the SD card to send the command to.
792 @param[in] BusTiming BusTiming at which the frequency change is done.
793 @param[in] FirstTimeSetup Flag to indicate whether the clock is being setup for the first time.
794 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
796 @retval EFI_SUCCESS The clock is supplied successfully.
797 @retval Others The clock isn't supplied successfully.
802 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
804 IN SD_MMC_BUS_MODE BusTiming
,
805 IN BOOLEAN FirstTimeSetup
,
815 UINT16 ControllerVer
;
816 EFI_PCI_IO_PROTOCOL
*PciIo
;
818 PciIo
= Private
->PciIo
;
819 BaseClkFreq
= Private
->BaseClkFreq
[Slot
];
820 ControllerVer
= Private
->ControllerVersion
[Slot
];
822 if (BaseClkFreq
== 0 || ClockFreq
== 0) {
823 return EFI_INVALID_PARAMETER
;
826 if (ClockFreq
> (BaseClkFreq
* 1000)) {
827 ClockFreq
= BaseClkFreq
* 1000;
831 // Calculate the divisor of base frequency.
834 SettingFreq
= BaseClkFreq
* 1000;
835 while (ClockFreq
< SettingFreq
) {
838 SettingFreq
= (BaseClkFreq
* 1000) / (2 * Divisor
);
839 Remainder
= (BaseClkFreq
* 1000) % (2 * Divisor
);
840 if ((ClockFreq
== SettingFreq
) && (Remainder
== 0)) {
843 if ((ClockFreq
== SettingFreq
) && (Remainder
!= 0)) {
848 DEBUG ((DEBUG_INFO
, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq
, Divisor
, ClockFreq
));
851 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
853 if ((ControllerVer
>= SD_MMC_HC_CTRL_VER_300
) &&
854 (ControllerVer
<= SD_MMC_HC_CTRL_VER_420
)) {
855 ASSERT (Divisor
<= 0x3FF);
856 ClockCtrl
= ((Divisor
& 0xFF) << 8) | ((Divisor
& 0x300) >> 2);
857 } else if ((ControllerVer
== SD_MMC_HC_CTRL_VER_100
) ||
858 (ControllerVer
== SD_MMC_HC_CTRL_VER_200
)) {
860 // Only the most significant bit can be used as divisor.
862 if (((Divisor
- 1) & Divisor
) != 0) {
863 Divisor
= 1 << (HighBitSet32 (Divisor
) + 1);
865 ASSERT (Divisor
<= 0x80);
866 ClockCtrl
= (Divisor
& 0xFF) << 8;
868 DEBUG ((DEBUG_ERROR
, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer
));
869 return EFI_UNSUPPORTED
;
873 // Stop bus clock at first
875 Status
= SdMmcHcStopClock (PciIo
, Slot
);
876 if (EFI_ERROR (Status
)) {
881 // Supply clock frequency with specified divisor
884 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_CLOCK_CTRL
, FALSE
, sizeof (ClockCtrl
), &ClockCtrl
);
885 if (EFI_ERROR (Status
)) {
886 DEBUG ((DEBUG_ERROR
, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
891 // Wait Internal Clock Stable in the Clock Control register to be 1
893 Status
= SdMmcHcWaitMmioSet (
896 SD_MMC_HC_CLOCK_CTRL
,
900 SD_MMC_HC_GENERIC_TIMEOUT
902 if (EFI_ERROR (Status
)) {
906 Status
= SdMmcHcStartSdClock (PciIo
, Slot
);
907 if (EFI_ERROR (Status
)) {
912 // We don't notify the platform on first time setup to avoid changing
913 // legacy behavior. During first time setup we also don't know what type
914 // of the card slot it is and which enum value of BusTiming applies.
916 if (!FirstTimeSetup
&& mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
917 Status
= mOverride
->NotifyPhase (
918 Private
->ControllerHandle
,
920 EdkiiSdMmcSwitchClockFreqPost
,
923 if (EFI_ERROR (Status
)) {
926 "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
934 Private
->Slot
[Slot
].CurrentFreq
= ClockFreq
;
940 SD/MMC bus power control.
942 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
944 @param[in] PciIo The PCI IO protocol instance.
945 @param[in] Slot The slot number of the SD card to send the command to.
946 @param[in] PowerCtrl The value setting to the power control register.
948 @retval TRUE There is a SD/MMC card attached.
949 @retval FALSE There is no a SD/MMC card attached.
953 SdMmcHcPowerControl (
954 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
964 PowerCtrl
&= (UINT8
)~BIT0
;
965 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_POWER_CTRL
, FALSE
, sizeof (PowerCtrl
), &PowerCtrl
);
966 if (EFI_ERROR (Status
)) {
971 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
974 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_POWER_CTRL
, FALSE
, sizeof (PowerCtrl
), &PowerCtrl
);
980 Set the SD/MMC bus width.
982 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
984 @param[in] PciIo The PCI IO protocol instance.
985 @param[in] Slot The slot number of the SD card to send the command to.
986 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
988 @retval EFI_SUCCESS The bus width is set successfully.
989 @retval Others The bus width isn't set successfully.
994 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1002 if (BusWidth
== 1) {
1003 HostCtrl1
= (UINT8
)~(BIT5
| BIT1
);
1004 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1005 } else if (BusWidth
== 4) {
1006 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, TRUE
, sizeof (HostCtrl1
), &HostCtrl1
);
1007 if (EFI_ERROR (Status
)) {
1011 HostCtrl1
&= (UINT8
)~BIT5
;
1012 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, FALSE
, sizeof (HostCtrl1
), &HostCtrl1
);
1013 } else if (BusWidth
== 8) {
1014 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, TRUE
, sizeof (HostCtrl1
), &HostCtrl1
);
1015 if (EFI_ERROR (Status
)) {
1018 HostCtrl1
&= (UINT8
)~BIT1
;
1020 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, FALSE
, sizeof (HostCtrl1
), &HostCtrl1
);
1023 return EFI_INVALID_PARAMETER
;
1030 Configure V4 controller enhancements at initialization.
1032 @param[in] PciIo The PCI IO protocol instance.
1033 @param[in] Slot The slot number of the SD card to send the command to.
1034 @param[in] Capability The capability of the slot.
1035 @param[in] ControllerVer The version of host controller.
1037 @retval EFI_SUCCESS The clock is supplied successfully.
1041 SdMmcHcInitV4Enhancements (
1042 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1044 IN SD_MMC_HC_SLOT_CAP Capability
,
1045 IN UINT16 ControllerVer
1052 // Check if controller version V4 or higher
1054 if (ControllerVer
>= SD_MMC_HC_CTRL_VER_400
) {
1055 HostCtrl2
= SD_MMC_HC_V4_EN
;
1057 // Check if controller version V4.0
1059 if (ControllerVer
== SD_MMC_HC_CTRL_VER_400
) {
1061 // Check if 64bit support is available
1063 if (Capability
.SysBus64V3
!= 0) {
1064 HostCtrl2
|= SD_MMC_HC_64_ADDR_EN
;
1065 DEBUG ((DEBUG_INFO
, "Enabled V4 64 bit system bus support\n"));
1069 // Check if controller version V4.10 or higher
1071 else if (ControllerVer
>= SD_MMC_HC_CTRL_VER_410
) {
1073 // Check if 64bit support is available
1075 if (Capability
.SysBus64V4
!= 0) {
1076 HostCtrl2
|= SD_MMC_HC_64_ADDR_EN
;
1077 DEBUG ((DEBUG_INFO
, "Enabled V4 64 bit system bus support\n"));
1079 HostCtrl2
|= SD_MMC_HC_26_DATA_LEN_ADMA_EN
;
1080 DEBUG ((DEBUG_INFO
, "Enabled V4 26 bit data length ADMA support\n"));
1082 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1083 if (EFI_ERROR (Status
)) {
1092 Supply SD/MMC card with maximum voltage at initialization.
1094 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
1096 @param[in] PciIo The PCI IO protocol instance.
1097 @param[in] Slot The slot number of the SD card to send the command to.
1098 @param[in] Capability The capability of the slot.
1100 @retval EFI_SUCCESS The voltage is supplied successfully.
1101 @retval Others The voltage isn't supplied successfully.
1105 SdMmcHcInitPowerVoltage (
1106 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1108 IN SD_MMC_HC_SLOT_CAP Capability
1116 // Calculate supported maximum voltage according to SD Bus Voltage Select
1118 if (Capability
.Voltage33
!= 0) {
1123 } else if (Capability
.Voltage30
!= 0) {
1128 } else if (Capability
.Voltage18
!= 0) {
1134 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1136 if (EFI_ERROR (Status
)) {
1141 return EFI_DEVICE_ERROR
;
1145 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
1147 Status
= SdMmcHcPowerControl (PciIo
, Slot
, MaxVoltage
);
1153 Initialize the Timeout Control register with most conservative value at initialization.
1155 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
1157 @param[in] PciIo The PCI IO protocol instance.
1158 @param[in] Slot The slot number of the SD card to send the command to.
1160 @retval EFI_SUCCESS The timeout control register is configured successfully.
1161 @retval Others The timeout control register isn't configured successfully.
1165 SdMmcHcInitTimeoutCtrl (
1166 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1174 Status
= SdMmcHcRwMmio (PciIo
, Slot
, SD_MMC_HC_TIMEOUT_CTRL
, FALSE
, sizeof (Timeout
), &Timeout
);
1180 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
1183 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1184 @param[in] Slot The slot number of the SD card to send the command to.
1186 @retval EFI_SUCCESS The host controller is initialized successfully.
1187 @retval Others The host controller isn't initialized successfully.
1192 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1197 EFI_PCI_IO_PROTOCOL
*PciIo
;
1198 SD_MMC_HC_SLOT_CAP Capability
;
1201 // Notify the SD/MMC override protocol that we are about to initialize
1202 // the SD/MMC host controller.
1204 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
1205 Status
= mOverride
->NotifyPhase (
1206 Private
->ControllerHandle
,
1208 EdkiiSdMmcInitHostPre
,
1210 if (EFI_ERROR (Status
)) {
1212 "%a: SD/MMC pre init notifier callback failed - %r\n",
1213 __FUNCTION__
, Status
));
1218 PciIo
= Private
->PciIo
;
1219 Capability
= Private
->Capability
[Slot
];
1221 Status
= SdMmcHcInitV4Enhancements (PciIo
, Slot
, Capability
, Private
->ControllerVersion
[Slot
]);
1222 if (EFI_ERROR (Status
)) {
1227 // Perform first time clock setup with 400 KHz frequency.
1228 // We send the 0 as the BusTiming value because at this time
1229 // we still do not know the slot type and which enum value will apply.
1230 // Since it is a first time setup SdMmcHcClockSupply won't notify
1231 // the platofrm driver anyway so it doesn't matter.
1233 Status
= SdMmcHcClockSupply (Private
, Slot
, 0, TRUE
, 400);
1234 if (EFI_ERROR (Status
)) {
1238 Status
= SdMmcHcInitPowerVoltage (PciIo
, Slot
, Capability
);
1239 if (EFI_ERROR (Status
)) {
1243 Status
= SdMmcHcInitTimeoutCtrl (PciIo
, Slot
);
1244 if (EFI_ERROR (Status
)) {
1249 // Notify the SD/MMC override protocol that we are have just initialized
1250 // the SD/MMC host controller.
1252 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
1253 Status
= mOverride
->NotifyPhase (
1254 Private
->ControllerHandle
,
1256 EdkiiSdMmcInitHostPost
,
1258 if (EFI_ERROR (Status
)) {
1260 "%a: SD/MMC post init notifier callback failed - %r\n",
1261 __FUNCTION__
, Status
));
1268 Set SD Host Controler control 2 registry according to selected speed.
1270 @param[in] ControllerHandle The handle of the controller.
1271 @param[in] PciIo The PCI IO protocol instance.
1272 @param[in] Slot The slot number of the SD card to send the command to.
1273 @param[in] Timing The timing to select.
1275 @retval EFI_SUCCESS The timing is set successfully.
1276 @retval Others The timing isn't set successfully.
1279 SdMmcHcUhsSignaling (
1280 IN EFI_HANDLE ControllerHandle
,
1281 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1283 IN SD_MMC_BUS_MODE Timing
1289 HostCtrl2
= (UINT8
)~SD_MMC_HC_CTRL_UHS_MASK
;
1290 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1291 if (EFI_ERROR (Status
)) {
1297 HostCtrl2
= SD_MMC_HC_CTRL_UHS_SDR12
;
1300 HostCtrl2
= SD_MMC_HC_CTRL_UHS_SDR25
;
1303 HostCtrl2
= SD_MMC_HC_CTRL_UHS_SDR50
;
1305 case SdMmcUhsSdr104
:
1306 HostCtrl2
= SD_MMC_HC_CTRL_UHS_SDR104
;
1309 HostCtrl2
= SD_MMC_HC_CTRL_UHS_DDR50
;
1311 case SdMmcMmcLegacy
:
1312 HostCtrl2
= SD_MMC_HC_CTRL_MMC_LEGACY
;
1315 HostCtrl2
= SD_MMC_HC_CTRL_MMC_HS_SDR
;
1318 HostCtrl2
= SD_MMC_HC_CTRL_MMC_HS_DDR
;
1321 HostCtrl2
= SD_MMC_HC_CTRL_MMC_HS200
;
1324 HostCtrl2
= SD_MMC_HC_CTRL_MMC_HS400
;
1330 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1331 if (EFI_ERROR (Status
)) {
1335 if (mOverride
!= NULL
&& mOverride
->NotifyPhase
!= NULL
) {
1336 Status
= mOverride
->NotifyPhase (
1339 EdkiiSdMmcUhsSignaling
,
1342 if (EFI_ERROR (Status
)) {
1345 "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
1357 Set driver strength in host controller.
1359 @param[in] PciIo The PCI IO protocol instance.
1360 @param[in] SlotIndex The slot index of the card.
1361 @param[in] DriverStrength DriverStrength to set in the controller.
1363 @retval EFI_SUCCESS Driver strength programmed successfully.
1364 @retval Others Failed to set driver strength.
1367 SdMmcSetDriverStrength (
1368 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1370 IN SD_DRIVER_STRENGTH_TYPE DriverStrength
1376 if (DriverStrength
== SdDriverStrengthIgnore
) {
1380 HostCtrl2
= (UINT16
)~SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK
;
1381 Status
= SdMmcHcAndMmio (PciIo
, SlotIndex
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1382 if (EFI_ERROR (Status
)) {
1386 HostCtrl2
= (DriverStrength
<< 4) & SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK
;
1387 return SdMmcHcOrMmio (PciIo
, SlotIndex
, SD_MMC_HC_HOST_CTRL2
, sizeof (HostCtrl2
), &HostCtrl2
);
1393 @param[in] PciIo The PCI IO protocol instance.
1394 @param[in] Slot The slot number of the SD card to send the command to.
1395 @param[in] On The boolean to turn on/off LED.
1397 @retval EFI_SUCCESS The LED is turned on/off successfully.
1398 @retval Others The LED isn't turned on/off successfully.
1403 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
1413 Status
= SdMmcHcOrMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1415 HostCtrl1
= (UINT8
)~BIT0
;
1416 Status
= SdMmcHcAndMmio (PciIo
, Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
1423 Build ADMA descriptor table for transfer.
1425 Refer to SD Host Controller Simplified spec 4.2 Section 1.13 for details.
1427 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1428 @param[in] ControllerVer The version of host controller.
1430 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
1431 @retval Others The ADMA descriptor table isn't created successfully.
1435 BuildAdmaDescTable (
1436 IN SD_MMC_HC_TRB
*Trb
,
1437 IN UINT16 ControllerVer
1440 EFI_PHYSICAL_ADDRESS Data
;
1447 EFI_PCI_IO_PROTOCOL
*PciIo
;
1450 UINT32 AdmaMaxDataPerLine
;
1454 AdmaMaxDataPerLine
= ADMA_MAX_DATA_PER_LINE_16B
;
1455 DescSize
= sizeof (SD_MMC_HC_ADMA_32_DESC_LINE
);
1458 Data
= Trb
->DataPhy
;
1459 DataLen
= Trb
->DataLen
;
1460 PciIo
= Trb
->Private
->PciIo
;
1463 // Check for valid ranges in 32bit ADMA Descriptor Table
1465 if ((Trb
->Mode
== SdMmcAdma32bMode
) &&
1466 ((Data
>= 0x100000000ul
) || ((Data
+ DataLen
) > 0x100000000ul
))) {
1467 return EFI_INVALID_PARAMETER
;
1470 // Check address field alignment
1472 if (Trb
->Mode
!= SdMmcAdma32bMode
) {
1474 // Address field shall be set on 64-bit boundary (Lower 3-bit is always set to 0)
1476 if ((Data
& (BIT0
| BIT1
| BIT2
)) != 0) {
1477 DEBUG ((DEBUG_INFO
, "The buffer [0x%x] to construct ADMA desc is not aligned to 8 bytes boundary!\n", Data
));
1481 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
1483 if ((Data
& (BIT0
| BIT1
)) != 0) {
1484 DEBUG ((DEBUG_INFO
, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data
));
1489 // Configure 64b ADMA.
1491 if (Trb
->Mode
== SdMmcAdma64bV3Mode
) {
1492 DescSize
= sizeof (SD_MMC_HC_ADMA_64_V3_DESC_LINE
);
1493 }else if (Trb
->Mode
== SdMmcAdma64bV4Mode
) {
1494 DescSize
= sizeof (SD_MMC_HC_ADMA_64_V4_DESC_LINE
);
1497 // Configure 26b data length.
1499 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1500 AdmaMaxDataPerLine
= ADMA_MAX_DATA_PER_LINE_26B
;
1503 Entries
= DivU64x32 ((DataLen
+ AdmaMaxDataPerLine
- 1), AdmaMaxDataPerLine
);
1504 TableSize
= (UINTN
)MultU64x32 (Entries
, DescSize
);
1505 Trb
->AdmaPages
= (UINT32
)EFI_SIZE_TO_PAGES (TableSize
);
1506 Status
= PciIo
->AllocateBuffer (
1509 EfiBootServicesData
,
1510 EFI_SIZE_TO_PAGES (TableSize
),
1514 if (EFI_ERROR (Status
)) {
1515 return EFI_OUT_OF_RESOURCES
;
1517 ZeroMem (AdmaDesc
, TableSize
);
1519 Status
= PciIo
->Map (
1521 EfiPciIoOperationBusMasterCommonBuffer
,
1528 if (EFI_ERROR (Status
) || (Bytes
!= TableSize
)) {
1530 // Map error or unable to map the whole RFis buffer into a contiguous region.
1534 EFI_SIZE_TO_PAGES (TableSize
),
1537 return EFI_OUT_OF_RESOURCES
;
1540 if ((Trb
->Mode
== SdMmcAdma32bMode
) &&
1541 (UINT64
)(UINTN
)Trb
->AdmaDescPhy
> 0x100000000ul
) {
1543 // The ADMA doesn't support 64bit addressing.
1549 Trb
->AdmaMap
= NULL
;
1553 EFI_SIZE_TO_PAGES (TableSize
),
1556 return EFI_DEVICE_ERROR
;
1559 Remaining
= DataLen
;
1561 if (Trb
->Mode
== SdMmcAdma32bMode
) {
1562 Trb
->Adma32Desc
= AdmaDesc
;
1563 } else if (Trb
->Mode
== SdMmcAdma64bV3Mode
) {
1564 Trb
->Adma64V3Desc
= AdmaDesc
;
1566 Trb
->Adma64V4Desc
= AdmaDesc
;
1569 for (Index
= 0; Index
< Entries
; Index
++) {
1570 if (Trb
->Mode
== SdMmcAdma32bMode
) {
1571 if (Remaining
<= AdmaMaxDataPerLine
) {
1572 Trb
->Adma32Desc
[Index
].Valid
= 1;
1573 Trb
->Adma32Desc
[Index
].Act
= 2;
1574 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1575 Trb
->Adma32Desc
[Index
].UpperLength
= (UINT16
)RShiftU64 (Remaining
, 16);
1577 Trb
->Adma32Desc
[Index
].LowerLength
= (UINT16
)(Remaining
& MAX_UINT16
);
1578 Trb
->Adma32Desc
[Index
].Address
= (UINT32
)Address
;
1581 Trb
->Adma32Desc
[Index
].Valid
= 1;
1582 Trb
->Adma32Desc
[Index
].Act
= 2;
1583 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1584 Trb
->Adma32Desc
[Index
].UpperLength
= 0;
1586 Trb
->Adma32Desc
[Index
].LowerLength
= 0;
1587 Trb
->Adma32Desc
[Index
].Address
= (UINT32
)Address
;
1589 } else if (Trb
->Mode
== SdMmcAdma64bV3Mode
) {
1590 if (Remaining
<= AdmaMaxDataPerLine
) {
1591 Trb
->Adma64V3Desc
[Index
].Valid
= 1;
1592 Trb
->Adma64V3Desc
[Index
].Act
= 2;
1593 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1594 Trb
->Adma64V3Desc
[Index
].UpperLength
= (UINT16
)RShiftU64 (Remaining
, 16);
1596 Trb
->Adma64V3Desc
[Index
].LowerLength
= (UINT16
)(Remaining
& MAX_UINT16
);
1597 Trb
->Adma64V3Desc
[Index
].LowerAddress
= (UINT32
)Address
;
1598 Trb
->Adma64V3Desc
[Index
].UpperAddress
= (UINT32
)RShiftU64 (Address
, 32);
1601 Trb
->Adma64V3Desc
[Index
].Valid
= 1;
1602 Trb
->Adma64V3Desc
[Index
].Act
= 2;
1603 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1604 Trb
->Adma64V3Desc
[Index
].UpperLength
= 0;
1606 Trb
->Adma64V3Desc
[Index
].LowerLength
= 0;
1607 Trb
->Adma64V3Desc
[Index
].LowerAddress
= (UINT32
)Address
;
1608 Trb
->Adma64V3Desc
[Index
].UpperAddress
= (UINT32
)RShiftU64 (Address
, 32);
1611 if (Remaining
<= AdmaMaxDataPerLine
) {
1612 Trb
->Adma64V4Desc
[Index
].Valid
= 1;
1613 Trb
->Adma64V4Desc
[Index
].Act
= 2;
1614 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1615 Trb
->Adma64V4Desc
[Index
].UpperLength
= (UINT16
)RShiftU64 (Remaining
, 16);
1617 Trb
->Adma64V4Desc
[Index
].LowerLength
= (UINT16
)(Remaining
& MAX_UINT16
);
1618 Trb
->Adma64V4Desc
[Index
].LowerAddress
= (UINT32
)Address
;
1619 Trb
->Adma64V4Desc
[Index
].UpperAddress
= (UINT32
)RShiftU64 (Address
, 32);
1622 Trb
->Adma64V4Desc
[Index
].Valid
= 1;
1623 Trb
->Adma64V4Desc
[Index
].Act
= 2;
1624 if (Trb
->AdmaLengthMode
== SdMmcAdmaLen26b
) {
1625 Trb
->Adma64V4Desc
[Index
].UpperLength
= 0;
1627 Trb
->Adma64V4Desc
[Index
].LowerLength
= 0;
1628 Trb
->Adma64V4Desc
[Index
].LowerAddress
= (UINT32
)Address
;
1629 Trb
->Adma64V4Desc
[Index
].UpperAddress
= (UINT32
)RShiftU64 (Address
, 32);
1633 Remaining
-= AdmaMaxDataPerLine
;
1634 Address
+= AdmaMaxDataPerLine
;
1638 // Set the last descriptor line as end of descriptor table
1640 if (Trb
->Mode
== SdMmcAdma32bMode
) {
1641 Trb
->Adma32Desc
[Index
].End
= 1;
1642 } else if (Trb
->Mode
== SdMmcAdma64bV3Mode
) {
1643 Trb
->Adma64V3Desc
[Index
].End
= 1;
1645 Trb
->Adma64V4Desc
[Index
].End
= 1;
1651 Prints the contents of the command packet to the debug port.
1653 @param[in] DebugLevel Debug level at which the packet should be printed.
1654 @param[in] Packet Pointer to packet to print.
1658 IN UINT32 DebugLevel
,
1659 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
1662 if (Packet
== NULL
) {
1666 DEBUG ((DebugLevel
, "Printing EFI_SD_MMC_PASS_THRU_COMMAND_PACKET\n"));
1667 if (Packet
->SdMmcCmdBlk
!= NULL
) {
1668 DEBUG ((DebugLevel
, "Command index: %d, argument: %X\n", Packet
->SdMmcCmdBlk
->CommandIndex
, Packet
->SdMmcCmdBlk
->CommandArgument
));
1669 DEBUG ((DebugLevel
, "Command type: %d, response type: %d\n", Packet
->SdMmcCmdBlk
->CommandType
, Packet
->SdMmcCmdBlk
->ResponseType
));
1671 if (Packet
->SdMmcStatusBlk
!= NULL
) {
1672 DEBUG ((DebugLevel
, "Response 0: %X, 1: %X, 2: %X, 3: %X\n",
1673 Packet
->SdMmcStatusBlk
->Resp0
,
1674 Packet
->SdMmcStatusBlk
->Resp1
,
1675 Packet
->SdMmcStatusBlk
->Resp2
,
1676 Packet
->SdMmcStatusBlk
->Resp3
1679 DEBUG ((DebugLevel
, "Timeout: %ld\n", Packet
->Timeout
));
1680 DEBUG ((DebugLevel
, "InDataBuffer: %p\n", Packet
->InDataBuffer
));
1681 DEBUG ((DebugLevel
, "OutDataBuffer: %p\n", Packet
->OutDataBuffer
));
1682 DEBUG ((DebugLevel
, "InTransferLength: %d\n", Packet
->InTransferLength
));
1683 DEBUG ((DebugLevel
, "OutTransferLength: %d\n", Packet
->OutTransferLength
));
1684 DEBUG ((DebugLevel
, "TransactionStatus: %r\n", Packet
->TransactionStatus
));
1688 Prints the contents of the TRB to the debug port.
1690 @param[in] DebugLevel Debug level at which the TRB should be printed.
1691 @param[in] Trb Pointer to the TRB structure.
1695 IN UINT32 DebugLevel
,
1696 IN SD_MMC_HC_TRB
*Trb
1703 DEBUG ((DebugLevel
, "Printing SD_MMC_HC_TRB\n"));
1704 DEBUG ((DebugLevel
, "Slot: %d\n", Trb
->Slot
));
1705 DEBUG ((DebugLevel
, "BlockSize: %d\n", Trb
->BlockSize
));
1706 DEBUG ((DebugLevel
, "Data: %p\n", Trb
->Data
));
1707 DEBUG ((DebugLevel
, "DataLen: %d\n", Trb
->DataLen
));
1708 DEBUG ((DebugLevel
, "Read: %d\n", Trb
->Read
));
1709 DEBUG ((DebugLevel
, "DataPhy: %lX\n", Trb
->DataPhy
));
1710 DEBUG ((DebugLevel
, "DataMap: %p\n", Trb
->DataMap
));
1711 DEBUG ((DebugLevel
, "Mode: %d\n", Trb
->Mode
));
1712 DEBUG ((DebugLevel
, "AdmaLengthMode: %d\n", Trb
->AdmaLengthMode
));
1713 DEBUG ((DebugLevel
, "Event: %p\n", Trb
->Event
));
1714 DEBUG ((DebugLevel
, "Started: %d\n", Trb
->Started
));
1715 DEBUG ((DebugLevel
, "CommandComplete: %d\n", Trb
->CommandComplete
));
1716 DEBUG ((DebugLevel
, "Timeout: %ld\n", Trb
->Timeout
));
1717 DEBUG ((DebugLevel
, "Retries: %d\n", Trb
->Retries
));
1718 DEBUG ((DebugLevel
, "PioModeTransferCompleted: %d\n", Trb
->PioModeTransferCompleted
));
1719 DEBUG ((DebugLevel
, "PioBlockIndex: %d\n", Trb
->PioBlockIndex
));
1720 DEBUG ((DebugLevel
, "Adma32Desc: %p\n", Trb
->Adma32Desc
));
1721 DEBUG ((DebugLevel
, "Adma64V3Desc: %p\n", Trb
->Adma64V3Desc
));
1722 DEBUG ((DebugLevel
, "Adma64V4Desc: %p\n", Trb
->Adma64V4Desc
));
1723 DEBUG ((DebugLevel
, "AdmaMap: %p\n", Trb
->AdmaMap
));
1724 DEBUG ((DebugLevel
, "AdmaPages: %X\n", Trb
->AdmaPages
));
1726 SdMmcPrintPacket (DebugLevel
, Trb
->Packet
);
1730 Sets up host memory to allow DMA transfer.
1732 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1733 @param[in] Slot The slot number of the SD card to send the command to.
1734 @param[in] Packet A pointer to the SD command data structure.
1736 @retval EFI_SUCCESS Memory has been mapped for DMA transfer.
1737 @retval Others Memory has not been mapped.
1740 SdMmcSetupMemoryForDmaTransfer (
1741 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1743 IN SD_MMC_HC_TRB
*Trb
1746 EFI_PCI_IO_PROTOCOL_OPERATION Flag
;
1747 EFI_PCI_IO_PROTOCOL
*PciIo
;
1752 Flag
= EfiPciIoOperationBusMasterWrite
;
1754 Flag
= EfiPciIoOperationBusMasterRead
;
1757 PciIo
= Private
->PciIo
;
1758 if (Trb
->Data
!= NULL
&& Trb
->DataLen
!= 0) {
1759 MapLength
= Trb
->DataLen
;
1760 Status
= PciIo
->Map (
1768 if (EFI_ERROR (Status
) || (Trb
->DataLen
!= MapLength
)) {
1769 return EFI_BAD_BUFFER_SIZE
;
1773 if (Trb
->Mode
== SdMmcAdma32bMode
||
1774 Trb
->Mode
== SdMmcAdma64bV3Mode
||
1775 Trb
->Mode
== SdMmcAdma64bV4Mode
) {
1776 Status
= BuildAdmaDescTable (Trb
, Private
->ControllerVersion
[Slot
]);
1777 if (EFI_ERROR (Status
)) {
1786 Create a new TRB for the SD/MMC cmd request.
1788 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1789 @param[in] Slot The slot number of the SD card to send the command to.
1790 @param[in] Packet A pointer to the SD command data structure.
1791 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
1792 not NULL, then nonblocking I/O is performed, and Event
1793 will be signaled when the Packet completes.
1795 @return Created Trb or NULL.
1800 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1802 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
,
1810 Trb
= AllocateZeroPool (sizeof (SD_MMC_HC_TRB
));
1815 Trb
->Signature
= SD_MMC_HC_TRB_SIG
;
1817 Trb
->BlockSize
= 0x200;
1818 Trb
->Packet
= Packet
;
1820 Trb
->Started
= FALSE
;
1821 Trb
->CommandComplete
= FALSE
;
1822 Trb
->Timeout
= Packet
->Timeout
;
1823 Trb
->Retries
= SD_MMC_TRB_RETRIES
;
1824 Trb
->PioModeTransferCompleted
= FALSE
;
1825 Trb
->PioBlockIndex
= 0;
1826 Trb
->Private
= Private
;
1828 if ((Packet
->InTransferLength
!= 0) && (Packet
->InDataBuffer
!= NULL
)) {
1829 Trb
->Data
= Packet
->InDataBuffer
;
1830 Trb
->DataLen
= Packet
->InTransferLength
;
1832 } else if ((Packet
->OutTransferLength
!= 0) && (Packet
->OutDataBuffer
!= NULL
)) {
1833 Trb
->Data
= Packet
->OutDataBuffer
;
1834 Trb
->DataLen
= Packet
->OutTransferLength
;
1836 } else if ((Packet
->InTransferLength
== 0) && (Packet
->OutTransferLength
== 0)) {
1843 if ((Trb
->DataLen
!= 0) && (Trb
->DataLen
< Trb
->BlockSize
)) {
1844 Trb
->BlockSize
= (UINT16
)Trb
->DataLen
;
1847 if (((Private
->Slot
[Trb
->Slot
].CardType
== EmmcCardType
) &&
1848 (Packet
->SdMmcCmdBlk
->CommandIndex
== EMMC_SEND_TUNING_BLOCK
)) ||
1849 ((Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) &&
1850 (Packet
->SdMmcCmdBlk
->CommandIndex
== SD_SEND_TUNING_BLOCK
))) {
1851 Trb
->Mode
= SdMmcPioMode
;
1853 if (Trb
->DataLen
== 0) {
1854 Trb
->Mode
= SdMmcNoData
;
1855 } else if (Private
->Capability
[Slot
].Adma2
!= 0) {
1856 Trb
->Mode
= SdMmcAdma32bMode
;
1857 Trb
->AdmaLengthMode
= SdMmcAdmaLen16b
;
1858 if ((Private
->ControllerVersion
[Slot
] == SD_MMC_HC_CTRL_VER_300
) &&
1859 (Private
->Capability
[Slot
].SysBus64V3
== 1)) {
1860 Trb
->Mode
= SdMmcAdma64bV3Mode
;
1861 } else if (((Private
->ControllerVersion
[Slot
] == SD_MMC_HC_CTRL_VER_400
) &&
1862 (Private
->Capability
[Slot
].SysBus64V3
== 1)) ||
1863 ((Private
->ControllerVersion
[Slot
] >= SD_MMC_HC_CTRL_VER_410
) &&
1864 (Private
->Capability
[Slot
].SysBus64V4
== 1))) {
1865 Trb
->Mode
= SdMmcAdma64bV4Mode
;
1867 if (Private
->ControllerVersion
[Slot
] >= SD_MMC_HC_CTRL_VER_410
) {
1868 Trb
->AdmaLengthMode
= SdMmcAdmaLen26b
;
1870 Status
= SdMmcSetupMemoryForDmaTransfer (Private
, Slot
, Trb
);
1871 if (EFI_ERROR (Status
)) {
1874 } else if (Private
->Capability
[Slot
].Sdma
!= 0) {
1875 Trb
->Mode
= SdMmcSdmaMode
;
1876 Status
= SdMmcSetupMemoryForDmaTransfer (Private
, Slot
, Trb
);
1877 if (EFI_ERROR (Status
)) {
1881 Trb
->Mode
= SdMmcPioMode
;
1885 if (Event
!= NULL
) {
1886 OldTpl
= gBS
->RaiseTPL (TPL_NOTIFY
);
1887 InsertTailList (&Private
->Queue
, &Trb
->TrbList
);
1888 gBS
->RestoreTPL (OldTpl
);
1899 Free the resource used by the TRB.
1901 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1906 IN SD_MMC_HC_TRB
*Trb
1909 EFI_PCI_IO_PROTOCOL
*PciIo
;
1911 PciIo
= Trb
->Private
->PciIo
;
1913 if (Trb
->AdmaMap
!= NULL
) {
1919 if (Trb
->Adma32Desc
!= NULL
) {
1926 if (Trb
->Adma64V3Desc
!= NULL
) {
1933 if (Trb
->Adma64V4Desc
!= NULL
) {
1940 if (Trb
->DataMap
!= NULL
) {
1951 Check if the env is ready for execute specified TRB.
1953 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1954 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1956 @retval EFI_SUCCESS The env is ready for TRB execution.
1957 @retval EFI_NOT_READY The env is not ready for TRB execution.
1958 @retval Others Some erros happen.
1963 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
1964 IN SD_MMC_HC_TRB
*Trb
1968 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
1969 EFI_PCI_IO_PROTOCOL
*PciIo
;
1970 UINT32 PresentState
;
1972 Packet
= Trb
->Packet
;
1974 if ((Packet
->SdMmcCmdBlk
->CommandType
== SdMmcCommandTypeAdtc
) ||
1975 (Packet
->SdMmcCmdBlk
->ResponseType
== SdMmcResponseTypeR1b
) ||
1976 (Packet
->SdMmcCmdBlk
->ResponseType
== SdMmcResponseTypeR5b
)) {
1978 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1979 // the Present State register to be 0
1981 PresentState
= BIT0
| BIT1
;
1984 // Wait Command Inhibit (CMD) in the Present State register
1987 PresentState
= BIT0
;
1990 PciIo
= Private
->PciIo
;
1991 Status
= SdMmcHcCheckMmioSet (
1994 SD_MMC_HC_PRESENT_STATE
,
1995 sizeof (PresentState
),
2004 Wait for the env to be ready for execute specified TRB.
2006 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2007 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2009 @retval EFI_SUCCESS The env is ready for TRB execution.
2010 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
2011 @retval Others Some erros happen.
2016 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2017 IN SD_MMC_HC_TRB
*Trb
2021 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
2023 BOOLEAN InfiniteWait
;
2026 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
2028 Packet
= Trb
->Packet
;
2029 Timeout
= Packet
->Timeout
;
2031 InfiniteWait
= TRUE
;
2033 InfiniteWait
= FALSE
;
2036 while (InfiniteWait
|| (Timeout
> 0)) {
2038 // Check Trb execution result by reading Normal Interrupt Status register.
2040 Status
= SdMmcCheckTrbEnv (Private
, Trb
);
2041 if (Status
!= EFI_NOT_READY
) {
2045 // Stall for 1 microsecond.
2056 Execute the specified TRB.
2058 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2059 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2061 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
2062 @retval Others Some erros happen when sending this request to the host controller.
2067 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2068 IN SD_MMC_HC_TRB
*Trb
2072 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
2073 EFI_PCI_IO_PROTOCOL
*PciIo
;
2083 BOOLEAN AddressingMode64
;
2085 AddressingMode64
= FALSE
;
2087 Packet
= Trb
->Packet
;
2088 PciIo
= Trb
->Private
->PciIo
;
2090 // Clear all bits in Error Interrupt Status Register
2093 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ERR_INT_STS
, FALSE
, sizeof (IntStatus
), &IntStatus
);
2094 if (EFI_ERROR (Status
)) {
2098 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
2101 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (IntStatus
), &IntStatus
);
2102 if (EFI_ERROR (Status
)) {
2106 if (Private
->ControllerVersion
[Trb
->Slot
] >= SD_MMC_HC_CTRL_VER_400
) {
2107 Status
= SdMmcHcCheckMmioSet(PciIo
, Trb
->Slot
, SD_MMC_HC_HOST_CTRL2
, sizeof(UINT16
),
2108 SD_MMC_HC_64_ADDR_EN
, SD_MMC_HC_64_ADDR_EN
);
2109 if (!EFI_ERROR (Status
)) {
2110 AddressingMode64
= TRUE
;
2115 // Set Host Control 1 register DMA Select field
2117 if ((Trb
->Mode
== SdMmcAdma32bMode
) ||
2118 (Trb
->Mode
== SdMmcAdma64bV4Mode
)) {
2120 Status
= SdMmcHcOrMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
2121 if (EFI_ERROR (Status
)) {
2124 } else if (Trb
->Mode
== SdMmcAdma64bV3Mode
) {
2125 HostCtrl1
= BIT4
|BIT3
;
2126 Status
= SdMmcHcOrMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_HOST_CTRL1
, sizeof (HostCtrl1
), &HostCtrl1
);
2127 if (EFI_ERROR (Status
)) {
2132 SdMmcHcLedOnOff (PciIo
, Trb
->Slot
, TRUE
);
2134 if (Trb
->Mode
== SdMmcSdmaMode
) {
2135 if ((!AddressingMode64
) &&
2136 ((UINT64
)(UINTN
)Trb
->DataPhy
>= 0x100000000ul
)) {
2137 return EFI_INVALID_PARAMETER
;
2140 SdmaAddr
= (UINT64
)(UINTN
)Trb
->DataPhy
;
2142 if (Private
->ControllerVersion
[Trb
->Slot
] >= SD_MMC_HC_CTRL_VER_400
) {
2143 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ADMA_SYS_ADDR
, FALSE
, sizeof (UINT64
), &SdmaAddr
);
2145 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_SDMA_ADDR
, FALSE
, sizeof (UINT32
), &SdmaAddr
);
2148 if (EFI_ERROR (Status
)) {
2151 } else if ((Trb
->Mode
== SdMmcAdma32bMode
) ||
2152 (Trb
->Mode
== SdMmcAdma64bV3Mode
) ||
2153 (Trb
->Mode
== SdMmcAdma64bV4Mode
)) {
2154 AdmaAddr
= (UINT64
)(UINTN
)Trb
->AdmaDescPhy
;
2155 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ADMA_SYS_ADDR
, FALSE
, sizeof (AdmaAddr
), &AdmaAddr
);
2156 if (EFI_ERROR (Status
)) {
2161 BlkSize
= Trb
->BlockSize
;
2162 if (Trb
->Mode
== SdMmcSdmaMode
) {
2164 // Set SDMA boundary to be 512K bytes.
2169 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_BLK_SIZE
, FALSE
, sizeof (BlkSize
), &BlkSize
);
2170 if (EFI_ERROR (Status
)) {
2175 if (Trb
->Mode
!= SdMmcNoData
) {
2177 // Calcuate Block Count.
2179 BlkCount
= (Trb
->DataLen
/ Trb
->BlockSize
);
2181 if (Private
->ControllerVersion
[Trb
->Slot
] >= SD_MMC_HC_CTRL_VER_410
) {
2182 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_SDMA_ADDR
, FALSE
, sizeof (UINT32
), &BlkCount
);
2184 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_BLK_COUNT
, FALSE
, sizeof (UINT16
), &BlkCount
);
2186 if (EFI_ERROR (Status
)) {
2190 Argument
= Packet
->SdMmcCmdBlk
->CommandArgument
;
2191 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_ARG1
, FALSE
, sizeof (Argument
), &Argument
);
2192 if (EFI_ERROR (Status
)) {
2197 if (Trb
->Mode
!= SdMmcNoData
) {
2198 if (Trb
->Mode
!= SdMmcPioMode
) {
2205 TransMode
|= BIT5
| BIT1
;
2208 // Only SD memory card needs to use AUTO CMD12 feature.
2210 if (Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) {
2217 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_TRANS_MOD
, FALSE
, sizeof (TransMode
), &TransMode
);
2218 if (EFI_ERROR (Status
)) {
2222 Cmd
= (UINT16
)LShiftU64(Packet
->SdMmcCmdBlk
->CommandIndex
, 8);
2223 if (Packet
->SdMmcCmdBlk
->CommandType
== SdMmcCommandTypeAdtc
) {
2227 // Convert ResponseType to value
2229 if (Packet
->SdMmcCmdBlk
->CommandType
!= SdMmcCommandTypeBc
) {
2230 switch (Packet
->SdMmcCmdBlk
->ResponseType
) {
2231 case SdMmcResponseTypeR1
:
2232 case SdMmcResponseTypeR5
:
2233 case SdMmcResponseTypeR6
:
2234 case SdMmcResponseTypeR7
:
2235 Cmd
|= (BIT1
| BIT3
| BIT4
);
2237 case SdMmcResponseTypeR2
:
2238 Cmd
|= (BIT0
| BIT3
);
2240 case SdMmcResponseTypeR3
:
2241 case SdMmcResponseTypeR4
:
2244 case SdMmcResponseTypeR1b
:
2245 case SdMmcResponseTypeR5b
:
2246 Cmd
|= (BIT0
| BIT1
| BIT3
| BIT4
);
2256 Status
= SdMmcHcRwMmio (PciIo
, Trb
->Slot
, SD_MMC_HC_COMMAND
, FALSE
, sizeof (Cmd
), &Cmd
);
2261 Performs SW reset based on passed error status mask.
2263 @param[in] Private Pointer to driver private data.
2264 @param[in] Slot Index of the slot to reset.
2265 @param[in] ErrIntStatus Error interrupt status mask.
2267 @retval EFI_SUCCESS Software reset performed successfully.
2268 @retval Other Software reset failed.
2271 SdMmcSoftwareReset (
2272 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2274 IN UINT16 ErrIntStatus
2281 if ((ErrIntStatus
& 0x0F) != 0) {
2284 if ((ErrIntStatus
& 0x70) != 0) {
2288 Status
= SdMmcHcRwMmio (
2296 if (EFI_ERROR (Status
)) {
2300 Status
= SdMmcHcWaitMmioSet (
2307 SD_MMC_HC_GENERIC_TIMEOUT
2309 if (EFI_ERROR (Status
)) {
2317 Checks the error status in error status register
2318 and issues appropriate software reset as described in
2319 SD specification section 3.10.
2321 @param[in] Private Pointer to driver private data.
2322 @param[in] Slot Index of the slot for device.
2323 @param[in] IntStatus Normal interrupt status mask.
2325 @retval EFI_CRC_ERROR CRC error happened during CMD execution.
2326 @retval EFI_SUCCESS No error reported.
2327 @retval Others Some other error happened.
2331 SdMmcCheckAndRecoverErrors (
2332 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2337 UINT16 ErrIntStatus
;
2339 EFI_STATUS ErrorStatus
;
2341 if ((IntStatus
& BIT15
) == 0) {
2345 Status
= SdMmcHcRwMmio (
2348 SD_MMC_HC_ERR_INT_STS
,
2350 sizeof (ErrIntStatus
),
2353 if (EFI_ERROR (Status
)) {
2357 DEBUG ((DEBUG_ERROR
, "Error reported by SDHCI\n"));
2358 DEBUG ((DEBUG_ERROR
, "Interrupt status = %X\n", IntStatus
));
2359 DEBUG ((DEBUG_ERROR
, "Error interrupt status = %X\n", ErrIntStatus
));
2362 // If the data timeout error is reported
2363 // but data transfer is signaled as completed we
2364 // have to ignore data timeout. We also assume that no
2365 // other error is present on the link since data transfer
2366 // completed successfully. Error interrupt status
2367 // register is going to be reset when the next command
2370 if (((ErrIntStatus
& BIT4
) != 0) && ((IntStatus
& BIT1
) != 0)) {
2375 // We treat both CMD and DAT CRC errors and
2376 // end bits errors as EFI_CRC_ERROR. This will
2377 // let higher layer know that the error possibly
2378 // happened due to random bus condition and the
2379 // command can be retried.
2381 if ((ErrIntStatus
& (BIT1
| BIT2
| BIT5
| BIT6
)) != 0) {
2382 ErrorStatus
= EFI_CRC_ERROR
;
2384 ErrorStatus
= EFI_DEVICE_ERROR
;
2387 Status
= SdMmcSoftwareReset (Private
, Slot
, ErrIntStatus
);
2388 if (EFI_ERROR (Status
)) {
2396 Reads the response data into the TRB buffer.
2397 This function assumes that caller made sure that
2398 command has completed.
2400 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2401 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2403 @retval EFI_SUCCESS Response read successfully.
2404 @retval Others Failed to get response.
2408 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2409 IN SD_MMC_HC_TRB
*Trb
2412 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
2417 Packet
= Trb
->Packet
;
2419 if (Packet
->SdMmcCmdBlk
->CommandType
== SdMmcCommandTypeBc
) {
2423 for (Index
= 0; Index
< 4; Index
++) {
2424 Status
= SdMmcHcRwMmio (
2427 SD_MMC_HC_RESPONSE
+ Index
* 4,
2432 if (EFI_ERROR (Status
)) {
2436 CopyMem (Packet
->SdMmcStatusBlk
, Response
, sizeof (Response
));
2442 Checks if the command completed. If the command
2443 completed it gets the response and records the
2444 command completion in the TRB.
2446 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2447 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2448 @param[in] IntStatus Snapshot of the normal interrupt status register.
2450 @retval EFI_SUCCESS Command completed successfully.
2451 @retval EFI_NOT_READY Command completion still pending.
2452 @retval Others Command failed to complete.
2455 SdMmcCheckCommandComplete (
2456 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2457 IN SD_MMC_HC_TRB
*Trb
,
2464 if ((IntStatus
& BIT0
) != 0) {
2466 Status
= SdMmcHcRwMmio (
2469 SD_MMC_HC_NOR_INT_STS
,
2474 if (EFI_ERROR (Status
)) {
2477 Status
= SdMmcGetResponse (Private
, Trb
);
2478 if (EFI_ERROR (Status
)) {
2481 Trb
->CommandComplete
= TRUE
;
2485 return EFI_NOT_READY
;
2489 Transfers data from card using PIO method.
2491 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2492 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2493 @param[in] IntStatus Snapshot of the normal interrupt status register.
2495 @retval EFI_SUCCESS PIO transfer completed successfully.
2496 @retval EFI_NOT_READY PIO transfer completion still pending.
2497 @retval Others PIO transfer failed to complete.
2500 SdMmcTransferDataWithPio (
2501 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2502 IN SD_MMC_HC_TRB
*Trb
,
2509 EFI_PCI_IO_PROTOCOL_WIDTH Width
;
2512 BlockCount
= (Trb
->DataLen
/ Trb
->BlockSize
);
2513 if (Trb
->DataLen
% Trb
->BlockSize
!= 0) {
2517 if (Trb
->PioBlockIndex
>= BlockCount
) {
2521 switch (Trb
->BlockSize
% sizeof (UINT32
)) {
2523 Width
= EfiPciIoWidthFifoUint32
;
2524 Count
= Trb
->BlockSize
/ sizeof (UINT32
);
2527 Width
= EfiPciIoWidthFifoUint16
;
2528 Count
= Trb
->BlockSize
/ sizeof (UINT16
);
2533 Width
= EfiPciIoWidthFifoUint8
;
2534 Count
= Trb
->BlockSize
;
2539 if ((IntStatus
& BIT5
) == 0) {
2540 return EFI_NOT_READY
;
2543 SdMmcHcRwMmio (Private
->PciIo
, Trb
->Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (Data16
), &Data16
);
2545 Status
= Private
->PciIo
->Mem
.Read (
2549 SD_MMC_HC_BUF_DAT_PORT
,
2551 (VOID
*)((UINT8
*)Trb
->Data
+ (Trb
->BlockSize
* Trb
->PioBlockIndex
))
2553 if (EFI_ERROR (Status
)) {
2556 Trb
->PioBlockIndex
++;
2558 if ((IntStatus
& BIT4
) == 0) {
2559 return EFI_NOT_READY
;
2562 SdMmcHcRwMmio (Private
->PciIo
, Trb
->Slot
, SD_MMC_HC_NOR_INT_STS
, FALSE
, sizeof (Data16
), &Data16
);
2564 Status
= Private
->PciIo
->Mem
.Write (
2568 SD_MMC_HC_BUF_DAT_PORT
,
2570 (VOID
*)((UINT8
*)Trb
->Data
+ (Trb
->BlockSize
* Trb
->PioBlockIndex
))
2572 if (EFI_ERROR (Status
)) {
2575 Trb
->PioBlockIndex
++;
2578 if (Trb
->PioBlockIndex
>= BlockCount
) {
2579 Trb
->PioModeTransferCompleted
= TRUE
;
2582 return EFI_NOT_READY
;
2587 Update the SDMA address on the SDMA buffer boundary interrupt.
2589 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2590 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2592 @retval EFI_SUCCESS Updated SDMA buffer address.
2593 @retval Others Failed to update SDMA buffer address.
2596 SdMmcUpdateSdmaAddress (
2597 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2598 IN SD_MMC_HC_TRB
*Trb
2604 SdmaAddr
= SD_MMC_SDMA_ROUND_UP ((UINTN
)Trb
->DataPhy
, SD_MMC_SDMA_BOUNDARY
);
2606 if (Private
->ControllerVersion
[Trb
->Slot
] >= SD_MMC_HC_CTRL_VER_400
) {
2607 Status
= SdMmcHcRwMmio (
2610 SD_MMC_HC_ADMA_SYS_ADDR
,
2616 Status
= SdMmcHcRwMmio (
2619 SD_MMC_HC_SDMA_ADDR
,
2626 if (EFI_ERROR (Status
)) {
2630 Trb
->DataPhy
= (UINT64
)(UINTN
)SdmaAddr
;
2635 Checks if the data transfer completed and performs any actions
2636 neccessary to continue the data transfer such as SDMA system
2637 address fixup or PIO data transfer.
2639 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2640 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2641 @param[in] IntStatus Snapshot of the normal interrupt status register.
2643 @retval EFI_SUCCESS Data transfer completed successfully.
2644 @retval EFI_NOT_READY Data transfer completion still pending.
2645 @retval Others Data transfer failed to complete.
2648 SdMmcCheckDataTransfer (
2649 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2650 IN SD_MMC_HC_TRB
*Trb
,
2657 if ((IntStatus
& BIT1
) != 0) {
2659 Status
= SdMmcHcRwMmio (
2662 SD_MMC_HC_NOR_INT_STS
,
2670 if (Trb
->Mode
== SdMmcPioMode
&& !Trb
->PioModeTransferCompleted
) {
2671 Status
= SdMmcTransferDataWithPio (Private
, Trb
, IntStatus
);
2672 if (EFI_ERROR (Status
)) {
2677 if ((Trb
->Mode
== SdMmcSdmaMode
) && ((IntStatus
& BIT3
) != 0)) {
2679 Status
= SdMmcHcRwMmio (
2682 SD_MMC_HC_NOR_INT_STS
,
2687 if (EFI_ERROR (Status
)) {
2690 Status
= SdMmcUpdateSdmaAddress (Private
, Trb
);
2691 if (EFI_ERROR (Status
)) {
2696 return EFI_NOT_READY
;
2700 Check the TRB execution result.
2702 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2703 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2705 @retval EFI_SUCCESS The TRB is executed successfully.
2706 @retval EFI_NOT_READY The TRB is not completed for execution.
2707 @retval Others Some erros happen when executing this request.
2711 SdMmcCheckTrbResult (
2712 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2713 IN SD_MMC_HC_TRB
*Trb
2717 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
2720 Packet
= Trb
->Packet
;
2722 // Check Trb execution result by reading Normal Interrupt Status register.
2724 Status
= SdMmcHcRwMmio (
2727 SD_MMC_HC_NOR_INT_STS
,
2732 if (EFI_ERROR (Status
)) {
2737 // Check if there are any errors reported by host controller
2738 // and if neccessary recover the controller before next command is executed.
2740 Status
= SdMmcCheckAndRecoverErrors (Private
, Trb
->Slot
, IntStatus
);
2741 if (EFI_ERROR (Status
)) {
2746 // Tuning commands are the only ones that do not generate command
2747 // complete interrupt. Process them here before entering the code
2748 // that waits for command completion.
2750 if (((Private
->Slot
[Trb
->Slot
].CardType
== EmmcCardType
) &&
2751 (Packet
->SdMmcCmdBlk
->CommandIndex
== EMMC_SEND_TUNING_BLOCK
)) ||
2752 ((Private
->Slot
[Trb
->Slot
].CardType
== SdCardType
) &&
2753 (Packet
->SdMmcCmdBlk
->CommandIndex
== SD_SEND_TUNING_BLOCK
))) {
2754 Status
= SdMmcTransferDataWithPio (Private
, Trb
, IntStatus
);
2758 if (!Trb
->CommandComplete
) {
2759 Status
= SdMmcCheckCommandComplete (Private
, Trb
, IntStatus
);
2760 if (EFI_ERROR (Status
)) {
2765 if (Packet
->SdMmcCmdBlk
->CommandType
== SdMmcCommandTypeAdtc
||
2766 Packet
->SdMmcCmdBlk
->ResponseType
== SdMmcResponseTypeR1b
||
2767 Packet
->SdMmcCmdBlk
->ResponseType
== SdMmcResponseTypeR5b
) {
2768 Status
= SdMmcCheckDataTransfer (Private
, Trb
, IntStatus
);
2770 Status
= EFI_SUCCESS
;
2774 if (Status
!= EFI_NOT_READY
) {
2775 SdMmcHcLedOnOff (Private
->PciIo
, Trb
->Slot
, FALSE
);
2776 if (EFI_ERROR (Status
)) {
2777 DEBUG ((DEBUG_ERROR
, "TRB failed with %r\n", Status
));
2778 SdMmcPrintTrb (DEBUG_ERROR
, Trb
);
2780 DEBUG ((DEBUG_VERBOSE
, "TRB success\n"));
2781 SdMmcPrintTrb (DEBUG_VERBOSE
, Trb
);
2789 Wait for the TRB execution result.
2791 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2792 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2794 @retval EFI_SUCCESS The TRB is executed successfully.
2795 @retval Others Some erros happen when executing this request.
2799 SdMmcWaitTrbResult (
2800 IN SD_MMC_HC_PRIVATE_DATA
*Private
,
2801 IN SD_MMC_HC_TRB
*Trb
2805 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET
*Packet
;
2807 BOOLEAN InfiniteWait
;
2809 Packet
= Trb
->Packet
;
2811 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
2813 Timeout
= Packet
->Timeout
;
2815 InfiniteWait
= TRUE
;
2817 InfiniteWait
= FALSE
;
2820 while (InfiniteWait
|| (Timeout
> 0)) {
2822 // Check Trb execution result by reading Normal Interrupt Status register.
2824 Status
= SdMmcCheckTrbResult (Private
, Trb
);
2825 if (Status
!= EFI_NOT_READY
) {
2829 // Stall for 1 microsecond.