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MdeModulePkg/SdMmcPciHcDxe: allow HC capabilities to be overridden
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcDxe / SdMmcPciHci.c
1 /** @file
2 This driver is used to manage SD/MMC PCI host controllers which are compliance
3 with SD Host Controller Simplified Specification version 3.00.
4
5 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
6
7 Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
8 This program and the accompanying materials
9 are licensed and made available under the terms and conditions of the BSD License
10 which accompanies this distribution. The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
12
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15
16 **/
17
18 #include "SdMmcPciHcDxe.h"
19
20 /**
21 Dump the content of SD/MMC host controller's Capability Register.
22
23 @param[in] Slot The slot number of the SD card to send the command to.
24 @param[in] Capability The buffer to store the capability data.
25
26 **/
27 VOID
28 DumpCapabilityReg (
29 IN UINT8 Slot,
30 IN SD_MMC_HC_SLOT_CAP *Capability
31 )
32 {
33 //
34 // Dump Capability Data
35 //
36 DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));
37 DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));
38 DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkFreq));
39 DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));
40 DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));
41 DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));
42 DEBUG ((DEBUG_INFO, " HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));
43 DEBUG ((DEBUG_INFO, " SDMA Support %a\n", Capability->Sdma ? "TRUE" : "FALSE"));
44 DEBUG ((DEBUG_INFO, " Suspend/Resume %a\n", Capability->SuspRes ? "TRUE" : "FALSE"));
45 DEBUG ((DEBUG_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));
46 DEBUG ((DEBUG_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));
47 DEBUG ((DEBUG_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));
48 DEBUG ((DEBUG_INFO, " 64-bit Sys Bus %a\n", Capability->SysBus64 ? "TRUE" : "FALSE"));
49 DEBUG ((DEBUG_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));
50 DEBUG ((DEBUG_INFO, " SlotType "));
51 if (Capability->SlotType == 0x00) {
52 DEBUG ((DEBUG_INFO, "%a\n", "Removable Slot"));
53 } else if (Capability->SlotType == 0x01) {
54 DEBUG ((DEBUG_INFO, "%a\n", "Embedded Slot"));
55 } else if (Capability->SlotType == 0x02) {
56 DEBUG ((DEBUG_INFO, "%a\n", "Shared Bus Slot"));
57 } else {
58 DEBUG ((DEBUG_INFO, "%a\n", "Reserved"));
59 }
60 DEBUG ((DEBUG_INFO, " SDR50 Support %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));
61 DEBUG ((DEBUG_INFO, " SDR104 Support %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));
62 DEBUG ((DEBUG_INFO, " DDR50 Support %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));
63 DEBUG ((DEBUG_INFO, " Driver Type A %a\n", Capability->DriverTypeA ? "TRUE" : "FALSE"));
64 DEBUG ((DEBUG_INFO, " Driver Type C %a\n", Capability->DriverTypeC ? "TRUE" : "FALSE"));
65 DEBUG ((DEBUG_INFO, " Driver Type D %a\n", Capability->DriverTypeD ? "TRUE" : "FALSE"));
66 DEBUG ((DEBUG_INFO, " Driver Type 4 %a\n", Capability->DriverType4 ? "TRUE" : "FALSE"));
67 if (Capability->TimerCount == 0) {
68 DEBUG ((DEBUG_INFO, " Retuning TimerCnt Disabled\n", 2 * (Capability->TimerCount - 1)));
69 } else {
70 DEBUG ((DEBUG_INFO, " Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));
71 }
72 DEBUG ((DEBUG_INFO, " SDR50 Tuning %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));
73 DEBUG ((DEBUG_INFO, " Retuning Mode Mode %d\n", Capability->RetuningMod + 1));
74 DEBUG ((DEBUG_INFO, " Clock Multiplier M = %d\n", Capability->ClkMultiplier + 1));
75 DEBUG ((DEBUG_INFO, " HS 400 %a\n", Capability->Hs400 ? "TRUE" : "FALSE"));
76 return;
77 }
78
79 /**
80 Read SlotInfo register from SD/MMC host controller pci config space.
81
82 @param[in] PciIo The PCI IO protocol instance.
83 @param[out] FirstBar The buffer to store the first BAR value.
84 @param[out] SlotNum The buffer to store the supported slot number.
85
86 @retval EFI_SUCCESS The operation succeeds.
87 @retval Others The operation fails.
88
89 **/
90 EFI_STATUS
91 EFIAPI
92 SdMmcHcGetSlotInfo (
93 IN EFI_PCI_IO_PROTOCOL *PciIo,
94 OUT UINT8 *FirstBar,
95 OUT UINT8 *SlotNum
96 )
97 {
98 EFI_STATUS Status;
99 SD_MMC_HC_SLOT_INFO SlotInfo;
100
101 Status = PciIo->Pci.Read (
102 PciIo,
103 EfiPciIoWidthUint8,
104 SD_MMC_HC_SLOT_OFFSET,
105 sizeof (SlotInfo),
106 &SlotInfo
107 );
108 if (EFI_ERROR (Status)) {
109 return Status;
110 }
111
112 *FirstBar = SlotInfo.FirstBar;
113 *SlotNum = SlotInfo.SlotNum + 1;
114 ASSERT ((*FirstBar + *SlotNum) < SD_MMC_HC_MAX_SLOT);
115 return EFI_SUCCESS;
116 }
117
118 /**
119 Read/Write specified SD/MMC host controller mmio register.
120
121 @param[in] PciIo The PCI IO protocol instance.
122 @param[in] BarIndex The BAR index of the standard PCI Configuration
123 header to use as the base address for the memory
124 operation to perform.
125 @param[in] Offset The offset within the selected BAR to start the
126 memory operation.
127 @param[in] Read A boolean to indicate it's read or write operation.
128 @param[in] Count The width of the mmio register in bytes.
129 Must be 1, 2 , 4 or 8 bytes.
130 @param[in, out] Data For read operations, the destination buffer to store
131 the results. For write operations, the source buffer
132 to write data from. The caller is responsible for
133 having ownership of the data buffer and ensuring its
134 size not less than Count bytes.
135
136 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
137 @retval EFI_SUCCESS The read/write operation succeeds.
138 @retval Others The read/write operation fails.
139
140 **/
141 EFI_STATUS
142 EFIAPI
143 SdMmcHcRwMmio (
144 IN EFI_PCI_IO_PROTOCOL *PciIo,
145 IN UINT8 BarIndex,
146 IN UINT32 Offset,
147 IN BOOLEAN Read,
148 IN UINT8 Count,
149 IN OUT VOID *Data
150 )
151 {
152 EFI_STATUS Status;
153
154 if ((PciIo == NULL) || (Data == NULL)) {
155 return EFI_INVALID_PARAMETER;
156 }
157
158 if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {
159 return EFI_INVALID_PARAMETER;
160 }
161
162 if (Read) {
163 Status = PciIo->Mem.Read (
164 PciIo,
165 EfiPciIoWidthUint8,
166 BarIndex,
167 (UINT64) Offset,
168 Count,
169 Data
170 );
171 } else {
172 Status = PciIo->Mem.Write (
173 PciIo,
174 EfiPciIoWidthUint8,
175 BarIndex,
176 (UINT64) Offset,
177 Count,
178 Data
179 );
180 }
181
182 return Status;
183 }
184
185 /**
186 Do OR operation with the value of the specified SD/MMC host controller mmio register.
187
188 @param[in] PciIo The PCI IO protocol instance.
189 @param[in] BarIndex The BAR index of the standard PCI Configuration
190 header to use as the base address for the memory
191 operation to perform.
192 @param[in] Offset The offset within the selected BAR to start the
193 memory operation.
194 @param[in] Count The width of the mmio register in bytes.
195 Must be 1, 2 , 4 or 8 bytes.
196 @param[in] OrData The pointer to the data used to do OR operation.
197 The caller is responsible for having ownership of
198 the data buffer and ensuring its size not less than
199 Count bytes.
200
201 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
202 @retval EFI_SUCCESS The OR operation succeeds.
203 @retval Others The OR operation fails.
204
205 **/
206 EFI_STATUS
207 EFIAPI
208 SdMmcHcOrMmio (
209 IN EFI_PCI_IO_PROTOCOL *PciIo,
210 IN UINT8 BarIndex,
211 IN UINT32 Offset,
212 IN UINT8 Count,
213 IN VOID *OrData
214 )
215 {
216 EFI_STATUS Status;
217 UINT64 Data;
218 UINT64 Or;
219
220 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
221 if (EFI_ERROR (Status)) {
222 return Status;
223 }
224
225 if (Count == 1) {
226 Or = *(UINT8*) OrData;
227 } else if (Count == 2) {
228 Or = *(UINT16*) OrData;
229 } else if (Count == 4) {
230 Or = *(UINT32*) OrData;
231 } else if (Count == 8) {
232 Or = *(UINT64*) OrData;
233 } else {
234 return EFI_INVALID_PARAMETER;
235 }
236
237 Data |= Or;
238 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
239
240 return Status;
241 }
242
243 /**
244 Do AND operation with the value of the specified SD/MMC host controller mmio register.
245
246 @param[in] PciIo The PCI IO protocol instance.
247 @param[in] BarIndex The BAR index of the standard PCI Configuration
248 header to use as the base address for the memory
249 operation to perform.
250 @param[in] Offset The offset within the selected BAR to start the
251 memory operation.
252 @param[in] Count The width of the mmio register in bytes.
253 Must be 1, 2 , 4 or 8 bytes.
254 @param[in] AndData The pointer to the data used to do AND operation.
255 The caller is responsible for having ownership of
256 the data buffer and ensuring its size not less than
257 Count bytes.
258
259 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
260 @retval EFI_SUCCESS The AND operation succeeds.
261 @retval Others The AND operation fails.
262
263 **/
264 EFI_STATUS
265 EFIAPI
266 SdMmcHcAndMmio (
267 IN EFI_PCI_IO_PROTOCOL *PciIo,
268 IN UINT8 BarIndex,
269 IN UINT32 Offset,
270 IN UINT8 Count,
271 IN VOID *AndData
272 )
273 {
274 EFI_STATUS Status;
275 UINT64 Data;
276 UINT64 And;
277
278 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
279 if (EFI_ERROR (Status)) {
280 return Status;
281 }
282
283 if (Count == 1) {
284 And = *(UINT8*) AndData;
285 } else if (Count == 2) {
286 And = *(UINT16*) AndData;
287 } else if (Count == 4) {
288 And = *(UINT32*) AndData;
289 } else if (Count == 8) {
290 And = *(UINT64*) AndData;
291 } else {
292 return EFI_INVALID_PARAMETER;
293 }
294
295 Data &= And;
296 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
297
298 return Status;
299 }
300
301 /**
302 Wait for the value of the specified MMIO register set to the test value.
303
304 @param[in] PciIo The PCI IO protocol instance.
305 @param[in] BarIndex The BAR index of the standard PCI Configuration
306 header to use as the base address for the memory
307 operation to perform.
308 @param[in] Offset The offset within the selected BAR to start the
309 memory operation.
310 @param[in] Count The width of the mmio register in bytes.
311 Must be 1, 2, 4 or 8 bytes.
312 @param[in] MaskValue The mask value of memory.
313 @param[in] TestValue The test value of memory.
314
315 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
316 @retval EFI_SUCCESS The MMIO register has expected value.
317 @retval Others The MMIO operation fails.
318
319 **/
320 EFI_STATUS
321 EFIAPI
322 SdMmcHcCheckMmioSet (
323 IN EFI_PCI_IO_PROTOCOL *PciIo,
324 IN UINT8 BarIndex,
325 IN UINT32 Offset,
326 IN UINT8 Count,
327 IN UINT64 MaskValue,
328 IN UINT64 TestValue
329 )
330 {
331 EFI_STATUS Status;
332 UINT64 Value;
333
334 //
335 // Access PCI MMIO space to see if the value is the tested one.
336 //
337 Value = 0;
338 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);
339 if (EFI_ERROR (Status)) {
340 return Status;
341 }
342
343 Value &= MaskValue;
344
345 if (Value == TestValue) {
346 return EFI_SUCCESS;
347 }
348
349 return EFI_NOT_READY;
350 }
351
352 /**
353 Wait for the value of the specified MMIO register set to the test value.
354
355 @param[in] PciIo The PCI IO protocol instance.
356 @param[in] BarIndex The BAR index of the standard PCI Configuration
357 header to use as the base address for the memory
358 operation to perform.
359 @param[in] Offset The offset within the selected BAR to start the
360 memory operation.
361 @param[in] Count The width of the mmio register in bytes.
362 Must be 1, 2, 4 or 8 bytes.
363 @param[in] MaskValue The mask value of memory.
364 @param[in] TestValue The test value of memory.
365 @param[in] Timeout The time out value for wait memory set, uses 1
366 microsecond as a unit.
367
368 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
369 range.
370 @retval EFI_SUCCESS The MMIO register has expected value.
371 @retval Others The MMIO operation fails.
372
373 **/
374 EFI_STATUS
375 EFIAPI
376 SdMmcHcWaitMmioSet (
377 IN EFI_PCI_IO_PROTOCOL *PciIo,
378 IN UINT8 BarIndex,
379 IN UINT32 Offset,
380 IN UINT8 Count,
381 IN UINT64 MaskValue,
382 IN UINT64 TestValue,
383 IN UINT64 Timeout
384 )
385 {
386 EFI_STATUS Status;
387 BOOLEAN InfiniteWait;
388
389 if (Timeout == 0) {
390 InfiniteWait = TRUE;
391 } else {
392 InfiniteWait = FALSE;
393 }
394
395 while (InfiniteWait || (Timeout > 0)) {
396 Status = SdMmcHcCheckMmioSet (
397 PciIo,
398 BarIndex,
399 Offset,
400 Count,
401 MaskValue,
402 TestValue
403 );
404 if (Status != EFI_NOT_READY) {
405 return Status;
406 }
407
408 //
409 // Stall for 1 microsecond.
410 //
411 gBS->Stall (1);
412
413 Timeout--;
414 }
415
416 return EFI_TIMEOUT;
417 }
418
419 /**
420 Software reset the specified SD/MMC host controller and enable all interrupts.
421
422 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
423 @param[in] Slot The slot number of the SD card to send the command to.
424
425 @retval EFI_SUCCESS The software reset executes successfully.
426 @retval Others The software reset fails.
427
428 **/
429 EFI_STATUS
430 SdMmcHcReset (
431 IN SD_MMC_HC_PRIVATE_DATA *Private,
432 IN UINT8 Slot
433 )
434 {
435 EFI_STATUS Status;
436 UINT8 SwReset;
437 EFI_PCI_IO_PROTOCOL *PciIo;
438
439 //
440 // Notify the SD/MMC override protocol that we are about to reset
441 // the SD/MMC host controller.
442 //
443 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
444 Status = mOverride->NotifyPhase (
445 Private->ControllerHandle,
446 Slot,
447 EdkiiSdMmcResetPre);
448 if (EFI_ERROR (Status)) {
449 DEBUG ((DEBUG_WARN,
450 "%a: SD/MMC pre reset notifier callback failed - %r\n",
451 __FUNCTION__, Status));
452 return Status;
453 }
454 }
455
456 PciIo = Private->PciIo;
457 SwReset = 0xFF;
458 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_SW_RST, FALSE, sizeof (SwReset), &SwReset);
459
460 if (EFI_ERROR (Status)) {
461 DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write full 1 fails: %r\n", Status));
462 return Status;
463 }
464
465 Status = SdMmcHcWaitMmioSet (
466 PciIo,
467 Slot,
468 SD_MMC_HC_SW_RST,
469 sizeof (SwReset),
470 0xFF,
471 0x00,
472 SD_MMC_HC_GENERIC_TIMEOUT
473 );
474 if (EFI_ERROR (Status)) {
475 DEBUG ((DEBUG_INFO, "SdMmcHcReset: reset done with %r\n", Status));
476 return Status;
477 }
478
479 //
480 // Enable all interrupt after reset all.
481 //
482 Status = SdMmcHcEnableInterrupt (PciIo, Slot);
483 if (EFI_ERROR (Status)) {
484 DEBUG ((DEBUG_INFO, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",
485 Status));
486 return Status;
487 }
488
489 //
490 // Notify the SD/MMC override protocol that we have just reset
491 // the SD/MMC host controller.
492 //
493 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
494 Status = mOverride->NotifyPhase (
495 Private->ControllerHandle,
496 Slot,
497 EdkiiSdMmcResetPost);
498 if (EFI_ERROR (Status)) {
499 DEBUG ((DEBUG_WARN,
500 "%a: SD/MMC post reset notifier callback failed - %r\n",
501 __FUNCTION__, Status));
502 }
503 }
504
505 return Status;
506 }
507
508 /**
509 Set all interrupt status bits in Normal and Error Interrupt Status Enable
510 register.
511
512 @param[in] PciIo The PCI IO protocol instance.
513 @param[in] Slot The slot number of the SD card to send the command to.
514
515 @retval EFI_SUCCESS The operation executes successfully.
516 @retval Others The operation fails.
517
518 **/
519 EFI_STATUS
520 SdMmcHcEnableInterrupt (
521 IN EFI_PCI_IO_PROTOCOL *PciIo,
522 IN UINT8 Slot
523 )
524 {
525 EFI_STATUS Status;
526 UINT16 IntStatus;
527
528 //
529 // Enable all bits in Error Interrupt Status Enable Register
530 //
531 IntStatus = 0xFFFF;
532 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
533 if (EFI_ERROR (Status)) {
534 return Status;
535 }
536 //
537 // Enable all bits in Normal Interrupt Status Enable Register
538 //
539 IntStatus = 0xFFFF;
540 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
541
542 return Status;
543 }
544
545 /**
546 Get the capability data from the specified slot.
547
548 @param[in] PciIo The PCI IO protocol instance.
549 @param[in] Slot The slot number of the SD card to send the command to.
550 @param[out] Capability The buffer to store the capability data.
551
552 @retval EFI_SUCCESS The operation executes successfully.
553 @retval Others The operation fails.
554
555 **/
556 EFI_STATUS
557 SdMmcHcGetCapability (
558 IN EFI_PCI_IO_PROTOCOL *PciIo,
559 IN UINT8 Slot,
560 OUT SD_MMC_HC_SLOT_CAP *Capability
561 )
562 {
563 EFI_STATUS Status;
564 UINT64 Cap;
565
566 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);
567 if (EFI_ERROR (Status)) {
568 return Status;
569 }
570
571 CopyMem (Capability, &Cap, sizeof (Cap));
572
573 return EFI_SUCCESS;
574 }
575
576 /**
577 Get the maximum current capability data from the specified slot.
578
579 @param[in] PciIo The PCI IO protocol instance.
580 @param[in] Slot The slot number of the SD card to send the command to.
581 @param[out] MaxCurrent The buffer to store the maximum current capability data.
582
583 @retval EFI_SUCCESS The operation executes successfully.
584 @retval Others The operation fails.
585
586 **/
587 EFI_STATUS
588 SdMmcHcGetMaxCurrent (
589 IN EFI_PCI_IO_PROTOCOL *PciIo,
590 IN UINT8 Slot,
591 OUT UINT64 *MaxCurrent
592 )
593 {
594 EFI_STATUS Status;
595
596 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);
597
598 return Status;
599 }
600
601 /**
602 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
603 slot.
604
605 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
606
607 @param[in] PciIo The PCI IO protocol instance.
608 @param[in] Slot The slot number of the SD card to send the command to.
609 @param[out] MediaPresent The pointer to the media present boolean value.
610
611 @retval EFI_SUCCESS There is no media change happened.
612 @retval EFI_MEDIA_CHANGED There is media change happened.
613 @retval Others The detection fails.
614
615 **/
616 EFI_STATUS
617 SdMmcHcCardDetect (
618 IN EFI_PCI_IO_PROTOCOL *PciIo,
619 IN UINT8 Slot,
620 OUT BOOLEAN *MediaPresent
621 )
622 {
623 EFI_STATUS Status;
624 UINT16 Data;
625 UINT32 PresentState;
626
627 //
628 // Check Present State Register to see if there is a card presented.
629 //
630 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
631 if (EFI_ERROR (Status)) {
632 return Status;
633 }
634
635 if ((PresentState & BIT16) != 0) {
636 *MediaPresent = TRUE;
637 } else {
638 *MediaPresent = FALSE;
639 }
640
641 //
642 // Check Normal Interrupt Status Register
643 //
644 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);
645 if (EFI_ERROR (Status)) {
646 return Status;
647 }
648
649 if ((Data & (BIT6 | BIT7)) != 0) {
650 //
651 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
652 //
653 Data &= BIT6 | BIT7;
654 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);
655 if (EFI_ERROR (Status)) {
656 return Status;
657 }
658
659 return EFI_MEDIA_CHANGED;
660 }
661
662 return EFI_SUCCESS;
663 }
664
665 /**
666 Stop SD/MMC card clock.
667
668 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
669
670 @param[in] PciIo The PCI IO protocol instance.
671 @param[in] Slot The slot number of the SD card to send the command to.
672
673 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.
674 @retval Others Fail to stop SD/MMC clock.
675
676 **/
677 EFI_STATUS
678 SdMmcHcStopClock (
679 IN EFI_PCI_IO_PROTOCOL *PciIo,
680 IN UINT8 Slot
681 )
682 {
683 EFI_STATUS Status;
684 UINT32 PresentState;
685 UINT16 ClockCtrl;
686
687 //
688 // Ensure no SD transactions are occurring on the SD Bus by
689 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
690 // in the Present State register to be 0.
691 //
692 Status = SdMmcHcWaitMmioSet (
693 PciIo,
694 Slot,
695 SD_MMC_HC_PRESENT_STATE,
696 sizeof (PresentState),
697 BIT0 | BIT1,
698 0,
699 SD_MMC_HC_GENERIC_TIMEOUT
700 );
701 if (EFI_ERROR (Status)) {
702 return Status;
703 }
704
705 //
706 // Set SD Clock Enable in the Clock Control register to 0
707 //
708 ClockCtrl = (UINT16)~BIT2;
709 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
710
711 return Status;
712 }
713
714 /**
715 SD/MMC card clock supply.
716
717 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
718
719 @param[in] PciIo The PCI IO protocol instance.
720 @param[in] Slot The slot number of the SD card to send the command to.
721 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
722 @param[in] Capability The capability of the slot.
723
724 @retval EFI_SUCCESS The clock is supplied successfully.
725 @retval Others The clock isn't supplied successfully.
726
727 **/
728 EFI_STATUS
729 SdMmcHcClockSupply (
730 IN EFI_PCI_IO_PROTOCOL *PciIo,
731 IN UINT8 Slot,
732 IN UINT64 ClockFreq,
733 IN SD_MMC_HC_SLOT_CAP Capability
734 )
735 {
736 EFI_STATUS Status;
737 UINT32 BaseClkFreq;
738 UINT32 SettingFreq;
739 UINT32 Divisor;
740 UINT32 Remainder;
741 UINT16 ControllerVer;
742 UINT16 ClockCtrl;
743
744 //
745 // Calculate a divisor for SD clock frequency
746 //
747 ASSERT (Capability.BaseClkFreq != 0);
748
749 BaseClkFreq = Capability.BaseClkFreq;
750 if (ClockFreq == 0) {
751 return EFI_INVALID_PARAMETER;
752 }
753
754 if (ClockFreq > (BaseClkFreq * 1000)) {
755 ClockFreq = BaseClkFreq * 1000;
756 }
757
758 //
759 // Calculate the divisor of base frequency.
760 //
761 Divisor = 0;
762 SettingFreq = BaseClkFreq * 1000;
763 while (ClockFreq < SettingFreq) {
764 Divisor++;
765
766 SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);
767 Remainder = (BaseClkFreq * 1000) % (2 * Divisor);
768 if ((ClockFreq == SettingFreq) && (Remainder == 0)) {
769 break;
770 }
771 if ((ClockFreq == SettingFreq) && (Remainder != 0)) {
772 SettingFreq ++;
773 }
774 }
775
776 DEBUG ((DEBUG_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));
777
778 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (ControllerVer), &ControllerVer);
779 if (EFI_ERROR (Status)) {
780 return Status;
781 }
782 //
783 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
784 //
785 if ((ControllerVer & 0xFF) == 2) {
786 ASSERT (Divisor <= 0x3FF);
787 ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);
788 } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {
789 //
790 // Only the most significant bit can be used as divisor.
791 //
792 if (((Divisor - 1) & Divisor) != 0) {
793 Divisor = 1 << (HighBitSet32 (Divisor) + 1);
794 }
795 ASSERT (Divisor <= 0x80);
796 ClockCtrl = (Divisor & 0xFF) << 8;
797 } else {
798 DEBUG ((DEBUG_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));
799 return EFI_UNSUPPORTED;
800 }
801
802 //
803 // Stop bus clock at first
804 //
805 Status = SdMmcHcStopClock (PciIo, Slot);
806 if (EFI_ERROR (Status)) {
807 return Status;
808 }
809
810 //
811 // Supply clock frequency with specified divisor
812 //
813 ClockCtrl |= BIT0;
814 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);
815 if (EFI_ERROR (Status)) {
816 DEBUG ((DEBUG_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
817 return Status;
818 }
819
820 //
821 // Wait Internal Clock Stable in the Clock Control register to be 1
822 //
823 Status = SdMmcHcWaitMmioSet (
824 PciIo,
825 Slot,
826 SD_MMC_HC_CLOCK_CTRL,
827 sizeof (ClockCtrl),
828 BIT1,
829 BIT1,
830 SD_MMC_HC_GENERIC_TIMEOUT
831 );
832 if (EFI_ERROR (Status)) {
833 return Status;
834 }
835
836 //
837 // Set SD Clock Enable in the Clock Control register to 1
838 //
839 ClockCtrl = BIT2;
840 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
841
842 return Status;
843 }
844
845 /**
846 SD/MMC bus power control.
847
848 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
849
850 @param[in] PciIo The PCI IO protocol instance.
851 @param[in] Slot The slot number of the SD card to send the command to.
852 @param[in] PowerCtrl The value setting to the power control register.
853
854 @retval TRUE There is a SD/MMC card attached.
855 @retval FALSE There is no a SD/MMC card attached.
856
857 **/
858 EFI_STATUS
859 SdMmcHcPowerControl (
860 IN EFI_PCI_IO_PROTOCOL *PciIo,
861 IN UINT8 Slot,
862 IN UINT8 PowerCtrl
863 )
864 {
865 EFI_STATUS Status;
866
867 //
868 // Clr SD Bus Power
869 //
870 PowerCtrl &= (UINT8)~BIT0;
871 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
872 if (EFI_ERROR (Status)) {
873 return Status;
874 }
875
876 //
877 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
878 //
879 PowerCtrl |= BIT0;
880 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
881
882 return Status;
883 }
884
885 /**
886 Set the SD/MMC bus width.
887
888 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
889
890 @param[in] PciIo The PCI IO protocol instance.
891 @param[in] Slot The slot number of the SD card to send the command to.
892 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
893
894 @retval EFI_SUCCESS The bus width is set successfully.
895 @retval Others The bus width isn't set successfully.
896
897 **/
898 EFI_STATUS
899 SdMmcHcSetBusWidth (
900 IN EFI_PCI_IO_PROTOCOL *PciIo,
901 IN UINT8 Slot,
902 IN UINT16 BusWidth
903 )
904 {
905 EFI_STATUS Status;
906 UINT8 HostCtrl1;
907
908 if (BusWidth == 1) {
909 HostCtrl1 = (UINT8)~(BIT5 | BIT1);
910 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
911 } else if (BusWidth == 4) {
912 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
913 if (EFI_ERROR (Status)) {
914 return Status;
915 }
916 HostCtrl1 |= BIT1;
917 HostCtrl1 &= (UINT8)~BIT5;
918 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
919 } else if (BusWidth == 8) {
920 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
921 if (EFI_ERROR (Status)) {
922 return Status;
923 }
924 HostCtrl1 &= (UINT8)~BIT1;
925 HostCtrl1 |= BIT5;
926 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
927 } else {
928 ASSERT (FALSE);
929 return EFI_INVALID_PARAMETER;
930 }
931
932 return Status;
933 }
934
935 /**
936 Supply SD/MMC card with lowest clock frequency at initialization.
937
938 @param[in] PciIo The PCI IO protocol instance.
939 @param[in] Slot The slot number of the SD card to send the command to.
940 @param[in] Capability The capability of the slot.
941
942 @retval EFI_SUCCESS The clock is supplied successfully.
943 @retval Others The clock isn't supplied successfully.
944
945 **/
946 EFI_STATUS
947 SdMmcHcInitClockFreq (
948 IN EFI_PCI_IO_PROTOCOL *PciIo,
949 IN UINT8 Slot,
950 IN SD_MMC_HC_SLOT_CAP Capability
951 )
952 {
953 EFI_STATUS Status;
954 UINT32 InitFreq;
955
956 //
957 // Calculate a divisor for SD clock frequency
958 //
959 if (Capability.BaseClkFreq == 0) {
960 //
961 // Don't support get Base Clock Frequency information via another method
962 //
963 return EFI_UNSUPPORTED;
964 }
965 //
966 // Supply 400KHz clock frequency at initialization phase.
967 //
968 InitFreq = 400;
969 Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, Capability);
970 return Status;
971 }
972
973 /**
974 Supply SD/MMC card with maximum voltage at initialization.
975
976 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
977
978 @param[in] PciIo The PCI IO protocol instance.
979 @param[in] Slot The slot number of the SD card to send the command to.
980 @param[in] Capability The capability of the slot.
981
982 @retval EFI_SUCCESS The voltage is supplied successfully.
983 @retval Others The voltage isn't supplied successfully.
984
985 **/
986 EFI_STATUS
987 SdMmcHcInitPowerVoltage (
988 IN EFI_PCI_IO_PROTOCOL *PciIo,
989 IN UINT8 Slot,
990 IN SD_MMC_HC_SLOT_CAP Capability
991 )
992 {
993 EFI_STATUS Status;
994 UINT8 MaxVoltage;
995 UINT8 HostCtrl2;
996
997 //
998 // Calculate supported maximum voltage according to SD Bus Voltage Select
999 //
1000 if (Capability.Voltage33 != 0) {
1001 //
1002 // Support 3.3V
1003 //
1004 MaxVoltage = 0x0E;
1005 } else if (Capability.Voltage30 != 0) {
1006 //
1007 // Support 3.0V
1008 //
1009 MaxVoltage = 0x0C;
1010 } else if (Capability.Voltage18 != 0) {
1011 //
1012 // Support 1.8V
1013 //
1014 MaxVoltage = 0x0A;
1015 HostCtrl2 = BIT3;
1016 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1017 gBS->Stall (5000);
1018 if (EFI_ERROR (Status)) {
1019 return Status;
1020 }
1021 } else {
1022 ASSERT (FALSE);
1023 return EFI_DEVICE_ERROR;
1024 }
1025
1026 //
1027 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
1028 //
1029 Status = SdMmcHcPowerControl (PciIo, Slot, MaxVoltage);
1030
1031 return Status;
1032 }
1033
1034 /**
1035 Initialize the Timeout Control register with most conservative value at initialization.
1036
1037 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
1038
1039 @param[in] PciIo The PCI IO protocol instance.
1040 @param[in] Slot The slot number of the SD card to send the command to.
1041
1042 @retval EFI_SUCCESS The timeout control register is configured successfully.
1043 @retval Others The timeout control register isn't configured successfully.
1044
1045 **/
1046 EFI_STATUS
1047 SdMmcHcInitTimeoutCtrl (
1048 IN EFI_PCI_IO_PROTOCOL *PciIo,
1049 IN UINT8 Slot
1050 )
1051 {
1052 EFI_STATUS Status;
1053 UINT8 Timeout;
1054
1055 Timeout = 0x0E;
1056 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);
1057
1058 return Status;
1059 }
1060
1061 /**
1062 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
1063 at initialization.
1064
1065 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1066 @param[in] Slot The slot number of the SD card to send the command to.
1067
1068 @retval EFI_SUCCESS The host controller is initialized successfully.
1069 @retval Others The host controller isn't initialized successfully.
1070
1071 **/
1072 EFI_STATUS
1073 SdMmcHcInitHost (
1074 IN SD_MMC_HC_PRIVATE_DATA *Private,
1075 IN UINT8 Slot
1076 )
1077 {
1078 EFI_STATUS Status;
1079 EFI_PCI_IO_PROTOCOL *PciIo;
1080 SD_MMC_HC_SLOT_CAP Capability;
1081
1082 //
1083 // Notify the SD/MMC override protocol that we are about to initialize
1084 // the SD/MMC host controller.
1085 //
1086 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1087 Status = mOverride->NotifyPhase (
1088 Private->ControllerHandle,
1089 Slot,
1090 EdkiiSdMmcInitHostPre);
1091 if (EFI_ERROR (Status)) {
1092 DEBUG ((DEBUG_WARN,
1093 "%a: SD/MMC pre init notifier callback failed - %r\n",
1094 __FUNCTION__, Status));
1095 return Status;
1096 }
1097 }
1098
1099 PciIo = Private->PciIo;
1100 Capability = Private->Capability[Slot];
1101
1102 Status = SdMmcHcInitClockFreq (PciIo, Slot, Capability);
1103 if (EFI_ERROR (Status)) {
1104 return Status;
1105 }
1106
1107 Status = SdMmcHcInitPowerVoltage (PciIo, Slot, Capability);
1108 if (EFI_ERROR (Status)) {
1109 return Status;
1110 }
1111
1112 Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);
1113 if (EFI_ERROR (Status)) {
1114 return Status;
1115 }
1116
1117 //
1118 // Notify the SD/MMC override protocol that we are have just initialized
1119 // the SD/MMC host controller.
1120 //
1121 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1122 Status = mOverride->NotifyPhase (
1123 Private->ControllerHandle,
1124 Slot,
1125 EdkiiSdMmcInitHostPost);
1126 if (EFI_ERROR (Status)) {
1127 DEBUG ((DEBUG_WARN,
1128 "%a: SD/MMC post init notifier callback failed - %r\n",
1129 __FUNCTION__, Status));
1130 }
1131 }
1132 return Status;
1133 }
1134
1135 /**
1136 Turn on/off LED.
1137
1138 @param[in] PciIo The PCI IO protocol instance.
1139 @param[in] Slot The slot number of the SD card to send the command to.
1140 @param[in] On The boolean to turn on/off LED.
1141
1142 @retval EFI_SUCCESS The LED is turned on/off successfully.
1143 @retval Others The LED isn't turned on/off successfully.
1144
1145 **/
1146 EFI_STATUS
1147 SdMmcHcLedOnOff (
1148 IN EFI_PCI_IO_PROTOCOL *PciIo,
1149 IN UINT8 Slot,
1150 IN BOOLEAN On
1151 )
1152 {
1153 EFI_STATUS Status;
1154 UINT8 HostCtrl1;
1155
1156 if (On) {
1157 HostCtrl1 = BIT0;
1158 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1159 } else {
1160 HostCtrl1 = (UINT8)~BIT0;
1161 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1162 }
1163
1164 return Status;
1165 }
1166
1167 /**
1168 Build ADMA descriptor table for transfer.
1169
1170 Refer to SD Host Controller Simplified spec 3.0 Section 1.13 for details.
1171
1172 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1173
1174 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
1175 @retval Others The ADMA descriptor table isn't created successfully.
1176
1177 **/
1178 EFI_STATUS
1179 BuildAdmaDescTable (
1180 IN SD_MMC_HC_TRB *Trb
1181 )
1182 {
1183 EFI_PHYSICAL_ADDRESS Data;
1184 UINT64 DataLen;
1185 UINT64 Entries;
1186 UINT32 Index;
1187 UINT64 Remaining;
1188 UINT32 Address;
1189 UINTN TableSize;
1190 EFI_PCI_IO_PROTOCOL *PciIo;
1191 EFI_STATUS Status;
1192 UINTN Bytes;
1193
1194 Data = Trb->DataPhy;
1195 DataLen = Trb->DataLen;
1196 PciIo = Trb->Private->PciIo;
1197 //
1198 // Only support 32bit ADMA Descriptor Table
1199 //
1200 if ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)) {
1201 return EFI_INVALID_PARAMETER;
1202 }
1203 //
1204 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
1205 // for 32-bit address descriptor table.
1206 //
1207 if ((Data & (BIT0 | BIT1)) != 0) {
1208 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));
1209 }
1210
1211 Entries = DivU64x32 ((DataLen + ADMA_MAX_DATA_PER_LINE - 1), ADMA_MAX_DATA_PER_LINE);
1212 TableSize = (UINTN)MultU64x32 (Entries, sizeof (SD_MMC_HC_ADMA_DESC_LINE));
1213 Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);
1214 Status = PciIo->AllocateBuffer (
1215 PciIo,
1216 AllocateAnyPages,
1217 EfiBootServicesData,
1218 EFI_SIZE_TO_PAGES (TableSize),
1219 (VOID **)&Trb->AdmaDesc,
1220 0
1221 );
1222 if (EFI_ERROR (Status)) {
1223 return EFI_OUT_OF_RESOURCES;
1224 }
1225 ZeroMem (Trb->AdmaDesc, TableSize);
1226 Bytes = TableSize;
1227 Status = PciIo->Map (
1228 PciIo,
1229 EfiPciIoOperationBusMasterCommonBuffer,
1230 Trb->AdmaDesc,
1231 &Bytes,
1232 &Trb->AdmaDescPhy,
1233 &Trb->AdmaMap
1234 );
1235
1236 if (EFI_ERROR (Status) || (Bytes != TableSize)) {
1237 //
1238 // Map error or unable to map the whole RFis buffer into a contiguous region.
1239 //
1240 PciIo->FreeBuffer (
1241 PciIo,
1242 EFI_SIZE_TO_PAGES (TableSize),
1243 Trb->AdmaDesc
1244 );
1245 return EFI_OUT_OF_RESOURCES;
1246 }
1247
1248 if ((UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {
1249 //
1250 // The ADMA doesn't support 64bit addressing.
1251 //
1252 PciIo->Unmap (
1253 PciIo,
1254 Trb->AdmaMap
1255 );
1256 PciIo->FreeBuffer (
1257 PciIo,
1258 EFI_SIZE_TO_PAGES (TableSize),
1259 Trb->AdmaDesc
1260 );
1261 return EFI_DEVICE_ERROR;
1262 }
1263
1264 Remaining = DataLen;
1265 Address = (UINT32)Data;
1266 for (Index = 0; Index < Entries; Index++) {
1267 if (Remaining <= ADMA_MAX_DATA_PER_LINE) {
1268 Trb->AdmaDesc[Index].Valid = 1;
1269 Trb->AdmaDesc[Index].Act = 2;
1270 Trb->AdmaDesc[Index].Length = (UINT16)Remaining;
1271 Trb->AdmaDesc[Index].Address = Address;
1272 break;
1273 } else {
1274 Trb->AdmaDesc[Index].Valid = 1;
1275 Trb->AdmaDesc[Index].Act = 2;
1276 Trb->AdmaDesc[Index].Length = 0;
1277 Trb->AdmaDesc[Index].Address = Address;
1278 }
1279
1280 Remaining -= ADMA_MAX_DATA_PER_LINE;
1281 Address += ADMA_MAX_DATA_PER_LINE;
1282 }
1283
1284 //
1285 // Set the last descriptor line as end of descriptor table
1286 //
1287 Trb->AdmaDesc[Index].End = 1;
1288 return EFI_SUCCESS;
1289 }
1290
1291 /**
1292 Create a new TRB for the SD/MMC cmd request.
1293
1294 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1295 @param[in] Slot The slot number of the SD card to send the command to.
1296 @param[in] Packet A pointer to the SD command data structure.
1297 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
1298 not NULL, then nonblocking I/O is performed, and Event
1299 will be signaled when the Packet completes.
1300
1301 @return Created Trb or NULL.
1302
1303 **/
1304 SD_MMC_HC_TRB *
1305 SdMmcCreateTrb (
1306 IN SD_MMC_HC_PRIVATE_DATA *Private,
1307 IN UINT8 Slot,
1308 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
1309 IN EFI_EVENT Event
1310 )
1311 {
1312 SD_MMC_HC_TRB *Trb;
1313 EFI_STATUS Status;
1314 EFI_TPL OldTpl;
1315 EFI_PCI_IO_PROTOCOL_OPERATION Flag;
1316 EFI_PCI_IO_PROTOCOL *PciIo;
1317 UINTN MapLength;
1318
1319 Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));
1320 if (Trb == NULL) {
1321 return NULL;
1322 }
1323
1324 Trb->Signature = SD_MMC_HC_TRB_SIG;
1325 Trb->Slot = Slot;
1326 Trb->BlockSize = 0x200;
1327 Trb->Packet = Packet;
1328 Trb->Event = Event;
1329 Trb->Started = FALSE;
1330 Trb->Timeout = Packet->Timeout;
1331 Trb->Private = Private;
1332
1333 if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
1334 Trb->Data = Packet->InDataBuffer;
1335 Trb->DataLen = Packet->InTransferLength;
1336 Trb->Read = TRUE;
1337 } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
1338 Trb->Data = Packet->OutDataBuffer;
1339 Trb->DataLen = Packet->OutTransferLength;
1340 Trb->Read = FALSE;
1341 } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {
1342 Trb->Data = NULL;
1343 Trb->DataLen = 0;
1344 } else {
1345 goto Error;
1346 }
1347
1348 if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {
1349 Trb->BlockSize = (UINT16)Trb->DataLen;
1350 }
1351
1352 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
1353 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
1354 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
1355 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
1356 Trb->Mode = SdMmcPioMode;
1357 } else {
1358 if (Trb->Read) {
1359 Flag = EfiPciIoOperationBusMasterWrite;
1360 } else {
1361 Flag = EfiPciIoOperationBusMasterRead;
1362 }
1363
1364 PciIo = Private->PciIo;
1365 if (Trb->DataLen != 0) {
1366 MapLength = Trb->DataLen;
1367 Status = PciIo->Map (
1368 PciIo,
1369 Flag,
1370 Trb->Data,
1371 &MapLength,
1372 &Trb->DataPhy,
1373 &Trb->DataMap
1374 );
1375 if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {
1376 Status = EFI_BAD_BUFFER_SIZE;
1377 goto Error;
1378 }
1379 }
1380
1381 if (Trb->DataLen == 0) {
1382 Trb->Mode = SdMmcNoData;
1383 } else if (Private->Capability[Slot].Adma2 != 0) {
1384 Trb->Mode = SdMmcAdmaMode;
1385 Status = BuildAdmaDescTable (Trb);
1386 if (EFI_ERROR (Status)) {
1387 PciIo->Unmap (PciIo, Trb->DataMap);
1388 goto Error;
1389 }
1390 } else if (Private->Capability[Slot].Sdma != 0) {
1391 Trb->Mode = SdMmcSdmaMode;
1392 } else {
1393 Trb->Mode = SdMmcPioMode;
1394 }
1395 }
1396
1397 if (Event != NULL) {
1398 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
1399 InsertTailList (&Private->Queue, &Trb->TrbList);
1400 gBS->RestoreTPL (OldTpl);
1401 }
1402
1403 return Trb;
1404
1405 Error:
1406 SdMmcFreeTrb (Trb);
1407 return NULL;
1408 }
1409
1410 /**
1411 Free the resource used by the TRB.
1412
1413 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1414
1415 **/
1416 VOID
1417 SdMmcFreeTrb (
1418 IN SD_MMC_HC_TRB *Trb
1419 )
1420 {
1421 EFI_PCI_IO_PROTOCOL *PciIo;
1422
1423 PciIo = Trb->Private->PciIo;
1424
1425 if (Trb->AdmaMap != NULL) {
1426 PciIo->Unmap (
1427 PciIo,
1428 Trb->AdmaMap
1429 );
1430 }
1431 if (Trb->AdmaDesc != NULL) {
1432 PciIo->FreeBuffer (
1433 PciIo,
1434 Trb->AdmaPages,
1435 Trb->AdmaDesc
1436 );
1437 }
1438 if (Trb->DataMap != NULL) {
1439 PciIo->Unmap (
1440 PciIo,
1441 Trb->DataMap
1442 );
1443 }
1444 FreePool (Trb);
1445 return;
1446 }
1447
1448 /**
1449 Check if the env is ready for execute specified TRB.
1450
1451 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1452 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1453
1454 @retval EFI_SUCCESS The env is ready for TRB execution.
1455 @retval EFI_NOT_READY The env is not ready for TRB execution.
1456 @retval Others Some erros happen.
1457
1458 **/
1459 EFI_STATUS
1460 SdMmcCheckTrbEnv (
1461 IN SD_MMC_HC_PRIVATE_DATA *Private,
1462 IN SD_MMC_HC_TRB *Trb
1463 )
1464 {
1465 EFI_STATUS Status;
1466 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1467 EFI_PCI_IO_PROTOCOL *PciIo;
1468 UINT32 PresentState;
1469
1470 Packet = Trb->Packet;
1471
1472 if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||
1473 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||
1474 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b)) {
1475 //
1476 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1477 // the Present State register to be 0
1478 //
1479 PresentState = BIT0 | BIT1;
1480 } else {
1481 //
1482 // Wait Command Inhibit (CMD) in the Present State register
1483 // to be 0
1484 //
1485 PresentState = BIT0;
1486 }
1487
1488 PciIo = Private->PciIo;
1489 Status = SdMmcHcCheckMmioSet (
1490 PciIo,
1491 Trb->Slot,
1492 SD_MMC_HC_PRESENT_STATE,
1493 sizeof (PresentState),
1494 PresentState,
1495 0
1496 );
1497
1498 return Status;
1499 }
1500
1501 /**
1502 Wait for the env to be ready for execute specified TRB.
1503
1504 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1505 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1506
1507 @retval EFI_SUCCESS The env is ready for TRB execution.
1508 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
1509 @retval Others Some erros happen.
1510
1511 **/
1512 EFI_STATUS
1513 SdMmcWaitTrbEnv (
1514 IN SD_MMC_HC_PRIVATE_DATA *Private,
1515 IN SD_MMC_HC_TRB *Trb
1516 )
1517 {
1518 EFI_STATUS Status;
1519 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1520 UINT64 Timeout;
1521 BOOLEAN InfiniteWait;
1522
1523 //
1524 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1525 //
1526 Packet = Trb->Packet;
1527 Timeout = Packet->Timeout;
1528 if (Timeout == 0) {
1529 InfiniteWait = TRUE;
1530 } else {
1531 InfiniteWait = FALSE;
1532 }
1533
1534 while (InfiniteWait || (Timeout > 0)) {
1535 //
1536 // Check Trb execution result by reading Normal Interrupt Status register.
1537 //
1538 Status = SdMmcCheckTrbEnv (Private, Trb);
1539 if (Status != EFI_NOT_READY) {
1540 return Status;
1541 }
1542 //
1543 // Stall for 1 microsecond.
1544 //
1545 gBS->Stall (1);
1546
1547 Timeout--;
1548 }
1549
1550 return EFI_TIMEOUT;
1551 }
1552
1553 /**
1554 Execute the specified TRB.
1555
1556 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1557 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1558
1559 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
1560 @retval Others Some erros happen when sending this request to the host controller.
1561
1562 **/
1563 EFI_STATUS
1564 SdMmcExecTrb (
1565 IN SD_MMC_HC_PRIVATE_DATA *Private,
1566 IN SD_MMC_HC_TRB *Trb
1567 )
1568 {
1569 EFI_STATUS Status;
1570 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1571 EFI_PCI_IO_PROTOCOL *PciIo;
1572 UINT16 Cmd;
1573 UINT16 IntStatus;
1574 UINT32 Argument;
1575 UINT16 BlkCount;
1576 UINT16 BlkSize;
1577 UINT16 TransMode;
1578 UINT8 HostCtrl1;
1579 UINT32 SdmaAddr;
1580 UINT64 AdmaAddr;
1581
1582 Packet = Trb->Packet;
1583 PciIo = Trb->Private->PciIo;
1584 //
1585 // Clear all bits in Error Interrupt Status Register
1586 //
1587 IntStatus = 0xFFFF;
1588 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1589 if (EFI_ERROR (Status)) {
1590 return Status;
1591 }
1592 //
1593 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
1594 //
1595 IntStatus = 0xFF3F;
1596 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1597 if (EFI_ERROR (Status)) {
1598 return Status;
1599 }
1600 //
1601 // Set Host Control 1 register DMA Select field
1602 //
1603 if (Trb->Mode == SdMmcAdmaMode) {
1604 HostCtrl1 = BIT4;
1605 Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1606 if (EFI_ERROR (Status)) {
1607 return Status;
1608 }
1609 }
1610
1611 SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);
1612
1613 if (Trb->Mode == SdMmcSdmaMode) {
1614 if ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul) {
1615 return EFI_INVALID_PARAMETER;
1616 }
1617
1618 SdmaAddr = (UINT32)(UINTN)Trb->DataPhy;
1619 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (SdmaAddr), &SdmaAddr);
1620 if (EFI_ERROR (Status)) {
1621 return Status;
1622 }
1623 } else if (Trb->Mode == SdMmcAdmaMode) {
1624 AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;
1625 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);
1626 if (EFI_ERROR (Status)) {
1627 return Status;
1628 }
1629 }
1630
1631 BlkSize = Trb->BlockSize;
1632 if (Trb->Mode == SdMmcSdmaMode) {
1633 //
1634 // Set SDMA boundary to be 512K bytes.
1635 //
1636 BlkSize |= 0x7000;
1637 }
1638
1639 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);
1640 if (EFI_ERROR (Status)) {
1641 return Status;
1642 }
1643
1644 BlkCount = 0;
1645 if (Trb->Mode != SdMmcNoData) {
1646 //
1647 // Calcuate Block Count.
1648 //
1649 BlkCount = (UINT16)(Trb->DataLen / Trb->BlockSize);
1650 }
1651 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (BlkCount), &BlkCount);
1652 if (EFI_ERROR (Status)) {
1653 return Status;
1654 }
1655
1656 Argument = Packet->SdMmcCmdBlk->CommandArgument;
1657 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);
1658 if (EFI_ERROR (Status)) {
1659 return Status;
1660 }
1661
1662 TransMode = 0;
1663 if (Trb->Mode != SdMmcNoData) {
1664 if (Trb->Mode != SdMmcPioMode) {
1665 TransMode |= BIT0;
1666 }
1667 if (Trb->Read) {
1668 TransMode |= BIT4;
1669 }
1670 if (BlkCount > 1) {
1671 TransMode |= BIT5 | BIT1;
1672 }
1673 //
1674 // Only SD memory card needs to use AUTO CMD12 feature.
1675 //
1676 if (Private->Slot[Trb->Slot].CardType == SdCardType) {
1677 if (BlkCount > 1) {
1678 TransMode |= BIT2;
1679 }
1680 }
1681 }
1682
1683 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);
1684 if (EFI_ERROR (Status)) {
1685 return Status;
1686 }
1687
1688 Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);
1689 if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {
1690 Cmd |= BIT5;
1691 }
1692 //
1693 // Convert ResponseType to value
1694 //
1695 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
1696 switch (Packet->SdMmcCmdBlk->ResponseType) {
1697 case SdMmcResponseTypeR1:
1698 case SdMmcResponseTypeR5:
1699 case SdMmcResponseTypeR6:
1700 case SdMmcResponseTypeR7:
1701 Cmd |= (BIT1 | BIT3 | BIT4);
1702 break;
1703 case SdMmcResponseTypeR2:
1704 Cmd |= (BIT0 | BIT3);
1705 break;
1706 case SdMmcResponseTypeR3:
1707 case SdMmcResponseTypeR4:
1708 Cmd |= BIT1;
1709 break;
1710 case SdMmcResponseTypeR1b:
1711 case SdMmcResponseTypeR5b:
1712 Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);
1713 break;
1714 default:
1715 ASSERT (FALSE);
1716 break;
1717 }
1718 }
1719 //
1720 // Execute cmd
1721 //
1722 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);
1723 return Status;
1724 }
1725
1726 /**
1727 Check the TRB execution result.
1728
1729 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1730 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1731
1732 @retval EFI_SUCCESS The TRB is executed successfully.
1733 @retval EFI_NOT_READY The TRB is not completed for execution.
1734 @retval Others Some erros happen when executing this request.
1735
1736 **/
1737 EFI_STATUS
1738 SdMmcCheckTrbResult (
1739 IN SD_MMC_HC_PRIVATE_DATA *Private,
1740 IN SD_MMC_HC_TRB *Trb
1741 )
1742 {
1743 EFI_STATUS Status;
1744 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1745 UINT16 IntStatus;
1746 UINT32 Response[4];
1747 UINT32 SdmaAddr;
1748 UINT8 Index;
1749 UINT8 SwReset;
1750 UINT32 PioLength;
1751
1752 SwReset = 0;
1753 Packet = Trb->Packet;
1754 //
1755 // Check Trb execution result by reading Normal Interrupt Status register.
1756 //
1757 Status = SdMmcHcRwMmio (
1758 Private->PciIo,
1759 Trb->Slot,
1760 SD_MMC_HC_NOR_INT_STS,
1761 TRUE,
1762 sizeof (IntStatus),
1763 &IntStatus
1764 );
1765 if (EFI_ERROR (Status)) {
1766 goto Done;
1767 }
1768 //
1769 // Check Transfer Complete bit is set or not.
1770 //
1771 if ((IntStatus & BIT1) == BIT1) {
1772 if ((IntStatus & BIT15) == BIT15) {
1773 //
1774 // Read Error Interrupt Status register to check if the error is
1775 // Data Timeout Error.
1776 // If yes, treat it as success as Transfer Complete has higher
1777 // priority than Data Timeout Error.
1778 //
1779 Status = SdMmcHcRwMmio (
1780 Private->PciIo,
1781 Trb->Slot,
1782 SD_MMC_HC_ERR_INT_STS,
1783 TRUE,
1784 sizeof (IntStatus),
1785 &IntStatus
1786 );
1787 if (!EFI_ERROR (Status)) {
1788 if ((IntStatus & BIT4) == BIT4) {
1789 Status = EFI_SUCCESS;
1790 } else {
1791 Status = EFI_DEVICE_ERROR;
1792 }
1793 }
1794 }
1795
1796 goto Done;
1797 }
1798 //
1799 // Check if there is a error happened during cmd execution.
1800 // If yes, then do error recovery procedure to follow SD Host Controller
1801 // Simplified Spec 3.0 section 3.10.1.
1802 //
1803 if ((IntStatus & BIT15) == BIT15) {
1804 Status = SdMmcHcRwMmio (
1805 Private->PciIo,
1806 Trb->Slot,
1807 SD_MMC_HC_ERR_INT_STS,
1808 TRUE,
1809 sizeof (IntStatus),
1810 &IntStatus
1811 );
1812 if (EFI_ERROR (Status)) {
1813 goto Done;
1814 }
1815 if ((IntStatus & 0x0F) != 0) {
1816 SwReset |= BIT1;
1817 }
1818 if ((IntStatus & 0xF0) != 0) {
1819 SwReset |= BIT2;
1820 }
1821
1822 Status = SdMmcHcRwMmio (
1823 Private->PciIo,
1824 Trb->Slot,
1825 SD_MMC_HC_SW_RST,
1826 FALSE,
1827 sizeof (SwReset),
1828 &SwReset
1829 );
1830 if (EFI_ERROR (Status)) {
1831 goto Done;
1832 }
1833 Status = SdMmcHcWaitMmioSet (
1834 Private->PciIo,
1835 Trb->Slot,
1836 SD_MMC_HC_SW_RST,
1837 sizeof (SwReset),
1838 0xFF,
1839 0,
1840 SD_MMC_HC_GENERIC_TIMEOUT
1841 );
1842 if (EFI_ERROR (Status)) {
1843 goto Done;
1844 }
1845
1846 Status = EFI_DEVICE_ERROR;
1847 goto Done;
1848 }
1849 //
1850 // Check if DMA interrupt is signalled for the SDMA transfer.
1851 //
1852 if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {
1853 //
1854 // Clear DMA interrupt bit.
1855 //
1856 IntStatus = BIT3;
1857 Status = SdMmcHcRwMmio (
1858 Private->PciIo,
1859 Trb->Slot,
1860 SD_MMC_HC_NOR_INT_STS,
1861 FALSE,
1862 sizeof (IntStatus),
1863 &IntStatus
1864 );
1865 if (EFI_ERROR (Status)) {
1866 goto Done;
1867 }
1868 //
1869 // Update SDMA Address register.
1870 //
1871 SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINT32)(UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);
1872 Status = SdMmcHcRwMmio (
1873 Private->PciIo,
1874 Trb->Slot,
1875 SD_MMC_HC_SDMA_ADDR,
1876 FALSE,
1877 sizeof (UINT32),
1878 &SdmaAddr
1879 );
1880 if (EFI_ERROR (Status)) {
1881 goto Done;
1882 }
1883 Trb->DataPhy = (UINT32)(UINTN)SdmaAddr;
1884 }
1885
1886 if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&
1887 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR1b) &&
1888 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR5b)) {
1889 if ((IntStatus & BIT0) == BIT0) {
1890 Status = EFI_SUCCESS;
1891 goto Done;
1892 }
1893 }
1894
1895 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
1896 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
1897 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
1898 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
1899 //
1900 // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,
1901 // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.
1902 // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.
1903 //
1904 if ((IntStatus & BIT5) == BIT5) {
1905 //
1906 // Clear Buffer Read Ready interrupt at first.
1907 //
1908 IntStatus = BIT5;
1909 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1910 //
1911 // Read data out from Buffer Port register
1912 //
1913 for (PioLength = 0; PioLength < Trb->DataLen; PioLength += 4) {
1914 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength);
1915 }
1916 Status = EFI_SUCCESS;
1917 goto Done;
1918 }
1919 }
1920
1921 Status = EFI_NOT_READY;
1922 Done:
1923 //
1924 // Get response data when the cmd is executed successfully.
1925 //
1926 if (!EFI_ERROR (Status)) {
1927 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
1928 for (Index = 0; Index < 4; Index++) {
1929 Status = SdMmcHcRwMmio (
1930 Private->PciIo,
1931 Trb->Slot,
1932 SD_MMC_HC_RESPONSE + Index * 4,
1933 TRUE,
1934 sizeof (UINT32),
1935 &Response[Index]
1936 );
1937 if (EFI_ERROR (Status)) {
1938 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
1939 return Status;
1940 }
1941 }
1942 CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));
1943 }
1944 }
1945
1946 if (Status != EFI_NOT_READY) {
1947 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
1948 }
1949
1950 return Status;
1951 }
1952
1953 /**
1954 Wait for the TRB execution result.
1955
1956 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1957 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1958
1959 @retval EFI_SUCCESS The TRB is executed successfully.
1960 @retval Others Some erros happen when executing this request.
1961
1962 **/
1963 EFI_STATUS
1964 SdMmcWaitTrbResult (
1965 IN SD_MMC_HC_PRIVATE_DATA *Private,
1966 IN SD_MMC_HC_TRB *Trb
1967 )
1968 {
1969 EFI_STATUS Status;
1970 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1971 UINT64 Timeout;
1972 BOOLEAN InfiniteWait;
1973
1974 Packet = Trb->Packet;
1975 //
1976 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1977 //
1978 Timeout = Packet->Timeout;
1979 if (Timeout == 0) {
1980 InfiniteWait = TRUE;
1981 } else {
1982 InfiniteWait = FALSE;
1983 }
1984
1985 while (InfiniteWait || (Timeout > 0)) {
1986 //
1987 // Check Trb execution result by reading Normal Interrupt Status register.
1988 //
1989 Status = SdMmcCheckTrbResult (Private, Trb);
1990 if (Status != EFI_NOT_READY) {
1991 return Status;
1992 }
1993 //
1994 // Stall for 1 microsecond.
1995 //
1996 gBS->Stall (1);
1997
1998 Timeout--;
1999 }
2000
2001 return EFI_TIMEOUT;
2002 }
2003
EFI Development Kit II mirror for PVE