MdeModulePkg/Bus/Pci/UhciDxe/Uhci.h

   1 /** @file
   2
   3 Copyright (c) 2004 - 2007, Intel Corporation
   4 All rights reserved. This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 Module Name:
  13
  14   Uhci.h
  15
  16 Abstract:
  17
  18   The definition for UHCI driver model and HC protocol routines.
  19
  20 Revision History
  21
  22
  23 **/
  24
  25 #ifndef _UHCI_H
  26 #define _UHCI_H
  27
  28
  29 #include <PiDxe.h>
  30
  31 #include <Protocol/Usb2HostController.h>
  32 #include <Protocol/UsbHostController.h>
  33 #include <Protocol/PciIo.h>
  34
  35 #include <Library/DebugLib.h>
  36 #include <Library/BaseMemoryLib.h>
  37 #include <Library/UefiDriverEntryPoint.h>
  38 #include <Library/UefiBootServicesTableLib.h>
  39 #include <Library/UefiLib.h>
  40 #include <Library/BaseLib.h>
  41 #include <Library/MemoryAllocationLib.h>
  42
  43 #include <IndustryStandard/Pci22.h>
  44
  45 typedef struct _USB_HC_DEV  USB_HC_DEV;
  46
  47 #include "UsbHcMem.h"
  48 #include "UhciQueue.h"
  49 #include "UhciReg.h"
  50 #include "UhciSched.h"
  51 #include "UhciDebug.h"
  52
  53 enum {
  54   UHC_1_MICROSECOND             = 1,
  55   UHC_1_MILLISECOND             = 1000 * UHC_1_MICROSECOND,
  56   UHC_1_SECOND                  = 1000 * UHC_1_MILLISECOND,
  57
  58   //
  59   // UHCI register operation timeout, set by experience
  60   //
  61   UHC_GENERIC_TIMEOUT           = UHC_1_SECOND,
  62
  63   //
  64   // Wait for force global resume(FGR) complete, refers to
  65   // specification[UHCI11-2.1.1]
  66   //
  67   UHC_FORCE_GLOBAL_RESUME_STALL = 20 * UHC_1_MILLISECOND,
  68
  69   //
  70   // Wait for roothub port reset and recovery, reset stall
  71   // is set by experience, and recovery stall refers to
  72   // specification[UHCI11-2.1.1]
  73   //
  74   UHC_ROOT_PORT_RESET_STALL     = 50 * UHC_1_MILLISECOND,
  75   UHC_ROOT_PORT_RECOVERY_STALL  = 10 * UHC_1_MILLISECOND,
  76
  77   //
  78   // Sync and Async transfer polling interval, set by experience,
  79   // and the unit of Async is 100us.
  80   //
  81   UHC_SYNC_POLL_INTERVAL        = 50 * UHC_1_MICROSECOND,
  82   UHC_ASYNC_POLL_INTERVAL       = 50 * 10000UL,
  83
  84   //
  85   // UHC raises TPL to TPL_NOTIFY to serialize all its operations
  86   // to protect shared data structures.
  87   //
  88   UHCI_TPL                 = TPL_NOTIFY,
  89
  90   USB_HC_DEV_SIGNATURE          = EFI_SIGNATURE_32 ('u', 'h', 'c', 'i')
  91 };
  92
  93 #pragma pack(1)
  94 typedef struct {
  95   UINT8               PI;
  96   UINT8               SubClassCode;
  97   UINT8               BaseCode;
  98 } USB_CLASSC;
  99 #pragma pack()
 100
 101 #define UHC_FROM_USB_HC_PROTO(This)   CR(This, USB_HC_DEV, UsbHc, USB_HC_DEV_SIGNATURE)
 102 #define UHC_FROM_USB2_HC_PROTO(This)  CR(This, USB_HC_DEV, Usb2Hc, USB_HC_DEV_SIGNATURE)
 103
 104 //
 105 // USB_HC_DEV support the UHCI hardware controller. It schedules
 106 // the asynchronous interrupt transfer with the same method as
 107 // EHCI: a reversed tree structure. For synchronous interrupt,
 108 // control and bulk transfer, it uses three static queue head to
 109 // schedule them. SyncIntQh is for interrupt transfer. LsCtrlQh is
 110 // for LOW speed control transfer, and FsCtrlBulkQh is for FULL
 111 // speed control or bulk transfer. This is because FULL speed contrl
 112 // or bulk transfer can reclaim the unused bandwidth. Some USB
 113 // device requires this bandwidth reclamation capability.
 114 //
 115 struct _USB_HC_DEV {
 116   UINT32                    Signature;
 117   EFI_USB_HC_PROTOCOL       UsbHc;
 118   EFI_USB2_HC_PROTOCOL      Usb2Hc;
 119   EFI_PCI_IO_PROTOCOL       *PciIo;
 120   UINT64                    OriginalPciAttributes;
 121
 122   //
 123   // Schedule data structures
 124   //
 125   UINT32                    *FrameBase;
 126   UHCI_QH_SW                *SyncIntQh;
 127   UHCI_QH_SW                *CtrlQh;
 128   UHCI_QH_SW                *BulkQh;
 129
 130   //
 131   // Structures to maintain asynchronus interrupt transfers.
 132   // When asynchronous interrutp transfer is unlinked from
 133   // the frame list, the hardware may still hold a pointer
 134   // to it. To synchronize with hardware, its resoureces are
 135   // released in two steps using Recycle and RecycleWait.
 136   // Check the asynchronous interrupt management routines.
 137   //
 138   LIST_ENTRY                AsyncIntList;
 139   EFI_EVENT                 AsyncIntMonitor;
 140   UHCI_ASYNC_REQUEST        *Recycle;
 141   UHCI_ASYNC_REQUEST        *RecycleWait;
 142
 143
 144   UINTN                     RootPorts;
 145   USBHC_MEM_POOL            *MemPool;
 146   EFI_UNICODE_STRING_TABLE  *CtrlNameTable;
 147   VOID                      *FrameMapping;
 148 };
 149
 150 extern EFI_DRIVER_BINDING_PROTOCOL   gUhciDriverBinding;
 151 extern EFI_COMPONENT_NAME_PROTOCOL   gUhciComponentName;
 152 extern EFI_COMPONENT_NAME2_PROTOCOL  gUhciComponentName2;
 153
 154 #endif