MdeModulePkg Xhci: Correct description of Timeout param in XhciReg.h
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciReg.h
1 /** @file
2
3 This file contains the register definition of XHCI host controller.
4
5 Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #ifndef _EFI_XHCI_REG_H_
17 #define _EFI_XHCI_REG_H_
18
19 #define PCI_IF_XHCI 0x30
20
21 //
22 // PCI Configuration Registers
23 //
24 #define XHC_BAR_INDEX 0x00
25
26 #define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset
27 #define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask
28
29 #define USB_HUB_CLASS_CODE 0x09
30 #define USB_HUB_SUBCLASS_CODE 0x00
31
32 #define XHC_CAP_USB_LEGACY 0x01
33 #define XHC_CAP_USB_DEBUG 0x0A
34
35 //============================================//
36 // XHCI register offset //
37 //============================================//
38
39 //
40 // Capability registers offset
41 //
42 #define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
43 #define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h
44 #define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1
45 #define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2
46 #define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3
47 #define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters
48 #define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset
49 #define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
50
51 //
52 // Operational registers offset
53 //
54 #define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
55 #define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
56 #define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
57 #define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
58 #define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
59 #define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
60 #define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
61 #define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
62
63 //
64 // Runtime registers offset
65 //
66 #define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset
67 #define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset
68 #define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset
69 #define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset
70 #define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
71 #define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
72
73 //
74 // Debug registers offset
75 //
76 #define XHC_DC_DCCTRL 0x20
77
78 #define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore
79 #define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore
80
81 #pragma pack (1)
82 typedef struct {
83 UINT8 MaxSlots; // Number of Device Slots
84 UINT16 MaxIntrs:11; // Number of Interrupters
85 UINT16 Rsvd:5;
86 UINT8 MaxPorts; // Number of Ports
87 } HCSPARAMS1;
88
89 //
90 // Structural Parameters 1 Register Bitmap Definition
91 //
92 typedef union {
93 UINT32 Dword;
94 HCSPARAMS1 Data;
95 } XHC_HCSPARAMS1;
96
97 typedef struct {
98 UINT32 Ist:4; // Isochronous Scheduling Threshold
99 UINT32 Erst:4; // Event Ring Segment Table Max
100 UINT32 Rsvd:13;
101 UINT32 ScratchBufHi:5; // Max Scratchpad Buffers Hi
102 UINT32 Spr:1; // Scratchpad Restore
103 UINT32 ScratchBufLo:5; // Max Scratchpad Buffers Lo
104 } HCSPARAMS2;
105
106 //
107 // Structural Parameters 2 Register Bitmap Definition
108 //
109 typedef union {
110 UINT32 Dword;
111 HCSPARAMS2 Data;
112 } XHC_HCSPARAMS2;
113
114 typedef struct {
115 UINT16 Ac64:1; // 64-bit Addressing Capability
116 UINT16 Bnc:1; // BW Negotiation Capability
117 UINT16 Csz:1; // Context Size
118 UINT16 Ppc:1; // Port Power Control
119 UINT16 Pind:1; // Port Indicators
120 UINT16 Lhrc:1; // Light HC Reset Capability
121 UINT16 Ltc:1; // Latency Tolerance Messaging Capability
122 UINT16 Nss:1; // No Secondary SID Support
123 UINT16 Pae:1; // Parse All Event Data
124 UINT16 Rsvd:3;
125 UINT16 MaxPsaSize:4; // Maximum Primary Stream Array Size
126 UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer
127 } HCCPARAMS;
128
129 //
130 // Capability Parameters Register Bitmap Definition
131 //
132 typedef union {
133 UINT32 Dword;
134 HCCPARAMS Data;
135 } XHC_HCCPARAMS;
136
137 #pragma pack ()
138
139 //
140 // Register Bit Definition
141 //
142 #define XHC_USBCMD_RUN BIT0 // Run/Stop
143 #define XHC_USBCMD_RESET BIT1 // Host Controller Reset
144 #define XHC_USBCMD_INTE BIT2 // Interrupter Enable
145 #define XHC_USBCMD_HSEE BIT3 // Host System Error Enable
146
147 #define XHC_USBSTS_HALT BIT0 // Host Controller Halted
148 #define XHC_USBSTS_HSE BIT2 // Host System Error
149 #define XHC_USBSTS_EINT BIT3 // Event Interrupt
150 #define XHC_USBSTS_PCD BIT4 // Port Change Detect
151 #define XHC_USBSTS_SSS BIT8 // Save State Status
152 #define XHC_USBSTS_RSS BIT9 // Restore State Status
153 #define XHC_USBSTS_SRE BIT10 // Save/Restore Error
154 #define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready
155 #define XHC_USBSTS_HCE BIT12 // Host Controller Error
156
157 #define XHC_PAGESIZE_MASK 0xFFFF // Page Size
158
159 #define XHC_CRCR_RCS BIT0 // Ring Cycle State
160 #define XHC_CRCR_CS BIT1 // Command Stop
161 #define XHC_CRCR_CA BIT2 // Command Abort
162 #define XHC_CRCR_CRR BIT3 // Command Ring Running
163
164 #define XHC_CONFIG_MASK 0xFF // Command Ring Running
165
166 #define XHC_PORTSC_CCS BIT0 // Current Connect Status
167 #define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
168 #define XHC_PORTSC_OCA BIT3 // Over-current Active
169 #define XHC_PORTSC_RESET BIT4 // Port Reset
170 #define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
171 #define XHC_PORTSC_PP BIT9 // Port Power
172 #define XHC_PORTSC_PS (BIT10|BIT11|BIT12) // Port Speed
173 #define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
174 #define XHC_PORTSC_CSC BIT17 // Connect Status Change
175 #define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
176 #define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
177 #define XHC_PORTSC_OCC BIT20 // Over-Current Change
178 #define XHC_PORTSC_PRC BIT21 // Port Reset Change
179 #define XHC_PORTSC_PLC BIT22 // Port Link State Change
180 #define XHC_PORTSC_CEC BIT23 // Port Config Error Change
181 #define XHC_PORTSC_CAS BIT24 // Cold Attach Status
182
183 #define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status
184 #define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled
185 #define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
186 #define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset
187 #define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
188 #define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
189 #define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change
190 #define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
191 #define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
192 #define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
193 #define XHC_IMAN_IP BIT0 // Interrupt Pending
194 #define XHC_IMAN_IE BIT1 // Interrupt Enable
195
196 #define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval
197 #define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter
198
199 //
200 // Hub Class Feature Selector for Clear Port Feature Request
201 // It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.
202 // For more details, Please refer to USB 3.0 Spec Table 10-7.
203 //
204 typedef enum {
205 Usb3PortBHPortReset = 28,
206 Usb3PortBHPortResetChange = 29
207 } XHC_PORT_FEATURE;
208
209 //
210 // Structure to map the hardware port states to the
211 // UEFI's port states.
212 //
213 typedef struct {
214 UINT32 HwState;
215 UINT16 UefiState;
216 } USB_PORT_STATE_MAP;
217
218 //
219 // Structure to map the hardware port states to feature selector for clear port feature request.
220 //
221 typedef struct {
222 UINT32 HwState;
223 UINT16 Selector;
224 } USB_CLEAR_PORT_MAP;
225
226 /**
227 Read 1-byte width XHCI capability register.
228
229 @param Xhc The XHCI Instance.
230 @param Offset The offset of the 1-byte width capability register.
231
232 @return The register content read.
233 @retval If err, return 0xFFFF.
234
235 **/
236 UINT8
237 XhcReadCapReg8 (
238 IN USB_XHCI_INSTANCE *Xhc,
239 IN UINT32 Offset
240 );
241
242 /**
243 Read 4-bytes width XHCI capability register.
244
245 @param Xhc The XHCI Instance.
246 @param Offset The offset of the 4-bytes width capability register.
247
248 @return The register content read.
249 @retval If err, return 0xFFFFFFFF.
250
251 **/
252 UINT32
253 XhcReadCapReg (
254 IN USB_XHCI_INSTANCE *Xhc,
255 IN UINT32 Offset
256 );
257
258 /**
259 Read 4-bytes width XHCI Operational register.
260
261 @param Xhc The XHCI Instance.
262 @param Offset The offset of the 4-bytes width operational register.
263
264 @return The register content read.
265 @retval If err, return 0xFFFFFFFF.
266
267 **/
268 UINT32
269 XhcReadOpReg (
270 IN USB_XHCI_INSTANCE *Xhc,
271 IN UINT32 Offset
272 );
273
274 /**
275 Write the data to the 4-bytes width XHCI operational register.
276
277 @param Xhc The XHCI Instance.
278 @param Offset The offset of the 4-bytes width operational register.
279 @param Data The data to write.
280
281 **/
282 VOID
283 XhcWriteOpReg (
284 IN USB_XHCI_INSTANCE *Xhc,
285 IN UINT32 Offset,
286 IN UINT32 Data
287 );
288
289 /**
290 Write the data to the 2-bytes width XHCI operational register.
291
292 @param Xhc The XHCI Instance.
293 @param Offset The offset of the 2-bytes width operational register.
294 @param Data The data to write.
295
296 **/
297 VOID
298 XhcWriteOpReg16 (
299 IN USB_XHCI_INSTANCE *Xhc,
300 IN UINT32 Offset,
301 IN UINT16 Data
302 );
303
304 /**
305 Read XHCI runtime register.
306
307 @param Xhc The XHCI Instance.
308 @param Offset The offset of the runtime register.
309
310 @return The register content read
311
312 **/
313 UINT32
314 XhcReadRuntimeReg (
315 IN USB_XHCI_INSTANCE *Xhc,
316 IN UINT32 Offset
317 );
318
319 /**
320 Write the data to the XHCI runtime register.
321
322 @param Xhc The XHCI Instance.
323 @param Offset The offset of the runtime register.
324 @param Data The data to write.
325
326 **/
327 VOID
328 XhcWriteRuntimeReg (
329 IN USB_XHCI_INSTANCE *Xhc,
330 IN UINT32 Offset,
331 IN UINT32 Data
332 );
333
334 /**
335 Read XHCI door bell register.
336
337 @param Xhc The XHCI Instance.
338 @param Offset The offset of the door bell register.
339
340 @return The register content read
341
342 **/
343 UINT32
344 XhcReadDoorBellReg (
345 IN USB_XHCI_INSTANCE *Xhc,
346 IN UINT32 Offset
347 );
348
349 /**
350 Write the data to the XHCI door bell register.
351
352 @param Xhc The XHCI Instance.
353 @param Offset The offset of the door bell register.
354 @param Data The data to write.
355
356 **/
357 VOID
358 XhcWriteDoorBellReg (
359 IN USB_XHCI_INSTANCE *Xhc,
360 IN UINT32 Offset,
361 IN UINT32 Data
362 );
363
364 /**
365 Set one bit of the operational register while keeping other bits.
366
367 @param Xhc The XHCI Instance.
368 @param Offset The offset of the operational register.
369 @param Bit The bit mask of the register to set.
370
371 **/
372 VOID
373 XhcSetOpRegBit (
374 IN USB_XHCI_INSTANCE *Xhc,
375 IN UINT32 Offset,
376 IN UINT32 Bit
377 );
378
379 /**
380 Clear one bit of the operational register while keeping other bits.
381
382 @param Xhc The XHCI Instance.
383 @param Offset The offset of the operational register.
384 @param Bit The bit mask of the register to clear.
385
386 **/
387 VOID
388 XhcClearOpRegBit (
389 IN USB_XHCI_INSTANCE *Xhc,
390 IN UINT32 Offset,
391 IN UINT32 Bit
392 );
393
394 /**
395 Wait the operation register's bit as specified by Bit
396 to be set (or clear).
397
398 @param Xhc The XHCI Instance.
399 @param Offset The offset of the operational register.
400 @param Bit The bit of the register to wait for.
401 @param WaitToSet Wait the bit to set or clear.
402 @param Timeout The time to wait before abort (in millisecond, ms).
403
404 @retval EFI_SUCCESS The bit successfully changed by host controller.
405 @retval EFI_TIMEOUT The time out occurred.
406
407 **/
408 EFI_STATUS
409 XhcWaitOpRegBit (
410 IN USB_XHCI_INSTANCE *Xhc,
411 IN UINT32 Offset,
412 IN UINT32 Bit,
413 IN BOOLEAN WaitToSet,
414 IN UINT32 Timeout
415 );
416
417 /**
418 Read XHCI runtime register.
419
420 @param Xhc The XHCI Instance.
421 @param Offset The offset of the runtime register.
422
423 @return The register content read
424
425 **/
426 UINT32
427 XhcReadRuntimeReg (
428 IN USB_XHCI_INSTANCE *Xhc,
429 IN UINT32 Offset
430 );
431
432 /**
433 Write the data to the XHCI runtime register.
434
435 @param Xhc The XHCI Instance.
436 @param Offset The offset of the runtime register.
437 @param Data The data to write.
438
439 **/
440 VOID
441 XhcWriteRuntimeReg (
442 IN USB_XHCI_INSTANCE *Xhc,
443 IN UINT32 Offset,
444 IN UINT32 Data
445 );
446
447 /**
448 Set one bit of the runtime register while keeping other bits.
449
450 @param Xhc The XHCI Instance.
451 @param Offset The offset of the runtime register.
452 @param Bit The bit mask of the register to set.
453
454 **/
455 VOID
456 XhcSetRuntimeRegBit (
457 IN USB_XHCI_INSTANCE *Xhc,
458 IN UINT32 Offset,
459 IN UINT32 Bit
460 );
461
462 /**
463 Clear one bit of the runtime register while keeping other bits.
464
465 @param Xhc The XHCI Instance.
466 @param Offset The offset of the runtime register.
467 @param Bit The bit mask of the register to set.
468
469 **/
470 VOID
471 XhcClearRuntimeRegBit (
472 IN USB_XHCI_INSTANCE *Xhc,
473 IN UINT32 Offset,
474 IN UINT32 Bit
475 );
476
477 /**
478 Read XHCI extended capability register.
479
480 @param Xhc The XHCI Instance.
481 @param Offset The offset of the extended capability register.
482
483 @return The register content read
484
485 **/
486 UINT32
487 XhcReadExtCapReg (
488 IN USB_XHCI_INSTANCE *Xhc,
489 IN UINT32 Offset
490 );
491
492 /**
493 Whether the XHCI host controller is halted.
494
495 @param Xhc The XHCI Instance.
496
497 @retval TRUE The controller is halted.
498 @retval FALSE It isn't halted.
499
500 **/
501 BOOLEAN
502 XhcIsHalt (
503 IN USB_XHCI_INSTANCE *Xhc
504 );
505
506 /**
507 Whether system error occurred.
508
509 @param Xhc The XHCI Instance.
510
511 @retval TRUE System error happened.
512 @retval FALSE No system error.
513
514 **/
515 BOOLEAN
516 XhcIsSysError (
517 IN USB_XHCI_INSTANCE *Xhc
518 );
519
520 /**
521 Reset the XHCI host controller.
522
523 @param Xhc The XHCI Instance.
524 @param Timeout Time to wait before abort (in millisecond, ms).
525
526 @retval EFI_SUCCESS The XHCI host controller is reset.
527 @return Others Failed to reset the XHCI before Timeout.
528
529 **/
530 EFI_STATUS
531 XhcResetHC (
532 IN USB_XHCI_INSTANCE *Xhc,
533 IN UINT32 Timeout
534 );
535
536 /**
537 Halt the XHCI host controller.
538
539 @param Xhc The XHCI Instance.
540 @param Timeout Time to wait before abort (in millisecond, ms).
541
542 @return EFI_SUCCESS The XHCI host controller is halt.
543 @return EFI_TIMEOUT Failed to halt the XHCI before Timeout.
544
545 **/
546 EFI_STATUS
547 XhcHaltHC (
548 IN USB_XHCI_INSTANCE *Xhc,
549 IN UINT32 Timeout
550 );
551
552 /**
553 Set the XHCI host controller to run.
554
555 @param Xhc The XHCI Instance.
556 @param Timeout Time to wait before abort (in millisecond, ms).
557
558 @return EFI_SUCCESS The XHCI host controller is running.
559 @return EFI_TIMEOUT Failed to set the XHCI to run before Timeout.
560
561 **/
562 EFI_STATUS
563 XhcRunHC (
564 IN USB_XHCI_INSTANCE *Xhc,
565 IN UINT32 Timeout
566 );
567
568 /**
569 Calculate the offset of the XHCI capability.
570
571 @param Xhc The XHCI Instance.
572 @param CapId The XHCI Capability ID.
573
574 @return The offset of XHCI legacy support capability register.
575
576 **/
577 UINT32
578 XhcGetCapabilityAddr (
579 IN USB_XHCI_INSTANCE *Xhc,
580 IN UINT8 CapId
581 );
582
583 #endif