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Enabling usb3.0 XHCI support.
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciSched.c
1 /** @file
2
3 XHCI transfer scheduling routines.
4
5 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #include "Xhci.h"
17
18 /**
19 Allocates a buffer of a certain pool type at a specified alignment.
20
21 Allocates the number bytes specified by AllocationSize of a certain pool type with an alignment
22 specified by Alignment. The allocated buffer is returned. If AllocationSize is 0, then a valid
23 buffer of 0 size is returned. If there is not enough memory at the specified alignment remaining
24 to satisfy the request, then NULL is returned.
25 If Alignment is not a power of two and Alignment is not zero, then ASSERT().
26
27 @param PoolType The type of pool to allocate.
28 @param AllocationSize The number of bytes to allocate.
29 @param Alignment The requested alignment of the allocation. Must be a power of two.
30 If Alignment is zero, then byte alignment is used.
31
32 @return A pointer to the allocated buffer or NULL if allocation fails.
33
34 **/
35 VOID *
36 InternalAllocateAlignedPool (
37 IN EFI_MEMORY_TYPE PoolType,
38 IN UINTN AllocationSize,
39 IN UINTN Alignment
40 )
41 {
42 VOID *RawAddress;
43 UINTN AlignedAddress;
44 UINTN AlignmentMask;
45 UINTN OverAllocationSize;
46 UINTN RealAllocationSize;
47 VOID **FreePointer;
48
49 //
50 // Alignment must be a power of two or zero.
51 //
52 ASSERT ((Alignment & (Alignment - 1)) == 0);
53
54 if (Alignment == 0) {
55 AlignmentMask = Alignment;
56 } else {
57 AlignmentMask = Alignment - 1;
58 }
59 //
60 // Calculate the extra memory size, over-allocate memory pool and get the aligned memory address.
61 //
62 OverAllocationSize = sizeof (RawAddress) + AlignmentMask;
63 RealAllocationSize = AllocationSize + OverAllocationSize;
64 //
65 // Make sure that AllocationSize plus OverAllocationSize does not overflow.
66 //
67 ASSERT (RealAllocationSize > AllocationSize);
68
69 RawAddress = NULL;
70 gBS->AllocatePool (PoolType, RealAllocationSize, &RawAddress);
71 if (RawAddress == NULL) {
72 return NULL;
73 }
74 AlignedAddress = ((UINTN) RawAddress + OverAllocationSize) & ~AlignmentMask;
75 //
76 // Save the original memory address just before the aligned address.
77 //
78 FreePointer = (VOID **)(AlignedAddress - sizeof (RawAddress));
79 *FreePointer = RawAddress;
80
81 return (VOID *) AlignedAddress;
82 }
83
84 /**
85 Allocates and zeros a buffer of a certain pool type at a specified alignment.
86
87 Allocates the number bytes specified by AllocationSize of a certain pool type with an alignment
88 specified by Alignment, clears the buffer with zeros, and returns a pointer to the allocated
89 buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there is not
90 enough memory at the specified alignment remaining to satisfy the request, then NULL is returned.
91 If Alignment is not a power of two and Alignment is not zero, then ASSERT().
92
93 @param PoolType The type of pool to allocate.
94 @param AllocationSize The number of bytes to allocate.
95 @param Alignment The requested alignment of the allocation. Must be a power of two.
96 If Alignment is zero, then byte alignment is used.
97
98 @return A pointer to the allocated buffer or NULL if allocation fails.
99
100 **/
101 VOID *
102 InternalAllocateAlignedZeroPool (
103 IN EFI_MEMORY_TYPE PoolType,
104 IN UINTN AllocationSize,
105 IN UINTN Alignment
106 )
107 {
108 VOID *Memory;
109 Memory = InternalAllocateAlignedPool (PoolType, AllocationSize, Alignment);
110 if (Memory != NULL) {
111 ZeroMem (Memory, AllocationSize);
112 }
113 return Memory;
114 }
115
116 /**
117 Allocates and zeros a buffer of type EfiBootServicesData at a specified alignment.
118
119 Allocates the number bytes specified by AllocationSize of type EfiBootServicesData with an
120 alignment specified by Alignment, clears the buffer with zeros, and returns a pointer to the
121 allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there
122 is not enough memory at the specified alignment remaining to satisfy the request, then NULL is
123 returned.
124 If Alignment is not a power of two and Alignment is not zero, then ASSERT().
125
126 @param AllocationSize The number of bytes to allocate.
127 @param Alignment The requested alignment of the allocation. Must be a power of two.
128 If Alignment is zero, then byte alignment is used.
129
130 @return A pointer to the allocated buffer or NULL if allocation fails.
131
132 **/
133 VOID *
134 EFIAPI
135 AllocateAlignedZeroPool (
136 IN UINTN AllocationSize,
137 IN UINTN Alignment
138 )
139 {
140 return InternalAllocateAlignedZeroPool (EfiBootServicesData, AllocationSize, Alignment);
141 }
142
143 /**
144 Frees a buffer that was previously allocated with one of the aligned pool allocation functions
145 in the Memory Allocation Library.
146
147 Frees the buffer specified by Buffer. Buffer must have been allocated on a previous call to the
148 aligned pool allocation services of the Memory Allocation Library.
149 If Buffer was not allocated with an aligned pool allocation function in the Memory Allocation
150 Library, then ASSERT().
151
152 @param Buffer Pointer to the buffer to free.
153
154 **/
155 VOID
156 EFIAPI
157 FreeAlignedPool (
158 IN VOID *Buffer
159 )
160 {
161 VOID *RawAddress;
162 VOID **FreePointer;
163 EFI_STATUS Status;
164
165 //
166 // Get the pre-saved original address in the over-allocate pool.
167 //
168 FreePointer = (VOID **)((UINTN) Buffer - sizeof (RawAddress));
169 RawAddress = *FreePointer;
170
171 Status = gBS->FreePool (RawAddress);
172 ASSERT_EFI_ERROR (Status);
173 }
174
175 /**
176 Create a command transfer TRB to support XHCI command interfaces.
177
178 @param Xhc The XHCI device.
179 @param CmdTrb The cmd TRB to be executed.
180
181 @return Created URB or NULL.
182
183 **/
184 URB*
185 XhcCreateCmdTrb (
186 IN USB_XHCI_DEV *Xhc,
187 IN TRB *CmdTrb
188 )
189 {
190 URB *Urb;
191
192 Urb = AllocateZeroPool (sizeof (URB));
193 if (Urb == NULL) {
194 return NULL;
195 }
196
197 Urb->Signature = XHC_URB_SIG;
198
199 Urb->Ring = &Xhc->CmdRing;
200 XhcSyncTrsRing (Xhc, Urb->Ring);
201 Urb->TrbNum = 1;
202 Urb->TrbStart = Urb->Ring->RingEnqueue;
203 CopyMem (Urb->TrbStart, CmdTrb, sizeof (TRB));
204 Urb->TrbStart->CycleBit = Urb->Ring->RingPCS & BIT0;
205 Urb->TrbEnd = Urb->TrbStart;
206
207 Urb->EvtRing = &Xhc->CmdEventRing;
208 XhcSyncEventRing (Xhc, Urb->EvtRing);
209 Urb->EvtTrbStart = Urb->EvtRing->EventRingEnqueue;
210
211 return Urb;
212 }
213
214 /**
215 Execute a XHCI cmd TRB pointed by CmdTrb.
216
217 @param Xhc The XHCI device.
218 @param CmdTrb The cmd TRB to be executed.
219 @param TimeOut Indicates the maximum time, in millisecond, which the
220 transfer is allowed to complete.
221 @param EvtTrb The event TRB corresponding to the cmd TRB.
222
223 @retval EFI_SUCCESS The transfer was completed successfully.
224 @retval EFI_INVALID_PARAMETER Some parameters are invalid.
225 @retval EFI_TIMEOUT The transfer failed due to timeout.
226 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
227
228 **/
229 EFI_STATUS
230 EFIAPI
231 XhcCmdTransfer (
232 IN USB_XHCI_DEV *Xhc,
233 IN TRB *CmdTrb,
234 IN UINTN TimeOut,
235 OUT TRB **EvtTrb
236 )
237 {
238 EFI_STATUS Status;
239 URB *Urb;
240
241 //
242 // Validate the parameters
243 //
244 if ((Xhc == NULL) || (CmdTrb == NULL)) {
245 return EFI_INVALID_PARAMETER;
246 }
247
248 Status = EFI_DEVICE_ERROR;
249
250 if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
251 DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: HC is halted\n"));
252 goto ON_EXIT;
253 }
254
255 //
256 // Create a new URB, then poll the execution status.
257 //
258 Urb = XhcCreateCmdTrb (Xhc, CmdTrb);
259
260 if (Urb == NULL) {
261 DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: failed to create URB\n"));
262 Status = EFI_OUT_OF_RESOURCES;
263 goto ON_EXIT;
264 }
265
266 ASSERT (Urb->EvtRing == &Xhc->CmdEventRing);
267
268 Status = XhcExecTransfer (Xhc, TRUE, Urb, TimeOut);
269 *EvtTrb = Urb->EvtTrbStart;
270
271 if (Urb->Result == EFI_USB_NOERROR) {
272 Status = EFI_SUCCESS;
273 }
274
275 FreePool (Urb);
276
277 ON_EXIT:
278 return Status;
279 }
280
281 /**
282 Create a new URB for a new transaction.
283
284 @param Xhc The XHCI device
285 @param DevAddr The device address
286 @param EpAddr Endpoint addrress
287 @param DevSpeed The device speed
288 @param MaxPacket The max packet length of the endpoint
289 @param Type The transaction type
290 @param Request The standard USB request for control transfer
291 @param Data The user data to transfer
292 @param DataLen The length of data buffer
293 @param Callback The function to call when data is transferred
294 @param Context The context to the callback
295
296 @return Created URB or NULL
297
298 **/
299 URB*
300 XhcCreateUrb (
301 IN USB_XHCI_DEV *Xhc,
302 IN UINT8 DevAddr,
303 IN UINT8 EpAddr,
304 IN UINT8 DevSpeed,
305 IN UINTN MaxPacket,
306 IN UINTN Type,
307 IN EFI_USB_DEVICE_REQUEST *Request,
308 IN VOID *Data,
309 IN UINTN DataLen,
310 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
311 IN VOID *Context
312 )
313 {
314 USB_ENDPOINT *Ep;
315 EFI_STATUS Status;
316 URB *Urb;
317
318 Urb = AllocateZeroPool (sizeof (URB));
319 if (Urb == NULL) {
320 return NULL;
321 }
322
323 Urb->Signature = XHC_URB_SIG;
324 InitializeListHead (&Urb->UrbList);
325
326 Ep = &Urb->Ep;
327 Ep->DevAddr = DevAddr;
328 Ep->EpAddr = EpAddr & 0x0F;
329 Ep->Direction = ((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;
330 Ep->DevSpeed = DevSpeed;
331 Ep->MaxPacket = MaxPacket;
332 Ep->Type = Type;
333
334 Urb->Request = Request;
335 Urb->Data = Data;
336 Urb->DataLen = DataLen;
337 Urb->Callback = Callback;
338 Urb->Context = Context;
339
340 Status = XhcCreateTransferTrb (Xhc, Urb);
341
342 return Urb;
343 }
344
345 /**
346 Create a transfer TRB.
347
348 @param Xhc The XHCI device
349 @param Urb The urb used to construct the transfer TRB.
350
351 @return Created TRB or NULL
352
353 **/
354 EFI_STATUS
355 EFIAPI
356 XhcCreateTransferTrb (
357 IN USB_XHCI_DEV *Xhc,
358 IN URB *Urb
359 )
360 {
361 DEVICE_CONTEXT *OutputDevContxt;
362 TRANSFER_RING *EPRing;
363 UINT8 EPType;
364 UINT8 SlotId;
365 UINT8 Dci;
366 TRB *TrbStart;
367 UINTN TotalLen;
368 UINTN Len;
369 UINTN TrbNum;
370
371 SlotId = XhcDevAddrToSlotId(Urb->Ep.DevAddr);
372 Dci = XhcEndpointToDci (Urb->Ep.EpAddr, Urb->Ep.Direction);
373 EPRing = (TRANSFER_RING *)(UINTN) UsbDevContext[SlotId].EndpointTransferRing[Dci-1];
374 Urb->Ring = EPRing;
375 OutputDevContxt = (DEVICE_CONTEXT *)(UINTN) Xhc->DCBAA[SlotId];
376 EPType = (UINT8) OutputDevContxt->EP[Dci-1].EPType;
377
378 //
379 // Construct the TRB
380 //
381 XhcSyncTrsRing (Xhc, EPRing);
382 Urb->TrbStart = EPRing->RingEnqueue;
383 switch (EPType) {
384 case ED_CONTROL_BIDIR:
385 Urb->EvtRing = &Xhc->CtrlTrEventRing;
386 XhcSyncEventRing (Xhc, Urb->EvtRing);
387 Urb->EvtTrbStart = Urb->EvtRing->EventRingEnqueue;
388 //
389 // For control transfer, create SETUP_STAGE_TRB first.
390 //
391 TrbStart = EPRing->RingEnqueue;
392 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->bmRequestType = Urb->Request->RequestType;
393 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->bRequest = Urb->Request->Request;
394 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->wValue = Urb->Request->Value;
395 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->wIndex = Urb->Request->Index;
396 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->wLength = Urb->Request->Length;
397 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->Lenth = 8;
398 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->IntTarget = Urb->EvtRing->EventInterrupter;
399 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->IOC = 1;
400 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->IDT = 1;
401 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->Type = TRB_TYPE_SETUP_STAGE;
402 if (Urb->Ep.Direction == EfiUsbDataIn) {
403 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->TRT = 3;
404 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
405 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->TRT = 2;
406 } else {
407 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->TRT = 0;
408 }
409 //
410 // Update the cycle bit
411 //
412 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->CycleBit = EPRing->RingPCS & BIT0;
413 Urb->TrbNum++;
414
415 //
416 // For control transfer, create DATA_STAGE_TRB.
417 //
418 if (Urb->DataLen > 0) {
419 XhcSyncTrsRing (Xhc, EPRing);
420 TrbStart = EPRing->RingEnqueue;
421 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->TRBPtrLo = XHC_LOW_32BIT(Urb->Data);
422 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->TRBPtrHi = XHC_HIGH_32BIT(Urb->Data);
423 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->Lenth = (UINT32) Urb->DataLen;
424 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->TDSize = 0;
425 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->IntTarget = Urb->EvtRing->EventInterrupter;
426 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->ISP = 1;
427 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->IOC = 1;
428 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->IDT = 0;
429 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->CH = 0;
430 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->Type = TRB_TYPE_DATA_STAGE;
431 if (Urb->Ep.Direction == EfiUsbDataIn) {
432 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->DIR = 1;
433 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
434 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->DIR = 0;
435 } else {
436 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->DIR = 0;
437 }
438 //
439 // Update the cycle bit
440 //
441 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->CycleBit = EPRing->RingPCS & BIT0;
442 Urb->TrbNum++;
443 }
444 //
445 // For control transfer, create STATUS_STAGE_TRB.
446 // Get the pointer to next TRB for status stage use
447 //
448 XhcSyncTrsRing (Xhc, EPRing);
449 TrbStart = EPRing->RingEnqueue;
450 ((TRANSFER_TRB_CONTROL_STATUS *) TrbStart)->IntTarget = Urb->EvtRing->EventInterrupter;
451 ((TRANSFER_TRB_CONTROL_STATUS *) TrbStart)->IOC = 1;
452 ((TRANSFER_TRB_CONTROL_STATUS *) TrbStart)->CH = 0;
453 ((TRANSFER_TRB_CONTROL_STATUS *) TrbStart)->Type = TRB_TYPE_STATUS_STAGE;
454 if (Urb->Ep.Direction == EfiUsbDataIn) {
455 ((TRANSFER_TRB_CONTROL_STATUS *) TrbStart)->DIR = 0;
456 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
457 ((TRANSFER_TRB_CONTROL_STATUS *) TrbStart)->DIR = 1;
458 } else {
459 ((TRANSFER_TRB_CONTROL_STATUS *) TrbStart)->DIR = 0;
460 }
461 //
462 // Update the cycle bit
463 //
464 ((TRANSFER_TRB_CONTROL_STATUS *) TrbStart)->CycleBit = EPRing->RingPCS & BIT0;
465 //
466 // Update the enqueue pointer
467 //
468 XhcSyncTrsRing (Xhc, EPRing);
469 Urb->TrbNum++;
470 Urb->TrbEnd = TrbStart;
471
472 break;
473
474 case ED_BULK_OUT:
475 case ED_BULK_IN:
476 Urb->EvtRing = &Xhc->BulkTrEventRing;
477 XhcSyncEventRing (Xhc, Urb->EvtRing);
478 Urb->EvtTrbStart = Urb->EvtRing->EventRingEnqueue;
479
480 TotalLen = 0;
481 Len = 0;
482 TrbNum = 0;
483 TrbStart = EPRing->RingEnqueue;
484 while (TotalLen < Urb->DataLen) {
485 if ((TotalLen + 0x10000) >= Urb->DataLen) {
486 Len = Urb->DataLen - TotalLen;
487 } else {
488 Len = 0x10000;
489 }
490 TrbStart = EPRing->RingEnqueue;
491 ((TRANSFER_TRB_NORMAL *) TrbStart)->TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->Data + TotalLen);
492 ((TRANSFER_TRB_NORMAL *) TrbStart)->TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->Data + TotalLen);
493 ((TRANSFER_TRB_NORMAL *) TrbStart)->Lenth = (UINT32) Len;
494 ((TRANSFER_TRB_NORMAL *) TrbStart)->TDSize = 0;
495 ((TRANSFER_TRB_NORMAL *) TrbStart)->IntTarget = Urb->EvtRing->EventInterrupter;
496 ((TRANSFER_TRB_NORMAL *) TrbStart)->ISP = 1;
497 ((TRANSFER_TRB_NORMAL *) TrbStart)->IOC = 1;
498 ((TRANSFER_TRB_NORMAL *) TrbStart)->Type = TRB_TYPE_NORMAL;
499 //
500 // Update the cycle bit
501 //
502 ((TRANSFER_TRB_NORMAL *) TrbStart)->CycleBit = EPRing->RingPCS & BIT0;
503
504 XhcSyncTrsRing (Xhc, EPRing);
505 TrbNum++;
506 TotalLen += Len;
507 }
508
509 Urb->TrbNum = TrbNum;
510 Urb->TrbEnd = TrbStart;
511 break;
512
513 case ED_INTERRUPT_OUT:
514 case ED_INTERRUPT_IN:
515 if (Urb->Ep.Type == XHC_INT_TRANSFER_ASYNC) {
516 Urb->EvtRing = &Xhc->AsynIntTrEventRing;
517 } else if(Urb->Ep.Type == XHC_INT_TRANSFER_SYNC){
518 Urb->EvtRing = &Xhc->IntTrEventRing;
519 } else {
520 DEBUG ((EFI_D_ERROR, "EP Interrupt type error!\n"));
521 ASSERT(FALSE);
522 }
523 XhcSyncEventRing (Xhc, Urb->EvtRing);
524 Urb->EvtTrbStart = Urb->EvtRing->EventRingEnqueue;
525
526 TotalLen = 0;
527 Len = 0;
528 TrbNum = 0;
529 TrbStart = EPRing->RingEnqueue;
530 while (TotalLen < Urb->DataLen) {
531 if ((TotalLen + 0x10000) >= Urb->DataLen) {
532 Len = Urb->DataLen - TotalLen;
533 } else {
534 Len = 0x10000;
535 }
536 TrbStart = EPRing->RingEnqueue;
537 ((TRANSFER_TRB_NORMAL *) TrbStart)->TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->Data + TotalLen);
538 ((TRANSFER_TRB_NORMAL *) TrbStart)->TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->Data + TotalLen);
539 ((TRANSFER_TRB_NORMAL *) TrbStart)->Lenth = (UINT32) Len;
540 ((TRANSFER_TRB_NORMAL *) TrbStart)->TDSize = 0;
541 ((TRANSFER_TRB_NORMAL *) TrbStart)->IntTarget = Urb->EvtRing->EventInterrupter;
542 ((TRANSFER_TRB_NORMAL *) TrbStart)->ISP = 1;
543 ((TRANSFER_TRB_NORMAL *) TrbStart)->IOC = 1;
544 ((TRANSFER_TRB_NORMAL *) TrbStart)->Type = TRB_TYPE_NORMAL;
545 //
546 // Update the cycle bit
547 //
548 ((TRANSFER_TRB_NORMAL *) TrbStart)->CycleBit = EPRing->RingPCS & BIT0;
549
550 XhcSyncTrsRing (Xhc, EPRing);
551 TrbNum++;
552 TotalLen += Len;
553 }
554
555 Urb->TrbNum = TrbNum;
556 Urb->TrbEnd = TrbStart;
557 break;
558
559 default:
560 DEBUG ((EFI_D_INFO, "Not supported EPType 0x%x!\n",EPType));
561 ASSERT (FALSE);
562 break;
563 }
564
565 return EFI_SUCCESS;
566 }
567
568
569 /**
570 Initialize the XHCI host controller for schedule.
571
572 @param Xhc The XHCI device to be initialized.
573
574 **/
575 VOID
576 XhcInitSched (
577 IN USB_XHCI_DEV *Xhc
578 )
579 {
580 VOID *Dcbaa;
581 UINT64 CmdRing;
582 UINTN Entries;
583 UINT32 MaxScratchpadBufs;
584 UINT64 *ScratchBuf;
585 UINT64 *ScratchEntryBuf;
586 UINT32 Index;
587
588 //
589 // Program the Max Device Slots Enabled (MaxSlotsEn) field in the CONFIG register (5.4.7)
590 // to enable the device slots that system software is going to use.
591 //
592 Xhc->MaxSlotsEn = Xhc->HcSParams1.Data.MaxSlots;
593 ASSERT (Xhc->MaxSlotsEn >= 1 && Xhc->MaxSlotsEn <= 255);
594 XhcWriteOpReg (Xhc, XHC_CONFIG_OFFSET, Xhc->MaxSlotsEn);
595
596 //
597 // The Device Context Base Address Array entry associated with each allocated Device Slot
598 // shall contain a 64-bit pointer to the base of the associated Device Context.
599 // The Device Context Base Address Array shall contain MaxSlotsEn + 1 entries.
600 // Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.
601 //
602 Entries = (Xhc->MaxSlotsEn + 1) * sizeof(UINT64);
603 Dcbaa = AllocateAlignedZeroPool(Entries, 64);
604 ASSERT (Dcbaa != NULL);
605
606 //
607 // A Scratchpad Buffer is a PAGESIZE block of system memory located on a PAGESIZE boundary.
608 // System software shall allocate the Scratchpad Buffer(s) before placing the xHC in to Run
609 // mode (Run/Stop(R/S) ='1').
610 //
611 MaxScratchpadBufs = ((Xhc->HcSParams2.Data.ScratchBufHi) << 5) | (Xhc->HcSParams2.Data.ScratchBufLo);
612 Xhc->MaxScratchpadBufs = MaxScratchpadBufs;
613 ASSERT (MaxScratchpadBufs >= 0 && MaxScratchpadBufs <= 1023);
614 if (MaxScratchpadBufs != 0) {
615 ScratchBuf = AllocateAlignedZeroPool(MaxScratchpadBufs * sizeof (UINT64), Xhc->PageSize);
616 ASSERT (ScratchBuf != NULL);
617 Xhc->ScratchBuf = ScratchBuf;
618
619 for (Index = 0; Index < MaxScratchpadBufs; Index++) {
620 ScratchEntryBuf = AllocateAlignedZeroPool(Xhc->PageSize, Xhc->PageSize);
621 *ScratchBuf++ = (UINT64)(UINTN)ScratchEntryBuf;
622 }
623
624 //
625 // The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the
626 // Device Context Base Address Array points to the Scratchpad Buffer Array.
627 //
628 *(UINT64 *)Dcbaa = (UINT64)(UINTN)Xhc->ScratchBuf;
629 }
630
631 //
632 // Program the Device Context Base Address Array Pointer (DCBAAP) register (5.4.6) with
633 // a 64-bit address pointing to where the Device Context Base Address Array is located.
634 //
635 Xhc->DCBAA = (UINT64 *)(UINTN)Dcbaa;
636 XhcWriteOpReg64 (Xhc, XHC_DCBAAP_OFFSET, (UINT64)Xhc->DCBAA);
637 DEBUG ((EFI_D_INFO, "XhcInitSched:DCBAA=0x%x\n", (UINT64)Xhc->DCBAA));
638
639 //
640 // Define the Command Ring Dequeue Pointer by programming the Command Ring Control Register
641 // (5.4.5) with a 64-bit address pointing to the starting address of the first TRB of the Command Ring.
642 // Note: The Command Ring is 64 byte aligned, so the low order 6 bits of the Command Ring Pointer shall
643 // always be '0'.
644 //
645 CreateTransferRing (Xhc, CMD_RING_TRB_NUMBER, &Xhc->CmdRing);
646 //
647 // The xHC uses the Enqueue Pointer to determine when a Transfer Ring is empty. As it fetches TRBs from a
648 // Transfer Ring it checks for a Cycle bit transition. If a transition detected, the ring is empty.
649 // So we set RCS as inverted PCS init value to let Command Ring empty
650 //
651 CmdRing = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0;
652 ASSERT ((CmdRing & 0x3F) == 0);
653 CmdRing |= XHC_CRCR_RCS;
654 XhcWriteOpReg64 (Xhc, XHC_CRCR_OFFSET, CmdRing);
655
656 DEBUG ((EFI_D_INFO, "XhcInitSched:XHC_CRCR=0x%x\n", Xhc->CmdRing.RingSeg0));
657
658 //
659 // Disable the 'interrupter enable' bit in USB_CMD
660 // and clear IE & IP bit in all Interrupter X Management Registers.
661 //
662 XhcClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_INTE);
663 for (Index = 0; Index < (UINT16)(Xhc->HcSParams1.Data.MaxIntrs); Index++) {
664 XhcClearRuntimeRegBit (Xhc, XHC_IMAN_OFFSET + (Index * 32), XHC_IMAN_IE);
665 XhcSetRuntimeRegBit (Xhc, XHC_IMAN_OFFSET + (Index * 32), XHC_IMAN_IP);
666 }
667
668 //
669 // Allocate EventRing for Cmd, Ctrl, Bulk, Interrupt, AsynInterrupt transfer
670 //
671 CreateEventRing (Xhc, CMD_INTER, &Xhc->CmdEventRing);
672 CreateEventRing (Xhc, CTRL_INTER, &Xhc->CtrlTrEventRing);
673 CreateEventRing (Xhc, BULK_INTER, &Xhc->BulkTrEventRing);
674 CreateEventRing (Xhc, INT_INTER, &Xhc->IntTrEventRing);
675 CreateEventRing (Xhc, INT_INTER_ASYNC, &Xhc->AsynIntTrEventRing);
676 }
677
678 /**
679 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted
680 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint
681 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is
682 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the
683 Stopped to the Running state.
684
685 @param Xhc The XHCI device.
686 @param Urb The urb which makes the endpoint halted.
687
688 @retval EFI_SUCCESS The recovery is successful.
689 @retval Others Failed to recovery halted endpoint.
690
691 **/
692 EFI_STATUS
693 EFIAPI
694 XhcRecoverHaltedEndpoint (
695 IN USB_XHCI_DEV *Xhc,
696 IN URB *Urb
697 )
698 {
699 EFI_STATUS Status;
700 EVT_TRB_COMMAND *EvtTrb;
701 CMD_TRB_RESET_ED CmdTrbResetED;
702 CMD_SET_TR_DEQ CmdSetTRDeq;
703 UINT8 Dci;
704 UINT8 SlotId;
705
706 Status = EFI_SUCCESS;
707 SlotId = XhcDevAddrToSlotId(Urb->Ep.DevAddr);
708 Dci = XhcEndpointToDci(Urb->Ep.EpAddr, Urb->Ep.Direction);
709
710 DEBUG ((EFI_D_INFO, "Recovery Halted Slot = %x,Dci = %x\n", SlotId, Dci));
711
712 //
713 // 1) Send Reset endpoint command to transit from halt to stop state
714 //
715 ZeroMem (&CmdTrbResetED, sizeof (CmdTrbResetED));
716 CmdTrbResetED.CycleBit = 1;
717 CmdTrbResetED.Type = TRB_TYPE_RESET_ENDPOINT;
718 CmdTrbResetED.EDID = Dci;
719 CmdTrbResetED.SlotId = SlotId;
720 Status = XhcCmdTransfer (
721 Xhc,
722 (TRB *) (UINTN) &CmdTrbResetED,
723 XHC_GENERIC_TIMEOUT,
724 (TRB **) (UINTN) &EvtTrb
725 );
726 ASSERT (!EFI_ERROR(Status));
727
728 //
729 // 2)Set dequeue pointer
730 //
731 ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));
732 CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (Urb->Ring->RingEnqueue) | Urb->Ring->RingPCS;
733 CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (Urb->Ring->RingEnqueue);
734 CmdSetTRDeq.CycleBit = 1;
735 CmdSetTRDeq.Type = TRB_TYPE_SET_TR_DEQUE;
736 CmdSetTRDeq.Endpoint = Dci;
737 CmdSetTRDeq.SlotId = SlotId;
738 Status = XhcCmdTransfer (
739 Xhc,
740 (TRB *) (UINTN) &CmdSetTRDeq,
741 XHC_GENERIC_TIMEOUT,
742 (TRB **) (UINTN) &EvtTrb
743 );
744 ASSERT (!EFI_ERROR(Status));
745
746 //
747 // 3)Ring the doorbell to transit from stop to active
748 //
749 XhcRingDoorBell (Xhc, SlotId, Dci);
750
751 return Status;
752 }
753
754 /**
755 Create XHCI event ring.
756
757 @param Xhc The XHCI device.
758 @param EventInterrupter The interrupter of event.
759 @param EventRing The created event ring.
760
761 **/
762 VOID
763 EFIAPI
764 CreateEventRing (
765 IN USB_XHCI_DEV *Xhc,
766 IN UINT8 EventInterrupter,
767 OUT EVENT_RING *EventRing
768 )
769 {
770 VOID *Buf;
771 EVENT_RING_SEG_TABLE_ENTRY *ERSTBase;
772
773 ASSERT (EventRing != NULL);
774
775 Buf = AllocateAlignedZeroPool(sizeof (TRB) * EVENT_RING_TRB_NUMBER, 64);
776 ASSERT (Buf != NULL);
777 ASSERT (((UINTN) Buf & 0x3F) == 0);
778
779 EventRing->EventRingSeg0 = Buf;
780 EventRing->EventInterrupter = EventInterrupter;
781 EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;
782 EventRing->EventRingDequeue = (TRB *) EventRing->EventRingSeg0;
783 EventRing->EventRingEnqueue = (TRB *) EventRing->EventRingSeg0;
784 //
785 // Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'
786 // and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.
787 //
788 EventRing->EventRingCCS = 1;
789
790 Buf = AllocateAlignedZeroPool(sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER, 64);
791 ASSERT (Buf != NULL);
792 ASSERT (((UINTN) Buf & 0x3F) == 0);
793
794 ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *) Buf;
795 EventRing->ERSTBase = ERSTBase;
796 ERSTBase->PtrLo = XHC_LOW_32BIT (EventRing->EventRingSeg0);
797 ERSTBase->PtrHi = XHC_HIGH_32BIT (EventRing->EventRingSeg0);
798 ERSTBase->RingTrbSize = EVENT_RING_TRB_NUMBER;
799
800 //
801 // Program the Interrupter Event Ring Segment Table Size (ERSTSZ) register (5.5.2.3.1)
802 //
803 XhcWriteRuntimeReg (
804 Xhc,
805 XHC_ERSTSZ_OFFSET + (32 * EventRing->EventInterrupter),
806 ERST_NUMBER
807 );
808 //
809 // Program the Interrupter Event Ring Dequeue Pointer (ERDP) register (5.5.2.3.3)
810 //
811 XhcWriteRuntimeReg64 (
812 Xhc,
813 XHC_ERDP_OFFSET + (32 * EventRing->EventInterrupter),
814 (UINT64)EventRing->EventRingDequeue
815 );
816 //
817 // Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register(5.5.2.3.2)
818 //
819 XhcWriteRuntimeReg64 (
820 Xhc,
821 XHC_ERSTBA_OFFSET + (32 * EventRing->EventInterrupter),
822 (UINT64) ERSTBase
823 );
824 //
825 // Need set IMAN IE bit to enble the ring interrupt
826 //
827 XhcSetRuntimeRegBit (Xhc, XHC_IMAN_OFFSET + (32 * EventRing->EventInterrupter), XHC_IMAN_IE);
828 }
829
830 /**
831 Create XHCI transfer ring.
832
833 @param Xhc The XHCI device.
834 @param TrbNum The number of TRB in the ring.
835 @param TransferRing The created transfer ring.
836
837 **/
838 VOID
839 EFIAPI
840 CreateTransferRing (
841 IN USB_XHCI_DEV *Xhc,
842 IN UINTN TrbNum,
843 OUT TRANSFER_RING *TransferRing
844 )
845 {
846 VOID *Buf;
847 LNK_TRB *EndTrb;
848
849 Buf = AllocateAlignedZeroPool(sizeof (TRB) * TrbNum, 64);
850 ASSERT (Buf != NULL);
851 ASSERT (((UINTN) Buf & 0x3F) == 0);
852
853 TransferRing->RingSeg0 = Buf;
854 TransferRing->TrbNumber = TrbNum;
855 TransferRing->RingEnqueue = (TRB *) TransferRing->RingSeg0;
856 TransferRing->RingDequeue = (TRB *) TransferRing->RingSeg0;
857 TransferRing->RingPCS = 1;
858 //
859 // 4.9.2 Transfer Ring Management
860 // To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to
861 // point to the first TRB in the ring.
862 //
863 EndTrb = (LNK_TRB*) ((UINTN)Buf + sizeof (TRB) * (TrbNum - 1));
864 EndTrb->Type = TRB_TYPE_LINK;
865 EndTrb->PtrLo = XHC_LOW_32BIT (Buf);
866 EndTrb->PtrHi = XHC_HIGH_32BIT (Buf);
867 //
868 // Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
869 //
870 EndTrb->TC = 1;
871 //
872 // Set Cycle bit as other TRB PCS init value
873 //
874 EndTrb->CycleBit = 0;
875 }
876
877 /**
878 Free XHCI event ring.
879
880 @param Xhc The XHCI device.
881 @param EventRing The event ring to be freed.
882
883 **/
884 EFI_STATUS
885 EFIAPI
886 XhcFreeEventRing (
887 IN USB_XHCI_DEV *Xhc,
888 IN EVENT_RING *EventRing
889 )
890 {
891 UINT8 Index;
892 EVENT_RING_SEG_TABLE_ENTRY *TablePtr;
893 VOID *RingBuf;
894 EVENT_RING_SEG_TABLE_ENTRY *EventRingPtr;
895 UINTN InterrupterTarget;
896
897 if(EventRing->EventRingSeg0 == NULL) {
898 return EFI_SUCCESS;
899 }
900
901 InterrupterTarget = EventRing->EventInterrupter;
902 //
903 // Get the Event Ring Segment Table base address
904 //
905 TablePtr = (EVENT_RING_SEG_TABLE_ENTRY *)(EventRing->ERSTBase);
906
907 //
908 // Get all the TRBs Ring and release
909 //
910 for (Index = 0; Index < ERST_NUMBER; Index++) {
911 EventRingPtr = TablePtr + Index;
912 RingBuf = (VOID *)(UINTN)(EventRingPtr->PtrLo | ((UINT64)EventRingPtr->PtrHi << 32));
913
914 if(RingBuf != NULL) {
915 FreeAlignedPool (RingBuf);
916 ZeroMem (EventRingPtr, sizeof (EVENT_RING_SEG_TABLE_ENTRY));
917 }
918 }
919
920 FreeAlignedPool (TablePtr);
921 return EFI_SUCCESS;
922 }
923
924 /**
925 Free the resouce allocated at initializing schedule.
926
927 @param Xhc The XHCI device.
928
929 **/
930 VOID
931 XhcFreeSched (
932 IN USB_XHCI_DEV *Xhc
933 )
934 {
935 UINT32 Index;
936
937 if (Xhc->ScratchBuf != NULL) {
938 for (Index = 0; Index < Xhc->MaxScratchpadBufs; Index++) {
939 FreeAlignedPool ((VOID*)(UINTN)*Xhc->ScratchBuf++);
940 }
941 }
942
943 if (Xhc->DCBAA != NULL) {
944 FreeAlignedPool (Xhc->DCBAA);
945 Xhc->DCBAA = NULL;
946 }
947
948 if (Xhc->CmdRing.RingSeg0 != NULL){
949 FreeAlignedPool (Xhc->CmdRing.RingSeg0);
950 Xhc->CmdRing.RingSeg0 = NULL;
951 }
952 XhcFreeEventRing (Xhc,&Xhc->CmdEventRing);
953 XhcFreeEventRing (Xhc,&Xhc->CtrlTrEventRing);
954 XhcFreeEventRing (Xhc,&Xhc->BulkTrEventRing);
955 XhcFreeEventRing (Xhc,&Xhc->AsynIntTrEventRing);
956 XhcFreeEventRing (Xhc,&Xhc->IntTrEventRing);
957 }
958
959 /**
960 Check if it is ring TRB.
961
962 @param Ring The transfer ring
963 @param Trb The TRB to check if it's in the transfer ring
964
965 @retval TRUE It is in the ring
966 @retval FALSE It is not in the ring
967
968 **/
969 BOOLEAN
970 IsTransferRingTrb (
971 IN TRANSFER_RING *Ring,
972 IN TRB *Trb
973 )
974 {
975 BOOLEAN Flag;
976 TRB *Trb1;
977 UINTN Index;
978
979 Trb1 = Ring->RingSeg0;
980 Flag = FALSE;
981
982 ASSERT (Ring->TrbNumber == CMD_RING_TRB_NUMBER || Ring->TrbNumber == TR_RING_TRB_NUMBER);
983
984 for (Index = 0; Index < Ring->TrbNumber; Index++) {
985 if (Trb == Trb1) {
986 Flag = TRUE;
987 break;
988 }
989 Trb1++;
990 }
991
992 return Flag;
993 }
994
995 /**
996 Check the URB's execution result and update the URB's
997 result accordingly.
998
999 @param Xhc The XHCI device.
1000 @param Urb The URB to check result.
1001
1002 @return Whether the result of URB transfer is finialized.
1003
1004 **/
1005 EFI_STATUS
1006 XhcCheckUrbResult (
1007 IN USB_XHCI_DEV *Xhc,
1008 IN URB *Urb
1009 )
1010 {
1011 BOOLEAN StartDone;
1012 BOOLEAN EndDone;
1013 EVT_TRB_TRANSFER *EvtTrb;
1014 TRB *TRBPtr;
1015 UINTN Index;
1016 UINT8 TRBType;
1017 EFI_STATUS Status;
1018
1019 ASSERT ((Xhc != NULL) && (Urb != NULL));
1020
1021 Urb->Completed = 0;
1022 Urb->Result = EFI_USB_NOERROR;
1023 Status = EFI_SUCCESS;
1024 EvtTrb = NULL;
1025
1026 if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
1027 Urb->Result |= EFI_USB_ERR_SYSTEM;
1028 Status = EFI_DEVICE_ERROR;
1029 goto EXIT;
1030 }
1031
1032 //
1033 // Restore the EventRingDequeue and poll the transfer event ring from beginning
1034 //
1035 StartDone = FALSE;
1036 EndDone = FALSE;
1037 Urb->EvtRing->EventRingDequeue = Urb->EvtTrbStart;
1038 for (Index = 0; Index < Urb->EvtRing->TrbNumber; Index++) {
1039 XhcSyncEventRing (Xhc, Urb->EvtRing);
1040 Status = XhcCheckNewEvent (Xhc, Urb->EvtRing, &(TRB *)EvtTrb);
1041 if (Status == EFI_NOT_READY) {
1042 Urb->Result |= EFI_USB_ERR_TIMEOUT;
1043 goto EXIT;
1044 }
1045
1046 TRBPtr = (TRB *)(UINTN)(EvtTrb->TRBPtrLo | (UINT64) EvtTrb->TRBPtrHi << 32);
1047
1048 switch (EvtTrb->Completcode) {
1049 case TRB_COMPLETION_STALL_ERROR:
1050 Urb->Result |= EFI_USB_ERR_STALL;
1051 Status = EFI_DEVICE_ERROR;
1052 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: STALL_ERROR! Completcode = %x\n",EvtTrb->Completcode));
1053 goto EXIT;
1054 break;
1055
1056 case TRB_COMPLETION_BABBLE_ERROR:
1057 Urb->Result |= EFI_USB_ERR_BABBLE;
1058 Status = EFI_DEVICE_ERROR;
1059 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: BABBLE_ERROR! Completcode = %x\n",EvtTrb->Completcode));
1060 goto EXIT;
1061 break;
1062
1063 case TRB_COMPLETION_DATA_BUFFER_ERROR:
1064 Urb->Result |= EFI_USB_ERR_BUFFER;
1065 Status = EFI_DEVICE_ERROR;
1066 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: ERR_BUFFER! Completcode = %x\n",EvtTrb->Completcode));
1067 goto EXIT;
1068 break;
1069
1070 case TRB_COMPLETION_USB_TRANSACTION_ERROR:
1071 Urb->Result |= EFI_USB_ERR_TIMEOUT;
1072 Status = EFI_DEVICE_ERROR;
1073 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! Completcode = %x\n",EvtTrb->Completcode));
1074 goto EXIT;
1075 break;
1076
1077 case TRB_COMPLETION_SHORT_PACKET:
1078 case TRB_COMPLETION_SUCCESS:
1079 if (IsTransferRingTrb (Urb->Ring, TRBPtr)) {
1080 if (EvtTrb->Completcode == TRB_COMPLETION_SHORT_PACKET) {
1081 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: short packet happens!\n"));
1082 }
1083 TRBType = (UINT8) (TRBPtr->Type);
1084 if ((TRBType == TRB_TYPE_DATA_STAGE) ||
1085 (TRBType == TRB_TYPE_NORMAL) ||
1086 (TRBType == TRB_TYPE_ISOCH)) {
1087 Urb->Completed += (Urb->DataLen - EvtTrb->Lenth);
1088 }
1089 }
1090 Status = EFI_SUCCESS;
1091 break;
1092
1093 default:
1094 DEBUG ((EFI_D_ERROR, "Transfer Default Error Occur! Completcode = 0x%x!\n",EvtTrb->Completcode));
1095 Urb->Result |= EFI_USB_ERR_TIMEOUT;
1096 Status = EFI_DEVICE_ERROR;
1097 goto EXIT;
1098 break;
1099 }
1100
1101 //
1102 // Only check first and end Trb event address
1103 //
1104 if (TRBPtr == Urb->TrbStart) {
1105 StartDone = TRUE;
1106 }
1107
1108 if (TRBPtr == Urb->TrbEnd) {
1109 EndDone = TRUE;
1110 }
1111
1112 if (StartDone && EndDone) {
1113 break;
1114 }
1115 }
1116
1117 EXIT:
1118 return Status;
1119 }
1120
1121
1122 /**
1123 Execute the transfer by polling the URB. This is a synchronous operation.
1124
1125 @param Xhc The XHCI device.
1126 @param CmdTransfer The executed URB is for cmd transfer or not.
1127 @param Urb The URB to execute.
1128 @param TimeOut The time to wait before abort, in millisecond.
1129
1130 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
1131 @return EFI_TIMEOUT The transfer failed due to time out.
1132 @return EFI_SUCCESS The transfer finished OK.
1133
1134 **/
1135 EFI_STATUS
1136 XhcExecTransfer (
1137 IN USB_XHCI_DEV *Xhc,
1138 IN BOOLEAN CmdTransfer,
1139 IN URB *Urb,
1140 IN UINTN TimeOut
1141 )
1142 {
1143 EFI_STATUS Status;
1144 UINTN Index;
1145 UINTN Loop;
1146 UINT8 SlotId;
1147 UINT8 Dci;
1148
1149 if (CmdTransfer) {
1150 SlotId = 0;
1151 Dci = 0;
1152 } else {
1153 SlotId = XhcDevAddrToSlotId(Urb->Ep.DevAddr);
1154 Dci = XhcEndpointToDci(Urb->Ep.EpAddr, Urb->Ep.Direction);
1155 }
1156
1157 Status = EFI_SUCCESS;
1158 Loop = (TimeOut * XHC_1_MILLISECOND / XHC_SYNC_POLL_INTERVAL) + 1;
1159 if (TimeOut == 0) {
1160 Loop = 0xFFFFFFFF;
1161 }
1162
1163 XhcRingDoorBell (Xhc, SlotId, Dci);
1164
1165 for (Index = 0; Index < Loop; Index++) {
1166 Status = XhcCheckUrbResult (Xhc, Urb);
1167 if ((Status != EFI_NOT_READY)) {
1168 break;
1169 }
1170 gBS->Stall (XHC_SYNC_POLL_INTERVAL);
1171 }
1172
1173 return Status;
1174 }
1175
1176 /**
1177 Delete a single asynchronous interrupt transfer for
1178 the device and endpoint.
1179
1180 @param Xhc The XHCI device.
1181 @param DevAddr The address of the target device.
1182 @param EpNum The endpoint of the target.
1183
1184 @retval EFI_SUCCESS An asynchronous transfer is removed.
1185 @retval EFI_NOT_FOUND No transfer for the device is found.
1186
1187 **/
1188 EFI_STATUS
1189 XhciDelAsyncIntTransfer (
1190 IN USB_XHCI_DEV *Xhc,
1191 IN UINT8 DevAddr,
1192 IN UINT8 EpNum
1193 )
1194 {
1195 LIST_ENTRY *Entry;
1196 LIST_ENTRY *Next;
1197 URB *Urb;
1198 EFI_USB_DATA_DIRECTION Direction;
1199 BOOLEAN Found;
1200
1201 Direction = ((EpNum & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;
1202 EpNum &= 0x0F;
1203
1204 Found = FALSE;
1205 Urb = NULL;
1206
1207 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
1208 Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
1209 if ((Urb->Ep.DevAddr == DevAddr) &&
1210 (Urb->Ep.EpAddr == EpNum) &&
1211 (Urb->Ep.Direction == Direction)) {
1212 RemoveEntryList (&Urb->UrbList);
1213 FreePool (Urb->Data);
1214 FreePool (Urb);
1215 return EFI_SUCCESS;
1216 }
1217 }
1218
1219 return EFI_NOT_FOUND;
1220 }
1221
1222 /**
1223 Remove all the asynchronous interrutp transfers.
1224
1225 @param Xhc The XHCI device.
1226
1227 **/
1228 VOID
1229 XhciDelAllAsyncIntTransfers (
1230 IN USB_XHCI_DEV *Xhc
1231 )
1232 {
1233 LIST_ENTRY *Entry;
1234 LIST_ENTRY *Next;
1235 URB *Urb;
1236
1237 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
1238 Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
1239 RemoveEntryList (&Urb->UrbList);
1240 FreePool (Urb->Data);
1241 FreePool (Urb);
1242 }
1243 }
1244
1245 /**
1246 Update the queue head for next round of asynchronous transfer
1247
1248 @param Xhc The XHCI device.
1249 @param Urb The URB to update
1250
1251 **/
1252 VOID
1253 XhcUpdateAsyncRequest (
1254 IN USB_XHCI_DEV* Xhc,
1255 IN URB *Urb
1256 )
1257 {
1258 EFI_STATUS Status;
1259
1260 if (Urb->Result == EFI_USB_NOERROR) {
1261 Status = XhcCreateTransferTrb (Xhc, Urb);
1262 ASSERT_EFI_ERROR (Status);
1263 Status = RingIntTransferDoorBell (Xhc, Urb);
1264 ASSERT_EFI_ERROR (Status);
1265 }
1266 }
1267
1268
1269 /**
1270 Interrupt transfer periodic check handler.
1271
1272 @param Event Interrupt event.
1273 @param Context Pointer to USB_XHCI_DEV.
1274
1275 **/
1276 VOID
1277 EFIAPI
1278 XhcMonitorAsyncRequests (
1279 IN EFI_EVENT Event,
1280 IN VOID *Context
1281 )
1282 {
1283 USB_XHCI_DEV *Xhc;
1284 LIST_ENTRY *Entry;
1285 LIST_ENTRY *Next;
1286 UINT8 *ProcBuf;
1287 URB *Urb;
1288 UINT8 SlotId;
1289 EFI_STATUS Status;
1290 EFI_TPL OldTpl;
1291
1292 OldTpl = gBS->RaiseTPL (XHC_TPL);
1293
1294 Xhc = (USB_XHCI_DEV*) Context;
1295
1296 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
1297 Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
1298
1299 //
1300 // Make sure that the device is available before every check.
1301 //
1302 SlotId = XhcDevAddrToSlotId(Urb->Ep.DevAddr);
1303 if (SlotId == 0) {
1304 continue;
1305 }
1306
1307 //
1308 // Check the result of URB execution. If it is still
1309 // active, check the next one.
1310 //
1311 Status = XhcCheckUrbResult (Xhc, Urb);
1312
1313 if (Status == EFI_NOT_READY) {
1314 continue;
1315 }
1316
1317 //
1318 // Allocate a buffer then copy the transferred data for user.
1319 // If failed to allocate the buffer, update the URB for next
1320 // round of transfer. Ignore the data of this round.
1321 //
1322 ProcBuf = NULL;
1323 if (Urb->Result == EFI_USB_NOERROR) {
1324 ASSERT (Urb->Completed <= Urb->DataLen);
1325
1326 ProcBuf = AllocatePool (Urb->Completed);
1327
1328 if (ProcBuf == NULL) {
1329 XhcUpdateAsyncRequest (Xhc, Urb);
1330 continue;
1331 }
1332
1333 CopyMem (ProcBuf, Urb->Data, Urb->Completed);
1334 }
1335
1336 XhcUpdateAsyncRequest (Xhc, Urb);
1337
1338 //
1339 // Leave error recovery to its related device driver. A
1340 // common case of the error recovery is to re-submit the
1341 // interrupt transfer which is linked to the head of the
1342 // list. This function scans from head to tail. So the
1343 // re-submitted interrupt transfer's callback function
1344 // will not be called again in this round. Don't touch this
1345 // URB after the callback, it may have been removed by the
1346 // callback.
1347 //
1348 if (Urb->Callback != NULL) {
1349 //
1350 // Restore the old TPL, USB bus maybe connect device in
1351 // his callback. Some drivers may has a lower TPL restriction.
1352 //
1353 gBS->RestoreTPL (OldTpl);
1354 (Urb->Callback) (ProcBuf, Urb->Completed, Urb->Context, Urb->Result);
1355 OldTpl = gBS->RaiseTPL (XHC_TPL);
1356 }
1357
1358 if (ProcBuf != NULL) {
1359 gBS->FreePool (ProcBuf);
1360 }
1361 }
1362 gBS->RestoreTPL (OldTpl);
1363 }
1364
1365 /**
1366 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.
1367
1368 @param Xhc The XHCI device.
1369 @param ParentRouteChart The route string pointed to the parent device if it exists.
1370 @param Port The port to be polled.
1371 @param PortState The port state.
1372
1373 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.
1374 @retval Others Should not appear.
1375
1376 **/
1377 EFI_STATUS
1378 EFIAPI
1379 XhcPollPortStatusChange (
1380 IN USB_XHCI_DEV* Xhc,
1381 IN USB_DEV_ROUTE ParentRouteChart,
1382 IN UINT8 Port,
1383 IN EFI_USB_PORT_STATUS *PortState
1384 )
1385 {
1386 EFI_STATUS Status;
1387 UINT8 Speed;
1388 UINT8 SlotId;
1389 USB_DEV_ROUTE RouteChart;
1390
1391 Status = EFI_SUCCESS;
1392
1393 if (ParentRouteChart.Dword == 0) {
1394 RouteChart.Field.RouteString = 0;
1395 RouteChart.Field.RootPortNum = Port + 1;
1396 RouteChart.Field.TierNum = 1;
1397 } else {
1398 if(Port < 14) {
1399 RouteChart.Field.RouteString = ParentRouteChart.Field.RouteString | (Port << (4 * (ParentRouteChart.Field.TierNum - 1)));
1400 } else {
1401 RouteChart.Field.RouteString = ParentRouteChart.Field.RouteString | (15 << (4 * (ParentRouteChart.Field.TierNum - 1)));
1402 }
1403 RouteChart.Field.RootPortNum = ParentRouteChart.Field.RootPortNum;
1404 RouteChart.Field.TierNum = ParentRouteChart.Field.TierNum + 1;
1405 }
1406
1407 if (((PortState->PortStatus & USB_PORT_STAT_ENABLE) != 0) &&
1408 ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0)) {
1409 //
1410 // Has a device attached, Identify device speed after port is enabled.
1411 //
1412 Speed = EFI_USB_SPEED_FULL;
1413 if ((PortState->PortStatus & USB_PORT_STAT_LOW_SPEED) != 0) {
1414 Speed = EFI_USB_SPEED_LOW;
1415 } else if ((PortState->PortStatus & USB_PORT_STAT_HIGH_SPEED) != 0) {
1416 Speed = EFI_USB_SPEED_HIGH;
1417 } else if ((PortState->PortStatus & USB_PORT_STAT_SUPER_SPEED) != 0) {
1418 Speed = EFI_USB_SPEED_SUPER;
1419 }
1420 //
1421 // Execute Enable_Slot cmd for attached device, initialize device context and assign device address.
1422 //
1423 SlotId = XhcRouteStringToSlotId (RouteChart);
1424 if (SlotId == 0) {
1425 Status = XhcInitializeDeviceSlot (Xhc, ParentRouteChart, Port, RouteChart, Speed);
1426 ASSERT_EFI_ERROR (Status);
1427 }
1428 } else if ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) == 0) {
1429 //
1430 // Device is detached. Disable the allocated device slot and release resource.
1431 //
1432 SlotId = XhcRouteStringToSlotId (RouteChart);
1433 if (SlotId != 0) {
1434 Status = XhcDisableSlotCmd (Xhc, SlotId);
1435 ASSERT_EFI_ERROR (Status);
1436 }
1437 }
1438 return Status;
1439 }
1440
1441
1442 /**
1443 Calculate the device context index by endpoint address and direction.
1444
1445 @param EpAddr The target endpoint number.
1446 @param Direction The direction of the target endpoint.
1447
1448 @return The device context index of endpoint.
1449
1450 **/
1451 UINT8
1452 XhcEndpointToDci (
1453 IN UINT8 EpAddr,
1454 IN UINT8 Direction
1455 )
1456 {
1457 UINT8 Index;
1458
1459 if (EpAddr == 0) {
1460 return 1;
1461 } else {
1462 Index = 2 * EpAddr;
1463 if (Direction == EfiUsbDataIn) {
1464 Index += 1;
1465 }
1466 return Index;
1467 }
1468 }
1469
1470 /**
1471 Find out the slot id according to device address assigned by XHCI's Address_Device cmd.
1472
1473 @param DevAddr The device address of the target device.
1474
1475 @return The slot id used by the device.
1476
1477 **/
1478 UINT8
1479 EFIAPI
1480 XhcDevAddrToSlotId (
1481 IN UINT8 DevAddr
1482 )
1483 {
1484 UINT8 Index;
1485
1486 for (Index = 0; Index < 255; Index++) {
1487 if (UsbDevContext[Index + 1].Enabled &&
1488 (UsbDevContext[Index + 1].SlotId != 0) &&
1489 (UsbDevContext[Index + 1].XhciDevAddr == DevAddr)) {
1490 break;
1491 }
1492 }
1493
1494 if (Index == 255) {
1495 return 0;
1496 }
1497
1498 return UsbDevContext[Index + 1].SlotId;
1499 }
1500
1501 /**
1502 Find out the actual device address according to the requested device address from UsbBus.
1503
1504 @param BusDevAddr The requested device address by UsbBus upper driver.
1505
1506 @return The actual device address assigned to the device.
1507
1508 **/
1509 UINT8
1510 EFIAPI
1511 XhcBusDevAddrToSlotId (
1512 IN UINT8 BusDevAddr
1513 )
1514 {
1515 UINT8 Index;
1516
1517 for (Index = 0; Index < 255; Index++) {
1518 if (UsbDevContext[Index + 1].Enabled &&
1519 (UsbDevContext[Index + 1].SlotId != 0) &&
1520 (UsbDevContext[Index + 1].BusDevAddr == BusDevAddr)) {
1521 break;
1522 }
1523 }
1524
1525 if (Index == 255) {
1526 return 0;
1527 }
1528
1529 return UsbDevContext[Index + 1].SlotId;
1530 }
1531
1532 /**
1533 Find out the slot id according to the device's route string.
1534
1535 @param RouteString The route string described the device location.
1536
1537 @return The slot id used by the device.
1538
1539 **/
1540 UINT8
1541 EFIAPI
1542 XhcRouteStringToSlotId (
1543 IN USB_DEV_ROUTE RouteString
1544 )
1545 {
1546 UINT8 Index;
1547
1548 for (Index = 0; Index < 255; Index++) {
1549 if (UsbDevContext[Index + 1].Enabled &&
1550 (UsbDevContext[Index + 1].SlotId != 0) &&
1551 (UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword)) {
1552 break;
1553 }
1554 }
1555
1556 if (Index == 255) {
1557 return 0;
1558 }
1559
1560 return UsbDevContext[Index + 1].SlotId;
1561 }
1562
1563 /**
1564 Synchronize the specified event ring to update the enqueue and dequeue pointer.
1565
1566 @param Xhc The XHCI device.
1567 @param EvtRing The event ring to sync.
1568
1569 @retval EFI_SUCCESS The event ring is synchronized successfully.
1570
1571 **/
1572 EFI_STATUS
1573 EFIAPI
1574 XhcSyncEventRing (
1575 IN USB_XHCI_DEV *Xhc,
1576 IN EVENT_RING *EvtRing
1577 )
1578 {
1579 UINTN Index;
1580 TRB *EvtTrb1;
1581 TRB *EvtTrb2;
1582 TRB *XhcDequeue;
1583
1584 ASSERT (EvtRing != NULL);
1585
1586 //
1587 // Calculate the EventRingEnqueue and EventRingCCS.
1588 // Note: only support single Segment
1589 //
1590 EvtTrb1 = EvtRing->EventRingSeg0;
1591 EvtTrb2 = EvtRing->EventRingSeg0;
1592
1593 for (Index = 0; Index < EvtRing->TrbNumber; Index++) {
1594 if (EvtTrb1->CycleBit != EvtTrb2->CycleBit) {
1595 break;
1596 }
1597 EvtTrb1++;
1598 }
1599
1600 if (Index < EvtRing->TrbNumber) {
1601 EvtRing->EventRingEnqueue = EvtTrb1;
1602 EvtRing->EventRingCCS = (EvtTrb2->CycleBit) ? 1 : 0;
1603 } else {
1604 EvtRing->EventRingEnqueue = EvtTrb2;
1605 EvtRing->EventRingCCS = (EvtTrb2->CycleBit) ? 0 : 1;
1606 }
1607
1608 //
1609 // Apply the EventRingDequeue to Xhc
1610 //
1611 XhcDequeue = (TRB *)(UINTN) XhcReadRuntimeReg64 (
1612 Xhc,
1613 XHC_ERDP_OFFSET + (32 * EvtRing->EventInterrupter)
1614 );
1615
1616 if (((UINT64) XhcDequeue & (~0x0F)) != ((UINT64) EvtRing->EventRingDequeue & (~0x0F))) {
1617 XhcWriteRuntimeReg64 (
1618 Xhc,
1619 XHC_ERDP_OFFSET + (32 * EvtRing->EventInterrupter),
1620 (UINT64)EvtRing->EventRingDequeue | BIT3
1621 );
1622 }
1623
1624 return EFI_SUCCESS;
1625 }
1626
1627 /**
1628 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
1629
1630 @param Xhc The XHCI device.
1631 @param TrsRing The transfer ring to sync.
1632
1633 @retval EFI_SUCCESS The transfer ring is synchronized successfully.
1634
1635 **/
1636 EFI_STATUS
1637 EFIAPI
1638 XhcSyncTrsRing (
1639 IN USB_XHCI_DEV *Xhc,
1640 IN TRANSFER_RING *TrsRing
1641 )
1642 {
1643 UINTN Index;
1644 TRB *TrsTrb;
1645
1646 ASSERT (TrsRing != NULL);
1647 //
1648 // Calculate the latest RingEnqueue and RingPCS
1649 //
1650 TrsTrb = TrsRing->RingEnqueue;
1651 ASSERT (TrsTrb != NULL);
1652
1653 for (Index = 0; Index < TrsRing->TrbNumber; Index++) {
1654 if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {
1655 break;
1656 }
1657 TrsTrb++;
1658 if ((UINT8) TrsTrb->Type == TRB_TYPE_LINK) {
1659 ASSERT (((LNK_TRB*)TrsTrb)->TC != 0);
1660 //
1661 // set cycle bit in Link TRB as normal
1662 //
1663 ((LNK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
1664 //
1665 // Toggle PCS maintained by software
1666 //
1667 TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1;
1668 TrsTrb = (TRB*)(UINTN)((TrsTrb->Dword1 | ((UINT64)TrsTrb->Dword2 << 32)) & ~0x0F);
1669 }
1670 }
1671
1672 ASSERT (Index != TrsRing->TrbNumber);
1673
1674 if (TrsTrb != TrsRing->RingEnqueue) {
1675 TrsRing->RingEnqueue = TrsTrb;
1676 }
1677
1678 //
1679 // Clear the Trb context for enqueue, but reserve the PCS bit
1680 //
1681 TrsTrb->Dword1 = 0;
1682 TrsTrb->Dword2 = 0;
1683 TrsTrb->Dword3 = 0;
1684 TrsTrb->RsvdZ1 = 0;
1685 TrsTrb->Type = 0;
1686 TrsTrb->RsvdZ2 = 0;
1687
1688 return EFI_SUCCESS;
1689 }
1690
1691 /**
1692 Check if there is a new generated event.
1693
1694 @param Xhc The XHCI device.
1695 @param EvtRing The event ring to check.
1696 @param NewEvtTrb The new event TRB found.
1697
1698 @retval EFI_SUCCESS Found a new event TRB at the event ring.
1699 @retval EFI_NOT_READY The event ring has no new event.
1700
1701 **/
1702 EFI_STATUS
1703 EFIAPI
1704 XhcCheckNewEvent (
1705 IN USB_XHCI_DEV *Xhc,
1706 IN EVENT_RING *EvtRing,
1707 OUT TRB **NewEvtTrb
1708 )
1709 {
1710 EFI_STATUS Status;
1711 TRB *EvtTrb;
1712
1713 ASSERT (EvtRing != NULL);
1714
1715 EvtTrb = EvtRing->EventRingDequeue;
1716 *NewEvtTrb = EvtRing->EventRingDequeue;
1717
1718 if (EvtRing->EventRingDequeue == EvtRing->EventRingEnqueue) {
1719 return EFI_NOT_READY;
1720 }
1721
1722 Status = EFI_SUCCESS;
1723
1724 if (((EvtTrb->Dword3 >> 24) & 0xFF) != TRB_COMPLETION_SUCCESS) {
1725 Status = EFI_DEVICE_ERROR;
1726 }
1727
1728 EvtRing->EventRingDequeue++;
1729 //
1730 // If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.
1731 //
1732 if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB) * EvtRing->TrbNumber)) {
1733 EvtRing->EventRingDequeue = EvtRing->EventRingSeg0;
1734 }
1735
1736 return Status;
1737 }
1738
1739 /**
1740 Ring the door bell to notify XHCI there is a transaction to be executed.
1741
1742 @param Xhc The XHCI device.
1743 @param SlotId The slot id of the target device.
1744 @param Dci The device context index of the target slot or endpoint.
1745
1746 @retval EFI_SUCCESS Successfully ring the door bell.
1747
1748 **/
1749 EFI_STATUS
1750 EFIAPI
1751 XhcRingDoorBell (
1752 IN USB_XHCI_DEV *Xhc,
1753 IN UINT8 SlotId,
1754 IN UINT8 Dci
1755 )
1756 {
1757 if (SlotId == 0) {
1758 XhcWriteDoorBellReg (Xhc, 0, 0);
1759 } else {
1760 XhcWriteDoorBellReg (Xhc, SlotId * sizeof (UINT32), Dci);
1761 }
1762
1763 return EFI_SUCCESS;
1764 }
1765
1766 /**
1767 Ring the door bell to notify XHCI there is a transaction to be executed through URB.
1768
1769 @param Xhc The XHCI device.
1770 @param Urb The URB to be rung.
1771
1772 @retval EFI_SUCCESS Successfully ring the door bell.
1773
1774 **/
1775 EFI_STATUS
1776 RingIntTransferDoorBell (
1777 IN USB_XHCI_DEV *Xhc,
1778 IN URB *Urb
1779 )
1780 {
1781 UINT8 SlotId;
1782 UINT8 Dci;
1783
1784 SlotId = XhcDevAddrToSlotId(Urb->Ep.DevAddr);
1785 Dci = XhcEndpointToDci(Urb->Ep.EpAddr, Urb->Ep.Direction);
1786 XhcRingDoorBell (Xhc, SlotId, Dci);
1787 return EFI_SUCCESS;
1788 }
1789
1790 /**
1791 Assign and initialize the device slot for a new device.
1792
1793 @param Xhc The XHCI device.
1794 @param ParentRouteChart The route string pointed to the parent device.
1795 @param ParentPort The port at which the device is located.
1796 @param RouteChart The route string pointed to the device.
1797 @param DeviceSpeed The device speed.
1798
1799 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1800
1801 **/
1802 EFI_STATUS
1803 EFIAPI
1804 XhcInitializeDeviceSlot (
1805 IN USB_XHCI_DEV *Xhc,
1806 IN USB_DEV_ROUTE ParentRouteChart,
1807 IN UINT16 ParentPort,
1808 IN USB_DEV_ROUTE RouteChart,
1809 IN UINT8 DeviceSpeed
1810 )
1811 {
1812 EFI_STATUS Status;
1813 EVT_TRB_COMMAND *EvtTrb;
1814 INPUT_CONTEXT *InputContext;
1815 DEVICE_CONTEXT *OutputDevContxt;
1816 TRANSFER_RING *EndpointTransferRing;
1817 CMD_TRB_ADDR_DEV CmdTrbAddr;
1818 UINT8 DeviceAddress;
1819 CMD_TRB_EN_SLOT CmdTrb;
1820 UINT8 SlotId;
1821 UINT8 ParentSlotId;
1822 DEVICE_CONTEXT *ParentDeviceContext;
1823
1824 ZeroMem (&CmdTrb, sizeof (CMD_TRB_EN_SLOT));
1825 CmdTrb.CycleBit = 1;
1826 CmdTrb.Type = TRB_TYPE_EN_SLOT;
1827
1828 Status = XhcCmdTransfer (
1829 Xhc,
1830 (TRB *) (UINTN) &CmdTrb,
1831 XHC_GENERIC_TIMEOUT,
1832 (TRB **) (UINTN) &EvtTrb
1833 );
1834 ASSERT_EFI_ERROR (Status);
1835 ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
1836 DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
1837 SlotId = (UINT8)EvtTrb->SlotId;
1838 ASSERT (SlotId != 0);
1839
1840 ZeroMem (&UsbDevContext[SlotId], sizeof (USB_DEV_CONTEXT));
1841 UsbDevContext[SlotId].Enabled = TRUE;
1842 UsbDevContext[SlotId].SlotId = SlotId;
1843 UsbDevContext[SlotId].RouteString.Dword = RouteChart.Dword;
1844 UsbDevContext[SlotId].ParentRouteString.Dword = ParentRouteChart.Dword;
1845
1846 //
1847 // 4.3.3 Device Slot Initialization
1848 // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
1849 //
1850 InputContext = AllocateAlignedZeroPool(sizeof (INPUT_CONTEXT), 64);
1851 ASSERT (InputContext != NULL);
1852 ASSERT (((UINTN) InputContext & 0x3F) == 0);
1853
1854 UsbDevContext[SlotId].InputContext = (VOID *) InputContext;
1855
1856 //
1857 // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
1858 // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input
1859 // Context are affected by the command.
1860 //
1861 InputContext->InputControlContext.Dword2 |= (BIT0 | BIT1);
1862
1863 //
1864 // 3) Initialize the Input Slot Context data structure
1865 //
1866 InputContext->Slot.RouteStr = RouteChart.Field.RouteString;
1867 InputContext->Slot.Speed = DeviceSpeed + 1;
1868 InputContext->Slot.ContextEntries = 1;
1869 InputContext->Slot.RootHubPortNum = RouteChart.Field.RootPortNum;
1870
1871 if (RouteChart.Field.RouteString) {
1872 //
1873 // The device is behind of hub device.
1874 //
1875 ParentSlotId = XhcRouteStringToSlotId(ParentRouteChart);
1876 ASSERT (ParentSlotId != 0);
1877 //
1878 //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
1879 //
1880 ParentDeviceContext = (DEVICE_CONTEXT *)UsbDevContext[ParentSlotId].OutputDevContxt;
1881 if ((ParentDeviceContext->Slot.TTPortNum == 0) &&
1882 (ParentDeviceContext->Slot.TTHubSlotId == 0)) {
1883 if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {
1884 //
1885 // Full/Low device attached to High speed hub port that isolates the high speed signaling
1886 // environment from Full/Low speed signaling environment for a device
1887 //
1888 InputContext->Slot.TTPortNum = ParentPort;
1889 InputContext->Slot.TTHubSlotId = ParentSlotId;
1890 }
1891 } else {
1892 //
1893 // Inherit the TT parameters from parent device.
1894 //
1895 InputContext->Slot.TTPortNum = ParentDeviceContext->Slot.TTPortNum;
1896 InputContext->Slot.TTHubSlotId = ParentDeviceContext->Slot.TTHubSlotId;
1897 //
1898 // If the device is a High speed device then down the speed to be the same as its parent Hub
1899 //
1900 if (DeviceSpeed == EFI_USB_SPEED_HIGH) {
1901 InputContext->Slot.Speed = ParentDeviceContext->Slot.Speed;
1902 }
1903 }
1904 }
1905
1906 //
1907 // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
1908 //
1909 EndpointTransferRing = AllocateAlignedZeroPool(sizeof (TRANSFER_RING), 64);
1910 UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;
1911 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)UsbDevContext[SlotId].EndpointTransferRing[0]);
1912 //
1913 // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
1914 //
1915 InputContext->EP[0].EPType = ED_CONTROL_BIDIR;
1916
1917 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
1918 InputContext->EP[0].MaxPacketSize = 512;
1919 } else if (DeviceSpeed == EFI_USB_SPEED_HIGH) {
1920 InputContext->EP[0].MaxPacketSize = 64;
1921 } else {
1922 InputContext->EP[0].MaxPacketSize = 8;
1923 }
1924 //
1925 // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
1926 // 1KB, and Bulk and Isoch endpoints 3KB.
1927 //
1928 InputContext->EP[0].AverageTRBLength = 8;
1929 InputContext->EP[0].MaxBurstSize = 0;
1930 InputContext->EP[0].Interval = 0;
1931 InputContext->EP[0].MaxPStreams = 0;
1932 InputContext->EP[0].Mult = 0;
1933 InputContext->EP[0].CErr = 3;
1934
1935 //
1936 // Init the DCS(dequeue cycle state) as the transfer ring's CCS
1937 //
1938 InputContext->EP[0].PtrLo = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0) | BIT0;
1939 InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0);
1940
1941 //
1942 // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
1943 //
1944 OutputDevContxt = AllocateAlignedZeroPool(sizeof (DEVICE_CONTEXT), 64);
1945 ASSERT (OutputDevContxt != NULL);
1946 ASSERT (((UINTN) OutputDevContxt & 0x3F) == 0);
1947
1948 UsbDevContext[SlotId].OutputDevContxt = OutputDevContxt;
1949 //
1950 // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
1951 // a pointer to the Output Device Context data structure (6.2.1).
1952 //
1953 Xhc->DCBAA[SlotId] = (UINT64) (UINTN) OutputDevContxt;
1954
1955 //
1956 // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
1957 // Context data structure described above.
1958 //
1959 ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
1960 CmdTrbAddr.PtrLo = XHC_LOW_32BIT (UsbDevContext[SlotId].InputContext);
1961 CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (UsbDevContext[SlotId].InputContext);
1962 CmdTrbAddr.CycleBit = 1;
1963 CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;
1964 CmdTrbAddr.SlotId = UsbDevContext[SlotId].SlotId;
1965 Status = XhcCmdTransfer (
1966 Xhc,
1967 (TRB *) (UINTN) &CmdTrbAddr,
1968 XHC_GENERIC_TIMEOUT,
1969 (TRB **) (UINTN) &EvtTrb
1970 );
1971 ASSERT (!EFI_ERROR(Status));
1972
1973 DeviceAddress = (UINT8) ((DEVICE_CONTEXT *) OutputDevContxt)->Slot.DeviceAddress;
1974 DEBUG ((EFI_D_INFO, " Address %d assigned succeefully\n", DeviceAddress));
1975
1976 UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
1977
1978 return Status;
1979 }
1980
1981 /**
1982 Disable the specified device slot.
1983
1984 @param Xhc The XHCI device.
1985 @param SlotId The slot id to be disabled.
1986
1987 @retval EFI_SUCCESS Successfully disable the device slot.
1988
1989 **/
1990 EFI_STATUS
1991 EFIAPI
1992 XhcDisableSlotCmd (
1993 IN USB_XHCI_DEV *Xhc,
1994 IN UINT8 SlotId
1995 )
1996 {
1997 EFI_STATUS Status;
1998 TRB *EvtTrb;
1999 CMD_TRB_DIS_SLOT CmdTrbDisSlot;
2000 UINT8 Index;
2001 VOID *RingSeg;
2002
2003 //
2004 // Disable the device slots occupied by these devices on its downstream ports.
2005 // Entry 0 is reserved.
2006 //
2007 for (Index = 0; Index < 255; Index++) {
2008 if (!UsbDevContext[Index + 1].Enabled ||
2009 (UsbDevContext[Index + 1].SlotId == 0) ||
2010 (UsbDevContext[Index + 1].ParentRouteString.Dword != UsbDevContext[SlotId].RouteString.Dword)) {
2011 continue;
2012 }
2013
2014 Status = XhcDisableSlotCmd (Xhc, UsbDevContext[Index + 1].SlotId);
2015
2016 if (EFI_ERROR (Status)) {
2017 DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
2018 UsbDevContext[Index + 1].SlotId = 0;
2019 }
2020 }
2021
2022 //
2023 // Construct the disable slot command
2024 //
2025 DEBUG ((EFI_D_INFO, "Disable device slot %d!\n", SlotId));
2026
2027 ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));
2028 CmdTrbDisSlot.CycleBit = 1;
2029 CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;
2030 CmdTrbDisSlot.SlotId = SlotId;
2031 Status = XhcCmdTransfer (
2032 Xhc,
2033 (TRB *) (UINTN) &CmdTrbDisSlot,
2034 XHC_GENERIC_TIMEOUT,
2035 (TRB **) (UINTN) &EvtTrb
2036 );
2037 ASSERT_EFI_ERROR(Status);
2038 //
2039 // Free the slot's device context entry
2040 //
2041 Xhc->DCBAA[SlotId] = 0;
2042
2043 //
2044 // Free the slot related data structure
2045 //
2046 for (Index = 0; Index < 31; Index++) {
2047 if (UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {
2048 RingSeg = ((TRANSFER_RING *)(UINTN)UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;
2049 if (RingSeg != NULL) {
2050 FreeAlignedPool(RingSeg);
2051 }
2052 FreeAlignedPool(UsbDevContext[SlotId].EndpointTransferRing[Index]);
2053 }
2054 }
2055
2056 for (Index = 0; Index < UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {
2057 if (UsbDevContext[SlotId].ConfDesc[Index] != NULL) {
2058 FreePool (UsbDevContext[SlotId].ConfDesc[Index]);
2059 }
2060 }
2061
2062 if (UsbDevContext[SlotId].InputContext != NULL) {
2063 FreeAlignedPool (UsbDevContext[SlotId].InputContext);
2064 }
2065
2066 if (UsbDevContext[SlotId].OutputDevContxt != NULL) {
2067 FreeAlignedPool (UsbDevContext[SlotId].OutputDevContxt);
2068 }
2069 //
2070 // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
2071 // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
2072 // remove urb from XHCI's asynchronous transfer list.
2073 //
2074 UsbDevContext[SlotId].Enabled = FALSE;
2075
2076 return Status;
2077 }
2078
2079 /**
2080 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
2081
2082 @param Xhc The XHCI device.
2083 @param SlotId The slot id to be configured.
2084 @param DeviceSpeed The device's speed.
2085 @param ConfigDesc The pointer to the usb device configuration descriptor.
2086
2087 @retval EFI_SUCCESS Successfully configure all the device endpoints.
2088
2089 **/
2090 EFI_STATUS
2091 EFIAPI
2092 XhcSetConfigCmd (
2093 IN USB_XHCI_DEV *Xhc,
2094 IN UINT8 SlotId,
2095 IN UINT8 DeviceSpeed,
2096 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
2097 )
2098 {
2099 EFI_STATUS Status;
2100
2101 USB_INTERFACE_DESCRIPTOR *IfDesc;
2102 USB_ENDPOINT_DESCRIPTOR *EpDesc;
2103 UINT8 Index;
2104 UINTN NumEp;
2105 UINTN EpIndex;
2106 UINT8 EpAddr;
2107 UINT8 Direction;
2108 UINT8 Dci;
2109 UINT8 MaxDci;
2110 UINT32 PhyAddr;
2111 UINT8 Interval;
2112
2113 TRANSFER_RING *EndpointTransferRing;
2114 CMD_CFG_ED CmdTrbCfgEP;
2115 INPUT_CONTEXT *InputContext;
2116 DEVICE_CONTEXT *OutputDevContxt;
2117 EVT_TRB_COMMAND *EvtTrb;
2118 //
2119 // 4.6.6 Configure Endpoint
2120 //
2121 InputContext = UsbDevContext[SlotId].InputContext;
2122 OutputDevContxt = UsbDevContext[SlotId].OutputDevContxt;
2123 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
2124 CopyMem (&InputContext->Slot, &OutputDevContxt->Slot, sizeof (SLOT_CONTEXT));
2125
2126 ASSERT (ConfigDesc != NULL);
2127
2128 MaxDci = 0;
2129
2130 IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
2131 for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {
2132 while (IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) {
2133 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
2134 }
2135
2136 NumEp = IfDesc->NumEndpoints;
2137
2138 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);
2139 for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
2140 while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
2141 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2142 }
2143
2144 EpAddr = EpDesc->EndpointAddress & 0x0F;
2145 Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
2146
2147 Dci = XhcEndpointToDci (EpAddr, Direction);
2148 if (Dci > MaxDci) {
2149 MaxDci = Dci;
2150 }
2151
2152 InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);
2153 InputContext->EP[Dci-1].MaxPacketSize = EpDesc->MaxPacketSize;
2154
2155 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
2156 //
2157 // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
2158 //
2159 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2160 } else {
2161 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2162 }
2163
2164 switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {
2165 case USB_ENDPOINT_BULK:
2166 if (Direction == EfiUsbDataIn) {
2167 InputContext->EP[Dci-1].CErr = 3;
2168 InputContext->EP[Dci-1].EPType = ED_BULK_IN;
2169 } else {
2170 InputContext->EP[Dci-1].CErr = 3;
2171 InputContext->EP[Dci-1].EPType = ED_BULK_OUT;
2172 }
2173
2174 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2175 if (UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
2176 EndpointTransferRing = AllocateAlignedZeroPool(sizeof (TRANSFER_RING), 64);
2177 UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
2178 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
2179 }
2180
2181 break;
2182 case USB_ENDPOINT_ISO:
2183 if (Direction == EfiUsbDataIn) {
2184 InputContext->EP[Dci-1].CErr = 0;
2185 InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;
2186 } else {
2187 InputContext->EP[Dci-1].CErr = 0;
2188 InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
2189 }
2190 break;
2191 case USB_ENDPOINT_INTERRUPT:
2192 if (Direction == EfiUsbDataIn) {
2193 InputContext->EP[Dci-1].CErr = 3;
2194 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;
2195 } else {
2196 InputContext->EP[Dci-1].CErr = 3;
2197 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
2198 }
2199 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2200 InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;
2201 //
2202 // Get the bInterval from descriptor and init the the interval field of endpoint context
2203 //
2204 if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {
2205 Interval = EpDesc->Interval;
2206 //
2207 // BUGBUG: Hard code the interval to MAX
2208 //
2209 InputContext->EP[Dci-1].Interval = 6;
2210 } else if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
2211 Interval = EpDesc->Interval;
2212 InputContext->EP[Dci-1].Interval = 0x0F;
2213 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2214 InputContext->EP[Dci-1].MaxESITPayload = 0x0002;
2215 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2216 InputContext->EP[Dci-1].CErr = 3;
2217 }
2218
2219 if (UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
2220 EndpointTransferRing = AllocateAlignedZeroPool(sizeof (TRANSFER_RING), 64);
2221 UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
2222 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
2223 }
2224 break;
2225
2226 case USB_ENDPOINT_CONTROL:
2227 default:
2228 ASSERT (0);
2229 break;
2230 }
2231
2232 PhyAddr = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0);
2233 PhyAddr &= ~(0x0F);
2234 PhyAddr |= ((TRANSFER_RING *)(UINTN)UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
2235 InputContext->EP[Dci-1].PtrLo = PhyAddr;
2236 InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0);
2237
2238 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2239 }
2240 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
2241 }
2242
2243 InputContext->InputControlContext.Dword2 |= BIT0;
2244 InputContext->Slot.ContextEntries = MaxDci;
2245 //
2246 // configure endpoint
2247 //
2248 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
2249 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (InputContext);
2250 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (InputContext);
2251 CmdTrbCfgEP.CycleBit = 1;
2252 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
2253 CmdTrbCfgEP.SlotId = UsbDevContext[SlotId].SlotId;
2254 DEBUG ((EFI_D_INFO, "Configure Endpoint\n"));
2255 Status = XhcCmdTransfer (
2256 Xhc,
2257 (TRB *) (UINTN) &CmdTrbCfgEP,
2258 XHC_GENERIC_TIMEOUT,
2259 (TRB **) (UINTN) &EvtTrb
2260 );
2261 ASSERT_EFI_ERROR(Status);
2262
2263 return Status;
2264 }
2265
2266 /**
2267 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
2268
2269 @param Xhc The XHCI device.
2270 @param SlotId The slot id to be evaluated.
2271 @param MaxPacketSize The max packet size supported by the device control transfer.
2272
2273 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
2274
2275 **/
2276 EFI_STATUS
2277 EFIAPI
2278 XhcEvaluateContext (
2279 IN USB_XHCI_DEV *Xhc,
2280 IN UINT8 SlotId,
2281 IN UINT32 MaxPacketSize
2282 )
2283 {
2284 EFI_STATUS Status;
2285 CMD_TRB_EVALU_CONTX CmdTrbEvalu;
2286 EVT_TRB_COMMAND *EvtTrb;
2287 INPUT_CONTEXT *InputContext;
2288
2289 ASSERT (UsbDevContext[SlotId].SlotId != 0);
2290
2291 //
2292 // 4.6.7 Evaluate Context
2293 //
2294 InputContext = UsbDevContext[SlotId].InputContext;
2295 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
2296
2297 InputContext->InputControlContext.Dword2 |= BIT1;
2298 InputContext->EP[0].MaxPacketSize = MaxPacketSize;
2299
2300 ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
2301 CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (InputContext);
2302 CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (InputContext);
2303 CmdTrbEvalu.CycleBit = 1;
2304 CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;
2305 CmdTrbEvalu.SlotId = UsbDevContext[SlotId].SlotId;
2306 DEBUG ((EFI_D_INFO, "Evaluate context\n"));
2307 Status = XhcCmdTransfer (
2308 Xhc,
2309 (TRB *) (UINTN) &CmdTrbEvalu,
2310 XHC_GENERIC_TIMEOUT,
2311 (TRB **) (UINTN) &EvtTrb
2312 );
2313 ASSERT (!EFI_ERROR(Status));
2314
2315 return Status;
2316 }
2317
2318 /**
2319 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
2320
2321 @param Xhc The XHCI device.
2322 @param SlotId The slot id to be configured.
2323 @param PortNum The total number of downstream port supported by the hub.
2324 @param TTT The TT think time of the hub device.
2325 @param MTT The multi-TT of the hub device.
2326
2327 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
2328
2329 **/
2330 EFI_STATUS
2331 XhcConfigHubContext (
2332 IN USB_XHCI_DEV *Xhc,
2333 IN UINT8 SlotId,
2334 IN UINT8 PortNum,
2335 IN UINT8 TTT,
2336 IN UINT8 MTT
2337 )
2338 {
2339 EFI_STATUS Status;
2340
2341 EVT_TRB_COMMAND *EvtTrb;
2342 INPUT_CONTEXT *InputContext;
2343 DEVICE_CONTEXT *OutputDevContxt;
2344 CMD_CFG_ED CmdTrbCfgEP;
2345
2346 ASSERT (UsbDevContext[SlotId].SlotId != 0);
2347 InputContext = UsbDevContext[SlotId].InputContext;
2348 OutputDevContxt = UsbDevContext[SlotId].OutputDevContxt;
2349
2350 //
2351 // 4.6.7 Evaluate Context
2352 //
2353 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
2354
2355 InputContext->InputControlContext.Dword2 |= BIT0;
2356
2357 //
2358 // Copy the slot context from OutputContext to Input context
2359 //
2360 CopyMem(&(InputContext->Slot), &(OutputDevContxt->Slot), sizeof (SLOT_CONTEXT));
2361 InputContext->Slot.Hub = 1;
2362 InputContext->Slot.PortNum = PortNum;
2363 InputContext->Slot.TTT = TTT;
2364 InputContext->Slot.MTT = MTT;
2365
2366 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
2367 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (InputContext);
2368 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (InputContext);
2369 CmdTrbCfgEP.CycleBit = 1;
2370 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
2371 CmdTrbCfgEP.SlotId = UsbDevContext[SlotId].SlotId;
2372 DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));
2373 Status = XhcCmdTransfer (
2374 Xhc,
2375 (TRB *) (UINTN) &CmdTrbCfgEP,
2376 XHC_GENERIC_TIMEOUT,
2377 (TRB **) (UINTN) &EvtTrb
2378 );
2379 ASSERT (!EFI_ERROR(Status));
2380
2381 return Status;
2382 }
2383
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