MdeModulePkg/XhciDxe: Check timeout URB again after stopping endpoint
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciSched.c
1 /** @file
2
3 XHCI transfer scheduling routines.
4
5 Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #include "Xhci.h"
17
18 /**
19 Create a command transfer TRB to support XHCI command interfaces.
20
21 @param Xhc The XHCI Instance.
22 @param CmdTrb The cmd TRB to be executed.
23
24 @return Created URB or NULL.
25
26 **/
27 URB*
28 XhcCreateCmdTrb (
29 IN USB_XHCI_INSTANCE *Xhc,
30 IN TRB_TEMPLATE *CmdTrb
31 )
32 {
33 URB *Urb;
34
35 Urb = AllocateZeroPool (sizeof (URB));
36 if (Urb == NULL) {
37 return NULL;
38 }
39
40 Urb->Signature = XHC_URB_SIG;
41
42 Urb->Ring = &Xhc->CmdRing;
43 XhcSyncTrsRing (Xhc, Urb->Ring);
44 Urb->TrbNum = 1;
45 Urb->TrbStart = Urb->Ring->RingEnqueue;
46 CopyMem (Urb->TrbStart, CmdTrb, sizeof (TRB_TEMPLATE));
47 Urb->TrbStart->CycleBit = Urb->Ring->RingPCS & BIT0;
48 Urb->TrbEnd = Urb->TrbStart;
49
50 return Urb;
51 }
52
53 /**
54 Execute a XHCI cmd TRB pointed by CmdTrb.
55
56 @param Xhc The XHCI Instance.
57 @param CmdTrb The cmd TRB to be executed.
58 @param Timeout Indicates the maximum time, in millisecond, which the
59 transfer is allowed to complete.
60 @param EvtTrb The event TRB corresponding to the cmd TRB.
61
62 @retval EFI_SUCCESS The transfer was completed successfully.
63 @retval EFI_INVALID_PARAMETER Some parameters are invalid.
64 @retval EFI_TIMEOUT The transfer failed due to timeout.
65 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
66
67 **/
68 EFI_STATUS
69 EFIAPI
70 XhcCmdTransfer (
71 IN USB_XHCI_INSTANCE *Xhc,
72 IN TRB_TEMPLATE *CmdTrb,
73 IN UINTN Timeout,
74 OUT TRB_TEMPLATE **EvtTrb
75 )
76 {
77 EFI_STATUS Status;
78 URB *Urb;
79
80 //
81 // Validate the parameters
82 //
83 if ((Xhc == NULL) || (CmdTrb == NULL)) {
84 return EFI_INVALID_PARAMETER;
85 }
86
87 Status = EFI_DEVICE_ERROR;
88
89 if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
90 DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: HC is halted\n"));
91 goto ON_EXIT;
92 }
93
94 //
95 // Create a new URB, then poll the execution status.
96 //
97 Urb = XhcCreateCmdTrb (Xhc, CmdTrb);
98
99 if (Urb == NULL) {
100 DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: failed to create URB\n"));
101 Status = EFI_OUT_OF_RESOURCES;
102 goto ON_EXIT;
103 }
104
105 Status = XhcExecTransfer (Xhc, TRUE, Urb, Timeout);
106 *EvtTrb = Urb->EvtTrb;
107
108 if (Urb->Result == EFI_USB_NOERROR) {
109 Status = EFI_SUCCESS;
110 }
111
112 XhcFreeUrb (Xhc, Urb);
113
114 ON_EXIT:
115 return Status;
116 }
117
118 /**
119 Create a new URB for a new transaction.
120
121 @param Xhc The XHCI Instance
122 @param BusAddr The logical device address assigned by UsbBus driver
123 @param EpAddr Endpoint addrress
124 @param DevSpeed The device speed
125 @param MaxPacket The max packet length of the endpoint
126 @param Type The transaction type
127 @param Request The standard USB request for control transfer
128 @param Data The user data to transfer
129 @param DataLen The length of data buffer
130 @param Callback The function to call when data is transferred
131 @param Context The context to the callback
132
133 @return Created URB or NULL
134
135 **/
136 URB*
137 XhcCreateUrb (
138 IN USB_XHCI_INSTANCE *Xhc,
139 IN UINT8 BusAddr,
140 IN UINT8 EpAddr,
141 IN UINT8 DevSpeed,
142 IN UINTN MaxPacket,
143 IN UINTN Type,
144 IN EFI_USB_DEVICE_REQUEST *Request,
145 IN VOID *Data,
146 IN UINTN DataLen,
147 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
148 IN VOID *Context
149 )
150 {
151 USB_ENDPOINT *Ep;
152 EFI_STATUS Status;
153 URB *Urb;
154
155 Urb = AllocateZeroPool (sizeof (URB));
156 if (Urb == NULL) {
157 return NULL;
158 }
159
160 Urb->Signature = XHC_URB_SIG;
161 InitializeListHead (&Urb->UrbList);
162
163 Ep = &Urb->Ep;
164 Ep->BusAddr = BusAddr;
165 Ep->EpAddr = (UINT8)(EpAddr & 0x0F);
166 Ep->Direction = ((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;
167 Ep->DevSpeed = DevSpeed;
168 Ep->MaxPacket = MaxPacket;
169 Ep->Type = Type;
170
171 Urb->Request = Request;
172 Urb->Data = Data;
173 Urb->DataLen = DataLen;
174 Urb->Callback = Callback;
175 Urb->Context = Context;
176
177 Status = XhcCreateTransferTrb (Xhc, Urb);
178 ASSERT_EFI_ERROR (Status);
179 if (EFI_ERROR (Status)) {
180 DEBUG ((EFI_D_ERROR, "XhcCreateUrb: XhcCreateTransferTrb Failed, Status = %r\n", Status));
181 FreePool (Urb);
182 Urb = NULL;
183 }
184
185 return Urb;
186 }
187
188 /**
189 Free an allocated URB.
190
191 @param Xhc The XHCI device.
192 @param Urb The URB to free.
193
194 **/
195 VOID
196 XhcFreeUrb (
197 IN USB_XHCI_INSTANCE *Xhc,
198 IN URB *Urb
199 )
200 {
201 if ((Xhc == NULL) || (Urb == NULL)) {
202 return;
203 }
204
205 if (Urb->DataMap != NULL) {
206 Xhc->PciIo->Unmap (Xhc->PciIo, Urb->DataMap);
207 }
208
209 FreePool (Urb);
210 }
211
212 /**
213 Create a transfer TRB.
214
215 @param Xhc The XHCI Instance
216 @param Urb The urb used to construct the transfer TRB.
217
218 @return Created TRB or NULL
219
220 **/
221 EFI_STATUS
222 XhcCreateTransferTrb (
223 IN USB_XHCI_INSTANCE *Xhc,
224 IN URB *Urb
225 )
226 {
227 VOID *OutputContext;
228 TRANSFER_RING *EPRing;
229 UINT8 EPType;
230 UINT8 SlotId;
231 UINT8 Dci;
232 TRB *TrbStart;
233 UINTN TotalLen;
234 UINTN Len;
235 UINTN TrbNum;
236 EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
237 EFI_PHYSICAL_ADDRESS PhyAddr;
238 VOID *Map;
239 EFI_STATUS Status;
240
241 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
242 if (SlotId == 0) {
243 return EFI_DEVICE_ERROR;
244 }
245
246 Urb->Finished = FALSE;
247 Urb->StartDone = FALSE;
248 Urb->EndDone = FALSE;
249 Urb->Completed = 0;
250 Urb->Result = EFI_USB_NOERROR;
251
252 Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
253 ASSERT (Dci < 32);
254 EPRing = (TRANSFER_RING *)(UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];
255 Urb->Ring = EPRing;
256 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
257 if (Xhc->HcCParams.Data.Csz == 0) {
258 EPType = (UINT8) ((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;
259 } else {
260 EPType = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;
261 }
262
263 if (Urb->Data != NULL) {
264 if (((UINT8) (Urb->Ep.Direction)) == EfiUsbDataIn) {
265 MapOp = EfiPciIoOperationBusMasterWrite;
266 } else {
267 MapOp = EfiPciIoOperationBusMasterRead;
268 }
269
270 Len = Urb->DataLen;
271 Status = Xhc->PciIo->Map (Xhc->PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);
272
273 if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {
274 DEBUG ((EFI_D_ERROR, "XhcCreateTransferTrb: Fail to map Urb->Data.\n"));
275 return EFI_OUT_OF_RESOURCES;
276 }
277
278 Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
279 Urb->DataMap = Map;
280 }
281
282 //
283 // Construct the TRB
284 //
285 XhcSyncTrsRing (Xhc, EPRing);
286 Urb->TrbStart = EPRing->RingEnqueue;
287 switch (EPType) {
288 case ED_CONTROL_BIDIR:
289 //
290 // For control transfer, create SETUP_STAGE_TRB first.
291 //
292 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
293 TrbStart->TrbCtrSetup.bmRequestType = Urb->Request->RequestType;
294 TrbStart->TrbCtrSetup.bRequest = Urb->Request->Request;
295 TrbStart->TrbCtrSetup.wValue = Urb->Request->Value;
296 TrbStart->TrbCtrSetup.wIndex = Urb->Request->Index;
297 TrbStart->TrbCtrSetup.wLength = Urb->Request->Length;
298 TrbStart->TrbCtrSetup.Length = 8;
299 TrbStart->TrbCtrSetup.IntTarget = 0;
300 TrbStart->TrbCtrSetup.IOC = 1;
301 TrbStart->TrbCtrSetup.IDT = 1;
302 TrbStart->TrbCtrSetup.Type = TRB_TYPE_SETUP_STAGE;
303 if (Urb->Ep.Direction == EfiUsbDataIn) {
304 TrbStart->TrbCtrSetup.TRT = 3;
305 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
306 TrbStart->TrbCtrSetup.TRT = 2;
307 } else {
308 TrbStart->TrbCtrSetup.TRT = 0;
309 }
310 //
311 // Update the cycle bit
312 //
313 TrbStart->TrbCtrSetup.CycleBit = EPRing->RingPCS & BIT0;
314 Urb->TrbNum++;
315
316 //
317 // For control transfer, create DATA_STAGE_TRB.
318 //
319 if (Urb->DataLen > 0) {
320 XhcSyncTrsRing (Xhc, EPRing);
321 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
322 TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT(Urb->DataPhy);
323 TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT(Urb->DataPhy);
324 TrbStart->TrbCtrData.Length = (UINT32) Urb->DataLen;
325 TrbStart->TrbCtrData.TDSize = 0;
326 TrbStart->TrbCtrData.IntTarget = 0;
327 TrbStart->TrbCtrData.ISP = 1;
328 TrbStart->TrbCtrData.IOC = 1;
329 TrbStart->TrbCtrData.IDT = 0;
330 TrbStart->TrbCtrData.CH = 0;
331 TrbStart->TrbCtrData.Type = TRB_TYPE_DATA_STAGE;
332 if (Urb->Ep.Direction == EfiUsbDataIn) {
333 TrbStart->TrbCtrData.DIR = 1;
334 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
335 TrbStart->TrbCtrData.DIR = 0;
336 } else {
337 TrbStart->TrbCtrData.DIR = 0;
338 }
339 //
340 // Update the cycle bit
341 //
342 TrbStart->TrbCtrData.CycleBit = EPRing->RingPCS & BIT0;
343 Urb->TrbNum++;
344 }
345 //
346 // For control transfer, create STATUS_STAGE_TRB.
347 // Get the pointer to next TRB for status stage use
348 //
349 XhcSyncTrsRing (Xhc, EPRing);
350 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
351 TrbStart->TrbCtrStatus.IntTarget = 0;
352 TrbStart->TrbCtrStatus.IOC = 1;
353 TrbStart->TrbCtrStatus.CH = 0;
354 TrbStart->TrbCtrStatus.Type = TRB_TYPE_STATUS_STAGE;
355 if (Urb->Ep.Direction == EfiUsbDataIn) {
356 TrbStart->TrbCtrStatus.DIR = 0;
357 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
358 TrbStart->TrbCtrStatus.DIR = 1;
359 } else {
360 TrbStart->TrbCtrStatus.DIR = 0;
361 }
362 //
363 // Update the cycle bit
364 //
365 TrbStart->TrbCtrStatus.CycleBit = EPRing->RingPCS & BIT0;
366 //
367 // Update the enqueue pointer
368 //
369 XhcSyncTrsRing (Xhc, EPRing);
370 Urb->TrbNum++;
371 Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;
372
373 break;
374
375 case ED_BULK_OUT:
376 case ED_BULK_IN:
377 TotalLen = 0;
378 Len = 0;
379 TrbNum = 0;
380 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
381 while (TotalLen < Urb->DataLen) {
382 if ((TotalLen + 0x10000) >= Urb->DataLen) {
383 Len = Urb->DataLen - TotalLen;
384 } else {
385 Len = 0x10000;
386 }
387 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
388 TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
389 TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
390 TrbStart->TrbNormal.Length = (UINT32) Len;
391 TrbStart->TrbNormal.TDSize = 0;
392 TrbStart->TrbNormal.IntTarget = 0;
393 TrbStart->TrbNormal.ISP = 1;
394 TrbStart->TrbNormal.IOC = 1;
395 TrbStart->TrbNormal.Type = TRB_TYPE_NORMAL;
396 //
397 // Update the cycle bit
398 //
399 TrbStart->TrbNormal.CycleBit = EPRing->RingPCS & BIT0;
400
401 XhcSyncTrsRing (Xhc, EPRing);
402 TrbNum++;
403 TotalLen += Len;
404 }
405
406 Urb->TrbNum = TrbNum;
407 Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;
408 break;
409
410 case ED_INTERRUPT_OUT:
411 case ED_INTERRUPT_IN:
412 TotalLen = 0;
413 Len = 0;
414 TrbNum = 0;
415 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
416 while (TotalLen < Urb->DataLen) {
417 if ((TotalLen + 0x10000) >= Urb->DataLen) {
418 Len = Urb->DataLen - TotalLen;
419 } else {
420 Len = 0x10000;
421 }
422 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
423 TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
424 TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
425 TrbStart->TrbNormal.Length = (UINT32) Len;
426 TrbStart->TrbNormal.TDSize = 0;
427 TrbStart->TrbNormal.IntTarget = 0;
428 TrbStart->TrbNormal.ISP = 1;
429 TrbStart->TrbNormal.IOC = 1;
430 TrbStart->TrbNormal.Type = TRB_TYPE_NORMAL;
431 //
432 // Update the cycle bit
433 //
434 TrbStart->TrbNormal.CycleBit = EPRing->RingPCS & BIT0;
435
436 XhcSyncTrsRing (Xhc, EPRing);
437 TrbNum++;
438 TotalLen += Len;
439 }
440
441 Urb->TrbNum = TrbNum;
442 Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;
443 break;
444
445 default:
446 DEBUG ((EFI_D_INFO, "Not supported EPType 0x%x!\n",EPType));
447 ASSERT (FALSE);
448 break;
449 }
450
451 return EFI_SUCCESS;
452 }
453
454
455 /**
456 Initialize the XHCI host controller for schedule.
457
458 @param Xhc The XHCI Instance to be initialized.
459
460 **/
461 VOID
462 XhcInitSched (
463 IN USB_XHCI_INSTANCE *Xhc
464 )
465 {
466 VOID *Dcbaa;
467 EFI_PHYSICAL_ADDRESS DcbaaPhy;
468 UINT64 CmdRing;
469 EFI_PHYSICAL_ADDRESS CmdRingPhy;
470 UINTN Entries;
471 UINT32 MaxScratchpadBufs;
472 UINT64 *ScratchBuf;
473 EFI_PHYSICAL_ADDRESS ScratchPhy;
474 UINT64 *ScratchEntry;
475 EFI_PHYSICAL_ADDRESS ScratchEntryPhy;
476 UINT32 Index;
477 UINTN *ScratchEntryMap;
478 EFI_STATUS Status;
479
480 //
481 // Initialize memory management.
482 //
483 Xhc->MemPool = UsbHcInitMemPool (Xhc->PciIo);
484 ASSERT (Xhc->MemPool != NULL);
485
486 //
487 // Program the Max Device Slots Enabled (MaxSlotsEn) field in the CONFIG register (5.4.7)
488 // to enable the device slots that system software is going to use.
489 //
490 Xhc->MaxSlotsEn = Xhc->HcSParams1.Data.MaxSlots;
491 ASSERT (Xhc->MaxSlotsEn >= 1 && Xhc->MaxSlotsEn <= 255);
492 XhcWriteOpReg (Xhc, XHC_CONFIG_OFFSET, Xhc->MaxSlotsEn);
493
494 //
495 // The Device Context Base Address Array entry associated with each allocated Device Slot
496 // shall contain a 64-bit pointer to the base of the associated Device Context.
497 // The Device Context Base Address Array shall contain MaxSlotsEn + 1 entries.
498 // Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.
499 //
500 Entries = (Xhc->MaxSlotsEn + 1) * sizeof(UINT64);
501 Dcbaa = UsbHcAllocateMem (Xhc->MemPool, Entries);
502 ASSERT (Dcbaa != NULL);
503 ZeroMem (Dcbaa, Entries);
504
505 //
506 // A Scratchpad Buffer is a PAGESIZE block of system memory located on a PAGESIZE boundary.
507 // System software shall allocate the Scratchpad Buffer(s) before placing the xHC in to Run
508 // mode (Run/Stop(R/S) ='1').
509 //
510 MaxScratchpadBufs = ((Xhc->HcSParams2.Data.ScratchBufHi) << 5) | (Xhc->HcSParams2.Data.ScratchBufLo);
511 Xhc->MaxScratchpadBufs = MaxScratchpadBufs;
512 ASSERT (MaxScratchpadBufs <= 1023);
513 if (MaxScratchpadBufs != 0) {
514 //
515 // Allocate the buffer to record the Mapping for each scratch buffer in order to Unmap them
516 //
517 ScratchEntryMap = AllocateZeroPool (sizeof (UINTN) * MaxScratchpadBufs);
518 ASSERT (ScratchEntryMap != NULL);
519 Xhc->ScratchEntryMap = ScratchEntryMap;
520
521 //
522 // Allocate the buffer to record the host address for each entry
523 //
524 ScratchEntry = AllocateZeroPool (sizeof (UINT64) * MaxScratchpadBufs);
525 ASSERT (ScratchEntry != NULL);
526 Xhc->ScratchEntry = ScratchEntry;
527
528 ScratchPhy = 0;
529 Status = UsbHcAllocateAlignedPages (
530 Xhc->PciIo,
531 EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),
532 Xhc->PageSize,
533 (VOID **) &ScratchBuf,
534 &ScratchPhy,
535 &Xhc->ScratchMap
536 );
537 ASSERT_EFI_ERROR (Status);
538
539 ZeroMem (ScratchBuf, MaxScratchpadBufs * sizeof (UINT64));
540 Xhc->ScratchBuf = ScratchBuf;
541
542 //
543 // Allocate each scratch buffer
544 //
545 for (Index = 0; Index < MaxScratchpadBufs; Index++) {
546 ScratchEntryPhy = 0;
547 Status = UsbHcAllocateAlignedPages (
548 Xhc->PciIo,
549 EFI_SIZE_TO_PAGES (Xhc->PageSize),
550 Xhc->PageSize,
551 (VOID **) &ScratchEntry[Index],
552 &ScratchEntryPhy,
553 (VOID **) &ScratchEntryMap[Index]
554 );
555 ASSERT_EFI_ERROR (Status);
556 ZeroMem ((VOID *)(UINTN)ScratchEntry[Index], Xhc->PageSize);
557 //
558 // Fill with the PCI device address
559 //
560 *ScratchBuf++ = ScratchEntryPhy;
561 }
562 //
563 // The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the
564 // Device Context Base Address Array points to the Scratchpad Buffer Array.
565 //
566 *(UINT64 *)Dcbaa = (UINT64)(UINTN) ScratchPhy;
567 }
568
569 //
570 // Program the Device Context Base Address Array Pointer (DCBAAP) register (5.4.6) with
571 // a 64-bit address pointing to where the Device Context Base Address Array is located.
572 //
573 Xhc->DCBAA = (UINT64 *)(UINTN)Dcbaa;
574 //
575 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
576 // So divide it to two 32-bytes width register access.
577 //
578 DcbaaPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Entries);
579 XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT(DcbaaPhy));
580 XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (DcbaaPhy));
581
582 DEBUG ((EFI_D_INFO, "XhcInitSched:DCBAA=0x%x\n", (UINT64)(UINTN)Xhc->DCBAA));
583
584 //
585 // Define the Command Ring Dequeue Pointer by programming the Command Ring Control Register
586 // (5.4.5) with a 64-bit address pointing to the starting address of the first TRB of the Command Ring.
587 // Note: The Command Ring is 64 byte aligned, so the low order 6 bits of the Command Ring Pointer shall
588 // always be '0'.
589 //
590 CreateTransferRing (Xhc, CMD_RING_TRB_NUMBER, &Xhc->CmdRing);
591 //
592 // The xHC uses the Enqueue Pointer to determine when a Transfer Ring is empty. As it fetches TRBs from a
593 // Transfer Ring it checks for a Cycle bit transition. If a transition detected, the ring is empty.
594 // So we set RCS as inverted PCS init value to let Command Ring empty
595 //
596 CmdRing = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0;
597 CmdRingPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID *)(UINTN) CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);
598 ASSERT ((CmdRingPhy & 0x3F) == 0);
599 CmdRingPhy |= XHC_CRCR_RCS;
600 //
601 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
602 // So divide it to two 32-bytes width register access.
603 //
604 XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT(CmdRingPhy));
605 XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET + 4, XHC_HIGH_32BIT (CmdRingPhy));
606
607 //
608 // Disable the 'interrupter enable' bit in USB_CMD
609 // and clear IE & IP bit in all Interrupter X Management Registers.
610 //
611 XhcClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_INTE);
612 for (Index = 0; Index < (UINT16)(Xhc->HcSParams1.Data.MaxIntrs); Index++) {
613 XhcClearRuntimeRegBit (Xhc, XHC_IMAN_OFFSET + (Index * 32), XHC_IMAN_IE);
614 XhcSetRuntimeRegBit (Xhc, XHC_IMAN_OFFSET + (Index * 32), XHC_IMAN_IP);
615 }
616
617 //
618 // Allocate EventRing for Cmd, Ctrl, Bulk, Interrupt, AsynInterrupt transfer
619 //
620 CreateEventRing (Xhc, &Xhc->EventRing);
621 DEBUG ((DEBUG_INFO, "XhcInitSched: Created CMD ring [%p~%p) EVENT ring [%p~%p)\n",
622 Xhc->CmdRing.RingSeg0, (UINTN)Xhc->CmdRing.RingSeg0 + sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER,
623 Xhc->EventRing.EventRingSeg0, (UINTN)Xhc->EventRing.EventRingSeg0 + sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER
624 ));
625 }
626
627 /**
628 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted
629 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint
630 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is
631 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the
632 Stopped to the Running state.
633
634 @param Xhc The XHCI Instance.
635 @param Urb The urb which makes the endpoint halted.
636
637 @retval EFI_SUCCESS The recovery is successful.
638 @retval Others Failed to recovery halted endpoint.
639
640 **/
641 EFI_STATUS
642 EFIAPI
643 XhcRecoverHaltedEndpoint (
644 IN USB_XHCI_INSTANCE *Xhc,
645 IN URB *Urb
646 )
647 {
648 EFI_STATUS Status;
649 UINT8 Dci;
650 UINT8 SlotId;
651
652 Status = EFI_SUCCESS;
653 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
654 if (SlotId == 0) {
655 return EFI_DEVICE_ERROR;
656 }
657 Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
658 ASSERT (Dci < 32);
659
660 DEBUG ((EFI_D_INFO, "Recovery Halted Slot = %x,Dci = %x\n", SlotId, Dci));
661
662 //
663 // 1) Send Reset endpoint command to transit from halt to stop state
664 //
665 Status = XhcResetEndpoint(Xhc, SlotId, Dci);
666 if (EFI_ERROR(Status)) {
667 DEBUG ((EFI_D_ERROR, "XhcRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
668 goto Done;
669 }
670
671 //
672 // 2)Set dequeue pointer
673 //
674 Status = XhcSetTrDequeuePointer(Xhc, SlotId, Dci, Urb);
675 if (EFI_ERROR(Status)) {
676 DEBUG ((EFI_D_ERROR, "XhcRecoverHaltedEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status));
677 goto Done;
678 }
679
680 //
681 // 3)Ring the doorbell to transit from stop to active
682 //
683 XhcRingDoorBell (Xhc, SlotId, Dci);
684
685 Done:
686 return Status;
687 }
688
689 /**
690 System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer
691 Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to
692 the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running
693 state.
694
695 @param Xhc The XHCI Instance.
696 @param Urb The urb which doesn't get completed in a specified timeout range.
697
698 @retval EFI_SUCCESS The dequeuing of the TDs is successful.
699 @retval EFI_ALREADY_STARTED The Urb is finished so no deque is needed.
700 @retval Others Failed to stop the endpoint and dequeue the TDs.
701
702 **/
703 EFI_STATUS
704 EFIAPI
705 XhcDequeueTrbFromEndpoint (
706 IN USB_XHCI_INSTANCE *Xhc,
707 IN URB *Urb
708 )
709 {
710 EFI_STATUS Status;
711 UINT8 Dci;
712 UINT8 SlotId;
713
714 Status = EFI_SUCCESS;
715 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
716 if (SlotId == 0) {
717 return EFI_DEVICE_ERROR;
718 }
719 Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
720 ASSERT (Dci < 32);
721
722 DEBUG ((EFI_D_INFO, "Stop Slot = %x,Dci = %x\n", SlotId, Dci));
723
724 //
725 // 1) Send Stop endpoint command to stop xHC from executing of the TDs on the endpoint
726 //
727 Status = XhcStopEndpoint(Xhc, SlotId, Dci, Urb);
728 if (EFI_ERROR(Status)) {
729 DEBUG ((EFI_D_ERROR, "XhcDequeueTrbFromEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
730 goto Done;
731 }
732
733 //
734 // 2)Set dequeue pointer
735 //
736 if (Urb->Finished && Urb->Result == EFI_USB_NOERROR) {
737 //
738 // Return Already Started to indicate the pending URB is finished.
739 // This fixes BULK data loss when transfer is detected as timeout
740 // but finished just before stopping endpoint.
741 //
742 Status = EFI_ALREADY_STARTED;
743 DEBUG ((DEBUG_INFO, "XhcDequeueTrbFromEndpoint: Pending URB is finished: Length Actual/Expect = %d/%d!\n", Urb->Completed, Urb->DataLen));
744 } else {
745 Status = XhcSetTrDequeuePointer(Xhc, SlotId, Dci, Urb);
746 if (EFI_ERROR (Status)) {
747 DEBUG ((DEBUG_ERROR, "XhcDequeueTrbFromEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status));
748 goto Done;
749 }
750 }
751
752 //
753 // 3)Ring the doorbell to transit from stop to active
754 //
755 XhcRingDoorBell (Xhc, SlotId, Dci);
756
757 Done:
758 return Status;
759 }
760
761 /**
762 Create XHCI event ring.
763
764 @param Xhc The XHCI Instance.
765 @param EventRing The created event ring.
766
767 **/
768 VOID
769 CreateEventRing (
770 IN USB_XHCI_INSTANCE *Xhc,
771 OUT EVENT_RING *EventRing
772 )
773 {
774 VOID *Buf;
775 EVENT_RING_SEG_TABLE_ENTRY *ERSTBase;
776 UINTN Size;
777 EFI_PHYSICAL_ADDRESS ERSTPhy;
778 EFI_PHYSICAL_ADDRESS DequeuePhy;
779
780 ASSERT (EventRing != NULL);
781
782 Size = sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER;
783 Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
784 ASSERT (Buf != NULL);
785 ASSERT (((UINTN) Buf & 0x3F) == 0);
786 ZeroMem (Buf, Size);
787
788 EventRing->EventRingSeg0 = Buf;
789 EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;
790 EventRing->EventRingDequeue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
791 EventRing->EventRingEnqueue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
792
793 DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);
794
795 //
796 // Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'
797 // and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.
798 //
799 EventRing->EventRingCCS = 1;
800
801 Size = sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER;
802 Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
803 ASSERT (Buf != NULL);
804 ASSERT (((UINTN) Buf & 0x3F) == 0);
805 ZeroMem (Buf, Size);
806
807 ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *) Buf;
808 EventRing->ERSTBase = ERSTBase;
809 ERSTBase->PtrLo = XHC_LOW_32BIT (DequeuePhy);
810 ERSTBase->PtrHi = XHC_HIGH_32BIT (DequeuePhy);
811 ERSTBase->RingTrbSize = EVENT_RING_TRB_NUMBER;
812
813 ERSTPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, ERSTBase, Size);
814
815 //
816 // Program the Interrupter Event Ring Segment Table Size (ERSTSZ) register (5.5.2.3.1)
817 //
818 XhcWriteRuntimeReg (
819 Xhc,
820 XHC_ERSTSZ_OFFSET,
821 ERST_NUMBER
822 );
823 //
824 // Program the Interrupter Event Ring Dequeue Pointer (ERDP) register (5.5.2.3.3)
825 //
826 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
827 // So divide it to two 32-bytes width register access.
828 //
829 XhcWriteRuntimeReg (
830 Xhc,
831 XHC_ERDP_OFFSET,
832 XHC_LOW_32BIT((UINT64)(UINTN)DequeuePhy)
833 );
834 XhcWriteRuntimeReg (
835 Xhc,
836 XHC_ERDP_OFFSET + 4,
837 XHC_HIGH_32BIT((UINT64)(UINTN)DequeuePhy)
838 );
839 //
840 // Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register(5.5.2.3.2)
841 //
842 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
843 // So divide it to two 32-bytes width register access.
844 //
845 XhcWriteRuntimeReg (
846 Xhc,
847 XHC_ERSTBA_OFFSET,
848 XHC_LOW_32BIT((UINT64)(UINTN)ERSTPhy)
849 );
850 XhcWriteRuntimeReg (
851 Xhc,
852 XHC_ERSTBA_OFFSET + 4,
853 XHC_HIGH_32BIT((UINT64)(UINTN)ERSTPhy)
854 );
855 //
856 // Need set IMAN IE bit to enble the ring interrupt
857 //
858 XhcSetRuntimeRegBit (Xhc, XHC_IMAN_OFFSET, XHC_IMAN_IE);
859 }
860
861 /**
862 Create XHCI transfer ring.
863
864 @param Xhc The XHCI Instance.
865 @param TrbNum The number of TRB in the ring.
866 @param TransferRing The created transfer ring.
867
868 **/
869 VOID
870 CreateTransferRing (
871 IN USB_XHCI_INSTANCE *Xhc,
872 IN UINTN TrbNum,
873 OUT TRANSFER_RING *TransferRing
874 )
875 {
876 VOID *Buf;
877 LINK_TRB *EndTrb;
878 EFI_PHYSICAL_ADDRESS PhyAddr;
879
880 Buf = UsbHcAllocateMem (Xhc->MemPool, sizeof (TRB_TEMPLATE) * TrbNum);
881 ASSERT (Buf != NULL);
882 ASSERT (((UINTN) Buf & 0x3F) == 0);
883 ZeroMem (Buf, sizeof (TRB_TEMPLATE) * TrbNum);
884
885 TransferRing->RingSeg0 = Buf;
886 TransferRing->TrbNumber = TrbNum;
887 TransferRing->RingEnqueue = (TRB_TEMPLATE *) TransferRing->RingSeg0;
888 TransferRing->RingDequeue = (TRB_TEMPLATE *) TransferRing->RingSeg0;
889 TransferRing->RingPCS = 1;
890 //
891 // 4.9.2 Transfer Ring Management
892 // To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to
893 // point to the first TRB in the ring.
894 //
895 EndTrb = (LINK_TRB *) ((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));
896 EndTrb->Type = TRB_TYPE_LINK;
897 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);
898 EndTrb->PtrLo = XHC_LOW_32BIT (PhyAddr);
899 EndTrb->PtrHi = XHC_HIGH_32BIT (PhyAddr);
900 //
901 // Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
902 //
903 EndTrb->TC = 1;
904 //
905 // Set Cycle bit as other TRB PCS init value
906 //
907 EndTrb->CycleBit = 0;
908 }
909
910 /**
911 Free XHCI event ring.
912
913 @param Xhc The XHCI Instance.
914 @param EventRing The event ring to be freed.
915
916 **/
917 EFI_STATUS
918 EFIAPI
919 XhcFreeEventRing (
920 IN USB_XHCI_INSTANCE *Xhc,
921 IN EVENT_RING *EventRing
922 )
923 {
924 if(EventRing->EventRingSeg0 == NULL) {
925 return EFI_SUCCESS;
926 }
927
928 //
929 // Free EventRing Segment 0
930 //
931 UsbHcFreeMem (Xhc->MemPool, EventRing->EventRingSeg0, sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER);
932
933 //
934 // Free ESRT table
935 //
936 UsbHcFreeMem (Xhc->MemPool, EventRing->ERSTBase, sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER);
937 return EFI_SUCCESS;
938 }
939
940 /**
941 Free the resouce allocated at initializing schedule.
942
943 @param Xhc The XHCI Instance.
944
945 **/
946 VOID
947 XhcFreeSched (
948 IN USB_XHCI_INSTANCE *Xhc
949 )
950 {
951 UINT32 Index;
952 UINT64 *ScratchEntry;
953
954 if (Xhc->ScratchBuf != NULL) {
955 ScratchEntry = Xhc->ScratchEntry;
956 for (Index = 0; Index < Xhc->MaxScratchpadBufs; Index++) {
957 //
958 // Free Scratchpad Buffers
959 //
960 UsbHcFreeAlignedPages (Xhc->PciIo, (VOID*)(UINTN)ScratchEntry[Index], EFI_SIZE_TO_PAGES (Xhc->PageSize), (VOID *) Xhc->ScratchEntryMap[Index]);
961 }
962 //
963 // Free Scratchpad Buffer Array
964 //
965 UsbHcFreeAlignedPages (Xhc->PciIo, Xhc->ScratchBuf, EFI_SIZE_TO_PAGES (Xhc->MaxScratchpadBufs * sizeof (UINT64)), Xhc->ScratchMap);
966 FreePool (Xhc->ScratchEntryMap);
967 FreePool (Xhc->ScratchEntry);
968 }
969
970 if (Xhc->CmdRing.RingSeg0 != NULL) {
971 UsbHcFreeMem (Xhc->MemPool, Xhc->CmdRing.RingSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);
972 Xhc->CmdRing.RingSeg0 = NULL;
973 }
974
975 XhcFreeEventRing (Xhc,&Xhc->EventRing);
976
977 if (Xhc->DCBAA != NULL) {
978 UsbHcFreeMem (Xhc->MemPool, Xhc->DCBAA, (Xhc->MaxSlotsEn + 1) * sizeof(UINT64));
979 Xhc->DCBAA = NULL;
980 }
981
982 //
983 // Free memory pool at last
984 //
985 if (Xhc->MemPool != NULL) {
986 UsbHcFreeMemPool (Xhc->MemPool);
987 Xhc->MemPool = NULL;
988 }
989 }
990
991 /**
992 Check if the Trb is a transaction of the URB.
993
994 @param Trb The TRB to be checked
995 @param Urb The URB to be checked.
996
997 @retval TRUE It is a transaction of the URB.
998 @retval FALSE It is not any transaction of the URB.
999
1000 **/
1001 BOOLEAN
1002 IsTransferRingTrb (
1003 IN USB_XHCI_INSTANCE *Xhc,
1004 IN TRB_TEMPLATE *Trb,
1005 IN URB *Urb
1006 )
1007 {
1008 LINK_TRB *LinkTrb;
1009 TRB_TEMPLATE *CheckedTrb;
1010 UINTN Index;
1011 EFI_PHYSICAL_ADDRESS PhyAddr;
1012
1013 CheckedTrb = Urb->TrbStart;
1014 for (Index = 0; Index < Urb->TrbNum; Index++) {
1015 if (Trb == CheckedTrb) {
1016 return TRUE;
1017 }
1018 CheckedTrb++;
1019 //
1020 // If the checked TRB is the link TRB at the end of the transfer ring,
1021 // recircle it to the head of the ring.
1022 //
1023 if (CheckedTrb->Type == TRB_TYPE_LINK) {
1024 LinkTrb = (LINK_TRB *) CheckedTrb;
1025 PhyAddr = (EFI_PHYSICAL_ADDRESS)(LinkTrb->PtrLo | LShiftU64 ((UINT64) LinkTrb->PtrHi, 32));
1026 CheckedTrb = (TRB_TEMPLATE *)(UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN) PhyAddr, sizeof (TRB_TEMPLATE));
1027 ASSERT (CheckedTrb == Urb->Ring->RingSeg0);
1028 }
1029 }
1030
1031 return FALSE;
1032 }
1033
1034 /**
1035 Check if the Trb is a transaction of the URBs in XHCI's asynchronous transfer list.
1036
1037 @param Xhc The XHCI Instance.
1038 @param Trb The TRB to be checked.
1039 @param Urb The pointer to the matched Urb.
1040
1041 @retval TRUE The Trb is matched with a transaction of the URBs in the async list.
1042 @retval FALSE The Trb is not matched with any URBs in the async list.
1043
1044 **/
1045 BOOLEAN
1046 IsAsyncIntTrb (
1047 IN USB_XHCI_INSTANCE *Xhc,
1048 IN TRB_TEMPLATE *Trb,
1049 OUT URB **Urb
1050 )
1051 {
1052 LIST_ENTRY *Entry;
1053 LIST_ENTRY *Next;
1054 URB *CheckedUrb;
1055
1056 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
1057 CheckedUrb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
1058 if (IsTransferRingTrb (Xhc, Trb, CheckedUrb)) {
1059 *Urb = CheckedUrb;
1060 return TRUE;
1061 }
1062 }
1063
1064 return FALSE;
1065 }
1066
1067
1068 /**
1069 Check the URB's execution result and update the URB's
1070 result accordingly.
1071
1072 @param Xhc The XHCI Instance.
1073 @param Urb The URB to check result.
1074
1075 @return Whether the result of URB transfer is finialized.
1076
1077 **/
1078 BOOLEAN
1079 XhcCheckUrbResult (
1080 IN USB_XHCI_INSTANCE *Xhc,
1081 IN URB *Urb
1082 )
1083 {
1084 EVT_TRB_TRANSFER *EvtTrb;
1085 TRB_TEMPLATE *TRBPtr;
1086 UINTN Index;
1087 UINT8 TRBType;
1088 EFI_STATUS Status;
1089 URB *AsyncUrb;
1090 URB *CheckedUrb;
1091 UINT64 XhcDequeue;
1092 UINT32 High;
1093 UINT32 Low;
1094 EFI_PHYSICAL_ADDRESS PhyAddr;
1095
1096 ASSERT ((Xhc != NULL) && (Urb != NULL));
1097
1098 Status = EFI_SUCCESS;
1099 AsyncUrb = NULL;
1100
1101 if (Urb->Finished) {
1102 goto EXIT;
1103 }
1104
1105 EvtTrb = NULL;
1106
1107 if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
1108 Urb->Result |= EFI_USB_ERR_SYSTEM;
1109 goto EXIT;
1110 }
1111
1112 //
1113 // Traverse the event ring to find out all new events from the previous check.
1114 //
1115 XhcSyncEventRing (Xhc, &Xhc->EventRing);
1116 for (Index = 0; Index < Xhc->EventRing.TrbNumber; Index++) {
1117 Status = XhcCheckNewEvent (Xhc, &Xhc->EventRing, ((TRB_TEMPLATE **)&EvtTrb));
1118 if (Status == EFI_NOT_READY) {
1119 //
1120 // All new events are handled, return directly.
1121 //
1122 goto EXIT;
1123 }
1124
1125 //
1126 // Only handle COMMAND_COMPLETETION_EVENT and TRANSFER_EVENT.
1127 //
1128 if ((EvtTrb->Type != TRB_TYPE_COMMAND_COMPLT_EVENT) && (EvtTrb->Type != TRB_TYPE_TRANS_EVENT)) {
1129 continue;
1130 }
1131
1132 //
1133 // Need convert pci device address to host address
1134 //
1135 PhyAddr = (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));
1136 TRBPtr = (TRB_TEMPLATE *)(UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN) PhyAddr, sizeof (TRB_TEMPLATE));
1137
1138 //
1139 // Update the status of URB including the pending URB, the URB that is currently checked,
1140 // and URBs in the XHCI's async interrupt transfer list.
1141 // This way is used to avoid that those completed async transfer events don't get
1142 // handled in time and are flushed by newer coming events.
1143 //
1144 if (Xhc->PendingUrb != NULL && IsTransferRingTrb (Xhc, TRBPtr, Xhc->PendingUrb)) {
1145 CheckedUrb = Xhc->PendingUrb;
1146 } else if (IsTransferRingTrb (Xhc, TRBPtr, Urb)) {
1147 CheckedUrb = Urb;
1148 } else if (IsAsyncIntTrb (Xhc, TRBPtr, &AsyncUrb)) {
1149 CheckedUrb = AsyncUrb;
1150 } else {
1151 continue;
1152 }
1153
1154 switch (EvtTrb->Completecode) {
1155 case TRB_COMPLETION_STALL_ERROR:
1156 CheckedUrb->Result |= EFI_USB_ERR_STALL;
1157 CheckedUrb->Finished = TRUE;
1158 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n",EvtTrb->Completecode));
1159 goto EXIT;
1160
1161 case TRB_COMPLETION_BABBLE_ERROR:
1162 CheckedUrb->Result |= EFI_USB_ERR_BABBLE;
1163 CheckedUrb->Finished = TRUE;
1164 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n",EvtTrb->Completecode));
1165 goto EXIT;
1166
1167 case TRB_COMPLETION_DATA_BUFFER_ERROR:
1168 CheckedUrb->Result |= EFI_USB_ERR_BUFFER;
1169 CheckedUrb->Finished = TRUE;
1170 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n",EvtTrb->Completecode));
1171 goto EXIT;
1172
1173 case TRB_COMPLETION_USB_TRANSACTION_ERROR:
1174 CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
1175 CheckedUrb->Finished = TRUE;
1176 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n",EvtTrb->Completecode));
1177 goto EXIT;
1178
1179 case TRB_COMPLETION_STOPPED:
1180 case TRB_COMPLETION_STOPPED_LENGTH_INVALID:
1181 CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
1182 CheckedUrb->Finished = TRUE;
1183 //
1184 // The pending URB is timeout and force stopped when stopping endpoint.
1185 // Continue the loop to receive the Command Complete Event for stopping endpoint.
1186 //
1187 continue;
1188
1189 case TRB_COMPLETION_SHORT_PACKET:
1190 case TRB_COMPLETION_SUCCESS:
1191 if (EvtTrb->Completecode == TRB_COMPLETION_SHORT_PACKET) {
1192 DEBUG ((EFI_D_VERBOSE, "XhcCheckUrbResult: short packet happens!\n"));
1193 }
1194
1195 TRBType = (UINT8) (TRBPtr->Type);
1196 if ((TRBType == TRB_TYPE_DATA_STAGE) ||
1197 (TRBType == TRB_TYPE_NORMAL) ||
1198 (TRBType == TRB_TYPE_ISOCH)) {
1199 CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL*)TRBPtr)->Length - EvtTrb->Length);
1200 }
1201
1202 break;
1203
1204 default:
1205 DEBUG ((EFI_D_ERROR, "Transfer Default Error Occur! Completecode = 0x%x!\n",EvtTrb->Completecode));
1206 CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
1207 CheckedUrb->Finished = TRUE;
1208 goto EXIT;
1209 }
1210
1211 //
1212 // Only check first and end Trb event address
1213 //
1214 if (TRBPtr == CheckedUrb->TrbStart) {
1215 CheckedUrb->StartDone = TRUE;
1216 }
1217
1218 if (TRBPtr == CheckedUrb->TrbEnd) {
1219 CheckedUrb->EndDone = TRUE;
1220 }
1221
1222 if (CheckedUrb->StartDone && CheckedUrb->EndDone) {
1223 CheckedUrb->Finished = TRUE;
1224 CheckedUrb->EvtTrb = (TRB_TEMPLATE *)EvtTrb;
1225 }
1226 }
1227
1228 EXIT:
1229
1230 //
1231 // Advance event ring to last available entry
1232 //
1233 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
1234 // So divide it to two 32-bytes width register access.
1235 //
1236 Low = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET);
1237 High = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);
1238 XhcDequeue = (UINT64)(LShiftU64((UINT64)High, 32) | Low);
1239
1240 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE));
1241
1242 if ((XhcDequeue & (~0x0F)) != (PhyAddr & (~0x0F))) {
1243 //
1244 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
1245 // So divide it to two 32-bytes width register access.
1246 //
1247 XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET, XHC_LOW_32BIT (PhyAddr) | BIT3);
1248 XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4, XHC_HIGH_32BIT (PhyAddr));
1249 }
1250
1251 return Urb->Finished;
1252 }
1253
1254
1255 /**
1256 Execute the transfer by polling the URB. This is a synchronous operation.
1257
1258 @param Xhc The XHCI Instance.
1259 @param CmdTransfer The executed URB is for cmd transfer or not.
1260 @param Urb The URB to execute.
1261 @param Timeout The time to wait before abort, in millisecond.
1262
1263 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
1264 @return EFI_TIMEOUT The transfer failed due to time out.
1265 @return EFI_SUCCESS The transfer finished OK.
1266
1267 **/
1268 EFI_STATUS
1269 XhcExecTransfer (
1270 IN USB_XHCI_INSTANCE *Xhc,
1271 IN BOOLEAN CmdTransfer,
1272 IN URB *Urb,
1273 IN UINTN Timeout
1274 )
1275 {
1276 EFI_STATUS Status;
1277 UINTN Index;
1278 UINT64 Loop;
1279 UINT8 SlotId;
1280 UINT8 Dci;
1281 BOOLEAN Finished;
1282
1283 if (CmdTransfer) {
1284 SlotId = 0;
1285 Dci = 0;
1286 } else {
1287 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
1288 if (SlotId == 0) {
1289 return EFI_DEVICE_ERROR;
1290 }
1291 Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
1292 ASSERT (Dci < 32);
1293 }
1294
1295 Status = EFI_SUCCESS;
1296 Loop = Timeout * XHC_1_MILLISECOND;
1297 if (Timeout == 0) {
1298 Loop = 0xFFFFFFFF;
1299 }
1300
1301 XhcRingDoorBell (Xhc, SlotId, Dci);
1302
1303 for (Index = 0; Index < Loop; Index++) {
1304 Finished = XhcCheckUrbResult (Xhc, Urb);
1305 if (Finished) {
1306 break;
1307 }
1308 gBS->Stall (XHC_1_MICROSECOND);
1309 }
1310
1311 if (Index == Loop) {
1312 Urb->Result = EFI_USB_ERR_TIMEOUT;
1313 Status = EFI_TIMEOUT;
1314 } else if (Urb->Result != EFI_USB_NOERROR) {
1315 Status = EFI_DEVICE_ERROR;
1316 }
1317
1318 return Status;
1319 }
1320
1321 /**
1322 Delete a single asynchronous interrupt transfer for
1323 the device and endpoint.
1324
1325 @param Xhc The XHCI Instance.
1326 @param BusAddr The logical device address assigned by UsbBus driver.
1327 @param EpNum The endpoint of the target.
1328
1329 @retval EFI_SUCCESS An asynchronous transfer is removed.
1330 @retval EFI_NOT_FOUND No transfer for the device is found.
1331
1332 **/
1333 EFI_STATUS
1334 XhciDelAsyncIntTransfer (
1335 IN USB_XHCI_INSTANCE *Xhc,
1336 IN UINT8 BusAddr,
1337 IN UINT8 EpNum
1338 )
1339 {
1340 LIST_ENTRY *Entry;
1341 LIST_ENTRY *Next;
1342 URB *Urb;
1343 EFI_USB_DATA_DIRECTION Direction;
1344 EFI_STATUS Status;
1345
1346 Direction = ((EpNum & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;
1347 EpNum &= 0x0F;
1348
1349 Urb = NULL;
1350
1351 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
1352 Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
1353 if ((Urb->Ep.BusAddr == BusAddr) &&
1354 (Urb->Ep.EpAddr == EpNum) &&
1355 (Urb->Ep.Direction == Direction)) {
1356 //
1357 // Device doesn't finish the IntTransfer until real data comes
1358 // So the TRB should be removed as well.
1359 //
1360 Status = XhcDequeueTrbFromEndpoint (Xhc, Urb);
1361 if (EFI_ERROR (Status)) {
1362 DEBUG ((EFI_D_ERROR, "XhciDelAsyncIntTransfer: XhcDequeueTrbFromEndpoint failed\n"));
1363 }
1364
1365 RemoveEntryList (&Urb->UrbList);
1366 FreePool (Urb->Data);
1367 XhcFreeUrb (Xhc, Urb);
1368 return EFI_SUCCESS;
1369 }
1370 }
1371
1372 return EFI_NOT_FOUND;
1373 }
1374
1375 /**
1376 Remove all the asynchronous interrutp transfers.
1377
1378 @param Xhc The XHCI Instance.
1379
1380 **/
1381 VOID
1382 XhciDelAllAsyncIntTransfers (
1383 IN USB_XHCI_INSTANCE *Xhc
1384 )
1385 {
1386 LIST_ENTRY *Entry;
1387 LIST_ENTRY *Next;
1388 URB *Urb;
1389 EFI_STATUS Status;
1390
1391 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
1392 Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
1393
1394 //
1395 // Device doesn't finish the IntTransfer until real data comes
1396 // So the TRB should be removed as well.
1397 //
1398 Status = XhcDequeueTrbFromEndpoint (Xhc, Urb);
1399 if (EFI_ERROR (Status)) {
1400 DEBUG ((EFI_D_ERROR, "XhciDelAllAsyncIntTransfers: XhcDequeueTrbFromEndpoint failed\n"));
1401 }
1402
1403 RemoveEntryList (&Urb->UrbList);
1404 FreePool (Urb->Data);
1405 XhcFreeUrb (Xhc, Urb);
1406 }
1407 }
1408
1409 /**
1410 Update the queue head for next round of asynchronous transfer
1411
1412 @param Xhc The XHCI Instance.
1413 @param Urb The URB to update
1414
1415 **/
1416 VOID
1417 XhcUpdateAsyncRequest (
1418 IN USB_XHCI_INSTANCE *Xhc,
1419 IN URB *Urb
1420 )
1421 {
1422 EFI_STATUS Status;
1423
1424 if (Urb->Result == EFI_USB_NOERROR) {
1425 Status = XhcCreateTransferTrb (Xhc, Urb);
1426 if (EFI_ERROR (Status)) {
1427 return;
1428 }
1429 Status = RingIntTransferDoorBell (Xhc, Urb);
1430 if (EFI_ERROR (Status)) {
1431 return;
1432 }
1433 }
1434 }
1435
1436 /**
1437 Flush data from PCI controller specific address to mapped system
1438 memory address.
1439
1440 @param Xhc The XHCI device.
1441 @param Urb The URB to unmap.
1442
1443 @retval EFI_SUCCESS Success to flush data to mapped system memory.
1444 @retval EFI_DEVICE_ERROR Fail to flush data to mapped system memory.
1445
1446 **/
1447 EFI_STATUS
1448 XhcFlushAsyncIntMap (
1449 IN USB_XHCI_INSTANCE *Xhc,
1450 IN URB *Urb
1451 )
1452 {
1453 EFI_STATUS Status;
1454 EFI_PHYSICAL_ADDRESS PhyAddr;
1455 EFI_PCI_IO_PROTOCOL_OPERATION MapOp;
1456 EFI_PCI_IO_PROTOCOL *PciIo;
1457 UINTN Len;
1458 VOID *Map;
1459
1460 PciIo = Xhc->PciIo;
1461 Len = Urb->DataLen;
1462
1463 if (Urb->Ep.Direction == EfiUsbDataIn) {
1464 MapOp = EfiPciIoOperationBusMasterWrite;
1465 } else {
1466 MapOp = EfiPciIoOperationBusMasterRead;
1467 }
1468
1469 if (Urb->DataMap != NULL) {
1470 Status = PciIo->Unmap (PciIo, Urb->DataMap);
1471 if (EFI_ERROR (Status)) {
1472 goto ON_ERROR;
1473 }
1474 }
1475
1476 Urb->DataMap = NULL;
1477
1478 Status = PciIo->Map (PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);
1479 if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {
1480 goto ON_ERROR;
1481 }
1482
1483 Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
1484 Urb->DataMap = Map;
1485 return EFI_SUCCESS;
1486
1487 ON_ERROR:
1488 return EFI_DEVICE_ERROR;
1489 }
1490
1491 /**
1492 Interrupt transfer periodic check handler.
1493
1494 @param Event Interrupt event.
1495 @param Context Pointer to USB_XHCI_INSTANCE.
1496
1497 **/
1498 VOID
1499 EFIAPI
1500 XhcMonitorAsyncRequests (
1501 IN EFI_EVENT Event,
1502 IN VOID *Context
1503 )
1504 {
1505 USB_XHCI_INSTANCE *Xhc;
1506 LIST_ENTRY *Entry;
1507 LIST_ENTRY *Next;
1508 UINT8 *ProcBuf;
1509 URB *Urb;
1510 UINT8 SlotId;
1511 EFI_STATUS Status;
1512 EFI_TPL OldTpl;
1513
1514 OldTpl = gBS->RaiseTPL (XHC_TPL);
1515
1516 Xhc = (USB_XHCI_INSTANCE*) Context;
1517
1518 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
1519 Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
1520
1521 //
1522 // Make sure that the device is available before every check.
1523 //
1524 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
1525 if (SlotId == 0) {
1526 continue;
1527 }
1528
1529 //
1530 // Check the result of URB execution. If it is still
1531 // active, check the next one.
1532 //
1533 XhcCheckUrbResult (Xhc, Urb);
1534
1535 if (!Urb->Finished) {
1536 continue;
1537 }
1538
1539 //
1540 // Flush any PCI posted write transactions from a PCI host
1541 // bridge to system memory.
1542 //
1543 Status = XhcFlushAsyncIntMap (Xhc, Urb);
1544 if (EFI_ERROR (Status)) {
1545 DEBUG ((EFI_D_ERROR, "XhcMonitorAsyncRequests: Fail to Flush AsyncInt Mapped Memeory\n"));
1546 }
1547
1548 //
1549 // Allocate a buffer then copy the transferred data for user.
1550 // If failed to allocate the buffer, update the URB for next
1551 // round of transfer. Ignore the data of this round.
1552 //
1553 ProcBuf = NULL;
1554 if (Urb->Result == EFI_USB_NOERROR) {
1555 ASSERT (Urb->Completed <= Urb->DataLen);
1556
1557 ProcBuf = AllocateZeroPool (Urb->Completed);
1558
1559 if (ProcBuf == NULL) {
1560 XhcUpdateAsyncRequest (Xhc, Urb);
1561 continue;
1562 }
1563
1564 CopyMem (ProcBuf, Urb->Data, Urb->Completed);
1565 }
1566
1567 //
1568 // Leave error recovery to its related device driver. A
1569 // common case of the error recovery is to re-submit the
1570 // interrupt transfer which is linked to the head of the
1571 // list. This function scans from head to tail. So the
1572 // re-submitted interrupt transfer's callback function
1573 // will not be called again in this round. Don't touch this
1574 // URB after the callback, it may have been removed by the
1575 // callback.
1576 //
1577 if (Urb->Callback != NULL) {
1578 //
1579 // Restore the old TPL, USB bus maybe connect device in
1580 // his callback. Some drivers may has a lower TPL restriction.
1581 //
1582 gBS->RestoreTPL (OldTpl);
1583 (Urb->Callback) (ProcBuf, Urb->Completed, Urb->Context, Urb->Result);
1584 OldTpl = gBS->RaiseTPL (XHC_TPL);
1585 }
1586
1587 if (ProcBuf != NULL) {
1588 gBS->FreePool (ProcBuf);
1589 }
1590
1591 XhcUpdateAsyncRequest (Xhc, Urb);
1592 }
1593 gBS->RestoreTPL (OldTpl);
1594 }
1595
1596 /**
1597 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.
1598
1599 @param Xhc The XHCI Instance.
1600 @param ParentRouteChart The route string pointed to the parent device if it exists.
1601 @param Port The port to be polled.
1602 @param PortState The port state.
1603
1604 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.
1605 @retval Others Should not appear.
1606
1607 **/
1608 EFI_STATUS
1609 EFIAPI
1610 XhcPollPortStatusChange (
1611 IN USB_XHCI_INSTANCE *Xhc,
1612 IN USB_DEV_ROUTE ParentRouteChart,
1613 IN UINT8 Port,
1614 IN EFI_USB_PORT_STATUS *PortState
1615 )
1616 {
1617 EFI_STATUS Status;
1618 UINT8 Speed;
1619 UINT8 SlotId;
1620 USB_DEV_ROUTE RouteChart;
1621
1622 Status = EFI_SUCCESS;
1623
1624 if ((PortState->PortChangeStatus & (USB_PORT_STAT_C_CONNECTION | USB_PORT_STAT_C_ENABLE | USB_PORT_STAT_C_OVERCURRENT | USB_PORT_STAT_C_RESET)) == 0) {
1625 return EFI_SUCCESS;
1626 }
1627
1628 if (ParentRouteChart.Dword == 0) {
1629 RouteChart.Route.RouteString = 0;
1630 RouteChart.Route.RootPortNum = Port + 1;
1631 RouteChart.Route.TierNum = 1;
1632 } else {
1633 if(Port < 14) {
1634 RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (Port << (4 * (ParentRouteChart.Route.TierNum - 1)));
1635 } else {
1636 RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (15 << (4 * (ParentRouteChart.Route.TierNum - 1)));
1637 }
1638 RouteChart.Route.RootPortNum = ParentRouteChart.Route.RootPortNum;
1639 RouteChart.Route.TierNum = ParentRouteChart.Route.TierNum + 1;
1640 }
1641
1642 SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);
1643 if (SlotId != 0) {
1644 if (Xhc->HcCParams.Data.Csz == 0) {
1645 Status = XhcDisableSlotCmd (Xhc, SlotId);
1646 } else {
1647 Status = XhcDisableSlotCmd64 (Xhc, SlotId);
1648 }
1649 }
1650
1651 if (((PortState->PortStatus & USB_PORT_STAT_ENABLE) != 0) &&
1652 ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0)) {
1653 //
1654 // Has a device attached, Identify device speed after port is enabled.
1655 //
1656 Speed = EFI_USB_SPEED_FULL;
1657 if ((PortState->PortStatus & USB_PORT_STAT_LOW_SPEED) != 0) {
1658 Speed = EFI_USB_SPEED_LOW;
1659 } else if ((PortState->PortStatus & USB_PORT_STAT_HIGH_SPEED) != 0) {
1660 Speed = EFI_USB_SPEED_HIGH;
1661 } else if ((PortState->PortStatus & USB_PORT_STAT_SUPER_SPEED) != 0) {
1662 Speed = EFI_USB_SPEED_SUPER;
1663 }
1664 //
1665 // Execute Enable_Slot cmd for attached device, initialize device context and assign device address.
1666 //
1667 SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);
1668 if ((SlotId == 0) && ((PortState->PortChangeStatus & USB_PORT_STAT_C_RESET) != 0)) {
1669 if (Xhc->HcCParams.Data.Csz == 0) {
1670 Status = XhcInitializeDeviceSlot (Xhc, ParentRouteChart, Port, RouteChart, Speed);
1671 } else {
1672 Status = XhcInitializeDeviceSlot64 (Xhc, ParentRouteChart, Port, RouteChart, Speed);
1673 }
1674 }
1675 }
1676
1677 return Status;
1678 }
1679
1680
1681 /**
1682 Calculate the device context index by endpoint address and direction.
1683
1684 @param EpAddr The target endpoint number.
1685 @param Direction The direction of the target endpoint.
1686
1687 @return The device context index of endpoint.
1688
1689 **/
1690 UINT8
1691 XhcEndpointToDci (
1692 IN UINT8 EpAddr,
1693 IN UINT8 Direction
1694 )
1695 {
1696 UINT8 Index;
1697
1698 if (EpAddr == 0) {
1699 return 1;
1700 } else {
1701 Index = (UINT8) (2 * EpAddr);
1702 if (Direction == EfiUsbDataIn) {
1703 Index += 1;
1704 }
1705 return Index;
1706 }
1707 }
1708
1709 /**
1710 Find out the actual device address according to the requested device address from UsbBus.
1711
1712 @param Xhc The XHCI Instance.
1713 @param BusDevAddr The requested device address by UsbBus upper driver.
1714
1715 @return The actual device address assigned to the device.
1716
1717 **/
1718 UINT8
1719 EFIAPI
1720 XhcBusDevAddrToSlotId (
1721 IN USB_XHCI_INSTANCE *Xhc,
1722 IN UINT8 BusDevAddr
1723 )
1724 {
1725 UINT8 Index;
1726
1727 for (Index = 0; Index < 255; Index++) {
1728 if (Xhc->UsbDevContext[Index + 1].Enabled &&
1729 (Xhc->UsbDevContext[Index + 1].SlotId != 0) &&
1730 (Xhc->UsbDevContext[Index + 1].BusDevAddr == BusDevAddr)) {
1731 break;
1732 }
1733 }
1734
1735 if (Index == 255) {
1736 return 0;
1737 }
1738
1739 return Xhc->UsbDevContext[Index + 1].SlotId;
1740 }
1741
1742 /**
1743 Find out the slot id according to the device's route string.
1744
1745 @param Xhc The XHCI Instance.
1746 @param RouteString The route string described the device location.
1747
1748 @return The slot id used by the device.
1749
1750 **/
1751 UINT8
1752 EFIAPI
1753 XhcRouteStringToSlotId (
1754 IN USB_XHCI_INSTANCE *Xhc,
1755 IN USB_DEV_ROUTE RouteString
1756 )
1757 {
1758 UINT8 Index;
1759
1760 for (Index = 0; Index < 255; Index++) {
1761 if (Xhc->UsbDevContext[Index + 1].Enabled &&
1762 (Xhc->UsbDevContext[Index + 1].SlotId != 0) &&
1763 (Xhc->UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword)) {
1764 break;
1765 }
1766 }
1767
1768 if (Index == 255) {
1769 return 0;
1770 }
1771
1772 return Xhc->UsbDevContext[Index + 1].SlotId;
1773 }
1774
1775 /**
1776 Synchronize the specified event ring to update the enqueue and dequeue pointer.
1777
1778 @param Xhc The XHCI Instance.
1779 @param EvtRing The event ring to sync.
1780
1781 @retval EFI_SUCCESS The event ring is synchronized successfully.
1782
1783 **/
1784 EFI_STATUS
1785 EFIAPI
1786 XhcSyncEventRing (
1787 IN USB_XHCI_INSTANCE *Xhc,
1788 IN EVENT_RING *EvtRing
1789 )
1790 {
1791 UINTN Index;
1792 TRB_TEMPLATE *EvtTrb1;
1793
1794 ASSERT (EvtRing != NULL);
1795
1796 //
1797 // Calculate the EventRingEnqueue and EventRingCCS.
1798 // Note: only support single Segment
1799 //
1800 EvtTrb1 = EvtRing->EventRingDequeue;
1801
1802 for (Index = 0; Index < EvtRing->TrbNumber; Index++) {
1803 if (EvtTrb1->CycleBit != EvtRing->EventRingCCS) {
1804 break;
1805 }
1806
1807 EvtTrb1++;
1808
1809 if ((UINTN)EvtTrb1 >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
1810 EvtTrb1 = EvtRing->EventRingSeg0;
1811 EvtRing->EventRingCCS = (EvtRing->EventRingCCS) ? 0 : 1;
1812 }
1813 }
1814
1815 if (Index < EvtRing->TrbNumber) {
1816 EvtRing->EventRingEnqueue = EvtTrb1;
1817 } else {
1818 ASSERT (FALSE);
1819 }
1820
1821 return EFI_SUCCESS;
1822 }
1823
1824 /**
1825 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
1826
1827 @param Xhc The XHCI Instance.
1828 @param TrsRing The transfer ring to sync.
1829
1830 @retval EFI_SUCCESS The transfer ring is synchronized successfully.
1831
1832 **/
1833 EFI_STATUS
1834 EFIAPI
1835 XhcSyncTrsRing (
1836 IN USB_XHCI_INSTANCE *Xhc,
1837 IN TRANSFER_RING *TrsRing
1838 )
1839 {
1840 UINTN Index;
1841 TRB_TEMPLATE *TrsTrb;
1842
1843 ASSERT (TrsRing != NULL);
1844 //
1845 // Calculate the latest RingEnqueue and RingPCS
1846 //
1847 TrsTrb = TrsRing->RingEnqueue;
1848 ASSERT (TrsTrb != NULL);
1849
1850 for (Index = 0; Index < TrsRing->TrbNumber; Index++) {
1851 if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {
1852 break;
1853 }
1854 TrsTrb++;
1855 if ((UINT8) TrsTrb->Type == TRB_TYPE_LINK) {
1856 ASSERT (((LINK_TRB*)TrsTrb)->TC != 0);
1857 //
1858 // set cycle bit in Link TRB as normal
1859 //
1860 ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
1861 //
1862 // Toggle PCS maintained by software
1863 //
1864 TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1;
1865 TrsTrb = (TRB_TEMPLATE *) TrsRing->RingSeg0; // Use host address
1866 }
1867 }
1868
1869 ASSERT (Index != TrsRing->TrbNumber);
1870
1871 if (TrsTrb != TrsRing->RingEnqueue) {
1872 TrsRing->RingEnqueue = TrsTrb;
1873 }
1874
1875 //
1876 // Clear the Trb context for enqueue, but reserve the PCS bit
1877 //
1878 TrsTrb->Parameter1 = 0;
1879 TrsTrb->Parameter2 = 0;
1880 TrsTrb->Status = 0;
1881 TrsTrb->RsvdZ1 = 0;
1882 TrsTrb->Type = 0;
1883 TrsTrb->Control = 0;
1884
1885 return EFI_SUCCESS;
1886 }
1887
1888 /**
1889 Check if there is a new generated event.
1890
1891 @param Xhc The XHCI Instance.
1892 @param EvtRing The event ring to check.
1893 @param NewEvtTrb The new event TRB found.
1894
1895 @retval EFI_SUCCESS Found a new event TRB at the event ring.
1896 @retval EFI_NOT_READY The event ring has no new event.
1897
1898 **/
1899 EFI_STATUS
1900 EFIAPI
1901 XhcCheckNewEvent (
1902 IN USB_XHCI_INSTANCE *Xhc,
1903 IN EVENT_RING *EvtRing,
1904 OUT TRB_TEMPLATE **NewEvtTrb
1905 )
1906 {
1907 ASSERT (EvtRing != NULL);
1908
1909 *NewEvtTrb = EvtRing->EventRingDequeue;
1910
1911 if (EvtRing->EventRingDequeue == EvtRing->EventRingEnqueue) {
1912 return EFI_NOT_READY;
1913 }
1914
1915 EvtRing->EventRingDequeue++;
1916 //
1917 // If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.
1918 //
1919 if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
1920 EvtRing->EventRingDequeue = EvtRing->EventRingSeg0;
1921 }
1922
1923 return EFI_SUCCESS;
1924 }
1925
1926 /**
1927 Ring the door bell to notify XHCI there is a transaction to be executed.
1928
1929 @param Xhc The XHCI Instance.
1930 @param SlotId The slot id of the target device.
1931 @param Dci The device context index of the target slot or endpoint.
1932
1933 @retval EFI_SUCCESS Successfully ring the door bell.
1934
1935 **/
1936 EFI_STATUS
1937 EFIAPI
1938 XhcRingDoorBell (
1939 IN USB_XHCI_INSTANCE *Xhc,
1940 IN UINT8 SlotId,
1941 IN UINT8 Dci
1942 )
1943 {
1944 if (SlotId == 0) {
1945 XhcWriteDoorBellReg (Xhc, 0, 0);
1946 } else {
1947 XhcWriteDoorBellReg (Xhc, SlotId * sizeof (UINT32), Dci);
1948 }
1949
1950 return EFI_SUCCESS;
1951 }
1952
1953 /**
1954 Ring the door bell to notify XHCI there is a transaction to be executed through URB.
1955
1956 @param Xhc The XHCI Instance.
1957 @param Urb The URB to be rung.
1958
1959 @retval EFI_SUCCESS Successfully ring the door bell.
1960
1961 **/
1962 EFI_STATUS
1963 RingIntTransferDoorBell (
1964 IN USB_XHCI_INSTANCE *Xhc,
1965 IN URB *Urb
1966 )
1967 {
1968 UINT8 SlotId;
1969 UINT8 Dci;
1970
1971 SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
1972 Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
1973 XhcRingDoorBell (Xhc, SlotId, Dci);
1974 return EFI_SUCCESS;
1975 }
1976
1977 /**
1978 Assign and initialize the device slot for a new device.
1979
1980 @param Xhc The XHCI Instance.
1981 @param ParentRouteChart The route string pointed to the parent device.
1982 @param ParentPort The port at which the device is located.
1983 @param RouteChart The route string pointed to the device.
1984 @param DeviceSpeed The device speed.
1985
1986 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1987
1988 **/
1989 EFI_STATUS
1990 EFIAPI
1991 XhcInitializeDeviceSlot (
1992 IN USB_XHCI_INSTANCE *Xhc,
1993 IN USB_DEV_ROUTE ParentRouteChart,
1994 IN UINT16 ParentPort,
1995 IN USB_DEV_ROUTE RouteChart,
1996 IN UINT8 DeviceSpeed
1997 )
1998 {
1999 EFI_STATUS Status;
2000 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
2001 INPUT_CONTEXT *InputContext;
2002 DEVICE_CONTEXT *OutputContext;
2003 TRANSFER_RING *EndpointTransferRing;
2004 CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;
2005 UINT8 DeviceAddress;
2006 CMD_TRB_ENABLE_SLOT CmdTrb;
2007 UINT8 SlotId;
2008 UINT8 ParentSlotId;
2009 DEVICE_CONTEXT *ParentDeviceContext;
2010 EFI_PHYSICAL_ADDRESS PhyAddr;
2011
2012 ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));
2013 CmdTrb.CycleBit = 1;
2014 CmdTrb.Type = TRB_TYPE_EN_SLOT;
2015
2016 Status = XhcCmdTransfer (
2017 Xhc,
2018 (TRB_TEMPLATE *) (UINTN) &CmdTrb,
2019 XHC_GENERIC_TIMEOUT,
2020 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2021 );
2022 if (EFI_ERROR (Status)) {
2023 DEBUG ((EFI_D_ERROR, "XhcInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status));
2024 return Status;
2025 }
2026 ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
2027 DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
2028 SlotId = (UINT8)EvtTrb->SlotId;
2029 ASSERT (SlotId != 0);
2030
2031 ZeroMem (&Xhc->UsbDevContext[SlotId], sizeof (USB_DEV_CONTEXT));
2032 Xhc->UsbDevContext[SlotId].Enabled = TRUE;
2033 Xhc->UsbDevContext[SlotId].SlotId = SlotId;
2034 Xhc->UsbDevContext[SlotId].RouteString.Dword = RouteChart.Dword;
2035 Xhc->UsbDevContext[SlotId].ParentRouteString.Dword = ParentRouteChart.Dword;
2036
2037 //
2038 // 4.3.3 Device Slot Initialization
2039 // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
2040 //
2041 InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT));
2042 ASSERT (InputContext != NULL);
2043 ASSERT (((UINTN) InputContext & 0x3F) == 0);
2044 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
2045
2046 Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;
2047
2048 //
2049 // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
2050 // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input
2051 // Context are affected by the command.
2052 //
2053 InputContext->InputControlContext.Dword2 |= (BIT0 | BIT1);
2054
2055 //
2056 // 3) Initialize the Input Slot Context data structure
2057 //
2058 InputContext->Slot.RouteString = RouteChart.Route.RouteString;
2059 InputContext->Slot.Speed = DeviceSpeed + 1;
2060 InputContext->Slot.ContextEntries = 1;
2061 InputContext->Slot.RootHubPortNum = RouteChart.Route.RootPortNum;
2062
2063 if (RouteChart.Route.RouteString) {
2064 //
2065 // The device is behind of hub device.
2066 //
2067 ParentSlotId = XhcRouteStringToSlotId(Xhc, ParentRouteChart);
2068 ASSERT (ParentSlotId != 0);
2069 //
2070 //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
2071 //
2072 ParentDeviceContext = (DEVICE_CONTEXT *)Xhc->UsbDevContext[ParentSlotId].OutputContext;
2073 if ((ParentDeviceContext->Slot.TTPortNum == 0) &&
2074 (ParentDeviceContext->Slot.TTHubSlotId == 0)) {
2075 if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {
2076 //
2077 // Full/Low device attached to High speed hub port that isolates the high speed signaling
2078 // environment from Full/Low speed signaling environment for a device
2079 //
2080 InputContext->Slot.TTPortNum = ParentPort;
2081 InputContext->Slot.TTHubSlotId = ParentSlotId;
2082 }
2083 } else {
2084 //
2085 // Inherit the TT parameters from parent device.
2086 //
2087 InputContext->Slot.TTPortNum = ParentDeviceContext->Slot.TTPortNum;
2088 InputContext->Slot.TTHubSlotId = ParentDeviceContext->Slot.TTHubSlotId;
2089 //
2090 // If the device is a High speed device then down the speed to be the same as its parent Hub
2091 //
2092 if (DeviceSpeed == EFI_USB_SPEED_HIGH) {
2093 InputContext->Slot.Speed = ParentDeviceContext->Slot.Speed;
2094 }
2095 }
2096 }
2097
2098 //
2099 // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
2100 //
2101 EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
2102 Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;
2103 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
2104 //
2105 // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
2106 //
2107 InputContext->EP[0].EPType = ED_CONTROL_BIDIR;
2108
2109 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
2110 InputContext->EP[0].MaxPacketSize = 512;
2111 } else if (DeviceSpeed == EFI_USB_SPEED_HIGH) {
2112 InputContext->EP[0].MaxPacketSize = 64;
2113 } else {
2114 InputContext->EP[0].MaxPacketSize = 8;
2115 }
2116 //
2117 // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
2118 // 1KB, and Bulk and Isoch endpoints 3KB.
2119 //
2120 InputContext->EP[0].AverageTRBLength = 8;
2121 InputContext->EP[0].MaxBurstSize = 0;
2122 InputContext->EP[0].Interval = 0;
2123 InputContext->EP[0].MaxPStreams = 0;
2124 InputContext->EP[0].Mult = 0;
2125 InputContext->EP[0].CErr = 3;
2126
2127 //
2128 // Init the DCS(dequeue cycle state) as the transfer ring's CCS
2129 //
2130 PhyAddr = UsbHcGetPciAddrForHostAddr (
2131 Xhc->MemPool,
2132 ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,
2133 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
2134 );
2135 InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;
2136 InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);
2137
2138 //
2139 // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
2140 //
2141 OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT));
2142 ASSERT (OutputContext != NULL);
2143 ASSERT (((UINTN) OutputContext & 0x3F) == 0);
2144 ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT));
2145
2146 Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;
2147 //
2148 // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
2149 // a pointer to the Output Device Context data structure (6.2.1).
2150 //
2151 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT));
2152 //
2153 // Fill DCBAA with PCI device address
2154 //
2155 Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;
2156
2157 //
2158 // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
2159 // Context data structure described above.
2160 //
2161 // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request
2162 // to device.
2163 //
2164 gBS->Stall (XHC_RESET_RECOVERY_DELAY);
2165 ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
2166 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
2167 CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
2168 CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);
2169 CmdTrbAddr.CycleBit = 1;
2170 CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;
2171 CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
2172 Status = XhcCmdTransfer (
2173 Xhc,
2174 (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,
2175 XHC_GENERIC_TIMEOUT,
2176 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2177 );
2178 if (!EFI_ERROR (Status)) {
2179 DeviceAddress = (UINT8) ((DEVICE_CONTEXT *) OutputContext)->Slot.DeviceAddress;
2180 DEBUG ((EFI_D_INFO, " Address %d assigned successfully\n", DeviceAddress));
2181 Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
2182 }
2183
2184 return Status;
2185 }
2186
2187 /**
2188 Assign and initialize the device slot for a new device.
2189
2190 @param Xhc The XHCI Instance.
2191 @param ParentRouteChart The route string pointed to the parent device.
2192 @param ParentPort The port at which the device is located.
2193 @param RouteChart The route string pointed to the device.
2194 @param DeviceSpeed The device speed.
2195
2196 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
2197
2198 **/
2199 EFI_STATUS
2200 EFIAPI
2201 XhcInitializeDeviceSlot64 (
2202 IN USB_XHCI_INSTANCE *Xhc,
2203 IN USB_DEV_ROUTE ParentRouteChart,
2204 IN UINT16 ParentPort,
2205 IN USB_DEV_ROUTE RouteChart,
2206 IN UINT8 DeviceSpeed
2207 )
2208 {
2209 EFI_STATUS Status;
2210 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
2211 INPUT_CONTEXT_64 *InputContext;
2212 DEVICE_CONTEXT_64 *OutputContext;
2213 TRANSFER_RING *EndpointTransferRing;
2214 CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;
2215 UINT8 DeviceAddress;
2216 CMD_TRB_ENABLE_SLOT CmdTrb;
2217 UINT8 SlotId;
2218 UINT8 ParentSlotId;
2219 DEVICE_CONTEXT_64 *ParentDeviceContext;
2220 EFI_PHYSICAL_ADDRESS PhyAddr;
2221
2222 ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));
2223 CmdTrb.CycleBit = 1;
2224 CmdTrb.Type = TRB_TYPE_EN_SLOT;
2225
2226 Status = XhcCmdTransfer (
2227 Xhc,
2228 (TRB_TEMPLATE *) (UINTN) &CmdTrb,
2229 XHC_GENERIC_TIMEOUT,
2230 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2231 );
2232 if (EFI_ERROR (Status)) {
2233 DEBUG ((EFI_D_ERROR, "XhcInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status));
2234 return Status;
2235 }
2236 ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
2237 DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
2238 SlotId = (UINT8)EvtTrb->SlotId;
2239 ASSERT (SlotId != 0);
2240
2241 ZeroMem (&Xhc->UsbDevContext[SlotId], sizeof (USB_DEV_CONTEXT));
2242 Xhc->UsbDevContext[SlotId].Enabled = TRUE;
2243 Xhc->UsbDevContext[SlotId].SlotId = SlotId;
2244 Xhc->UsbDevContext[SlotId].RouteString.Dword = RouteChart.Dword;
2245 Xhc->UsbDevContext[SlotId].ParentRouteString.Dword = ParentRouteChart.Dword;
2246
2247 //
2248 // 4.3.3 Device Slot Initialization
2249 // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
2250 //
2251 InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT_64));
2252 ASSERT (InputContext != NULL);
2253 ASSERT (((UINTN) InputContext & 0x3F) == 0);
2254 ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
2255
2256 Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;
2257
2258 //
2259 // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
2260 // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input
2261 // Context are affected by the command.
2262 //
2263 InputContext->InputControlContext.Dword2 |= (BIT0 | BIT1);
2264
2265 //
2266 // 3) Initialize the Input Slot Context data structure
2267 //
2268 InputContext->Slot.RouteString = RouteChart.Route.RouteString;
2269 InputContext->Slot.Speed = DeviceSpeed + 1;
2270 InputContext->Slot.ContextEntries = 1;
2271 InputContext->Slot.RootHubPortNum = RouteChart.Route.RootPortNum;
2272
2273 if (RouteChart.Route.RouteString) {
2274 //
2275 // The device is behind of hub device.
2276 //
2277 ParentSlotId = XhcRouteStringToSlotId(Xhc, ParentRouteChart);
2278 ASSERT (ParentSlotId != 0);
2279 //
2280 //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
2281 //
2282 ParentDeviceContext = (DEVICE_CONTEXT_64 *)Xhc->UsbDevContext[ParentSlotId].OutputContext;
2283 if ((ParentDeviceContext->Slot.TTPortNum == 0) &&
2284 (ParentDeviceContext->Slot.TTHubSlotId == 0)) {
2285 if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {
2286 //
2287 // Full/Low device attached to High speed hub port that isolates the high speed signaling
2288 // environment from Full/Low speed signaling environment for a device
2289 //
2290 InputContext->Slot.TTPortNum = ParentPort;
2291 InputContext->Slot.TTHubSlotId = ParentSlotId;
2292 }
2293 } else {
2294 //
2295 // Inherit the TT parameters from parent device.
2296 //
2297 InputContext->Slot.TTPortNum = ParentDeviceContext->Slot.TTPortNum;
2298 InputContext->Slot.TTHubSlotId = ParentDeviceContext->Slot.TTHubSlotId;
2299 //
2300 // If the device is a High speed device then down the speed to be the same as its parent Hub
2301 //
2302 if (DeviceSpeed == EFI_USB_SPEED_HIGH) {
2303 InputContext->Slot.Speed = ParentDeviceContext->Slot.Speed;
2304 }
2305 }
2306 }
2307
2308 //
2309 // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
2310 //
2311 EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
2312 Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;
2313 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
2314 //
2315 // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
2316 //
2317 InputContext->EP[0].EPType = ED_CONTROL_BIDIR;
2318
2319 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
2320 InputContext->EP[0].MaxPacketSize = 512;
2321 } else if (DeviceSpeed == EFI_USB_SPEED_HIGH) {
2322 InputContext->EP[0].MaxPacketSize = 64;
2323 } else {
2324 InputContext->EP[0].MaxPacketSize = 8;
2325 }
2326 //
2327 // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
2328 // 1KB, and Bulk and Isoch endpoints 3KB.
2329 //
2330 InputContext->EP[0].AverageTRBLength = 8;
2331 InputContext->EP[0].MaxBurstSize = 0;
2332 InputContext->EP[0].Interval = 0;
2333 InputContext->EP[0].MaxPStreams = 0;
2334 InputContext->EP[0].Mult = 0;
2335 InputContext->EP[0].CErr = 3;
2336
2337 //
2338 // Init the DCS(dequeue cycle state) as the transfer ring's CCS
2339 //
2340 PhyAddr = UsbHcGetPciAddrForHostAddr (
2341 Xhc->MemPool,
2342 ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,
2343 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
2344 );
2345 InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;
2346 InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);
2347
2348 //
2349 // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
2350 //
2351 OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT_64));
2352 ASSERT (OutputContext != NULL);
2353 ASSERT (((UINTN) OutputContext & 0x3F) == 0);
2354 ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT_64));
2355
2356 Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;
2357 //
2358 // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
2359 // a pointer to the Output Device Context data structure (6.2.1).
2360 //
2361 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT_64));
2362 //
2363 // Fill DCBAA with PCI device address
2364 //
2365 Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;
2366
2367 //
2368 // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
2369 // Context data structure described above.
2370 //
2371 // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request
2372 // to device.
2373 //
2374 gBS->Stall (XHC_RESET_RECOVERY_DELAY);
2375 ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
2376 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
2377 CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
2378 CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);
2379 CmdTrbAddr.CycleBit = 1;
2380 CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;
2381 CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
2382 Status = XhcCmdTransfer (
2383 Xhc,
2384 (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,
2385 XHC_GENERIC_TIMEOUT,
2386 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2387 );
2388 if (!EFI_ERROR (Status)) {
2389 DeviceAddress = (UINT8) ((DEVICE_CONTEXT_64 *) OutputContext)->Slot.DeviceAddress;
2390 DEBUG ((EFI_D_INFO, " Address %d assigned successfully\n", DeviceAddress));
2391 Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
2392 }
2393 return Status;
2394 }
2395
2396
2397 /**
2398 Disable the specified device slot.
2399
2400 @param Xhc The XHCI Instance.
2401 @param SlotId The slot id to be disabled.
2402
2403 @retval EFI_SUCCESS Successfully disable the device slot.
2404
2405 **/
2406 EFI_STATUS
2407 EFIAPI
2408 XhcDisableSlotCmd (
2409 IN USB_XHCI_INSTANCE *Xhc,
2410 IN UINT8 SlotId
2411 )
2412 {
2413 EFI_STATUS Status;
2414 TRB_TEMPLATE *EvtTrb;
2415 CMD_TRB_DISABLE_SLOT CmdTrbDisSlot;
2416 UINT8 Index;
2417 VOID *RingSeg;
2418
2419 //
2420 // Disable the device slots occupied by these devices on its downstream ports.
2421 // Entry 0 is reserved.
2422 //
2423 for (Index = 0; Index < 255; Index++) {
2424 if (!Xhc->UsbDevContext[Index + 1].Enabled ||
2425 (Xhc->UsbDevContext[Index + 1].SlotId == 0) ||
2426 (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {
2427 continue;
2428 }
2429
2430 Status = XhcDisableSlotCmd (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
2431
2432 if (EFI_ERROR (Status)) {
2433 DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
2434 Xhc->UsbDevContext[Index + 1].SlotId = 0;
2435 }
2436 }
2437
2438 //
2439 // Construct the disable slot command
2440 //
2441 DEBUG ((EFI_D_INFO, "Disable device slot %d!\n", SlotId));
2442
2443 ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));
2444 CmdTrbDisSlot.CycleBit = 1;
2445 CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;
2446 CmdTrbDisSlot.SlotId = SlotId;
2447 Status = XhcCmdTransfer (
2448 Xhc,
2449 (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,
2450 XHC_GENERIC_TIMEOUT,
2451 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2452 );
2453 if (EFI_ERROR (Status)) {
2454 DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
2455 return Status;
2456 }
2457 //
2458 // Free the slot's device context entry
2459 //
2460 Xhc->DCBAA[SlotId] = 0;
2461
2462 //
2463 // Free the slot related data structure
2464 //
2465 for (Index = 0; Index < 31; Index++) {
2466 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {
2467 RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;
2468 if (RingSeg != NULL) {
2469 UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
2470 }
2471 FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
2472 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;
2473 }
2474 }
2475
2476 for (Index = 0; Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {
2477 if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] != NULL) {
2478 FreePool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]);
2479 }
2480 }
2481
2482 if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting != NULL) {
2483 FreePool (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting);
2484 }
2485
2486 if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {
2487 UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
2488 }
2489
2490 if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {
2491 UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT));
2492 }
2493 //
2494 // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
2495 // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
2496 // remove urb from XHCI's asynchronous transfer list.
2497 //
2498 Xhc->UsbDevContext[SlotId].Enabled = FALSE;
2499 Xhc->UsbDevContext[SlotId].SlotId = 0;
2500
2501 return Status;
2502 }
2503
2504 /**
2505 Disable the specified device slot.
2506
2507 @param Xhc The XHCI Instance.
2508 @param SlotId The slot id to be disabled.
2509
2510 @retval EFI_SUCCESS Successfully disable the device slot.
2511
2512 **/
2513 EFI_STATUS
2514 EFIAPI
2515 XhcDisableSlotCmd64 (
2516 IN USB_XHCI_INSTANCE *Xhc,
2517 IN UINT8 SlotId
2518 )
2519 {
2520 EFI_STATUS Status;
2521 TRB_TEMPLATE *EvtTrb;
2522 CMD_TRB_DISABLE_SLOT CmdTrbDisSlot;
2523 UINT8 Index;
2524 VOID *RingSeg;
2525
2526 //
2527 // Disable the device slots occupied by these devices on its downstream ports.
2528 // Entry 0 is reserved.
2529 //
2530 for (Index = 0; Index < 255; Index++) {
2531 if (!Xhc->UsbDevContext[Index + 1].Enabled ||
2532 (Xhc->UsbDevContext[Index + 1].SlotId == 0) ||
2533 (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {
2534 continue;
2535 }
2536
2537 Status = XhcDisableSlotCmd64 (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
2538
2539 if (EFI_ERROR (Status)) {
2540 DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
2541 Xhc->UsbDevContext[Index + 1].SlotId = 0;
2542 }
2543 }
2544
2545 //
2546 // Construct the disable slot command
2547 //
2548 DEBUG ((EFI_D_INFO, "Disable device slot %d!\n", SlotId));
2549
2550 ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));
2551 CmdTrbDisSlot.CycleBit = 1;
2552 CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;
2553 CmdTrbDisSlot.SlotId = SlotId;
2554 Status = XhcCmdTransfer (
2555 Xhc,
2556 (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,
2557 XHC_GENERIC_TIMEOUT,
2558 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2559 );
2560 if (EFI_ERROR (Status)) {
2561 DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
2562 return Status;
2563 }
2564 //
2565 // Free the slot's device context entry
2566 //
2567 Xhc->DCBAA[SlotId] = 0;
2568
2569 //
2570 // Free the slot related data structure
2571 //
2572 for (Index = 0; Index < 31; Index++) {
2573 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {
2574 RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;
2575 if (RingSeg != NULL) {
2576 UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
2577 }
2578 FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
2579 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;
2580 }
2581 }
2582
2583 for (Index = 0; Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {
2584 if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] != NULL) {
2585 FreePool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]);
2586 }
2587 }
2588
2589 if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting != NULL) {
2590 FreePool (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting);
2591 }
2592
2593 if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {
2594 UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
2595 }
2596
2597 if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {
2598 UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT_64));
2599 }
2600 //
2601 // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
2602 // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
2603 // remove urb from XHCI's asynchronous transfer list.
2604 //
2605 Xhc->UsbDevContext[SlotId].Enabled = FALSE;
2606 Xhc->UsbDevContext[SlotId].SlotId = 0;
2607
2608 return Status;
2609 }
2610
2611 /**
2612 Initialize endpoint context in input context.
2613
2614 @param Xhc The XHCI Instance.
2615 @param SlotId The slot id to be configured.
2616 @param DeviceSpeed The device's speed.
2617 @param InputContext The pointer to the input context.
2618 @param IfDesc The pointer to the usb device interface descriptor.
2619
2620 @return The maximum device context index of endpoint.
2621
2622 **/
2623 UINT8
2624 EFIAPI
2625 XhcInitializeEndpointContext (
2626 IN USB_XHCI_INSTANCE *Xhc,
2627 IN UINT8 SlotId,
2628 IN UINT8 DeviceSpeed,
2629 IN INPUT_CONTEXT *InputContext,
2630 IN USB_INTERFACE_DESCRIPTOR *IfDesc
2631 )
2632 {
2633 USB_ENDPOINT_DESCRIPTOR *EpDesc;
2634 UINTN NumEp;
2635 UINTN EpIndex;
2636 UINT8 EpAddr;
2637 UINT8 Direction;
2638 UINT8 Dci;
2639 UINT8 MaxDci;
2640 EFI_PHYSICAL_ADDRESS PhyAddr;
2641 UINT8 Interval;
2642 TRANSFER_RING *EndpointTransferRing;
2643
2644 MaxDci = 0;
2645
2646 NumEp = IfDesc->NumEndpoints;
2647
2648 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);
2649 for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
2650 while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
2651 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2652 }
2653
2654 if (EpDesc->Length < sizeof (USB_ENDPOINT_DESCRIPTOR)) {
2655 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2656 continue;
2657 }
2658
2659 EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);
2660 Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
2661
2662 Dci = XhcEndpointToDci (EpAddr, Direction);
2663 ASSERT (Dci < 32);
2664 if (Dci > MaxDci) {
2665 MaxDci = Dci;
2666 }
2667
2668 InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);
2669 InputContext->EP[Dci-1].MaxPacketSize = EpDesc->MaxPacketSize;
2670
2671 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
2672 //
2673 // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
2674 //
2675 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2676 } else {
2677 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2678 }
2679
2680 switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {
2681 case USB_ENDPOINT_BULK:
2682 if (Direction == EfiUsbDataIn) {
2683 InputContext->EP[Dci-1].CErr = 3;
2684 InputContext->EP[Dci-1].EPType = ED_BULK_IN;
2685 } else {
2686 InputContext->EP[Dci-1].CErr = 3;
2687 InputContext->EP[Dci-1].EPType = ED_BULK_OUT;
2688 }
2689
2690 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2691 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
2692 EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
2693 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
2694 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
2695 DEBUG ((DEBUG_INFO, "Endpoint[%x]: Created BULK ring [%p~%p)\n",
2696 EpDesc->EndpointAddress,
2697 EndpointTransferRing->RingSeg0,
2698 (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
2699 ));
2700 }
2701
2702 break;
2703 case USB_ENDPOINT_ISO:
2704 if (Direction == EfiUsbDataIn) {
2705 InputContext->EP[Dci-1].CErr = 0;
2706 InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;
2707 } else {
2708 InputContext->EP[Dci-1].CErr = 0;
2709 InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
2710 }
2711 //
2712 // Get the bInterval from descriptor and init the the interval field of endpoint context.
2713 // Refer to XHCI 1.1 spec section 6.2.3.6.
2714 //
2715 if (DeviceSpeed == EFI_USB_SPEED_FULL) {
2716 Interval = EpDesc->Interval;
2717 ASSERT (Interval >= 1 && Interval <= 16);
2718 InputContext->EP[Dci-1].Interval = Interval + 2;
2719 } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
2720 Interval = EpDesc->Interval;
2721 ASSERT (Interval >= 1 && Interval <= 16);
2722 InputContext->EP[Dci-1].Interval = Interval - 1;
2723 }
2724
2725 //
2726 // Do not support isochronous transfer now.
2727 //
2728 DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
2729 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2730 continue;
2731 case USB_ENDPOINT_INTERRUPT:
2732 if (Direction == EfiUsbDataIn) {
2733 InputContext->EP[Dci-1].CErr = 3;
2734 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;
2735 } else {
2736 InputContext->EP[Dci-1].CErr = 3;
2737 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
2738 }
2739 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2740 InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;
2741 //
2742 // Get the bInterval from descriptor and init the the interval field of endpoint context
2743 //
2744 if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {
2745 Interval = EpDesc->Interval;
2746 //
2747 // Calculate through the bInterval field of Endpoint descriptor.
2748 //
2749 ASSERT (Interval != 0);
2750 InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32((UINT32)Interval) + 3;
2751 } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
2752 Interval = EpDesc->Interval;
2753 ASSERT (Interval >= 1 && Interval <= 16);
2754 //
2755 // Refer to XHCI 1.0 spec section 6.2.3.6, table 61
2756 //
2757 InputContext->EP[Dci-1].Interval = Interval - 1;
2758 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2759 InputContext->EP[Dci-1].MaxESITPayload = 0x0002;
2760 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2761 InputContext->EP[Dci-1].CErr = 3;
2762 }
2763
2764 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
2765 EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
2766 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
2767 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
2768 DEBUG ((DEBUG_INFO, "Endpoint[%x]: Created INT ring [%p~%p)\n",
2769 EpDesc->EndpointAddress,
2770 EndpointTransferRing->RingSeg0,
2771 (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
2772 ));
2773 }
2774 break;
2775
2776 case USB_ENDPOINT_CONTROL:
2777 //
2778 // Do not support control transfer now.
2779 //
2780 DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unsupport Control EP found, Transfer ring is not allocated.\n"));
2781 default:
2782 DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext: Unknown EP found, Transfer ring is not allocated.\n"));
2783 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2784 continue;
2785 }
2786
2787 PhyAddr = UsbHcGetPciAddrForHostAddr (
2788 Xhc->MemPool,
2789 ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
2790 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
2791 );
2792 PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
2793 PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
2794 InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
2795 InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
2796
2797 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2798 }
2799
2800 return MaxDci;
2801 }
2802
2803 /**
2804 Initialize endpoint context in input context.
2805
2806 @param Xhc The XHCI Instance.
2807 @param SlotId The slot id to be configured.
2808 @param DeviceSpeed The device's speed.
2809 @param InputContext The pointer to the input context.
2810 @param IfDesc The pointer to the usb device interface descriptor.
2811
2812 @return The maximum device context index of endpoint.
2813
2814 **/
2815 UINT8
2816 EFIAPI
2817 XhcInitializeEndpointContext64 (
2818 IN USB_XHCI_INSTANCE *Xhc,
2819 IN UINT8 SlotId,
2820 IN UINT8 DeviceSpeed,
2821 IN INPUT_CONTEXT_64 *InputContext,
2822 IN USB_INTERFACE_DESCRIPTOR *IfDesc
2823 )
2824 {
2825 USB_ENDPOINT_DESCRIPTOR *EpDesc;
2826 UINTN NumEp;
2827 UINTN EpIndex;
2828 UINT8 EpAddr;
2829 UINT8 Direction;
2830 UINT8 Dci;
2831 UINT8 MaxDci;
2832 EFI_PHYSICAL_ADDRESS PhyAddr;
2833 UINT8 Interval;
2834 TRANSFER_RING *EndpointTransferRing;
2835
2836 MaxDci = 0;
2837
2838 NumEp = IfDesc->NumEndpoints;
2839
2840 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);
2841 for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
2842 while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
2843 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2844 }
2845
2846 if (EpDesc->Length < sizeof (USB_ENDPOINT_DESCRIPTOR)) {
2847 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2848 continue;
2849 }
2850
2851 EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);
2852 Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
2853
2854 Dci = XhcEndpointToDci (EpAddr, Direction);
2855 ASSERT (Dci < 32);
2856 if (Dci > MaxDci) {
2857 MaxDci = Dci;
2858 }
2859
2860 InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);
2861 InputContext->EP[Dci-1].MaxPacketSize = EpDesc->MaxPacketSize;
2862
2863 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
2864 //
2865 // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
2866 //
2867 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2868 } else {
2869 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2870 }
2871
2872 switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {
2873 case USB_ENDPOINT_BULK:
2874 if (Direction == EfiUsbDataIn) {
2875 InputContext->EP[Dci-1].CErr = 3;
2876 InputContext->EP[Dci-1].EPType = ED_BULK_IN;
2877 } else {
2878 InputContext->EP[Dci-1].CErr = 3;
2879 InputContext->EP[Dci-1].EPType = ED_BULK_OUT;
2880 }
2881
2882 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2883 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
2884 EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
2885 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
2886 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
2887 DEBUG ((DEBUG_INFO, "Endpoint64[%x]: Created BULK ring [%p~%p)\n",
2888 EpDesc->EndpointAddress,
2889 EndpointTransferRing->RingSeg0,
2890 (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
2891 ));
2892 }
2893
2894 break;
2895 case USB_ENDPOINT_ISO:
2896 if (Direction == EfiUsbDataIn) {
2897 InputContext->EP[Dci-1].CErr = 0;
2898 InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;
2899 } else {
2900 InputContext->EP[Dci-1].CErr = 0;
2901 InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
2902 }
2903 //
2904 // Get the bInterval from descriptor and init the the interval field of endpoint context.
2905 // Refer to XHCI 1.1 spec section 6.2.3.6.
2906 //
2907 if (DeviceSpeed == EFI_USB_SPEED_FULL) {
2908 Interval = EpDesc->Interval;
2909 ASSERT (Interval >= 1 && Interval <= 16);
2910 InputContext->EP[Dci-1].Interval = Interval + 2;
2911 } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
2912 Interval = EpDesc->Interval;
2913 ASSERT (Interval >= 1 && Interval <= 16);
2914 InputContext->EP[Dci-1].Interval = Interval - 1;
2915 }
2916
2917 //
2918 // Do not support isochronous transfer now.
2919 //
2920 DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
2921 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2922 continue;
2923 case USB_ENDPOINT_INTERRUPT:
2924 if (Direction == EfiUsbDataIn) {
2925 InputContext->EP[Dci-1].CErr = 3;
2926 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;
2927 } else {
2928 InputContext->EP[Dci-1].CErr = 3;
2929 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
2930 }
2931 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2932 InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;
2933 //
2934 // Get the bInterval from descriptor and init the the interval field of endpoint context
2935 //
2936 if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {
2937 Interval = EpDesc->Interval;
2938 //
2939 // Calculate through the bInterval field of Endpoint descriptor.
2940 //
2941 ASSERT (Interval != 0);
2942 InputContext->EP[Dci-1].Interval = (UINT32)HighBitSet32((UINT32)Interval) + 3;
2943 } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
2944 Interval = EpDesc->Interval;
2945 ASSERT (Interval >= 1 && Interval <= 16);
2946 //
2947 // Refer to XHCI 1.0 spec section 6.2.3.6, table 61
2948 //
2949 InputContext->EP[Dci-1].Interval = Interval - 1;
2950 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2951 InputContext->EP[Dci-1].MaxESITPayload = 0x0002;
2952 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2953 InputContext->EP[Dci-1].CErr = 3;
2954 }
2955
2956 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
2957 EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
2958 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
2959 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
2960 DEBUG ((DEBUG_INFO, "Endpoint64[%x]: Created INT ring [%p~%p)\n",
2961 EpDesc->EndpointAddress,
2962 EndpointTransferRing->RingSeg0,
2963 (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
2964 ));
2965 }
2966 break;
2967
2968 case USB_ENDPOINT_CONTROL:
2969 //
2970 // Do not support control transfer now.
2971 //
2972 DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unsupport Control EP found, Transfer ring is not allocated.\n"));
2973 default:
2974 DEBUG ((EFI_D_INFO, "XhcInitializeEndpointContext64: Unknown EP found, Transfer ring is not allocated.\n"));
2975 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2976 continue;
2977 }
2978
2979 PhyAddr = UsbHcGetPciAddrForHostAddr (
2980 Xhc->MemPool,
2981 ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
2982 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
2983 );
2984 PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
2985 PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
2986 InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
2987 InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
2988
2989 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2990 }
2991
2992 return MaxDci;
2993 }
2994
2995 /**
2996 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
2997
2998 @param Xhc The XHCI Instance.
2999 @param SlotId The slot id to be configured.
3000 @param DeviceSpeed The device's speed.
3001 @param ConfigDesc The pointer to the usb device configuration descriptor.
3002
3003 @retval EFI_SUCCESS Successfully configure all the device endpoints.
3004
3005 **/
3006 EFI_STATUS
3007 EFIAPI
3008 XhcSetConfigCmd (
3009 IN USB_XHCI_INSTANCE *Xhc,
3010 IN UINT8 SlotId,
3011 IN UINT8 DeviceSpeed,
3012 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
3013 )
3014 {
3015 EFI_STATUS Status;
3016 USB_INTERFACE_DESCRIPTOR *IfDesc;
3017 UINT8 Index;
3018 UINT8 Dci;
3019 UINT8 MaxDci;
3020 EFI_PHYSICAL_ADDRESS PhyAddr;
3021
3022 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
3023 INPUT_CONTEXT *InputContext;
3024 DEVICE_CONTEXT *OutputContext;
3025 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
3026 //
3027 // 4.6.6 Configure Endpoint
3028 //
3029 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
3030 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
3031 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
3032 CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT));
3033
3034 ASSERT (ConfigDesc != NULL);
3035
3036 MaxDci = 0;
3037
3038 IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
3039 for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {
3040 while ((IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) || (IfDesc->AlternateSetting != 0)) {
3041 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
3042 }
3043
3044 if (IfDesc->Length < sizeof (USB_INTERFACE_DESCRIPTOR)) {
3045 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
3046 continue;
3047 }
3048
3049 Dci = XhcInitializeEndpointContext (Xhc, SlotId, DeviceSpeed, InputContext, IfDesc);
3050 if (Dci > MaxDci) {
3051 MaxDci = Dci;
3052 }
3053
3054 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
3055 }
3056
3057 InputContext->InputControlContext.Dword2 |= BIT0;
3058 InputContext->Slot.ContextEntries = MaxDci;
3059 //
3060 // configure endpoint
3061 //
3062 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
3063 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
3064 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
3065 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
3066 CmdTrbCfgEP.CycleBit = 1;
3067 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
3068 CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
3069 DEBUG ((EFI_D_INFO, "Configure Endpoint\n"));
3070 Status = XhcCmdTransfer (
3071 Xhc,
3072 (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
3073 XHC_GENERIC_TIMEOUT,
3074 (TRB_TEMPLATE **) (UINTN) &EvtTrb
3075 );
3076 if (EFI_ERROR (Status)) {
3077 DEBUG ((EFI_D_ERROR, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status));
3078 } else {
3079 Xhc->UsbDevContext[SlotId].ActiveConfiguration = ConfigDesc->ConfigurationValue;
3080 }
3081
3082 return Status;
3083 }
3084
3085 /**
3086 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
3087
3088 @param Xhc The XHCI Instance.
3089 @param SlotId The slot id to be configured.
3090 @param DeviceSpeed The device's speed.
3091 @param ConfigDesc The pointer to the usb device configuration descriptor.
3092
3093 @retval EFI_SUCCESS Successfully configure all the device endpoints.
3094
3095 **/
3096 EFI_STATUS
3097 EFIAPI
3098 XhcSetConfigCmd64 (
3099 IN USB_XHCI_INSTANCE *Xhc,
3100 IN UINT8 SlotId,
3101 IN UINT8 DeviceSpeed,
3102 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
3103 )