3 XHCI transfer scheduling routines.
5 Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 Create a command transfer TRB to support XHCI command interfaces.
21 @param Xhc The XHCI Instance.
22 @param CmdTrb The cmd TRB to be executed.
24 @return Created URB or NULL.
29 IN USB_XHCI_INSTANCE
*Xhc
,
30 IN TRB_TEMPLATE
*CmdTrb
35 Urb
= AllocateZeroPool (sizeof (URB
));
40 Urb
->Signature
= XHC_URB_SIG
;
42 Urb
->Ring
= &Xhc
->CmdRing
;
43 XhcSyncTrsRing (Xhc
, Urb
->Ring
);
45 Urb
->TrbStart
= Urb
->Ring
->RingEnqueue
;
46 CopyMem (Urb
->TrbStart
, CmdTrb
, sizeof (TRB_TEMPLATE
));
47 Urb
->TrbStart
->CycleBit
= Urb
->Ring
->RingPCS
& BIT0
;
48 Urb
->TrbEnd
= Urb
->TrbStart
;
54 Execute a XHCI cmd TRB pointed by CmdTrb.
56 @param Xhc The XHCI Instance.
57 @param CmdTrb The cmd TRB to be executed.
58 @param Timeout Indicates the maximum time, in millisecond, which the
59 transfer is allowed to complete.
60 @param EvtTrb The event TRB corresponding to the cmd TRB.
62 @retval EFI_SUCCESS The transfer was completed successfully.
63 @retval EFI_INVALID_PARAMETER Some parameters are invalid.
64 @retval EFI_TIMEOUT The transfer failed due to timeout.
65 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
71 IN USB_XHCI_INSTANCE
*Xhc
,
72 IN TRB_TEMPLATE
*CmdTrb
,
74 OUT TRB_TEMPLATE
**EvtTrb
81 // Validate the parameters
83 if ((Xhc
== NULL
) || (CmdTrb
== NULL
)) {
84 return EFI_INVALID_PARAMETER
;
87 Status
= EFI_DEVICE_ERROR
;
89 if (XhcIsHalt (Xhc
) || XhcIsSysError (Xhc
)) {
90 DEBUG ((EFI_D_ERROR
, "XhcCmdTransfer: HC is halted\n"));
95 // Create a new URB, then poll the execution status.
97 Urb
= XhcCreateCmdTrb (Xhc
, CmdTrb
);
100 DEBUG ((EFI_D_ERROR
, "XhcCmdTransfer: failed to create URB\n"));
101 Status
= EFI_OUT_OF_RESOURCES
;
105 Status
= XhcExecTransfer (Xhc
, TRUE
, Urb
, Timeout
);
106 *EvtTrb
= Urb
->EvtTrb
;
108 if (Urb
->Result
== EFI_USB_NOERROR
) {
109 Status
= EFI_SUCCESS
;
112 XhcFreeUrb (Xhc
, Urb
);
119 Create a new URB for a new transaction.
121 @param Xhc The XHCI Instance
122 @param BusAddr The logical device address assigned by UsbBus driver
123 @param EpAddr Endpoint addrress
124 @param DevSpeed The device speed
125 @param MaxPacket The max packet length of the endpoint
126 @param Type The transaction type
127 @param Request The standard USB request for control transfer
128 @param Data The user data to transfer
129 @param DataLen The length of data buffer
130 @param Callback The function to call when data is transferred
131 @param Context The context to the callback
133 @return Created URB or NULL
138 IN USB_XHCI_INSTANCE
*Xhc
,
144 IN EFI_USB_DEVICE_REQUEST
*Request
,
147 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback
,
155 Urb
= AllocateZeroPool (sizeof (URB
));
160 Urb
->Signature
= XHC_URB_SIG
;
161 InitializeListHead (&Urb
->UrbList
);
164 Ep
->BusAddr
= BusAddr
;
165 Ep
->EpAddr
= (UINT8
)(EpAddr
& 0x0F);
166 Ep
->Direction
= ((EpAddr
& 0x80) != 0) ? EfiUsbDataIn
: EfiUsbDataOut
;
167 Ep
->DevSpeed
= DevSpeed
;
168 Ep
->MaxPacket
= MaxPacket
;
171 Urb
->Request
= Request
;
173 Urb
->DataLen
= DataLen
;
174 Urb
->Callback
= Callback
;
175 Urb
->Context
= Context
;
177 Status
= XhcCreateTransferTrb (Xhc
, Urb
);
178 ASSERT_EFI_ERROR (Status
);
179 if (EFI_ERROR (Status
)) {
180 DEBUG ((EFI_D_ERROR
, "XhcCreateUrb: XhcCreateTransferTrb Failed, Status = %r\n", Status
));
189 Free an allocated URB.
191 @param Xhc The XHCI device.
192 @param Urb The URB to free.
197 IN USB_XHCI_INSTANCE
*Xhc
,
201 if ((Xhc
== NULL
) || (Urb
== NULL
)) {
205 if (Urb
->DataMap
!= NULL
) {
206 Xhc
->PciIo
->Unmap (Xhc
->PciIo
, Urb
->DataMap
);
213 Create a transfer TRB.
215 @param Xhc The XHCI Instance
216 @param Urb The urb used to construct the transfer TRB.
218 @return Created TRB or NULL
222 XhcCreateTransferTrb (
223 IN USB_XHCI_INSTANCE
*Xhc
,
228 TRANSFER_RING
*EPRing
;
236 EFI_PCI_IO_PROTOCOL_OPERATION MapOp
;
237 EFI_PHYSICAL_ADDRESS PhyAddr
;
241 SlotId
= XhcBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
243 return EFI_DEVICE_ERROR
;
246 Urb
->Finished
= FALSE
;
247 Urb
->StartDone
= FALSE
;
248 Urb
->EndDone
= FALSE
;
250 Urb
->Result
= EFI_USB_NOERROR
;
252 Dci
= XhcEndpointToDci (Urb
->Ep
.EpAddr
, (UINT8
)(Urb
->Ep
.Direction
));
254 EPRing
= (TRANSFER_RING
*)(UINTN
) Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1];
256 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
257 if (Xhc
->HcCParams
.Data
.Csz
== 0) {
258 EPType
= (UINT8
) ((DEVICE_CONTEXT
*)OutputContext
)->EP
[Dci
-1].EPType
;
260 EPType
= (UINT8
) ((DEVICE_CONTEXT_64
*)OutputContext
)->EP
[Dci
-1].EPType
;
263 if (Urb
->Data
!= NULL
) {
264 if (((UINT8
) (Urb
->Ep
.Direction
)) == EfiUsbDataIn
) {
265 MapOp
= EfiPciIoOperationBusMasterWrite
;
267 MapOp
= EfiPciIoOperationBusMasterRead
;
271 Status
= Xhc
->PciIo
->Map (Xhc
->PciIo
, MapOp
, Urb
->Data
, &Len
, &PhyAddr
, &Map
);
273 if (EFI_ERROR (Status
) || (Len
!= Urb
->DataLen
)) {
274 DEBUG ((EFI_D_ERROR
, "XhcCreateTransferTrb: Fail to map Urb->Data.\n"));
275 return EFI_OUT_OF_RESOURCES
;
278 Urb
->DataPhy
= (VOID
*) ((UINTN
) PhyAddr
);
285 XhcSyncTrsRing (Xhc
, EPRing
);
286 Urb
->TrbStart
= EPRing
->RingEnqueue
;
288 case ED_CONTROL_BIDIR
:
290 // For control transfer, create SETUP_STAGE_TRB first.
292 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
293 TrbStart
->TrbCtrSetup
.bmRequestType
= Urb
->Request
->RequestType
;
294 TrbStart
->TrbCtrSetup
.bRequest
= Urb
->Request
->Request
;
295 TrbStart
->TrbCtrSetup
.wValue
= Urb
->Request
->Value
;
296 TrbStart
->TrbCtrSetup
.wIndex
= Urb
->Request
->Index
;
297 TrbStart
->TrbCtrSetup
.wLength
= Urb
->Request
->Length
;
298 TrbStart
->TrbCtrSetup
.Length
= 8;
299 TrbStart
->TrbCtrSetup
.IntTarget
= 0;
300 TrbStart
->TrbCtrSetup
.IOC
= 1;
301 TrbStart
->TrbCtrSetup
.IDT
= 1;
302 TrbStart
->TrbCtrSetup
.Type
= TRB_TYPE_SETUP_STAGE
;
303 if (Urb
->Ep
.Direction
== EfiUsbDataIn
) {
304 TrbStart
->TrbCtrSetup
.TRT
= 3;
305 } else if (Urb
->Ep
.Direction
== EfiUsbDataOut
) {
306 TrbStart
->TrbCtrSetup
.TRT
= 2;
308 TrbStart
->TrbCtrSetup
.TRT
= 0;
311 // Update the cycle bit
313 TrbStart
->TrbCtrSetup
.CycleBit
= EPRing
->RingPCS
& BIT0
;
317 // For control transfer, create DATA_STAGE_TRB.
319 if (Urb
->DataLen
> 0) {
320 XhcSyncTrsRing (Xhc
, EPRing
);
321 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
322 TrbStart
->TrbCtrData
.TRBPtrLo
= XHC_LOW_32BIT(Urb
->DataPhy
);
323 TrbStart
->TrbCtrData
.TRBPtrHi
= XHC_HIGH_32BIT(Urb
->DataPhy
);
324 TrbStart
->TrbCtrData
.Length
= (UINT32
) Urb
->DataLen
;
325 TrbStart
->TrbCtrData
.TDSize
= 0;
326 TrbStart
->TrbCtrData
.IntTarget
= 0;
327 TrbStart
->TrbCtrData
.ISP
= 1;
328 TrbStart
->TrbCtrData
.IOC
= 1;
329 TrbStart
->TrbCtrData
.IDT
= 0;
330 TrbStart
->TrbCtrData
.CH
= 0;
331 TrbStart
->TrbCtrData
.Type
= TRB_TYPE_DATA_STAGE
;
332 if (Urb
->Ep
.Direction
== EfiUsbDataIn
) {
333 TrbStart
->TrbCtrData
.DIR = 1;
334 } else if (Urb
->Ep
.Direction
== EfiUsbDataOut
) {
335 TrbStart
->TrbCtrData
.DIR = 0;
337 TrbStart
->TrbCtrData
.DIR = 0;
340 // Update the cycle bit
342 TrbStart
->TrbCtrData
.CycleBit
= EPRing
->RingPCS
& BIT0
;
346 // For control transfer, create STATUS_STAGE_TRB.
347 // Get the pointer to next TRB for status stage use
349 XhcSyncTrsRing (Xhc
, EPRing
);
350 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
351 TrbStart
->TrbCtrStatus
.IntTarget
= 0;
352 TrbStart
->TrbCtrStatus
.IOC
= 1;
353 TrbStart
->TrbCtrStatus
.CH
= 0;
354 TrbStart
->TrbCtrStatus
.Type
= TRB_TYPE_STATUS_STAGE
;
355 if (Urb
->Ep
.Direction
== EfiUsbDataIn
) {
356 TrbStart
->TrbCtrStatus
.DIR = 0;
357 } else if (Urb
->Ep
.Direction
== EfiUsbDataOut
) {
358 TrbStart
->TrbCtrStatus
.DIR = 1;
360 TrbStart
->TrbCtrStatus
.DIR = 0;
363 // Update the cycle bit
365 TrbStart
->TrbCtrStatus
.CycleBit
= EPRing
->RingPCS
& BIT0
;
367 // Update the enqueue pointer
369 XhcSyncTrsRing (Xhc
, EPRing
);
371 Urb
->TrbEnd
= (TRB_TEMPLATE
*)(UINTN
)TrbStart
;
380 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
381 while (TotalLen
< Urb
->DataLen
) {
382 if ((TotalLen
+ 0x10000) >= Urb
->DataLen
) {
383 Len
= Urb
->DataLen
- TotalLen
;
387 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
388 TrbStart
->TrbNormal
.TRBPtrLo
= XHC_LOW_32BIT((UINT8
*) Urb
->DataPhy
+ TotalLen
);
389 TrbStart
->TrbNormal
.TRBPtrHi
= XHC_HIGH_32BIT((UINT8
*) Urb
->DataPhy
+ TotalLen
);
390 TrbStart
->TrbNormal
.Length
= (UINT32
) Len
;
391 TrbStart
->TrbNormal
.TDSize
= 0;
392 TrbStart
->TrbNormal
.IntTarget
= 0;
393 TrbStart
->TrbNormal
.ISP
= 1;
394 TrbStart
->TrbNormal
.IOC
= 1;
395 TrbStart
->TrbNormal
.Type
= TRB_TYPE_NORMAL
;
397 // Update the cycle bit
399 TrbStart
->TrbNormal
.CycleBit
= EPRing
->RingPCS
& BIT0
;
401 XhcSyncTrsRing (Xhc
, EPRing
);
406 Urb
->TrbNum
= TrbNum
;
407 Urb
->TrbEnd
= (TRB_TEMPLATE
*)(UINTN
)TrbStart
;
410 case ED_INTERRUPT_OUT
:
411 case ED_INTERRUPT_IN
:
415 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
416 while (TotalLen
< Urb
->DataLen
) {
417 if ((TotalLen
+ 0x10000) >= Urb
->DataLen
) {
418 Len
= Urb
->DataLen
- TotalLen
;
422 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
423 TrbStart
->TrbNormal
.TRBPtrLo
= XHC_LOW_32BIT((UINT8
*) Urb
->DataPhy
+ TotalLen
);
424 TrbStart
->TrbNormal
.TRBPtrHi
= XHC_HIGH_32BIT((UINT8
*) Urb
->DataPhy
+ TotalLen
);
425 TrbStart
->TrbNormal
.Length
= (UINT32
) Len
;
426 TrbStart
->TrbNormal
.TDSize
= 0;
427 TrbStart
->TrbNormal
.IntTarget
= 0;
428 TrbStart
->TrbNormal
.ISP
= 1;
429 TrbStart
->TrbNormal
.IOC
= 1;
430 TrbStart
->TrbNormal
.Type
= TRB_TYPE_NORMAL
;
432 // Update the cycle bit
434 TrbStart
->TrbNormal
.CycleBit
= EPRing
->RingPCS
& BIT0
;
436 XhcSyncTrsRing (Xhc
, EPRing
);
441 Urb
->TrbNum
= TrbNum
;
442 Urb
->TrbEnd
= (TRB_TEMPLATE
*)(UINTN
)TrbStart
;
446 DEBUG ((EFI_D_INFO
, "Not supported EPType 0x%x!\n",EPType
));
456 Initialize the XHCI host controller for schedule.
458 @param Xhc The XHCI Instance to be initialized.
463 IN USB_XHCI_INSTANCE
*Xhc
467 EFI_PHYSICAL_ADDRESS DcbaaPhy
;
469 EFI_PHYSICAL_ADDRESS CmdRingPhy
;
471 UINT32 MaxScratchpadBufs
;
473 EFI_PHYSICAL_ADDRESS ScratchPhy
;
474 UINT64
*ScratchEntry
;
475 EFI_PHYSICAL_ADDRESS ScratchEntryPhy
;
477 UINTN
*ScratchEntryMap
;
481 // Initialize memory management.
483 Xhc
->MemPool
= UsbHcInitMemPool (Xhc
->PciIo
);
484 ASSERT (Xhc
->MemPool
!= NULL
);
487 // Program the Max Device Slots Enabled (MaxSlotsEn) field in the CONFIG register (5.4.7)
488 // to enable the device slots that system software is going to use.
490 Xhc
->MaxSlotsEn
= Xhc
->HcSParams1
.Data
.MaxSlots
;
491 ASSERT (Xhc
->MaxSlotsEn
>= 1 && Xhc
->MaxSlotsEn
<= 255);
492 XhcWriteOpReg (Xhc
, XHC_CONFIG_OFFSET
, Xhc
->MaxSlotsEn
);
495 // The Device Context Base Address Array entry associated with each allocated Device Slot
496 // shall contain a 64-bit pointer to the base of the associated Device Context.
497 // The Device Context Base Address Array shall contain MaxSlotsEn + 1 entries.
498 // Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.
500 Entries
= (Xhc
->MaxSlotsEn
+ 1) * sizeof(UINT64
);
501 Dcbaa
= UsbHcAllocateMem (Xhc
->MemPool
, Entries
);
502 ASSERT (Dcbaa
!= NULL
);
503 ZeroMem (Dcbaa
, Entries
);
506 // A Scratchpad Buffer is a PAGESIZE block of system memory located on a PAGESIZE boundary.
507 // System software shall allocate the Scratchpad Buffer(s) before placing the xHC in to Run
508 // mode (Run/Stop(R/S) ='1').
510 MaxScratchpadBufs
= ((Xhc
->HcSParams2
.Data
.ScratchBufHi
) << 5) | (Xhc
->HcSParams2
.Data
.ScratchBufLo
);
511 Xhc
->MaxScratchpadBufs
= MaxScratchpadBufs
;
512 ASSERT (MaxScratchpadBufs
<= 1023);
513 if (MaxScratchpadBufs
!= 0) {
515 // Allocate the buffer to record the Mapping for each scratch buffer in order to Unmap them
517 ScratchEntryMap
= AllocateZeroPool (sizeof (UINTN
) * MaxScratchpadBufs
);
518 ASSERT (ScratchEntryMap
!= NULL
);
519 Xhc
->ScratchEntryMap
= ScratchEntryMap
;
522 // Allocate the buffer to record the host address for each entry
524 ScratchEntry
= AllocateZeroPool (sizeof (UINT64
) * MaxScratchpadBufs
);
525 ASSERT (ScratchEntry
!= NULL
);
526 Xhc
->ScratchEntry
= ScratchEntry
;
529 Status
= UsbHcAllocateAlignedPages (
531 EFI_SIZE_TO_PAGES (MaxScratchpadBufs
* sizeof (UINT64
)),
533 (VOID
**) &ScratchBuf
,
537 ASSERT_EFI_ERROR (Status
);
539 ZeroMem (ScratchBuf
, MaxScratchpadBufs
* sizeof (UINT64
));
540 Xhc
->ScratchBuf
= ScratchBuf
;
543 // Allocate each scratch buffer
545 for (Index
= 0; Index
< MaxScratchpadBufs
; Index
++) {
547 Status
= UsbHcAllocateAlignedPages (
549 EFI_SIZE_TO_PAGES (Xhc
->PageSize
),
551 (VOID
**) &ScratchEntry
[Index
],
553 (VOID
**) &ScratchEntryMap
[Index
]
555 ASSERT_EFI_ERROR (Status
);
556 ZeroMem ((VOID
*)(UINTN
)ScratchEntry
[Index
], Xhc
->PageSize
);
558 // Fill with the PCI device address
560 *ScratchBuf
++ = ScratchEntryPhy
;
563 // The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the
564 // Device Context Base Address Array points to the Scratchpad Buffer Array.
566 *(UINT64
*)Dcbaa
= (UINT64
)(UINTN
) ScratchPhy
;
570 // Program the Device Context Base Address Array Pointer (DCBAAP) register (5.4.6) with
571 // a 64-bit address pointing to where the Device Context Base Address Array is located.
573 Xhc
->DCBAA
= (UINT64
*)(UINTN
)Dcbaa
;
575 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
576 // So divide it to two 32-bytes width register access.
578 DcbaaPhy
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Dcbaa
, Entries
);
579 XhcWriteOpReg (Xhc
, XHC_DCBAAP_OFFSET
, XHC_LOW_32BIT(DcbaaPhy
));
580 XhcWriteOpReg (Xhc
, XHC_DCBAAP_OFFSET
+ 4, XHC_HIGH_32BIT (DcbaaPhy
));
582 DEBUG ((EFI_D_INFO
, "XhcInitSched:DCBAA=0x%x\n", (UINT64
)(UINTN
)Xhc
->DCBAA
));
585 // Define the Command Ring Dequeue Pointer by programming the Command Ring Control Register
586 // (5.4.5) with a 64-bit address pointing to the starting address of the first TRB of the Command Ring.
587 // Note: The Command Ring is 64 byte aligned, so the low order 6 bits of the Command Ring Pointer shall
590 CreateTransferRing (Xhc
, CMD_RING_TRB_NUMBER
, &Xhc
->CmdRing
);
592 // The xHC uses the Enqueue Pointer to determine when a Transfer Ring is empty. As it fetches TRBs from a
593 // Transfer Ring it checks for a Cycle bit transition. If a transition detected, the ring is empty.
594 // So we set RCS as inverted PCS init value to let Command Ring empty
596 CmdRing
= (UINT64
)(UINTN
)Xhc
->CmdRing
.RingSeg0
;
597 CmdRingPhy
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, (VOID
*)(UINTN
) CmdRing
, sizeof (TRB_TEMPLATE
) * CMD_RING_TRB_NUMBER
);
598 ASSERT ((CmdRingPhy
& 0x3F) == 0);
599 CmdRingPhy
|= XHC_CRCR_RCS
;
601 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
602 // So divide it to two 32-bytes width register access.
604 XhcWriteOpReg (Xhc
, XHC_CRCR_OFFSET
, XHC_LOW_32BIT(CmdRingPhy
));
605 XhcWriteOpReg (Xhc
, XHC_CRCR_OFFSET
+ 4, XHC_HIGH_32BIT (CmdRingPhy
));
607 DEBUG ((EFI_D_INFO
, "XhcInitSched:XHC_CRCR=0x%x\n", Xhc
->CmdRing
.RingSeg0
));
610 // Disable the 'interrupter enable' bit in USB_CMD
611 // and clear IE & IP bit in all Interrupter X Management Registers.
613 XhcClearOpRegBit (Xhc
, XHC_USBCMD_OFFSET
, XHC_USBCMD_INTE
);
614 for (Index
= 0; Index
< (UINT16
)(Xhc
->HcSParams1
.Data
.MaxIntrs
); Index
++) {
615 XhcClearRuntimeRegBit (Xhc
, XHC_IMAN_OFFSET
+ (Index
* 32), XHC_IMAN_IE
);
616 XhcSetRuntimeRegBit (Xhc
, XHC_IMAN_OFFSET
+ (Index
* 32), XHC_IMAN_IP
);
620 // Allocate EventRing for Cmd, Ctrl, Bulk, Interrupt, AsynInterrupt transfer
622 CreateEventRing (Xhc
, &Xhc
->EventRing
);
623 DEBUG ((EFI_D_INFO
, "XhcInitSched:XHC_EVENTRING=0x%x\n", Xhc
->EventRing
.EventRingSeg0
));
627 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted
628 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint
629 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is
630 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the
631 Stopped to the Running state.
633 @param Xhc The XHCI Instance.
634 @param Urb The urb which makes the endpoint halted.
636 @retval EFI_SUCCESS The recovery is successful.
637 @retval Others Failed to recovery halted endpoint.
642 XhcRecoverHaltedEndpoint (
643 IN USB_XHCI_INSTANCE
*Xhc
,
651 Status
= EFI_SUCCESS
;
652 SlotId
= XhcBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
654 return EFI_DEVICE_ERROR
;
656 Dci
= XhcEndpointToDci (Urb
->Ep
.EpAddr
, (UINT8
)(Urb
->Ep
.Direction
));
659 DEBUG ((EFI_D_INFO
, "Recovery Halted Slot = %x,Dci = %x\n", SlotId
, Dci
));
662 // 1) Send Reset endpoint command to transit from halt to stop state
664 Status
= XhcResetEndpoint(Xhc
, SlotId
, Dci
);
665 if (EFI_ERROR(Status
)) {
666 DEBUG ((EFI_D_ERROR
, "XhcRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status
));
671 // 2)Set dequeue pointer
673 Status
= XhcSetTrDequeuePointer(Xhc
, SlotId
, Dci
, Urb
);
674 if (EFI_ERROR(Status
)) {
675 DEBUG ((EFI_D_ERROR
, "XhcRecoverHaltedEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status
));
680 // 3)Ring the doorbell to transit from stop to active
682 XhcRingDoorBell (Xhc
, SlotId
, Dci
);
689 System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer
690 Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to
691 the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running
694 @param Xhc The XHCI Instance.
695 @param Urb The urb which doesn't get completed in a specified timeout range.
697 @retval EFI_SUCCESS The dequeuing of the TDs is successful.
698 @retval Others Failed to stop the endpoint and dequeue the TDs.
703 XhcDequeueTrbFromEndpoint (
704 IN USB_XHCI_INSTANCE
*Xhc
,
712 Status
= EFI_SUCCESS
;
713 SlotId
= XhcBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
715 return EFI_DEVICE_ERROR
;
717 Dci
= XhcEndpointToDci (Urb
->Ep
.EpAddr
, (UINT8
)(Urb
->Ep
.Direction
));
720 DEBUG ((EFI_D_INFO
, "Stop Slot = %x,Dci = %x\n", SlotId
, Dci
));
723 // 1) Send Stop endpoint command to stop xHC from executing of the TDs on the endpoint
725 Status
= XhcStopEndpoint(Xhc
, SlotId
, Dci
);
726 if (EFI_ERROR(Status
)) {
727 DEBUG ((EFI_D_ERROR
, "XhcDequeueTrbFromEndpoint: Stop Endpoint Failed, Status = %r\n", Status
));
732 // 2)Set dequeue pointer
734 Status
= XhcSetTrDequeuePointer(Xhc
, SlotId
, Dci
, Urb
);
735 if (EFI_ERROR(Status
)) {
736 DEBUG ((EFI_D_ERROR
, "XhcDequeueTrbFromEndpoint: Set Transfer Ring Dequeue Pointer Failed, Status = %r\n", Status
));
741 // 3)Ring the doorbell to transit from stop to active
743 XhcRingDoorBell (Xhc
, SlotId
, Dci
);
750 Create XHCI event ring.
752 @param Xhc The XHCI Instance.
753 @param EventRing The created event ring.
758 IN USB_XHCI_INSTANCE
*Xhc
,
759 OUT EVENT_RING
*EventRing
763 EVENT_RING_SEG_TABLE_ENTRY
*ERSTBase
;
765 EFI_PHYSICAL_ADDRESS ERSTPhy
;
766 EFI_PHYSICAL_ADDRESS DequeuePhy
;
768 ASSERT (EventRing
!= NULL
);
770 Size
= sizeof (TRB_TEMPLATE
) * EVENT_RING_TRB_NUMBER
;
771 Buf
= UsbHcAllocateMem (Xhc
->MemPool
, Size
);
772 ASSERT (Buf
!= NULL
);
773 ASSERT (((UINTN
) Buf
& 0x3F) == 0);
776 EventRing
->EventRingSeg0
= Buf
;
777 EventRing
->TrbNumber
= EVENT_RING_TRB_NUMBER
;
778 EventRing
->EventRingDequeue
= (TRB_TEMPLATE
*) EventRing
->EventRingSeg0
;
779 EventRing
->EventRingEnqueue
= (TRB_TEMPLATE
*) EventRing
->EventRingSeg0
;
781 DequeuePhy
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Buf
, Size
);
784 // Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'
785 // and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.
787 EventRing
->EventRingCCS
= 1;
789 Size
= sizeof (EVENT_RING_SEG_TABLE_ENTRY
) * ERST_NUMBER
;
790 Buf
= UsbHcAllocateMem (Xhc
->MemPool
, Size
);
791 ASSERT (Buf
!= NULL
);
792 ASSERT (((UINTN
) Buf
& 0x3F) == 0);
795 ERSTBase
= (EVENT_RING_SEG_TABLE_ENTRY
*) Buf
;
796 EventRing
->ERSTBase
= ERSTBase
;
797 ERSTBase
->PtrLo
= XHC_LOW_32BIT (DequeuePhy
);
798 ERSTBase
->PtrHi
= XHC_HIGH_32BIT (DequeuePhy
);
799 ERSTBase
->RingTrbSize
= EVENT_RING_TRB_NUMBER
;
801 ERSTPhy
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, ERSTBase
, Size
);
804 // Program the Interrupter Event Ring Segment Table Size (ERSTSZ) register (5.5.2.3.1)
812 // Program the Interrupter Event Ring Dequeue Pointer (ERDP) register (5.5.2.3.3)
814 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
815 // So divide it to two 32-bytes width register access.
820 XHC_LOW_32BIT((UINT64
)(UINTN
)DequeuePhy
)
825 XHC_HIGH_32BIT((UINT64
)(UINTN
)DequeuePhy
)
828 // Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register(5.5.2.3.2)
830 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
831 // So divide it to two 32-bytes width register access.
836 XHC_LOW_32BIT((UINT64
)(UINTN
)ERSTPhy
)
840 XHC_ERSTBA_OFFSET
+ 4,
841 XHC_HIGH_32BIT((UINT64
)(UINTN
)ERSTPhy
)
844 // Need set IMAN IE bit to enble the ring interrupt
846 XhcSetRuntimeRegBit (Xhc
, XHC_IMAN_OFFSET
, XHC_IMAN_IE
);
850 Create XHCI transfer ring.
852 @param Xhc The XHCI Instance.
853 @param TrbNum The number of TRB in the ring.
854 @param TransferRing The created transfer ring.
859 IN USB_XHCI_INSTANCE
*Xhc
,
861 OUT TRANSFER_RING
*TransferRing
866 EFI_PHYSICAL_ADDRESS PhyAddr
;
868 Buf
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (TRB_TEMPLATE
) * TrbNum
);
869 ASSERT (Buf
!= NULL
);
870 ASSERT (((UINTN
) Buf
& 0x3F) == 0);
871 ZeroMem (Buf
, sizeof (TRB_TEMPLATE
) * TrbNum
);
873 TransferRing
->RingSeg0
= Buf
;
874 TransferRing
->TrbNumber
= TrbNum
;
875 TransferRing
->RingEnqueue
= (TRB_TEMPLATE
*) TransferRing
->RingSeg0
;
876 TransferRing
->RingDequeue
= (TRB_TEMPLATE
*) TransferRing
->RingSeg0
;
877 TransferRing
->RingPCS
= 1;
879 // 4.9.2 Transfer Ring Management
880 // To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to
881 // point to the first TRB in the ring.
883 EndTrb
= (LINK_TRB
*) ((UINTN
)Buf
+ sizeof (TRB_TEMPLATE
) * (TrbNum
- 1));
884 EndTrb
->Type
= TRB_TYPE_LINK
;
885 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Buf
, sizeof (TRB_TEMPLATE
) * TrbNum
);
886 EndTrb
->PtrLo
= XHC_LOW_32BIT (PhyAddr
);
887 EndTrb
->PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
889 // Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
893 // Set Cycle bit as other TRB PCS init value
895 EndTrb
->CycleBit
= 0;
899 Free XHCI event ring.
901 @param Xhc The XHCI Instance.
902 @param EventRing The event ring to be freed.
908 IN USB_XHCI_INSTANCE
*Xhc
,
909 IN EVENT_RING
*EventRing
912 if(EventRing
->EventRingSeg0
== NULL
) {
917 // Free EventRing Segment 0
919 UsbHcFreeMem (Xhc
->MemPool
, EventRing
->EventRingSeg0
, sizeof (TRB_TEMPLATE
) * EVENT_RING_TRB_NUMBER
);
924 UsbHcFreeMem (Xhc
->MemPool
, EventRing
->ERSTBase
, sizeof (EVENT_RING_SEG_TABLE_ENTRY
) * ERST_NUMBER
);
929 Free the resouce allocated at initializing schedule.
931 @param Xhc The XHCI Instance.
936 IN USB_XHCI_INSTANCE
*Xhc
940 UINT64
*ScratchEntry
;
942 if (Xhc
->ScratchBuf
!= NULL
) {
943 ScratchEntry
= Xhc
->ScratchEntry
;
944 for (Index
= 0; Index
< Xhc
->MaxScratchpadBufs
; Index
++) {
946 // Free Scratchpad Buffers
948 UsbHcFreeAlignedPages (Xhc
->PciIo
, (VOID
*)(UINTN
)ScratchEntry
[Index
], EFI_SIZE_TO_PAGES (Xhc
->PageSize
), (VOID
*) Xhc
->ScratchEntryMap
[Index
]);
951 // Free Scratchpad Buffer Array
953 UsbHcFreeAlignedPages (Xhc
->PciIo
, Xhc
->ScratchBuf
, EFI_SIZE_TO_PAGES (Xhc
->MaxScratchpadBufs
* sizeof (UINT64
)), Xhc
->ScratchMap
);
954 FreePool (Xhc
->ScratchEntryMap
);
955 FreePool (Xhc
->ScratchEntry
);
958 if (Xhc
->CmdRing
.RingSeg0
!= NULL
) {
959 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->CmdRing
.RingSeg0
, sizeof (TRB_TEMPLATE
) * CMD_RING_TRB_NUMBER
);
960 Xhc
->CmdRing
.RingSeg0
= NULL
;
963 XhcFreeEventRing (Xhc
,&Xhc
->EventRing
);
965 if (Xhc
->DCBAA
!= NULL
) {
966 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->DCBAA
, (Xhc
->MaxSlotsEn
+ 1) * sizeof(UINT64
));
971 // Free memory pool at last
973 if (Xhc
->MemPool
!= NULL
) {
974 UsbHcFreeMemPool (Xhc
->MemPool
);
980 Check if the Trb is a transaction of the URBs in XHCI's asynchronous transfer list.
982 @param Xhc The XHCI Instance.
983 @param Trb The TRB to be checked.
984 @param Urb The pointer to the matched Urb.
986 @retval TRUE The Trb is matched with a transaction of the URBs in the async list.
987 @retval FALSE The Trb is not matched with any URBs in the async list.
992 IN USB_XHCI_INSTANCE
*Xhc
,
993 IN TRB_TEMPLATE
*Trb
,
999 TRB_TEMPLATE
*CheckedTrb
;
1003 EFI_LIST_FOR_EACH_SAFE (Entry
, Next
, &Xhc
->AsyncIntTransfers
) {
1004 CheckedUrb
= EFI_LIST_CONTAINER (Entry
, URB
, UrbList
);
1005 CheckedTrb
= CheckedUrb
->TrbStart
;
1006 for (Index
= 0; Index
< CheckedUrb
->TrbNum
; Index
++) {
1007 if (Trb
== CheckedTrb
) {
1013 // If the checked TRB is the link TRB at the end of the transfer ring,
1014 // recircle it to the head of the ring.
1016 if (CheckedTrb
->Type
== TRB_TYPE_LINK
) {
1017 CheckedTrb
= (TRB_TEMPLATE
*) CheckedUrb
->Ring
->RingSeg0
;
1026 Check if the Trb is a transaction of the URB.
1028 @param Trb The TRB to be checked
1029 @param Urb The transfer ring to be checked.
1031 @retval TRUE It is a transaction of the URB.
1032 @retval FALSE It is not any transaction of the URB.
1037 IN TRB_TEMPLATE
*Trb
,
1041 TRB_TEMPLATE
*CheckedTrb
;
1044 CheckedTrb
= Urb
->Ring
->RingSeg0
;
1046 ASSERT (Urb
->Ring
->TrbNumber
== CMD_RING_TRB_NUMBER
|| Urb
->Ring
->TrbNumber
== TR_RING_TRB_NUMBER
);
1048 for (Index
= 0; Index
< Urb
->Ring
->TrbNumber
; Index
++) {
1049 if (Trb
== CheckedTrb
) {
1059 Check the URB's execution result and update the URB's
1062 @param Xhc The XHCI Instance.
1063 @param Urb The URB to check result.
1065 @return Whether the result of URB transfer is finialized.
1070 IN USB_XHCI_INSTANCE
*Xhc
,
1074 EVT_TRB_TRANSFER
*EvtTrb
;
1075 TRB_TEMPLATE
*TRBPtr
;
1084 EFI_PHYSICAL_ADDRESS PhyAddr
;
1086 ASSERT ((Xhc
!= NULL
) && (Urb
!= NULL
));
1088 Status
= EFI_SUCCESS
;
1091 if (Urb
->Finished
) {
1097 if (XhcIsHalt (Xhc
) || XhcIsSysError (Xhc
)) {
1098 Urb
->Result
|= EFI_USB_ERR_SYSTEM
;
1103 // Traverse the event ring to find out all new events from the previous check.
1105 XhcSyncEventRing (Xhc
, &Xhc
->EventRing
);
1106 for (Index
= 0; Index
< Xhc
->EventRing
.TrbNumber
; Index
++) {
1107 Status
= XhcCheckNewEvent (Xhc
, &Xhc
->EventRing
, ((TRB_TEMPLATE
**)&EvtTrb
));
1108 if (Status
== EFI_NOT_READY
) {
1110 // All new events are handled, return directly.
1116 // Only handle COMMAND_COMPLETETION_EVENT and TRANSFER_EVENT.
1118 if ((EvtTrb
->Type
!= TRB_TYPE_COMMAND_COMPLT_EVENT
) && (EvtTrb
->Type
!= TRB_TYPE_TRANS_EVENT
)) {
1123 // Need convert pci device address to host address
1125 PhyAddr
= (EFI_PHYSICAL_ADDRESS
)(EvtTrb
->TRBPtrLo
| LShiftU64 ((UINT64
) EvtTrb
->TRBPtrHi
, 32));
1126 TRBPtr
= (TRB_TEMPLATE
*)(UINTN
) UsbHcGetHostAddrForPciAddr (Xhc
->MemPool
, (VOID
*)(UINTN
) PhyAddr
, sizeof (TRB_TEMPLATE
));
1129 // Update the status of Urb according to the finished event regardless of whether
1130 // the urb is current checked one or in the XHCI's async transfer list.
1131 // This way is used to avoid that those completed async transfer events don't get
1132 // handled in time and are flushed by newer coming events.
1134 if (IsTransferRingTrb (TRBPtr
, Urb
)) {
1136 } else if (IsAsyncIntTrb (Xhc
, TRBPtr
, &AsyncUrb
)) {
1137 CheckedUrb
= AsyncUrb
;
1142 switch (EvtTrb
->Completecode
) {
1143 case TRB_COMPLETION_STALL_ERROR
:
1144 CheckedUrb
->Result
|= EFI_USB_ERR_STALL
;
1145 CheckedUrb
->Finished
= TRUE
;
1146 DEBUG ((EFI_D_ERROR
, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n",EvtTrb
->Completecode
));
1149 case TRB_COMPLETION_BABBLE_ERROR
:
1150 CheckedUrb
->Result
|= EFI_USB_ERR_BABBLE
;
1151 CheckedUrb
->Finished
= TRUE
;
1152 DEBUG ((EFI_D_ERROR
, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n",EvtTrb
->Completecode
));
1155 case TRB_COMPLETION_DATA_BUFFER_ERROR
:
1156 CheckedUrb
->Result
|= EFI_USB_ERR_BUFFER
;
1157 CheckedUrb
->Finished
= TRUE
;
1158 DEBUG ((EFI_D_ERROR
, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n",EvtTrb
->Completecode
));
1161 case TRB_COMPLETION_USB_TRANSACTION_ERROR
:
1162 CheckedUrb
->Result
|= EFI_USB_ERR_TIMEOUT
;
1163 CheckedUrb
->Finished
= TRUE
;
1164 DEBUG ((EFI_D_ERROR
, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n",EvtTrb
->Completecode
));
1167 case TRB_COMPLETION_SHORT_PACKET
:
1168 case TRB_COMPLETION_SUCCESS
:
1169 if (EvtTrb
->Completecode
== TRB_COMPLETION_SHORT_PACKET
) {
1170 DEBUG ((EFI_D_VERBOSE
, "XhcCheckUrbResult: short packet happens!\n"));
1173 TRBType
= (UINT8
) (TRBPtr
->Type
);
1174 if ((TRBType
== TRB_TYPE_DATA_STAGE
) ||
1175 (TRBType
== TRB_TYPE_NORMAL
) ||
1176 (TRBType
== TRB_TYPE_ISOCH
)) {
1177 CheckedUrb
->Completed
+= (((TRANSFER_TRB_NORMAL
*)TRBPtr
)->Length
- EvtTrb
->Length
);
1183 DEBUG ((EFI_D_ERROR
, "Transfer Default Error Occur! Completecode = 0x%x!\n",EvtTrb
->Completecode
));
1184 CheckedUrb
->Result
|= EFI_USB_ERR_TIMEOUT
;
1185 CheckedUrb
->Finished
= TRUE
;
1190 // Only check first and end Trb event address
1192 if (TRBPtr
== CheckedUrb
->TrbStart
) {
1193 CheckedUrb
->StartDone
= TRUE
;
1196 if (TRBPtr
== CheckedUrb
->TrbEnd
) {
1197 CheckedUrb
->EndDone
= TRUE
;
1200 if (CheckedUrb
->StartDone
&& CheckedUrb
->EndDone
) {
1201 CheckedUrb
->Finished
= TRUE
;
1202 CheckedUrb
->EvtTrb
= (TRB_TEMPLATE
*)EvtTrb
;
1209 // Advance event ring to last available entry
1211 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
1212 // So divide it to two 32-bytes width register access.
1214 Low
= XhcReadRuntimeReg (Xhc
, XHC_ERDP_OFFSET
);
1215 High
= XhcReadRuntimeReg (Xhc
, XHC_ERDP_OFFSET
+ 4);
1216 XhcDequeue
= (UINT64
)(LShiftU64((UINT64
)High
, 32) | Low
);
1218 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Xhc
->EventRing
.EventRingDequeue
, sizeof (TRB_TEMPLATE
));
1220 if ((XhcDequeue
& (~0x0F)) != (PhyAddr
& (~0x0F))) {
1222 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
1223 // So divide it to two 32-bytes width register access.
1225 XhcWriteRuntimeReg (Xhc
, XHC_ERDP_OFFSET
, XHC_LOW_32BIT (PhyAddr
) | BIT3
);
1226 XhcWriteRuntimeReg (Xhc
, XHC_ERDP_OFFSET
+ 4, XHC_HIGH_32BIT (PhyAddr
));
1229 return Urb
->Finished
;
1234 Execute the transfer by polling the URB. This is a synchronous operation.
1236 @param Xhc The XHCI Instance.
1237 @param CmdTransfer The executed URB is for cmd transfer or not.
1238 @param Urb The URB to execute.
1239 @param Timeout The time to wait before abort, in millisecond.
1241 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
1242 @return EFI_TIMEOUT The transfer failed due to time out.
1243 @return EFI_SUCCESS The transfer finished OK.
1248 IN USB_XHCI_INSTANCE
*Xhc
,
1249 IN BOOLEAN CmdTransfer
,
1265 SlotId
= XhcBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
1267 return EFI_DEVICE_ERROR
;
1269 Dci
= XhcEndpointToDci (Urb
->Ep
.EpAddr
, (UINT8
)(Urb
->Ep
.Direction
));
1273 Status
= EFI_SUCCESS
;
1274 Loop
= Timeout
* XHC_1_MILLISECOND
;
1279 XhcRingDoorBell (Xhc
, SlotId
, Dci
);
1281 for (Index
= 0; Index
< Loop
; Index
++) {
1282 Finished
= XhcCheckUrbResult (Xhc
, Urb
);
1286 gBS
->Stall (XHC_1_MICROSECOND
);
1289 if (Index
== Loop
) {
1290 Urb
->Result
= EFI_USB_ERR_TIMEOUT
;
1291 Status
= EFI_TIMEOUT
;
1292 } else if (Urb
->Result
!= EFI_USB_NOERROR
) {
1293 Status
= EFI_DEVICE_ERROR
;
1300 Delete a single asynchronous interrupt transfer for
1301 the device and endpoint.
1303 @param Xhc The XHCI Instance.
1304 @param BusAddr The logical device address assigned by UsbBus driver.
1305 @param EpNum The endpoint of the target.
1307 @retval EFI_SUCCESS An asynchronous transfer is removed.
1308 @retval EFI_NOT_FOUND No transfer for the device is found.
1312 XhciDelAsyncIntTransfer (
1313 IN USB_XHCI_INSTANCE
*Xhc
,
1321 EFI_USB_DATA_DIRECTION Direction
;
1323 Direction
= ((EpNum
& 0x80) != 0) ? EfiUsbDataIn
: EfiUsbDataOut
;
1328 EFI_LIST_FOR_EACH_SAFE (Entry
, Next
, &Xhc
->AsyncIntTransfers
) {
1329 Urb
= EFI_LIST_CONTAINER (Entry
, URB
, UrbList
);
1330 if ((Urb
->Ep
.BusAddr
== BusAddr
) &&
1331 (Urb
->Ep
.EpAddr
== EpNum
) &&
1332 (Urb
->Ep
.Direction
== Direction
)) {
1333 RemoveEntryList (&Urb
->UrbList
);
1334 FreePool (Urb
->Data
);
1335 XhcFreeUrb (Xhc
, Urb
);
1340 return EFI_NOT_FOUND
;
1344 Remove all the asynchronous interrutp transfers.
1346 @param Xhc The XHCI Instance.
1350 XhciDelAllAsyncIntTransfers (
1351 IN USB_XHCI_INSTANCE
*Xhc
1358 EFI_LIST_FOR_EACH_SAFE (Entry
, Next
, &Xhc
->AsyncIntTransfers
) {
1359 Urb
= EFI_LIST_CONTAINER (Entry
, URB
, UrbList
);
1360 RemoveEntryList (&Urb
->UrbList
);
1361 FreePool (Urb
->Data
);
1362 XhcFreeUrb (Xhc
, Urb
);
1367 Update the queue head for next round of asynchronous transfer
1369 @param Xhc The XHCI Instance.
1370 @param Urb The URB to update
1374 XhcUpdateAsyncRequest (
1375 IN USB_XHCI_INSTANCE
*Xhc
,
1381 if (Urb
->Result
== EFI_USB_NOERROR
) {
1382 Status
= XhcCreateTransferTrb (Xhc
, Urb
);
1383 if (EFI_ERROR (Status
)) {
1386 Status
= RingIntTransferDoorBell (Xhc
, Urb
);
1387 if (EFI_ERROR (Status
)) {
1394 Flush data from PCI controller specific address to mapped system
1397 @param Xhc The XHCI device.
1398 @param Urb The URB to unmap.
1400 @retval EFI_SUCCESS Success to flush data to mapped system memory.
1401 @retval EFI_DEVICE_ERROR Fail to flush data to mapped system memory.
1405 XhcFlushAsyncIntMap (
1406 IN USB_XHCI_INSTANCE
*Xhc
,
1411 EFI_PHYSICAL_ADDRESS PhyAddr
;
1412 EFI_PCI_IO_PROTOCOL_OPERATION MapOp
;
1413 EFI_PCI_IO_PROTOCOL
*PciIo
;
1420 if (Urb
->Ep
.Direction
== EfiUsbDataIn
) {
1421 MapOp
= EfiPciIoOperationBusMasterWrite
;
1423 MapOp
= EfiPciIoOperationBusMasterRead
;
1426 if (Urb
->DataMap
!= NULL
) {
1427 Status
= PciIo
->Unmap (PciIo
, Urb
->DataMap
);
1428 if (EFI_ERROR (Status
)) {
1433 Urb
->DataMap
= NULL
;
1435 Status
= PciIo
->Map (PciIo
, MapOp
, Urb
->Data
, &Len
, &PhyAddr
, &Map
);
1436 if (EFI_ERROR (Status
) || (Len
!= Urb
->DataLen
)) {
1440 Urb
->DataPhy
= (VOID
*) ((UINTN
) PhyAddr
);
1445 return EFI_DEVICE_ERROR
;
1449 Interrupt transfer periodic check handler.
1451 @param Event Interrupt event.
1452 @param Context Pointer to USB_XHCI_INSTANCE.
1457 XhcMonitorAsyncRequests (
1462 USB_XHCI_INSTANCE
*Xhc
;
1471 OldTpl
= gBS
->RaiseTPL (XHC_TPL
);
1473 Xhc
= (USB_XHCI_INSTANCE
*) Context
;
1475 EFI_LIST_FOR_EACH_SAFE (Entry
, Next
, &Xhc
->AsyncIntTransfers
) {
1476 Urb
= EFI_LIST_CONTAINER (Entry
, URB
, UrbList
);
1479 // Make sure that the device is available before every check.
1481 SlotId
= XhcBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
1487 // Check the result of URB execution. If it is still
1488 // active, check the next one.
1490 XhcCheckUrbResult (Xhc
, Urb
);
1492 if (!Urb
->Finished
) {
1497 // Flush any PCI posted write transactions from a PCI host
1498 // bridge to system memory.
1500 Status
= XhcFlushAsyncIntMap (Xhc
, Urb
);
1501 if (EFI_ERROR (Status
)) {
1502 DEBUG ((EFI_D_ERROR
, "XhcMonitorAsyncRequests: Fail to Flush AsyncInt Mapped Memeory\n"));
1506 // Allocate a buffer then copy the transferred data for user.
1507 // If failed to allocate the buffer, update the URB for next
1508 // round of transfer. Ignore the data of this round.
1511 if (Urb
->Result
== EFI_USB_NOERROR
) {
1512 ASSERT (Urb
->Completed
<= Urb
->DataLen
);
1514 ProcBuf
= AllocateZeroPool (Urb
->Completed
);
1516 if (ProcBuf
== NULL
) {
1517 XhcUpdateAsyncRequest (Xhc
, Urb
);
1521 CopyMem (ProcBuf
, Urb
->Data
, Urb
->Completed
);
1525 // Leave error recovery to its related device driver. A
1526 // common case of the error recovery is to re-submit the
1527 // interrupt transfer which is linked to the head of the
1528 // list. This function scans from head to tail. So the
1529 // re-submitted interrupt transfer's callback function
1530 // will not be called again in this round. Don't touch this
1531 // URB after the callback, it may have been removed by the
1534 if (Urb
->Callback
!= NULL
) {
1536 // Restore the old TPL, USB bus maybe connect device in
1537 // his callback. Some drivers may has a lower TPL restriction.
1539 gBS
->RestoreTPL (OldTpl
);
1540 (Urb
->Callback
) (ProcBuf
, Urb
->Completed
, Urb
->Context
, Urb
->Result
);
1541 OldTpl
= gBS
->RaiseTPL (XHC_TPL
);
1544 if (ProcBuf
!= NULL
) {
1545 gBS
->FreePool (ProcBuf
);
1548 XhcUpdateAsyncRequest (Xhc
, Urb
);
1550 gBS
->RestoreTPL (OldTpl
);
1554 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.
1556 @param Xhc The XHCI Instance.
1557 @param ParentRouteChart The route string pointed to the parent device if it exists.
1558 @param Port The port to be polled.
1559 @param PortState The port state.
1561 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.
1562 @retval Others Should not appear.
1567 XhcPollPortStatusChange (
1568 IN USB_XHCI_INSTANCE
*Xhc
,
1569 IN USB_DEV_ROUTE ParentRouteChart
,
1571 IN EFI_USB_PORT_STATUS
*PortState
1577 USB_DEV_ROUTE RouteChart
;
1579 Status
= EFI_SUCCESS
;
1581 if ((PortState
->PortChangeStatus
& (USB_PORT_STAT_C_CONNECTION
| USB_PORT_STAT_C_ENABLE
| USB_PORT_STAT_C_OVERCURRENT
| USB_PORT_STAT_C_RESET
)) == 0) {
1585 if (ParentRouteChart
.Dword
== 0) {
1586 RouteChart
.Route
.RouteString
= 0;
1587 RouteChart
.Route
.RootPortNum
= Port
+ 1;
1588 RouteChart
.Route
.TierNum
= 1;
1591 RouteChart
.Route
.RouteString
= ParentRouteChart
.Route
.RouteString
| (Port
<< (4 * (ParentRouteChart
.Route
.TierNum
- 1)));
1593 RouteChart
.Route
.RouteString
= ParentRouteChart
.Route
.RouteString
| (15 << (4 * (ParentRouteChart
.Route
.TierNum
- 1)));
1595 RouteChart
.Route
.RootPortNum
= ParentRouteChart
.Route
.RootPortNum
;
1596 RouteChart
.Route
.TierNum
= ParentRouteChart
.Route
.TierNum
+ 1;
1599 SlotId
= XhcRouteStringToSlotId (Xhc
, RouteChart
);
1601 if (Xhc
->HcCParams
.Data
.Csz
== 0) {
1602 Status
= XhcDisableSlotCmd (Xhc
, SlotId
);
1604 Status
= XhcDisableSlotCmd64 (Xhc
, SlotId
);
1608 if (((PortState
->PortStatus
& USB_PORT_STAT_ENABLE
) != 0) &&
1609 ((PortState
->PortStatus
& USB_PORT_STAT_CONNECTION
) != 0)) {
1611 // Has a device attached, Identify device speed after port is enabled.
1613 Speed
= EFI_USB_SPEED_FULL
;
1614 if ((PortState
->PortStatus
& USB_PORT_STAT_LOW_SPEED
) != 0) {
1615 Speed
= EFI_USB_SPEED_LOW
;
1616 } else if ((PortState
->PortStatus
& USB_PORT_STAT_HIGH_SPEED
) != 0) {
1617 Speed
= EFI_USB_SPEED_HIGH
;
1618 } else if ((PortState
->PortStatus
& USB_PORT_STAT_SUPER_SPEED
) != 0) {
1619 Speed
= EFI_USB_SPEED_SUPER
;
1622 // Execute Enable_Slot cmd for attached device, initialize device context and assign device address.
1624 SlotId
= XhcRouteStringToSlotId (Xhc
, RouteChart
);
1625 if ((SlotId
== 0) && ((PortState
->PortChangeStatus
& USB_PORT_STAT_C_RESET
) != 0)) {
1626 if (Xhc
->HcCParams
.Data
.Csz
== 0) {
1627 Status
= XhcInitializeDeviceSlot (Xhc
, ParentRouteChart
, Port
, RouteChart
, Speed
);
1629 Status
= XhcInitializeDeviceSlot64 (Xhc
, ParentRouteChart
, Port
, RouteChart
, Speed
);
1639 Calculate the device context index by endpoint address and direction.
1641 @param EpAddr The target endpoint number.
1642 @param Direction The direction of the target endpoint.
1644 @return The device context index of endpoint.
1658 Index
= (UINT8
) (2 * EpAddr
);
1659 if (Direction
== EfiUsbDataIn
) {
1667 Find out the actual device address according to the requested device address from UsbBus.
1669 @param Xhc The XHCI Instance.
1670 @param BusDevAddr The requested device address by UsbBus upper driver.
1672 @return The actual device address assigned to the device.
1677 XhcBusDevAddrToSlotId (
1678 IN USB_XHCI_INSTANCE
*Xhc
,
1684 for (Index
= 0; Index
< 255; Index
++) {
1685 if (Xhc
->UsbDevContext
[Index
+ 1].Enabled
&&
1686 (Xhc
->UsbDevContext
[Index
+ 1].SlotId
!= 0) &&
1687 (Xhc
->UsbDevContext
[Index
+ 1].BusDevAddr
== BusDevAddr
)) {
1696 return Xhc
->UsbDevContext
[Index
+ 1].SlotId
;
1700 Find out the slot id according to the device's route string.
1702 @param Xhc The XHCI Instance.
1703 @param RouteString The route string described the device location.
1705 @return The slot id used by the device.
1710 XhcRouteStringToSlotId (
1711 IN USB_XHCI_INSTANCE
*Xhc
,
1712 IN USB_DEV_ROUTE RouteString
1717 for (Index
= 0; Index
< 255; Index
++) {
1718 if (Xhc
->UsbDevContext
[Index
+ 1].Enabled
&&
1719 (Xhc
->UsbDevContext
[Index
+ 1].SlotId
!= 0) &&
1720 (Xhc
->UsbDevContext
[Index
+ 1].RouteString
.Dword
== RouteString
.Dword
)) {
1729 return Xhc
->UsbDevContext
[Index
+ 1].SlotId
;
1733 Synchronize the specified event ring to update the enqueue and dequeue pointer.
1735 @param Xhc The XHCI Instance.
1736 @param EvtRing The event ring to sync.
1738 @retval EFI_SUCCESS The event ring is synchronized successfully.
1744 IN USB_XHCI_INSTANCE
*Xhc
,
1745 IN EVENT_RING
*EvtRing
1749 TRB_TEMPLATE
*EvtTrb1
;
1751 ASSERT (EvtRing
!= NULL
);
1754 // Calculate the EventRingEnqueue and EventRingCCS.
1755 // Note: only support single Segment
1757 EvtTrb1
= EvtRing
->EventRingDequeue
;
1759 for (Index
= 0; Index
< EvtRing
->TrbNumber
; Index
++) {
1760 if (EvtTrb1
->CycleBit
!= EvtRing
->EventRingCCS
) {
1766 if ((UINTN
)EvtTrb1
>= ((UINTN
) EvtRing
->EventRingSeg0
+ sizeof (TRB_TEMPLATE
) * EvtRing
->TrbNumber
)) {
1767 EvtTrb1
= EvtRing
->EventRingSeg0
;
1768 EvtRing
->EventRingCCS
= (EvtRing
->EventRingCCS
) ? 0 : 1;
1772 if (Index
< EvtRing
->TrbNumber
) {
1773 EvtRing
->EventRingEnqueue
= EvtTrb1
;
1782 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
1784 @param Xhc The XHCI Instance.
1785 @param TrsRing The transfer ring to sync.
1787 @retval EFI_SUCCESS The transfer ring is synchronized successfully.
1793 IN USB_XHCI_INSTANCE
*Xhc
,
1794 IN TRANSFER_RING
*TrsRing
1798 TRB_TEMPLATE
*TrsTrb
;
1800 ASSERT (TrsRing
!= NULL
);
1802 // Calculate the latest RingEnqueue and RingPCS
1804 TrsTrb
= TrsRing
->RingEnqueue
;
1805 ASSERT (TrsTrb
!= NULL
);
1807 for (Index
= 0; Index
< TrsRing
->TrbNumber
; Index
++) {
1808 if (TrsTrb
->CycleBit
!= (TrsRing
->RingPCS
& BIT0
)) {
1812 if ((UINT8
) TrsTrb
->Type
== TRB_TYPE_LINK
) {
1813 ASSERT (((LINK_TRB
*)TrsTrb
)->TC
!= 0);
1815 // set cycle bit in Link TRB as normal
1817 ((LINK_TRB
*)TrsTrb
)->CycleBit
= TrsRing
->RingPCS
& BIT0
;
1819 // Toggle PCS maintained by software
1821 TrsRing
->RingPCS
= (TrsRing
->RingPCS
& BIT0
) ? 0 : 1;
1822 TrsTrb
= (TRB_TEMPLATE
*) TrsRing
->RingSeg0
; // Use host address
1826 ASSERT (Index
!= TrsRing
->TrbNumber
);
1828 if (TrsTrb
!= TrsRing
->RingEnqueue
) {
1829 TrsRing
->RingEnqueue
= TrsTrb
;
1833 // Clear the Trb context for enqueue, but reserve the PCS bit
1835 TrsTrb
->Parameter1
= 0;
1836 TrsTrb
->Parameter2
= 0;
1840 TrsTrb
->Control
= 0;
1846 Check if there is a new generated event.
1848 @param Xhc The XHCI Instance.
1849 @param EvtRing The event ring to check.
1850 @param NewEvtTrb The new event TRB found.
1852 @retval EFI_SUCCESS Found a new event TRB at the event ring.
1853 @retval EFI_NOT_READY The event ring has no new event.
1859 IN USB_XHCI_INSTANCE
*Xhc
,
1860 IN EVENT_RING
*EvtRing
,
1861 OUT TRB_TEMPLATE
**NewEvtTrb
1864 ASSERT (EvtRing
!= NULL
);
1866 *NewEvtTrb
= EvtRing
->EventRingDequeue
;
1868 if (EvtRing
->EventRingDequeue
== EvtRing
->EventRingEnqueue
) {
1869 return EFI_NOT_READY
;
1872 EvtRing
->EventRingDequeue
++;
1874 // If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.
1876 if ((UINTN
)EvtRing
->EventRingDequeue
>= ((UINTN
) EvtRing
->EventRingSeg0
+ sizeof (TRB_TEMPLATE
) * EvtRing
->TrbNumber
)) {
1877 EvtRing
->EventRingDequeue
= EvtRing
->EventRingSeg0
;
1884 Ring the door bell to notify XHCI there is a transaction to be executed.
1886 @param Xhc The XHCI Instance.
1887 @param SlotId The slot id of the target device.
1888 @param Dci The device context index of the target slot or endpoint.
1890 @retval EFI_SUCCESS Successfully ring the door bell.
1896 IN USB_XHCI_INSTANCE
*Xhc
,
1902 XhcWriteDoorBellReg (Xhc
, 0, 0);
1904 XhcWriteDoorBellReg (Xhc
, SlotId
* sizeof (UINT32
), Dci
);
1911 Ring the door bell to notify XHCI there is a transaction to be executed through URB.
1913 @param Xhc The XHCI Instance.
1914 @param Urb The URB to be rung.
1916 @retval EFI_SUCCESS Successfully ring the door bell.
1920 RingIntTransferDoorBell (
1921 IN USB_XHCI_INSTANCE
*Xhc
,
1928 SlotId
= XhcBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
1929 Dci
= XhcEndpointToDci (Urb
->Ep
.EpAddr
, (UINT8
)(Urb
->Ep
.Direction
));
1930 XhcRingDoorBell (Xhc
, SlotId
, Dci
);
1935 Assign and initialize the device slot for a new device.
1937 @param Xhc The XHCI Instance.
1938 @param ParentRouteChart The route string pointed to the parent device.
1939 @param ParentPort The port at which the device is located.
1940 @param RouteChart The route string pointed to the device.
1941 @param DeviceSpeed The device speed.
1943 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1948 XhcInitializeDeviceSlot (
1949 IN USB_XHCI_INSTANCE
*Xhc
,
1950 IN USB_DEV_ROUTE ParentRouteChart
,
1951 IN UINT16 ParentPort
,
1952 IN USB_DEV_ROUTE RouteChart
,
1953 IN UINT8 DeviceSpeed
1957 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
1958 INPUT_CONTEXT
*InputContext
;
1959 DEVICE_CONTEXT
*OutputContext
;
1960 TRANSFER_RING
*EndpointTransferRing
;
1961 CMD_TRB_ADDRESS_DEVICE CmdTrbAddr
;
1962 UINT8 DeviceAddress
;
1963 CMD_TRB_ENABLE_SLOT CmdTrb
;
1966 DEVICE_CONTEXT
*ParentDeviceContext
;
1967 EFI_PHYSICAL_ADDRESS PhyAddr
;
1969 ZeroMem (&CmdTrb
, sizeof (CMD_TRB_ENABLE_SLOT
));
1970 CmdTrb
.CycleBit
= 1;
1971 CmdTrb
.Type
= TRB_TYPE_EN_SLOT
;
1973 Status
= XhcCmdTransfer (
1975 (TRB_TEMPLATE
*) (UINTN
) &CmdTrb
,
1976 XHC_GENERIC_TIMEOUT
,
1977 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
1979 if (EFI_ERROR (Status
)) {
1980 DEBUG ((EFI_D_ERROR
, "XhcInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status
));
1983 ASSERT (EvtTrb
->SlotId
<= Xhc
->MaxSlotsEn
);
1984 DEBUG ((EFI_D_INFO
, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb
->SlotId
));
1985 SlotId
= (UINT8
)EvtTrb
->SlotId
;
1986 ASSERT (SlotId
!= 0);
1988 ZeroMem (&Xhc
->UsbDevContext
[SlotId
], sizeof (USB_DEV_CONTEXT
));
1989 Xhc
->UsbDevContext
[SlotId
].Enabled
= TRUE
;
1990 Xhc
->UsbDevContext
[SlotId
].SlotId
= SlotId
;
1991 Xhc
->UsbDevContext
[SlotId
].RouteString
.Dword
= RouteChart
.Dword
;
1992 Xhc
->UsbDevContext
[SlotId
].ParentRouteString
.Dword
= ParentRouteChart
.Dword
;
1995 // 4.3.3 Device Slot Initialization
1996 // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
1998 InputContext
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (INPUT_CONTEXT
));
1999 ASSERT (InputContext
!= NULL
);
2000 ASSERT (((UINTN
) InputContext
& 0x3F) == 0);
2001 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
2003 Xhc
->UsbDevContext
[SlotId
].InputContext
= (VOID
*) InputContext
;
2006 // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
2007 // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input
2008 // Context are affected by the command.
2010 InputContext
->InputControlContext
.Dword2
|= (BIT0
| BIT1
);
2013 // 3) Initialize the Input Slot Context data structure
2015 InputContext
->Slot
.RouteString
= RouteChart
.Route
.RouteString
;
2016 InputContext
->Slot
.Speed
= DeviceSpeed
+ 1;
2017 InputContext
->Slot
.ContextEntries
= 1;
2018 InputContext
->Slot
.RootHubPortNum
= RouteChart
.Route
.RootPortNum
;
2020 if (RouteChart
.Route
.RouteString
) {
2022 // The device is behind of hub device.
2024 ParentSlotId
= XhcRouteStringToSlotId(Xhc
, ParentRouteChart
);
2025 ASSERT (ParentSlotId
!= 0);
2027 //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
2029 ParentDeviceContext
= (DEVICE_CONTEXT
*)Xhc
->UsbDevContext
[ParentSlotId
].OutputContext
;
2030 if ((ParentDeviceContext
->Slot
.TTPortNum
== 0) &&
2031 (ParentDeviceContext
->Slot
.TTHubSlotId
== 0)) {
2032 if ((ParentDeviceContext
->Slot
.Speed
== (EFI_USB_SPEED_HIGH
+ 1)) && (DeviceSpeed
< EFI_USB_SPEED_HIGH
)) {
2034 // Full/Low device attached to High speed hub port that isolates the high speed signaling
2035 // environment from Full/Low speed signaling environment for a device
2037 InputContext
->Slot
.TTPortNum
= ParentPort
;
2038 InputContext
->Slot
.TTHubSlotId
= ParentSlotId
;
2042 // Inherit the TT parameters from parent device.
2044 InputContext
->Slot
.TTPortNum
= ParentDeviceContext
->Slot
.TTPortNum
;
2045 InputContext
->Slot
.TTHubSlotId
= ParentDeviceContext
->Slot
.TTHubSlotId
;
2047 // If the device is a High speed device then down the speed to be the same as its parent Hub
2049 if (DeviceSpeed
== EFI_USB_SPEED_HIGH
) {
2050 InputContext
->Slot
.Speed
= ParentDeviceContext
->Slot
.Speed
;
2056 // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
2058 EndpointTransferRing
= AllocateZeroPool (sizeof (TRANSFER_RING
));
2059 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0] = EndpointTransferRing
;
2060 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0]);
2062 // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
2064 InputContext
->EP
[0].EPType
= ED_CONTROL_BIDIR
;
2066 if (DeviceSpeed
== EFI_USB_SPEED_SUPER
) {
2067 InputContext
->EP
[0].MaxPacketSize
= 512;
2068 } else if (DeviceSpeed
== EFI_USB_SPEED_HIGH
) {
2069 InputContext
->EP
[0].MaxPacketSize
= 64;
2071 InputContext
->EP
[0].MaxPacketSize
= 8;
2074 // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
2075 // 1KB, and Bulk and Isoch endpoints 3KB.
2077 InputContext
->EP
[0].AverageTRBLength
= 8;
2078 InputContext
->EP
[0].MaxBurstSize
= 0;
2079 InputContext
->EP
[0].Interval
= 0;
2080 InputContext
->EP
[0].MaxPStreams
= 0;
2081 InputContext
->EP
[0].Mult
= 0;
2082 InputContext
->EP
[0].CErr
= 3;
2085 // Init the DCS(dequeue cycle state) as the transfer ring's CCS
2087 PhyAddr
= UsbHcGetPciAddrForHostAddr (
2089 ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0])->RingSeg0
,
2090 sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
2092 InputContext
->EP
[0].PtrLo
= XHC_LOW_32BIT (PhyAddr
) | BIT0
;
2093 InputContext
->EP
[0].PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2096 // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
2098 OutputContext
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (DEVICE_CONTEXT
));
2099 ASSERT (OutputContext
!= NULL
);
2100 ASSERT (((UINTN
) OutputContext
& 0x3F) == 0);
2101 ZeroMem (OutputContext
, sizeof (DEVICE_CONTEXT
));
2103 Xhc
->UsbDevContext
[SlotId
].OutputContext
= OutputContext
;
2105 // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
2106 // a pointer to the Output Device Context data structure (6.2.1).
2108 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, OutputContext
, sizeof (DEVICE_CONTEXT
));
2110 // Fill DCBAA with PCI device address
2112 Xhc
->DCBAA
[SlotId
] = (UINT64
) (UINTN
) PhyAddr
;
2115 // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
2116 // Context data structure described above.
2118 // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request
2121 gBS
->Stall (XHC_RESET_RECOVERY_DELAY
);
2122 ZeroMem (&CmdTrbAddr
, sizeof (CmdTrbAddr
));
2123 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].InputContext
, sizeof (INPUT_CONTEXT
));
2124 CmdTrbAddr
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2125 CmdTrbAddr
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2126 CmdTrbAddr
.CycleBit
= 1;
2127 CmdTrbAddr
.Type
= TRB_TYPE_ADDRESS_DEV
;
2128 CmdTrbAddr
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
2129 Status
= XhcCmdTransfer (
2131 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbAddr
,
2132 XHC_GENERIC_TIMEOUT
,
2133 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2135 if (!EFI_ERROR (Status
)) {
2136 DeviceAddress
= (UINT8
) ((DEVICE_CONTEXT
*) OutputContext
)->Slot
.DeviceAddress
;
2137 DEBUG ((EFI_D_INFO
, " Address %d assigned successfully\n", DeviceAddress
));
2138 Xhc
->UsbDevContext
[SlotId
].XhciDevAddr
= DeviceAddress
;
2145 Assign and initialize the device slot for a new device.
2147 @param Xhc The XHCI Instance.
2148 @param ParentRouteChart The route string pointed to the parent device.
2149 @param ParentPort The port at which the device is located.
2150 @param RouteChart The route string pointed to the device.
2151 @param DeviceSpeed The device speed.
2153 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
2158 XhcInitializeDeviceSlot64 (
2159 IN USB_XHCI_INSTANCE
*Xhc
,
2160 IN USB_DEV_ROUTE ParentRouteChart
,
2161 IN UINT16 ParentPort
,
2162 IN USB_DEV_ROUTE RouteChart
,
2163 IN UINT8 DeviceSpeed
2167 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
2168 INPUT_CONTEXT_64
*InputContext
;
2169 DEVICE_CONTEXT_64
*OutputContext
;
2170 TRANSFER_RING
*EndpointTransferRing
;
2171 CMD_TRB_ADDRESS_DEVICE CmdTrbAddr
;
2172 UINT8 DeviceAddress
;
2173 CMD_TRB_ENABLE_SLOT CmdTrb
;
2176 DEVICE_CONTEXT_64
*ParentDeviceContext
;
2177 EFI_PHYSICAL_ADDRESS PhyAddr
;
2179 ZeroMem (&CmdTrb
, sizeof (CMD_TRB_ENABLE_SLOT
));
2180 CmdTrb
.CycleBit
= 1;
2181 CmdTrb
.Type
= TRB_TYPE_EN_SLOT
;
2183 Status
= XhcCmdTransfer (
2185 (TRB_TEMPLATE
*) (UINTN
) &CmdTrb
,
2186 XHC_GENERIC_TIMEOUT
,
2187 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2189 if (EFI_ERROR (Status
)) {
2190 DEBUG ((EFI_D_ERROR
, "XhcInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status
));
2193 ASSERT (EvtTrb
->SlotId
<= Xhc
->MaxSlotsEn
);
2194 DEBUG ((EFI_D_INFO
, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb
->SlotId
));
2195 SlotId
= (UINT8
)EvtTrb
->SlotId
;
2196 ASSERT (SlotId
!= 0);
2198 ZeroMem (&Xhc
->UsbDevContext
[SlotId
], sizeof (USB_DEV_CONTEXT
));
2199 Xhc
->UsbDevContext
[SlotId
].Enabled
= TRUE
;
2200 Xhc
->UsbDevContext
[SlotId
].SlotId
= SlotId
;
2201 Xhc
->UsbDevContext
[SlotId
].RouteString
.Dword
= RouteChart
.Dword
;
2202 Xhc
->UsbDevContext
[SlotId
].ParentRouteString
.Dword
= ParentRouteChart
.Dword
;
2205 // 4.3.3 Device Slot Initialization
2206 // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
2208 InputContext
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (INPUT_CONTEXT_64
));
2209 ASSERT (InputContext
!= NULL
);
2210 ASSERT (((UINTN
) InputContext
& 0x3F) == 0);
2211 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
2213 Xhc
->UsbDevContext
[SlotId
].InputContext
= (VOID
*) InputContext
;
2216 // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
2217 // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input
2218 // Context are affected by the command.
2220 InputContext
->InputControlContext
.Dword2
|= (BIT0
| BIT1
);
2223 // 3) Initialize the Input Slot Context data structure
2225 InputContext
->Slot
.RouteString
= RouteChart
.Route
.RouteString
;
2226 InputContext
->Slot
.Speed
= DeviceSpeed
+ 1;
2227 InputContext
->Slot
.ContextEntries
= 1;
2228 InputContext
->Slot
.RootHubPortNum
= RouteChart
.Route
.RootPortNum
;
2230 if (RouteChart
.Route
.RouteString
) {
2232 // The device is behind of hub device.
2234 ParentSlotId
= XhcRouteStringToSlotId(Xhc
, ParentRouteChart
);
2235 ASSERT (ParentSlotId
!= 0);
2237 //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
2239 ParentDeviceContext
= (DEVICE_CONTEXT_64
*)Xhc
->UsbDevContext
[ParentSlotId
].OutputContext
;
2240 if ((ParentDeviceContext
->Slot
.TTPortNum
== 0) &&
2241 (ParentDeviceContext
->Slot
.TTHubSlotId
== 0)) {
2242 if ((ParentDeviceContext
->Slot
.Speed
== (EFI_USB_SPEED_HIGH
+ 1)) && (DeviceSpeed
< EFI_USB_SPEED_HIGH
)) {
2244 // Full/Low device attached to High speed hub port that isolates the high speed signaling
2245 // environment from Full/Low speed signaling environment for a device
2247 InputContext
->Slot
.TTPortNum
= ParentPort
;
2248 InputContext
->Slot
.TTHubSlotId
= ParentSlotId
;
2252 // Inherit the TT parameters from parent device.
2254 InputContext
->Slot
.TTPortNum
= ParentDeviceContext
->Slot
.TTPortNum
;
2255 InputContext
->Slot
.TTHubSlotId
= ParentDeviceContext
->Slot
.TTHubSlotId
;
2257 // If the device is a High speed device then down the speed to be the same as its parent Hub
2259 if (DeviceSpeed
== EFI_USB_SPEED_HIGH
) {
2260 InputContext
->Slot
.Speed
= ParentDeviceContext
->Slot
.Speed
;
2266 // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
2268 EndpointTransferRing
= AllocateZeroPool (sizeof (TRANSFER_RING
));
2269 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0] = EndpointTransferRing
;
2270 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0]);
2272 // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
2274 InputContext
->EP
[0].EPType
= ED_CONTROL_BIDIR
;
2276 if (DeviceSpeed
== EFI_USB_SPEED_SUPER
) {
2277 InputContext
->EP
[0].MaxPacketSize
= 512;
2278 } else if (DeviceSpeed
== EFI_USB_SPEED_HIGH
) {
2279 InputContext
->EP
[0].MaxPacketSize
= 64;
2281 InputContext
->EP
[0].MaxPacketSize
= 8;
2284 // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
2285 // 1KB, and Bulk and Isoch endpoints 3KB.
2287 InputContext
->EP
[0].AverageTRBLength
= 8;
2288 InputContext
->EP
[0].MaxBurstSize
= 0;
2289 InputContext
->EP
[0].Interval
= 0;
2290 InputContext
->EP
[0].MaxPStreams
= 0;
2291 InputContext
->EP
[0].Mult
= 0;
2292 InputContext
->EP
[0].CErr
= 3;
2295 // Init the DCS(dequeue cycle state) as the transfer ring's CCS
2297 PhyAddr
= UsbHcGetPciAddrForHostAddr (
2299 ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0])->RingSeg0
,
2300 sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
2302 InputContext
->EP
[0].PtrLo
= XHC_LOW_32BIT (PhyAddr
) | BIT0
;
2303 InputContext
->EP
[0].PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2306 // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
2308 OutputContext
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (DEVICE_CONTEXT_64
));
2309 ASSERT (OutputContext
!= NULL
);
2310 ASSERT (((UINTN
) OutputContext
& 0x3F) == 0);
2311 ZeroMem (OutputContext
, sizeof (DEVICE_CONTEXT_64
));
2313 Xhc
->UsbDevContext
[SlotId
].OutputContext
= OutputContext
;
2315 // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
2316 // a pointer to the Output Device Context data structure (6.2.1).
2318 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, OutputContext
, sizeof (DEVICE_CONTEXT_64
));
2320 // Fill DCBAA with PCI device address
2322 Xhc
->DCBAA
[SlotId
] = (UINT64
) (UINTN
) PhyAddr
;
2325 // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
2326 // Context data structure described above.
2328 // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request
2331 gBS
->Stall (XHC_RESET_RECOVERY_DELAY
);
2332 ZeroMem (&CmdTrbAddr
, sizeof (CmdTrbAddr
));
2333 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].InputContext
, sizeof (INPUT_CONTEXT_64
));
2334 CmdTrbAddr
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2335 CmdTrbAddr
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2336 CmdTrbAddr
.CycleBit
= 1;
2337 CmdTrbAddr
.Type
= TRB_TYPE_ADDRESS_DEV
;
2338 CmdTrbAddr
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
2339 Status
= XhcCmdTransfer (
2341 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbAddr
,
2342 XHC_GENERIC_TIMEOUT
,
2343 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2345 if (!EFI_ERROR (Status
)) {
2346 DeviceAddress
= (UINT8
) ((DEVICE_CONTEXT_64
*) OutputContext
)->Slot
.DeviceAddress
;
2347 DEBUG ((EFI_D_INFO
, " Address %d assigned successfully\n", DeviceAddress
));
2348 Xhc
->UsbDevContext
[SlotId
].XhciDevAddr
= DeviceAddress
;
2355 Disable the specified device slot.
2357 @param Xhc The XHCI Instance.
2358 @param SlotId The slot id to be disabled.
2360 @retval EFI_SUCCESS Successfully disable the device slot.
2366 IN USB_XHCI_INSTANCE
*Xhc
,
2371 TRB_TEMPLATE
*EvtTrb
;
2372 CMD_TRB_DISABLE_SLOT CmdTrbDisSlot
;
2377 // Disable the device slots occupied by these devices on its downstream ports.
2378 // Entry 0 is reserved.
2380 for (Index
= 0; Index
< 255; Index
++) {
2381 if (!Xhc
->UsbDevContext
[Index
+ 1].Enabled
||
2382 (Xhc
->UsbDevContext
[Index
+ 1].SlotId
== 0) ||
2383 (Xhc
->UsbDevContext
[Index
+ 1].ParentRouteString
.Dword
!= Xhc
->UsbDevContext
[SlotId
].RouteString
.Dword
)) {
2387 Status
= XhcDisableSlotCmd (Xhc
, Xhc
->UsbDevContext
[Index
+ 1].SlotId
);
2389 if (EFI_ERROR (Status
)) {
2390 DEBUG ((EFI_D_ERROR
, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
2391 Xhc
->UsbDevContext
[Index
+ 1].SlotId
= 0;
2396 // Construct the disable slot command
2398 DEBUG ((EFI_D_INFO
, "Disable device slot %d!\n", SlotId
));
2400 ZeroMem (&CmdTrbDisSlot
, sizeof (CmdTrbDisSlot
));
2401 CmdTrbDisSlot
.CycleBit
= 1;
2402 CmdTrbDisSlot
.Type
= TRB_TYPE_DIS_SLOT
;
2403 CmdTrbDisSlot
.SlotId
= SlotId
;
2404 Status
= XhcCmdTransfer (
2406 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbDisSlot
,
2407 XHC_GENERIC_TIMEOUT
,
2408 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2410 if (EFI_ERROR (Status
)) {
2411 DEBUG ((EFI_D_ERROR
, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status
));
2415 // Free the slot's device context entry
2417 Xhc
->DCBAA
[SlotId
] = 0;
2420 // Free the slot related data structure
2422 for (Index
= 0; Index
< 31; Index
++) {
2423 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
] != NULL
) {
2424 RingSeg
= ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
])->RingSeg0
;
2425 if (RingSeg
!= NULL
) {
2426 UsbHcFreeMem (Xhc
->MemPool
, RingSeg
, sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
);
2428 FreePool (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
]);
2429 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
] = NULL
;
2433 for (Index
= 0; Index
< Xhc
->UsbDevContext
[SlotId
].DevDesc
.NumConfigurations
; Index
++) {
2434 if (Xhc
->UsbDevContext
[SlotId
].ConfDesc
[Index
] != NULL
) {
2435 FreePool (Xhc
->UsbDevContext
[SlotId
].ConfDesc
[Index
]);
2439 if (Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
!= NULL
) {
2440 FreePool (Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
);
2443 if (Xhc
->UsbDevContext
[SlotId
].InputContext
!= NULL
) {
2444 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].InputContext
, sizeof (INPUT_CONTEXT
));
2447 if (Xhc
->UsbDevContext
[SlotId
].OutputContext
!= NULL
) {
2448 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].OutputContext
, sizeof (DEVICE_CONTEXT
));
2451 // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
2452 // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
2453 // remove urb from XHCI's asynchronous transfer list.
2455 Xhc
->UsbDevContext
[SlotId
].Enabled
= FALSE
;
2456 Xhc
->UsbDevContext
[SlotId
].SlotId
= 0;
2462 Disable the specified device slot.
2464 @param Xhc The XHCI Instance.
2465 @param SlotId The slot id to be disabled.
2467 @retval EFI_SUCCESS Successfully disable the device slot.
2472 XhcDisableSlotCmd64 (
2473 IN USB_XHCI_INSTANCE
*Xhc
,
2478 TRB_TEMPLATE
*EvtTrb
;
2479 CMD_TRB_DISABLE_SLOT CmdTrbDisSlot
;
2484 // Disable the device slots occupied by these devices on its downstream ports.
2485 // Entry 0 is reserved.
2487 for (Index
= 0; Index
< 255; Index
++) {
2488 if (!Xhc
->UsbDevContext
[Index
+ 1].Enabled
||
2489 (Xhc
->UsbDevContext
[Index
+ 1].SlotId
== 0) ||
2490 (Xhc
->UsbDevContext
[Index
+ 1].ParentRouteString
.Dword
!= Xhc
->UsbDevContext
[SlotId
].RouteString
.Dword
)) {
2494 Status
= XhcDisableSlotCmd64 (Xhc
, Xhc
->UsbDevContext
[Index
+ 1].SlotId
);
2496 if (EFI_ERROR (Status
)) {
2497 DEBUG ((EFI_D_ERROR
, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
2498 Xhc
->UsbDevContext
[Index
+ 1].SlotId
= 0;
2503 // Construct the disable slot command
2505 DEBUG ((EFI_D_INFO
, "Disable device slot %d!\n", SlotId
));
2507 ZeroMem (&CmdTrbDisSlot
, sizeof (CmdTrbDisSlot
));
2508 CmdTrbDisSlot
.CycleBit
= 1;
2509 CmdTrbDisSlot
.Type
= TRB_TYPE_DIS_SLOT
;
2510 CmdTrbDisSlot
.SlotId
= SlotId
;
2511 Status
= XhcCmdTransfer (
2513 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbDisSlot
,
2514 XHC_GENERIC_TIMEOUT
,
2515 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2517 if (EFI_ERROR (Status
)) {
2518 DEBUG ((EFI_D_ERROR
, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status
));
2522 // Free the slot's device context entry
2524 Xhc
->DCBAA
[SlotId
] = 0;
2527 // Free the slot related data structure
2529 for (Index
= 0; Index
< 31; Index
++) {
2530 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
] != NULL
) {
2531 RingSeg
= ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
])->RingSeg0
;
2532 if (RingSeg
!= NULL
) {
2533 UsbHcFreeMem (Xhc
->MemPool
, RingSeg
, sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
);
2535 FreePool (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
]);
2536 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
] = NULL
;
2540 for (Index
= 0; Index
< Xhc
->UsbDevContext
[SlotId
].DevDesc
.NumConfigurations
; Index
++) {
2541 if (Xhc
->UsbDevContext
[SlotId
].ConfDesc
[Index
] != NULL
) {
2542 FreePool (Xhc
->UsbDevContext
[SlotId
].ConfDesc
[Index
]);
2546 if (Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
!= NULL
) {
2547 FreePool (Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
);
2550 if (Xhc
->UsbDevContext
[SlotId
].InputContext
!= NULL
) {
2551 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].InputContext
, sizeof (INPUT_CONTEXT_64
));
2554 if (Xhc
->UsbDevContext
[SlotId
].OutputContext
!= NULL
) {
2555 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].OutputContext
, sizeof (DEVICE_CONTEXT_64
));
2558 // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
2559 // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
2560 // remove urb from XHCI's asynchronous transfer list.
2562 Xhc
->UsbDevContext
[SlotId
].Enabled
= FALSE
;
2563 Xhc
->UsbDevContext
[SlotId
].SlotId
= 0;
2569 Initialize endpoint context in input context.
2571 @param Xhc The XHCI Instance.
2572 @param SlotId The slot id to be configured.
2573 @param DeviceSpeed The device's speed.
2574 @param InputContext The pointer to the input context.
2575 @param IfDesc The pointer to the usb device interface descriptor.
2577 @return The maximum device context index of endpoint.
2582 XhcInitializeEndpointContext (
2583 IN USB_XHCI_INSTANCE
*Xhc
,
2585 IN UINT8 DeviceSpeed
,
2586 IN INPUT_CONTEXT
*InputContext
,
2587 IN USB_INTERFACE_DESCRIPTOR
*IfDesc
2590 USB_ENDPOINT_DESCRIPTOR
*EpDesc
;
2597 EFI_PHYSICAL_ADDRESS PhyAddr
;
2599 TRANSFER_RING
*EndpointTransferRing
;
2603 NumEp
= IfDesc
->NumEndpoints
;
2605 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)(IfDesc
+ 1);
2606 for (EpIndex
= 0; EpIndex
< NumEp
; EpIndex
++) {
2607 while (EpDesc
->DescriptorType
!= USB_DESC_TYPE_ENDPOINT
) {
2608 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2611 if (EpDesc
->Length
< sizeof (USB_ENDPOINT_DESCRIPTOR
)) {
2612 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2616 EpAddr
= (UINT8
)(EpDesc
->EndpointAddress
& 0x0F);
2617 Direction
= (UINT8
)((EpDesc
->EndpointAddress
& 0x80) ? EfiUsbDataIn
: EfiUsbDataOut
);
2619 Dci
= XhcEndpointToDci (EpAddr
, Direction
);
2625 InputContext
->InputControlContext
.Dword2
|= (BIT0
<< Dci
);
2626 InputContext
->EP
[Dci
-1].MaxPacketSize
= EpDesc
->MaxPacketSize
;
2628 if (DeviceSpeed
== EFI_USB_SPEED_SUPER
) {
2630 // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
2632 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2634 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2637 switch (EpDesc
->Attributes
& USB_ENDPOINT_TYPE_MASK
) {
2638 case USB_ENDPOINT_BULK
:
2639 if (Direction
== EfiUsbDataIn
) {
2640 InputContext
->EP
[Dci
-1].CErr
= 3;
2641 InputContext
->EP
[Dci
-1].EPType
= ED_BULK_IN
;
2643 InputContext
->EP
[Dci
-1].CErr
= 3;
2644 InputContext
->EP
[Dci
-1].EPType
= ED_BULK_OUT
;
2647 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2648 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] == NULL
) {
2649 EndpointTransferRing
= AllocateZeroPool(sizeof (TRANSFER_RING
));
2650 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] = (VOID
*) EndpointTransferRing
;
2651 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1]);
2655 case USB_ENDPOINT_ISO
:
2656 if (Direction
== EfiUsbDataIn
) {
2657 InputContext
->EP
[Dci
-1].CErr
= 0;
2658 InputContext
->EP
[Dci
-1].EPType
= ED_ISOCH_IN
;
2660 InputContext
->EP
[Dci
-1].CErr
= 0;
2661 InputContext
->EP
[Dci
-1].EPType
= ED_ISOCH_OUT
;
2664 // Get the bInterval from descriptor and init the the interval field of endpoint context.
2665 // Refer to XHCI 1.1 spec section 6.2.3.6.
2667 if (DeviceSpeed
== EFI_USB_SPEED_FULL
) {
2668 Interval
= EpDesc
->Interval
;
2669 ASSERT (Interval
>= 1 && Interval
<= 16);
2670 InputContext
->EP
[Dci
-1].Interval
= Interval
+ 2;
2671 } else if ((DeviceSpeed
== EFI_USB_SPEED_HIGH
) || (DeviceSpeed
== EFI_USB_SPEED_SUPER
)) {
2672 Interval
= EpDesc
->Interval
;
2673 ASSERT (Interval
>= 1 && Interval
<= 16);
2674 InputContext
->EP
[Dci
-1].Interval
= Interval
- 1;
2678 // Do not support isochronous transfer now.
2680 DEBUG ((EFI_D_INFO
, "XhcInitializeEndpointContext: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
2681 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2683 case USB_ENDPOINT_INTERRUPT
:
2684 if (Direction
== EfiUsbDataIn
) {
2685 InputContext
->EP
[Dci
-1].CErr
= 3;
2686 InputContext
->EP
[Dci
-1].EPType
= ED_INTERRUPT_IN
;
2688 InputContext
->EP
[Dci
-1].CErr
= 3;
2689 InputContext
->EP
[Dci
-1].EPType
= ED_INTERRUPT_OUT
;
2691 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2692 InputContext
->EP
[Dci
-1].MaxESITPayload
= EpDesc
->MaxPacketSize
;
2694 // Get the bInterval from descriptor and init the the interval field of endpoint context
2696 if ((DeviceSpeed
== EFI_USB_SPEED_FULL
) || (DeviceSpeed
== EFI_USB_SPEED_LOW
)) {
2697 Interval
= EpDesc
->Interval
;
2699 // Calculate through the bInterval field of Endpoint descriptor.
2701 ASSERT (Interval
!= 0);
2702 InputContext
->EP
[Dci
-1].Interval
= (UINT32
)HighBitSet32((UINT32
)Interval
) + 3;
2703 } else if ((DeviceSpeed
== EFI_USB_SPEED_HIGH
) || (DeviceSpeed
== EFI_USB_SPEED_SUPER
)) {
2704 Interval
= EpDesc
->Interval
;
2705 ASSERT (Interval
>= 1 && Interval
<= 16);
2707 // Refer to XHCI 1.0 spec section 6.2.3.6, table 61
2709 InputContext
->EP
[Dci
-1].Interval
= Interval
- 1;
2710 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2711 InputContext
->EP
[Dci
-1].MaxESITPayload
= 0x0002;
2712 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2713 InputContext
->EP
[Dci
-1].CErr
= 3;
2716 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] == NULL
) {
2717 EndpointTransferRing
= AllocateZeroPool(sizeof (TRANSFER_RING
));
2718 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] = (VOID
*) EndpointTransferRing
;
2719 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1]);
2723 case USB_ENDPOINT_CONTROL
:
2725 // Do not support control transfer now.
2727 DEBUG ((EFI_D_INFO
, "XhcInitializeEndpointContext: Unsupport Control EP found, Transfer ring is not allocated.\n"));
2729 DEBUG ((EFI_D_INFO
, "XhcInitializeEndpointContext: Unknown EP found, Transfer ring is not allocated.\n"));
2730 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2734 PhyAddr
= UsbHcGetPciAddrForHostAddr (
2736 ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1])->RingSeg0
,
2737 sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
2739 PhyAddr
&= ~((EFI_PHYSICAL_ADDRESS
)0x0F);
2740 PhyAddr
|= (EFI_PHYSICAL_ADDRESS
)((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1])->RingPCS
;
2741 InputContext
->EP
[Dci
-1].PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2742 InputContext
->EP
[Dci
-1].PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2744 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2751 Initialize endpoint context in input context.
2753 @param Xhc The XHCI Instance.
2754 @param SlotId The slot id to be configured.
2755 @param DeviceSpeed The device's speed.
2756 @param InputContext The pointer to the input context.
2757 @param IfDesc The pointer to the usb device interface descriptor.
2759 @return The maximum device context index of endpoint.
2764 XhcInitializeEndpointContext64 (
2765 IN USB_XHCI_INSTANCE
*Xhc
,
2767 IN UINT8 DeviceSpeed
,
2768 IN INPUT_CONTEXT_64
*InputContext
,
2769 IN USB_INTERFACE_DESCRIPTOR
*IfDesc
2772 USB_ENDPOINT_DESCRIPTOR
*EpDesc
;
2779 EFI_PHYSICAL_ADDRESS PhyAddr
;
2781 TRANSFER_RING
*EndpointTransferRing
;
2785 NumEp
= IfDesc
->NumEndpoints
;
2787 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)(IfDesc
+ 1);
2788 for (EpIndex
= 0; EpIndex
< NumEp
; EpIndex
++) {
2789 while (EpDesc
->DescriptorType
!= USB_DESC_TYPE_ENDPOINT
) {
2790 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2793 if (EpDesc
->Length
< sizeof (USB_ENDPOINT_DESCRIPTOR
)) {
2794 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2798 EpAddr
= (UINT8
)(EpDesc
->EndpointAddress
& 0x0F);
2799 Direction
= (UINT8
)((EpDesc
->EndpointAddress
& 0x80) ? EfiUsbDataIn
: EfiUsbDataOut
);
2801 Dci
= XhcEndpointToDci (EpAddr
, Direction
);
2807 InputContext
->InputControlContext
.Dword2
|= (BIT0
<< Dci
);
2808 InputContext
->EP
[Dci
-1].MaxPacketSize
= EpDesc
->MaxPacketSize
;
2810 if (DeviceSpeed
== EFI_USB_SPEED_SUPER
) {
2812 // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
2814 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2816 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2819 switch (EpDesc
->Attributes
& USB_ENDPOINT_TYPE_MASK
) {
2820 case USB_ENDPOINT_BULK
:
2821 if (Direction
== EfiUsbDataIn
) {
2822 InputContext
->EP
[Dci
-1].CErr
= 3;
2823 InputContext
->EP
[Dci
-1].EPType
= ED_BULK_IN
;
2825 InputContext
->EP
[Dci
-1].CErr
= 3;
2826 InputContext
->EP
[Dci
-1].EPType
= ED_BULK_OUT
;
2829 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2830 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] == NULL
) {
2831 EndpointTransferRing
= AllocateZeroPool(sizeof (TRANSFER_RING
));
2832 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] = (VOID
*) EndpointTransferRing
;
2833 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1]);
2837 case USB_ENDPOINT_ISO
:
2838 if (Direction
== EfiUsbDataIn
) {
2839 InputContext
->EP
[Dci
-1].CErr
= 0;
2840 InputContext
->EP
[Dci
-1].EPType
= ED_ISOCH_IN
;
2842 InputContext
->EP
[Dci
-1].CErr
= 0;
2843 InputContext
->EP
[Dci
-1].EPType
= ED_ISOCH_OUT
;
2846 // Get the bInterval from descriptor and init the the interval field of endpoint context.
2847 // Refer to XHCI 1.1 spec section 6.2.3.6.
2849 if (DeviceSpeed
== EFI_USB_SPEED_FULL
) {
2850 Interval
= EpDesc
->Interval
;
2851 ASSERT (Interval
>= 1 && Interval
<= 16);
2852 InputContext
->EP
[Dci
-1].Interval
= Interval
+ 2;
2853 } else if ((DeviceSpeed
== EFI_USB_SPEED_HIGH
) || (DeviceSpeed
== EFI_USB_SPEED_SUPER
)) {
2854 Interval
= EpDesc
->Interval
;
2855 ASSERT (Interval
>= 1 && Interval
<= 16);
2856 InputContext
->EP
[Dci
-1].Interval
= Interval
- 1;
2860 // Do not support isochronous transfer now.
2862 DEBUG ((EFI_D_INFO
, "XhcInitializeEndpointContext64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
2863 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2865 case USB_ENDPOINT_INTERRUPT
:
2866 if (Direction
== EfiUsbDataIn
) {
2867 InputContext
->EP
[Dci
-1].CErr
= 3;
2868 InputContext
->EP
[Dci
-1].EPType
= ED_INTERRUPT_IN
;
2870 InputContext
->EP
[Dci
-1].CErr
= 3;
2871 InputContext
->EP
[Dci
-1].EPType
= ED_INTERRUPT_OUT
;
2873 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2874 InputContext
->EP
[Dci
-1].MaxESITPayload
= EpDesc
->MaxPacketSize
;
2876 // Get the bInterval from descriptor and init the the interval field of endpoint context
2878 if ((DeviceSpeed
== EFI_USB_SPEED_FULL
) || (DeviceSpeed
== EFI_USB_SPEED_LOW
)) {
2879 Interval
= EpDesc
->Interval
;
2881 // Calculate through the bInterval field of Endpoint descriptor.
2883 ASSERT (Interval
!= 0);
2884 InputContext
->EP
[Dci
-1].Interval
= (UINT32
)HighBitSet32((UINT32
)Interval
) + 3;
2885 } else if ((DeviceSpeed
== EFI_USB_SPEED_HIGH
) || (DeviceSpeed
== EFI_USB_SPEED_SUPER
)) {
2886 Interval
= EpDesc
->Interval
;
2887 ASSERT (Interval
>= 1 && Interval
<= 16);
2889 // Refer to XHCI 1.0 spec section 6.2.3.6, table 61
2891 InputContext
->EP
[Dci
-1].Interval
= Interval
- 1;
2892 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2893 InputContext
->EP
[Dci
-1].MaxESITPayload
= 0x0002;
2894 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2895 InputContext
->EP
[Dci
-1].CErr
= 3;
2898 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] == NULL
) {
2899 EndpointTransferRing
= AllocateZeroPool(sizeof (TRANSFER_RING
));
2900 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] = (VOID
*) EndpointTransferRing
;
2901 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1]);
2905 case USB_ENDPOINT_CONTROL
:
2907 // Do not support control transfer now.
2909 DEBUG ((EFI_D_INFO
, "XhcInitializeEndpointContext64: Unsupport Control EP found, Transfer ring is not allocated.\n"));
2911 DEBUG ((EFI_D_INFO
, "XhcInitializeEndpointContext64: Unknown EP found, Transfer ring is not allocated.\n"));
2912 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2916 PhyAddr
= UsbHcGetPciAddrForHostAddr (
2918 ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1])->RingSeg0
,
2919 sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
2921 PhyAddr
&= ~((EFI_PHYSICAL_ADDRESS
)0x0F);
2922 PhyAddr
|= (EFI_PHYSICAL_ADDRESS
)((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1])->RingPCS
;
2923 InputContext
->EP
[Dci
-1].PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2924 InputContext
->EP
[Dci
-1].PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2926 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2933 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
2935 @param Xhc The XHCI Instance.
2936 @param SlotId The slot id to be configured.
2937 @param DeviceSpeed The device's speed.
2938 @param ConfigDesc The pointer to the usb device configuration descriptor.
2940 @retval EFI_SUCCESS Successfully configure all the device endpoints.
2946 IN USB_XHCI_INSTANCE
*Xhc
,
2948 IN UINT8 DeviceSpeed
,
2949 IN USB_CONFIG_DESCRIPTOR
*ConfigDesc
2953 USB_INTERFACE_DESCRIPTOR
*IfDesc
;
2957 EFI_PHYSICAL_ADDRESS PhyAddr
;
2959 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
2960 INPUT_CONTEXT
*InputContext
;
2961 DEVICE_CONTEXT
*OutputContext
;
2962 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
2964 // 4.6.6 Configure Endpoint
2966 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
2967 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
2968 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
2969 CopyMem (&InputContext
->Slot
, &OutputContext
->Slot
, sizeof (SLOT_CONTEXT
));
2971 ASSERT (ConfigDesc
!= NULL
);
2975 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)(ConfigDesc
+ 1);
2976 for (Index
= 0; Index
< ConfigDesc
->NumInterfaces
; Index
++) {
2977 while ((IfDesc
->DescriptorType
!= USB_DESC_TYPE_INTERFACE
) || (IfDesc
->AlternateSetting
!= 0)) {
2978 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
2981 if (IfDesc
->Length
< sizeof (USB_INTERFACE_DESCRIPTOR
)) {
2982 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
2986 Dci
= XhcInitializeEndpointContext (Xhc
, SlotId
, DeviceSpeed
, InputContext
, IfDesc
);
2991 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
2994 InputContext
->InputControlContext
.Dword2
|= BIT0
;
2995 InputContext
->Slot
.ContextEntries
= MaxDci
;
2997 // configure endpoint
2999 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
3000 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT
));
3001 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3002 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3003 CmdTrbCfgEP
.CycleBit
= 1;
3004 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
3005 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3006 DEBUG ((EFI_D_INFO
, "Configure Endpoint\n"));
3007 Status
= XhcCmdTransfer (
3009 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
3010 XHC_GENERIC_TIMEOUT
,
3011 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3013 if (EFI_ERROR (Status
)) {
3014 DEBUG ((EFI_D_ERROR
, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status
));
3016 Xhc
->UsbDevContext
[SlotId
].ActiveConfiguration
= ConfigDesc
->ConfigurationValue
;
3023 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
3025 @param Xhc The XHCI Instance.
3026 @param SlotId The slot id to be configured.
3027 @param DeviceSpeed The device's speed.
3028 @param ConfigDesc The pointer to the usb device configuration descriptor.
3030 @retval EFI_SUCCESS Successfully configure all the device endpoints.
3036 IN USB_XHCI_INSTANCE
*Xhc
,
3038 IN UINT8 DeviceSpeed
,
3039 IN USB_CONFIG_DESCRIPTOR
*ConfigDesc
3043 USB_INTERFACE_DESCRIPTOR
*IfDesc
;
3047 EFI_PHYSICAL_ADDRESS PhyAddr
;
3049 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
3050 INPUT_CONTEXT_64
*InputContext
;
3051 DEVICE_CONTEXT_64
*OutputContext
;
3052 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3054 // 4.6.6 Configure Endpoint
3056 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
3057 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
3058 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
3059 CopyMem (&InputContext
->Slot
, &OutputContext
->Slot
, sizeof (SLOT_CONTEXT_64
));
3061 ASSERT (ConfigDesc
!= NULL
);
3065 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)(ConfigDesc
+ 1);
3066 for (Index
= 0; Index
< ConfigDesc
->NumInterfaces
; Index
++) {
3067 while ((IfDesc
->DescriptorType
!= USB_DESC_TYPE_INTERFACE
) || (IfDesc
->AlternateSetting
!= 0)) {
3068 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
3071 if (IfDesc
->Length
< sizeof (USB_INTERFACE_DESCRIPTOR
)) {
3072 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
3076 Dci
= XhcInitializeEndpointContext64 (Xhc
, SlotId
, DeviceSpeed
, InputContext
, IfDesc
);
3081 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
3084 InputContext
->InputControlContext
.Dword2
|= BIT0
;
3085 InputContext
->Slot
.ContextEntries
= MaxDci
;
3087 // configure endpoint
3089 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
3090 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT_64
));
3091 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3092 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3093 CmdTrbCfgEP
.CycleBit
= 1;
3094 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
3095 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3096 DEBUG ((EFI_D_INFO
, "Configure Endpoint\n"));
3097 Status
= XhcCmdTransfer (
3099 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
3100 XHC_GENERIC_TIMEOUT
,
3101 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3103 if (EFI_ERROR (Status
)) {
3104 DEBUG ((EFI_D_ERROR
, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status
));
3106 Xhc
->UsbDevContext
[SlotId
].ActiveConfiguration
= ConfigDesc
->ConfigurationValue
;
3113 Stop endpoint through XHCI's Stop_Endpoint cmd.
3115 @param Xhc The XHCI Instance.
3116 @param SlotId The slot id to be configured.
3117 @param Dci The device context index of endpoint.
3119 @retval EFI_SUCCESS Stop endpoint successfully.
3120 @retval Others Failed to stop endpoint.
3126 IN USB_XHCI_INSTANCE
*Xhc
,
3132 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3133 CMD_TRB_STOP_ENDPOINT CmdTrbStopED
;
3135 DEBUG ((EFI_D_INFO
, "XhcStopEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId
, Dci
));
3138 // Send stop endpoint command to transit Endpoint from running to stop state
3140 ZeroMem (&CmdTrbStopED
, sizeof (CmdTrbStopED
));
3141 CmdTrbStopED
.CycleBit
= 1;
3142 CmdTrbStopED
.Type
= TRB_TYPE_STOP_ENDPOINT
;
3143 CmdTrbStopED
.EDID
= Dci
;
3144 CmdTrbStopED
.SlotId
= SlotId
;
3145 Status
= XhcCmdTransfer (
3147 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbStopED
,
3148 XHC_GENERIC_TIMEOUT
,
3149 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3151 if (EFI_ERROR(Status
)) {
3152 DEBUG ((EFI_D_ERROR
, "XhcStopEndpoint: Stop Endpoint Failed, Status = %r\n", Status
));
3159 Reset endpoint through XHCI's Reset_Endpoint cmd.
3161 @param Xhc The XHCI Instance.
3162 @param SlotId The slot id to be configured.
3163 @param Dci The device context index of endpoint.
3165 @retval EFI_SUCCESS Reset endpoint successfully.
3166 @retval Others Failed to reset endpoint.
3172 IN USB_XHCI_INSTANCE
*Xhc
,
3178 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3179 CMD_TRB_RESET_ENDPOINT CmdTrbResetED
;
3181 DEBUG ((EFI_D_INFO
, "XhcResetEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId
, Dci
));
3184 // Send stop endpoint command to transit Endpoint from running to stop state
3186 ZeroMem (&CmdTrbResetED
, sizeof (CmdTrbResetED
));
3187 CmdTrbResetED
.CycleBit
= 1;
3188 CmdTrbResetED
.Type
= TRB_TYPE_RESET_ENDPOINT
;
3189 CmdTrbResetED
.EDID
= Dci
;
3190 CmdTrbResetED
.SlotId
= SlotId
;
3191 Status
= XhcCmdTransfer (
3193 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbResetED
,
3194 XHC_GENERIC_TIMEOUT
,
3195 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3197 if (EFI_ERROR(Status
)) {
3198 DEBUG ((EFI_D_ERROR
, "XhcResetEndpoint: Reset Endpoint Failed, Status = %r\n", Status
));
3205 Set transfer ring dequeue pointer through XHCI's Set_Tr_Dequeue_Pointer cmd.
3207 @param Xhc The XHCI Instance.
3208 @param SlotId The slot id to be configured.
3209 @param Dci The device context index of endpoint.
3210 @param Urb The dequeue pointer of the transfer ring specified
3211 by the urb to be updated.
3213 @retval EFI_SUCCESS Set transfer ring dequeue pointer succeeds.
3214 @retval Others Failed to set transfer ring dequeue pointer.
3219 XhcSetTrDequeuePointer (
3220 IN USB_XHCI_INSTANCE
*Xhc
,
3227 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3228 CMD_SET_TR_DEQ_POINTER CmdSetTRDeq
;
3229 EFI_PHYSICAL_ADDRESS PhyAddr
;
3231 DEBUG ((EFI_D_INFO
, "XhcSetTrDequeuePointer: Slot = 0x%x, Dci = 0x%x, Urb = 0x%x\n", SlotId
, Dci
, Urb
));
3234 // Send stop endpoint command to transit Endpoint from running to stop state
3236 ZeroMem (&CmdSetTRDeq
, sizeof (CmdSetTRDeq
));
3237 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Urb
->Ring
->RingEnqueue
, sizeof (CMD_SET_TR_DEQ_POINTER
));
3238 CmdSetTRDeq
.PtrLo
= XHC_LOW_32BIT (PhyAddr
) | Urb
->Ring
->RingPCS
;
3239 CmdSetTRDeq
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3240 CmdSetTRDeq
.CycleBit
= 1;
3241 CmdSetTRDeq
.Type
= TRB_TYPE_SET_TR_DEQUE
;
3242 CmdSetTRDeq
.Endpoint
= Dci
;
3243 CmdSetTRDeq
.SlotId
= SlotId
;
3244 Status
= XhcCmdTransfer (
3246 (TRB_TEMPLATE
*) (UINTN
) &CmdSetTRDeq
,
3247 XHC_GENERIC_TIMEOUT
,
3248 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3250 if (EFI_ERROR(Status
)) {
3251 DEBUG ((EFI_D_ERROR
, "XhcSetTrDequeuePointer: Set TR Dequeue Pointer Failed, Status = %r\n", Status
));
3258 Set interface through XHCI's Configure_Endpoint cmd.
3260 @param Xhc The XHCI Instance.
3261 @param SlotId The slot id to be configured.
3262 @param DeviceSpeed The device's speed.
3263 @param ConfigDesc The pointer to the usb device configuration descriptor.
3264 @param Request USB device request to send.
3266 @retval EFI_SUCCESS Successfully set interface.
3272 IN USB_XHCI_INSTANCE
*Xhc
,
3274 IN UINT8 DeviceSpeed
,
3275 IN USB_CONFIG_DESCRIPTOR
*ConfigDesc
,
3276 IN EFI_USB_DEVICE_REQUEST
*Request
3280 USB_INTERFACE_DESCRIPTOR
*IfDescActive
;
3281 USB_INTERFACE_DESCRIPTOR
*IfDescSet
;
3282 USB_INTERFACE_DESCRIPTOR
*IfDesc
;
3283 USB_ENDPOINT_DESCRIPTOR
*EpDesc
;
3290 EFI_PHYSICAL_ADDRESS PhyAddr
;
3293 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
3294 INPUT_CONTEXT
*InputContext
;
3295 DEVICE_CONTEXT
*OutputContext
;
3296 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3298 Status
= EFI_SUCCESS
;
3300 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
3301 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
3303 // XHCI 4.6.6 Configure Endpoint
3304 // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
3305 // Context and Add Context flags as follows:
3306 // 1) If an endpoint is not modified by the Alternate Interface setting, then software shall set the Drop
3307 // Context and Add Context flags to '0'.
3309 // Except the interface indicated by Reqeust->Index, no impact to other interfaces.
3310 // So the default Drop Context and Add Context flags can be '0' to cover 1).
3312 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
3313 CopyMem (&InputContext
->Slot
, &OutputContext
->Slot
, sizeof (SLOT_CONTEXT
));
3315 ASSERT (ConfigDesc
!= NULL
);
3319 IfDescActive
= NULL
;
3322 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)(ConfigDesc
+ 1);
3323 while ((UINTN
) IfDesc
< ((UINTN
) ConfigDesc
+ ConfigDesc
->TotalLength
)) {
3324 if ((IfDesc
->DescriptorType
== USB_DESC_TYPE_INTERFACE
) && (IfDesc
->Length
>= sizeof (USB_INTERFACE_DESCRIPTOR
))) {
3325 if (IfDesc
->InterfaceNumber
== (UINT8
) Request
->Index
) {
3326 if (IfDesc
->AlternateSetting
== Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
[IfDesc
->InterfaceNumber
]) {
3328 // Find out the active interface descriptor.
3330 IfDescActive
= IfDesc
;
3331 } else if (IfDesc
->AlternateSetting
== (UINT8
) Request
->Value
) {
3333 // Find out the interface descriptor to set.
3339 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
3343 // XHCI 4.6.6 Configure Endpoint
3344 // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
3345 // Context and Add Context flags as follows:
3346 // 2) If an endpoint previously disabled, is enabled by the Alternate Interface setting, then software shall set
3347 // the Drop Context flag to '0' and Add Context flag to '1', and initialize the Input Endpoint Context.
3348 // 3) If an endpoint previously enabled, is disabled by the Alternate Interface setting, then software shall set
3349 // the Drop Context flag to '1' and Add Context flag to '0'.
3350 // 4) If a parameter of an enabled endpoint is modified by an Alternate Interface setting, the Drop Context
3351 // and Add Context flags shall be set to '1'.
3353 // Below codes are to cover 2), 3) and 4).
3356 if ((IfDescActive
!= NULL
) && (IfDescSet
!= NULL
)) {
3357 NumEp
= IfDescActive
->NumEndpoints
;
3358 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*) (IfDescActive
+ 1);
3359 for (EpIndex
= 0; EpIndex
< NumEp
; EpIndex
++) {
3360 while (EpDesc
->DescriptorType
!= USB_DESC_TYPE_ENDPOINT
) {
3361 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
3364 if (EpDesc
->Length
< sizeof (USB_ENDPOINT_DESCRIPTOR
)) {
3365 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
3369 EpAddr
= (UINT8
) (EpDesc
->EndpointAddress
& 0x0F);
3370 Direction
= (UINT8
) ((EpDesc
->EndpointAddress
& 0x80) ? EfiUsbDataIn
: EfiUsbDataOut
);
3372 Dci
= XhcEndpointToDci (EpAddr
, Direction
);
3378 // XHCI 4.3.6 - Setting Alternate Interfaces
3379 // 1) Stop any Running Transfer Rings affected by the Alternate Interface setting.
3381 Status
= XhcStopEndpoint (Xhc
, SlotId
, Dci
);
3382 if (EFI_ERROR (Status
)) {
3386 // XHCI 4.3.6 - Setting Alternate Interfaces
3387 // 2) Free Transfer Rings of all endpoints that will be affected by the Alternate Interface setting.
3389 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1] != NULL
) {
3390 RingSeg
= ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1])->RingSeg0
;
3391 if (RingSeg
!= NULL
) {
3392 UsbHcFreeMem (Xhc
->MemPool
, RingSeg
, sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
);
3394 FreePool (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1]);
3395 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1] = NULL
;
3399 // Set the Drop Context flag to '1'.
3401 InputContext
->InputControlContext
.Dword1
|= (BIT0
<< Dci
);
3403 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
3407 // XHCI 4.3.6 - Setting Alternate Interfaces
3408 // 3) Clear all the Endpoint Context fields of each endpoint that will be disabled by the Alternate
3409 // Interface setting, to '0'.
3411 // The step 3) has been covered by the ZeroMem () to InputContext at the start of the function.
3415 // XHCI 4.3.6 - Setting Alternate Interfaces
3416 // 4) For each endpoint enabled by the Configure Endpoint Command:
3417 // a. Allocate a Transfer Ring.
3418 // b. Initialize the Transfer Ring Segment(s) by clearing all fields of all TRBs to '0'.
3419 // c. Initialize the Endpoint Context data structure.
3421 Dci
= XhcInitializeEndpointContext (Xhc
, SlotId
, DeviceSpeed
, InputContext
, IfDescSet
);
3426 InputContext
->InputControlContext
.Dword2
|= BIT0
;
3427 InputContext
->Slot
.ContextEntries
= MaxDci
;
3429 // XHCI 4.3.6 - Setting Alternate Interfaces
3430 // 5) Issue and successfully complete a Configure Endpoint Command.
3432 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
3433 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT
));
3434 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3435 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3436 CmdTrbCfgEP
.CycleBit
= 1;
3437 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
3438 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3439 DEBUG ((EFI_D_INFO
, "SetInterface: Configure Endpoint\n"));
3440 Status
= XhcCmdTransfer (
3442 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
3443 XHC_GENERIC_TIMEOUT
,
3444 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3446 if (EFI_ERROR (Status
)) {
3447 DEBUG ((EFI_D_ERROR
, "SetInterface: Config Endpoint Failed, Status = %r\n", Status
));
3450 // Update the active AlternateSetting.
3452 Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
[(UINT8
) Request
->Index
] = (UINT8
) Request
->Value
;
3460 Set interface through XHCI's Configure_Endpoint cmd.
3462 @param Xhc The XHCI Instance.
3463 @param SlotId The slot id to be configured.
3464 @param DeviceSpeed The device's speed.
3465 @param ConfigDesc The pointer to the usb device configuration descriptor.
3466 @param Request USB device request to send.
3468 @retval EFI_SUCCESS Successfully set interface.
3474 IN USB_XHCI_INSTANCE
*Xhc
,
3476 IN UINT8 DeviceSpeed
,
3477 IN USB_CONFIG_DESCRIPTOR
*ConfigDesc
,
3478 IN EFI_USB_DEVICE_REQUEST
*Request
3482 USB_INTERFACE_DESCRIPTOR
*IfDescActive
;
3483 USB_INTERFACE_DESCRIPTOR
*IfDescSet
;
3484 USB_INTERFACE_DESCRIPTOR
*IfDesc
;
3485 USB_ENDPOINT_DESCRIPTOR
*EpDesc
;
3492 EFI_PHYSICAL_ADDRESS PhyAddr
;
3495 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
3496 INPUT_CONTEXT_64
*InputContext
;
3497 DEVICE_CONTEXT_64
*OutputContext
;
3498 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3500 Status
= EFI_SUCCESS
;
3502 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
3503 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
3505 // XHCI 4.6.6 Configure Endpoint
3506 // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
3507 // Context and Add Context flags as follows:
3508 // 1) If an endpoint is not modified by the Alternate Interface setting, then software shall set the Drop
3509 // Context and Add Context flags to '0'.
3511 // Except the interface indicated by Reqeust->Index, no impact to other interfaces.
3512 // So the default Drop Context and Add Context flags can be '0' to cover 1).
3514 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
3515 CopyMem (&InputContext
->Slot
, &OutputContext
->Slot
, sizeof (SLOT_CONTEXT_64
));
3517 ASSERT (ConfigDesc
!= NULL
);
3521 IfDescActive
= NULL
;
3524 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)(ConfigDesc
+ 1);
3525 while ((UINTN
) IfDesc
< ((UINTN
) ConfigDesc
+ ConfigDesc
->TotalLength
)) {
3526 if ((IfDesc
->DescriptorType
== USB_DESC_TYPE_INTERFACE
) && (IfDesc
->Length
>= sizeof (USB_INTERFACE_DESCRIPTOR
))) {
3527 if (IfDesc
->InterfaceNumber
== (UINT8
) Request
->Index
) {
3528 if (IfDesc
->AlternateSetting
== Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
[IfDesc
->InterfaceNumber
]) {
3530 // Find out the active interface descriptor.
3532 IfDescActive
= IfDesc
;
3533 } else if (IfDesc
->AlternateSetting
== (UINT8
) Request
->Value
) {
3535 // Find out the interface descriptor to set.
3541 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
3545 // XHCI 4.6.6 Configure Endpoint
3546 // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
3547 // Context and Add Context flags as follows:
3548 // 2) If an endpoint previously disabled, is enabled by the Alternate Interface setting, then software shall set
3549 // the Drop Context flag to '0' and Add Context flag to '1', and initialize the Input Endpoint Context.
3550 // 3) If an endpoint previously enabled, is disabled by the Alternate Interface setting, then software shall set
3551 // the Drop Context flag to '1' and Add Context flag to '0'.
3552 // 4) If a parameter of an enabled endpoint is modified by an Alternate Interface setting, the Drop Context
3553 // and Add Context flags shall be set to '1'.
3555 // Below codes are to cover 2), 3) and 4).
3558 if ((IfDescActive
!= NULL
) && (IfDescSet
!= NULL
)) {
3559 NumEp
= IfDescActive
->NumEndpoints
;
3560 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*) (IfDescActive
+ 1);
3561 for (EpIndex
= 0; EpIndex
< NumEp
; EpIndex
++) {
3562 while (EpDesc
->DescriptorType
!= USB_DESC_TYPE_ENDPOINT
) {
3563 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
3566 if (EpDesc
->Length
< sizeof (USB_ENDPOINT_DESCRIPTOR
)) {
3567 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
3571 EpAddr
= (UINT8
) (EpDesc
->EndpointAddress
& 0x0F);
3572 Direction
= (UINT8
) ((EpDesc
->EndpointAddress
& 0x80) ? EfiUsbDataIn
: EfiUsbDataOut
);
3574 Dci
= XhcEndpointToDci (EpAddr
, Direction
);
3580 // XHCI 4.3.6 - Setting Alternate Interfaces
3581 // 1) Stop any Running Transfer Rings affected by the Alternate Interface setting.
3583 Status
= XhcStopEndpoint (Xhc
, SlotId
, Dci
);
3584 if (EFI_ERROR (Status
)) {
3588 // XHCI 4.3.6 - Setting Alternate Interfaces
3589 // 2) Free Transfer Rings of all endpoints that will be affected by the Alternate Interface setting.
3591 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1] != NULL
) {
3592 RingSeg
= ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1])->RingSeg0
;
3593 if (RingSeg
!= NULL
) {
3594 UsbHcFreeMem (Xhc
->MemPool
, RingSeg
, sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
);
3596 FreePool (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1]);
3597 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1] = NULL
;
3601 // Set the Drop Context flag to '1'.
3603 InputContext
->InputControlContext
.Dword1
|= (BIT0
<< Dci
);
3605 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
3609 // XHCI 4.3.6 - Setting Alternate Interfaces
3610 // 3) Clear all the Endpoint Context fields of each endpoint that will be disabled by the Alternate
3611 // Interface setting, to '0'.
3613 // The step 3) has been covered by the ZeroMem () to InputContext at the start of the function.
3617 // XHCI 4.3.6 - Setting Alternate Interfaces
3618 // 4) For each endpoint enabled by the Configure Endpoint Command:
3619 // a. Allocate a Transfer Ring.
3620 // b. Initialize the Transfer Ring Segment(s) by clearing all fields of all TRBs to '0'.
3621 // c. Initialize the Endpoint Context data structure.
3623 Dci
= XhcInitializeEndpointContext64 (Xhc
, SlotId
, DeviceSpeed
, InputContext
, IfDescSet
);
3628 InputContext
->InputControlContext
.Dword2
|= BIT0
;
3629 InputContext
->Slot
.ContextEntries
= MaxDci
;
3631 // XHCI 4.3.6 - Setting Alternate Interfaces
3632 // 5) Issue and successfully complete a Configure Endpoint Command.
3634 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
3635 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT_64
));
3636 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3637 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3638 CmdTrbCfgEP
.CycleBit
= 1;
3639 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
3640 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3641 DEBUG ((EFI_D_INFO
, "SetInterface64: Configure Endpoint\n"));
3642 Status
= XhcCmdTransfer (
3644 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
3645 XHC_GENERIC_TIMEOUT
,
3646 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3648 if (EFI_ERROR (Status
)) {
3649 DEBUG ((EFI_D_ERROR
, "SetInterface64: Config Endpoint Failed, Status = %r\n", Status
));
3652 // Update the active AlternateSetting.
3654 Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
[(UINT8
) Request
->Index
] = (UINT8
) Request
->Value
;
3662 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
3664 @param Xhc The XHCI Instance.
3665 @param SlotId The slot id to be evaluated.
3666 @param MaxPacketSize The max packet size supported by the device control transfer.
3668 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
3673 XhcEvaluateContext (
3674 IN USB_XHCI_INSTANCE
*Xhc
,
3676 IN UINT32 MaxPacketSize
3680 CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu
;
3681 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3682 INPUT_CONTEXT
*InputContext
;
3683 EFI_PHYSICAL_ADDRESS PhyAddr
;
3685 ASSERT (Xhc
->UsbDevContext
[SlotId
].SlotId
!= 0);
3688 // 4.6.7 Evaluate Context
3690 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
3691 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
3693 InputContext
->InputControlContext
.Dword2
|= BIT1
;
3694 InputContext
->EP
[0].MaxPacketSize
= MaxPacketSize
;
3696 ZeroMem (&CmdTrbEvalu
, sizeof (CmdTrbEvalu
));
3697 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT
));
3698 CmdTrbEvalu
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3699 CmdTrbEvalu
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3700 CmdTrbEvalu
.CycleBit
= 1;
3701 CmdTrbEvalu
.Type
= TRB_TYPE_EVALU_CONTXT
;
3702 CmdTrbEvalu
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3703 DEBUG ((EFI_D_INFO
, "Evaluate context\n"));
3704 Status
= XhcCmdTransfer (
3706 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbEvalu
,
3707 XHC_GENERIC_TIMEOUT
,
3708 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3710 if (EFI_ERROR (Status
)) {
3711 DEBUG ((EFI_D_ERROR
, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status
));
3717 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
3719 @param Xhc The XHCI Instance.
3720 @param SlotId The slot id to be evaluated.
3721 @param MaxPacketSize The max packet size supported by the device control transfer.
3723 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
3728 XhcEvaluateContext64 (
3729 IN USB_XHCI_INSTANCE
*Xhc
,
3731 IN UINT32 MaxPacketSize
3735 CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu
;
3736 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3737 INPUT_CONTEXT_64
*InputContext
;
3738 EFI_PHYSICAL_ADDRESS PhyAddr
;
3740 ASSERT (Xhc
->UsbDevContext
[SlotId
].SlotId
!= 0);
3743 // 4.6.7 Evaluate Context
3745 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
3746 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
3748 InputContext
->InputControlContext
.Dword2
|= BIT1
;
3749 InputContext
->EP
[0].MaxPacketSize
= MaxPacketSize
;
3751 ZeroMem (&CmdTrbEvalu
, sizeof (CmdTrbEvalu
));
3752 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT_64
));
3753 CmdTrbEvalu
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3754 CmdTrbEvalu
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3755 CmdTrbEvalu
.CycleBit
= 1;
3756 CmdTrbEvalu
.Type
= TRB_TYPE_EVALU_CONTXT
;
3757 CmdTrbEvalu
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3758 DEBUG ((EFI_D_INFO
, "Evaluate context\n"));
3759 Status
= XhcCmdTransfer (
3761 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbEvalu
,
3762 XHC_GENERIC_TIMEOUT
,
3763 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3765 if (EFI_ERROR (Status
)) {
3766 DEBUG ((EFI_D_ERROR
, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status
));
3773 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
3775 @param Xhc The XHCI Instance.
3776 @param SlotId The slot id to be configured.
3777 @param PortNum The total number of downstream port supported by the hub.
3778 @param TTT The TT think time of the hub device.
3779 @param MTT The multi-TT of the hub device.
3781 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
3785 XhcConfigHubContext (
3786 IN USB_XHCI_INSTANCE
*Xhc
,
3794 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3795 INPUT_CONTEXT
*InputContext
;
3796 DEVICE_CONTEXT
*OutputContext
;
3797 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
3798 EFI_PHYSICAL_ADDRESS PhyAddr
;
3800 ASSERT (Xhc
->UsbDevContext
[SlotId
].SlotId
!= 0);
3801 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
3802 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
3805 // 4.6.7 Evaluate Context
3807 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
3809 InputContext
->InputControlContext
.Dword2
|= BIT0
;
3812 // Copy the slot context from OutputContext to Input context
3814 CopyMem(&(InputContext
->Slot
), &(OutputContext
->Slot
), sizeof (SLOT_CONTEXT
));
3815 InputContext
->Slot
.Hub
= 1;
3816 InputContext
->Slot
.PortNum
= PortNum
;
3817 InputContext
->Slot
.TTT
= TTT
;
3818 InputContext
->Slot
.MTT
= MTT
;
3820 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
3821 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT
));
3822 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3823 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3824 CmdTrbCfgEP
.CycleBit
= 1;
3825 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
3826 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3827 DEBUG ((EFI_D_INFO
, "Configure Hub Slot Context\n"));
3828 Status
= XhcCmdTransfer (
3830 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
3831 XHC_GENERIC_TIMEOUT
,
3832 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3834 if (EFI_ERROR (Status
)) {
3835 DEBUG ((EFI_D_ERROR
, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status
));
3841 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
3843 @param Xhc The XHCI Instance.
3844 @param SlotId The slot id to be configured.
3845 @param PortNum The total number of downstream port supported by the hub.
3846 @param TTT The TT think time of the hub device.
3847 @param MTT The multi-TT of the hub device.
3849 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
3853 XhcConfigHubContext64 (
3854 IN USB_XHCI_INSTANCE
*Xhc
,
3862 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3863 INPUT_CONTEXT_64
*InputContext
;
3864 DEVICE_CONTEXT_64
*OutputContext
;
3865 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
3866 EFI_PHYSICAL_ADDRESS PhyAddr
;
3868 ASSERT (Xhc
->UsbDevContext
[SlotId
].SlotId
!= 0);
3869 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
3870 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
3873 // 4.6.7 Evaluate Context
3875 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
3877 InputContext
->InputControlContext
.Dword2
|= BIT0
;
3880 // Copy the slot context from OutputContext to Input context
3882 CopyMem(&(InputContext
->Slot
), &(OutputContext
->Slot
), sizeof (SLOT_CONTEXT_64
));
3883 InputContext
->Slot
.Hub
= 1;
3884 InputContext
->Slot
.PortNum
= PortNum
;
3885 InputContext
->Slot
.TTT
= TTT
;
3886 InputContext
->Slot
.MTT
= MTT
;
3888 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
3889 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT_64
));
3890 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3891 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3892 CmdTrbCfgEP
.CycleBit
= 1;
3893 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
3894 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3895 DEBUG ((EFI_D_INFO
, "Configure Hub Slot Context\n"));
3896 Status
= XhcCmdTransfer (
3898 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
3899 XHC_GENERIC_TIMEOUT
,
3900 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3902 if (EFI_ERROR (Status
)) {
3903 DEBUG ((EFI_D_ERROR
, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status
));