3 XHCI transfer scheduling routines.
5 Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 Create a command transfer TRB to support XHCI command interfaces.
21 @param Xhc The XHCI Instance.
22 @param CmdTrb The cmd TRB to be executed.
24 @return Created URB or NULL.
29 IN USB_XHCI_INSTANCE
*Xhc
,
30 IN TRB_TEMPLATE
*CmdTrb
35 Urb
= AllocateZeroPool (sizeof (URB
));
40 Urb
->Signature
= XHC_URB_SIG
;
42 Urb
->Ring
= &Xhc
->CmdRing
;
43 XhcSyncTrsRing (Xhc
, Urb
->Ring
);
45 Urb
->TrbStart
= Urb
->Ring
->RingEnqueue
;
46 CopyMem (Urb
->TrbStart
, CmdTrb
, sizeof (TRB_TEMPLATE
));
47 Urb
->TrbStart
->CycleBit
= Urb
->Ring
->RingPCS
& BIT0
;
48 Urb
->TrbEnd
= Urb
->TrbStart
;
54 Execute a XHCI cmd TRB pointed by CmdTrb.
56 @param Xhc The XHCI Instance.
57 @param CmdTrb The cmd TRB to be executed.
58 @param Timeout Indicates the maximum time, in millisecond, which the
59 transfer is allowed to complete.
60 @param EvtTrb The event TRB corresponding to the cmd TRB.
62 @retval EFI_SUCCESS The transfer was completed successfully.
63 @retval EFI_INVALID_PARAMETER Some parameters are invalid.
64 @retval EFI_TIMEOUT The transfer failed due to timeout.
65 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
71 IN USB_XHCI_INSTANCE
*Xhc
,
72 IN TRB_TEMPLATE
*CmdTrb
,
74 OUT TRB_TEMPLATE
**EvtTrb
81 // Validate the parameters
83 if ((Xhc
== NULL
) || (CmdTrb
== NULL
)) {
84 return EFI_INVALID_PARAMETER
;
87 Status
= EFI_DEVICE_ERROR
;
89 if (XhcIsHalt (Xhc
) || XhcIsSysError (Xhc
)) {
90 DEBUG ((EFI_D_ERROR
, "XhcCmdTransfer: HC is halted\n"));
95 // Create a new URB, then poll the execution status.
97 Urb
= XhcCreateCmdTrb (Xhc
, CmdTrb
);
100 DEBUG ((EFI_D_ERROR
, "XhcCmdTransfer: failed to create URB\n"));
101 Status
= EFI_OUT_OF_RESOURCES
;
105 Status
= XhcExecTransfer (Xhc
, TRUE
, Urb
, Timeout
);
106 *EvtTrb
= Urb
->EvtTrb
;
108 if (Urb
->Result
== EFI_USB_NOERROR
) {
109 Status
= EFI_SUCCESS
;
112 XhcFreeUrb (Xhc
, Urb
);
119 Create a new URB for a new transaction.
121 @param Xhc The XHCI Instance
122 @param BusAddr The logical device address assigned by UsbBus driver
123 @param EpAddr Endpoint addrress
124 @param DevSpeed The device speed
125 @param MaxPacket The max packet length of the endpoint
126 @param Type The transaction type
127 @param Request The standard USB request for control transfer
128 @param Data The user data to transfer
129 @param DataLen The length of data buffer
130 @param Callback The function to call when data is transferred
131 @param Context The context to the callback
133 @return Created URB or NULL
138 IN USB_XHCI_INSTANCE
*Xhc
,
144 IN EFI_USB_DEVICE_REQUEST
*Request
,
147 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback
,
155 Urb
= AllocateZeroPool (sizeof (URB
));
160 Urb
->Signature
= XHC_URB_SIG
;
161 InitializeListHead (&Urb
->UrbList
);
164 Ep
->BusAddr
= BusAddr
;
165 Ep
->EpAddr
= (UINT8
)(EpAddr
& 0x0F);
166 Ep
->Direction
= ((EpAddr
& 0x80) != 0) ? EfiUsbDataIn
: EfiUsbDataOut
;
167 Ep
->DevSpeed
= DevSpeed
;
168 Ep
->MaxPacket
= MaxPacket
;
171 Urb
->Request
= Request
;
173 Urb
->DataLen
= DataLen
;
174 Urb
->Callback
= Callback
;
175 Urb
->Context
= Context
;
177 Status
= XhcCreateTransferTrb (Xhc
, Urb
);
178 ASSERT_EFI_ERROR (Status
);
179 if (EFI_ERROR (Status
)) {
180 DEBUG ((EFI_D_ERROR
, "XhcCreateUrb: XhcCreateTransferTrb Failed, Status = %r\n", Status
));
189 Free an allocated URB.
191 @param Xhc The XHCI device.
192 @param Urb The URB to free.
197 IN USB_XHCI_INSTANCE
*Xhc
,
201 if ((Xhc
== NULL
) || (Urb
== NULL
)) {
205 if (Urb
->DataMap
!= NULL
) {
206 Xhc
->PciIo
->Unmap (Xhc
->PciIo
, Urb
->DataMap
);
213 Create a transfer TRB.
215 @param Xhc The XHCI Instance
216 @param Urb The urb used to construct the transfer TRB.
218 @return Created TRB or NULL
222 XhcCreateTransferTrb (
223 IN USB_XHCI_INSTANCE
*Xhc
,
228 TRANSFER_RING
*EPRing
;
236 EFI_PCI_IO_PROTOCOL_OPERATION MapOp
;
237 EFI_PHYSICAL_ADDRESS PhyAddr
;
241 SlotId
= XhcBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
243 return EFI_DEVICE_ERROR
;
246 Urb
->Finished
= FALSE
;
247 Urb
->StartDone
= FALSE
;
248 Urb
->EndDone
= FALSE
;
250 Urb
->Result
= EFI_USB_NOERROR
;
252 Dci
= XhcEndpointToDci (Urb
->Ep
.EpAddr
, (UINT8
)(Urb
->Ep
.Direction
));
254 EPRing
= (TRANSFER_RING
*)(UINTN
) Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1];
256 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
257 if (Xhc
->HcCParams
.Data
.Csz
== 0) {
258 EPType
= (UINT8
) ((DEVICE_CONTEXT
*)OutputContext
)->EP
[Dci
-1].EPType
;
260 EPType
= (UINT8
) ((DEVICE_CONTEXT_64
*)OutputContext
)->EP
[Dci
-1].EPType
;
263 if (Urb
->Data
!= NULL
) {
264 if (((UINT8
) (Urb
->Ep
.Direction
)) == EfiUsbDataIn
) {
265 MapOp
= EfiPciIoOperationBusMasterWrite
;
267 MapOp
= EfiPciIoOperationBusMasterRead
;
271 Status
= Xhc
->PciIo
->Map (Xhc
->PciIo
, MapOp
, Urb
->Data
, &Len
, &PhyAddr
, &Map
);
273 if (EFI_ERROR (Status
) || (Len
!= Urb
->DataLen
)) {
274 DEBUG ((EFI_D_ERROR
, "XhcCreateTransferTrb: Fail to map Urb->Data.\n"));
275 return EFI_OUT_OF_RESOURCES
;
278 Urb
->DataPhy
= (VOID
*) ((UINTN
) PhyAddr
);
285 XhcSyncTrsRing (Xhc
, EPRing
);
286 Urb
->TrbStart
= EPRing
->RingEnqueue
;
288 case ED_CONTROL_BIDIR
:
290 // For control transfer, create SETUP_STAGE_TRB first.
292 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
293 TrbStart
->TrbCtrSetup
.bmRequestType
= Urb
->Request
->RequestType
;
294 TrbStart
->TrbCtrSetup
.bRequest
= Urb
->Request
->Request
;
295 TrbStart
->TrbCtrSetup
.wValue
= Urb
->Request
->Value
;
296 TrbStart
->TrbCtrSetup
.wIndex
= Urb
->Request
->Index
;
297 TrbStart
->TrbCtrSetup
.wLength
= Urb
->Request
->Length
;
298 TrbStart
->TrbCtrSetup
.Length
= 8;
299 TrbStart
->TrbCtrSetup
.IntTarget
= 0;
300 TrbStart
->TrbCtrSetup
.IOC
= 1;
301 TrbStart
->TrbCtrSetup
.IDT
= 1;
302 TrbStart
->TrbCtrSetup
.Type
= TRB_TYPE_SETUP_STAGE
;
303 if (Urb
->Ep
.Direction
== EfiUsbDataIn
) {
304 TrbStart
->TrbCtrSetup
.TRT
= 3;
305 } else if (Urb
->Ep
.Direction
== EfiUsbDataOut
) {
306 TrbStart
->TrbCtrSetup
.TRT
= 2;
308 TrbStart
->TrbCtrSetup
.TRT
= 0;
311 // Update the cycle bit
313 TrbStart
->TrbCtrSetup
.CycleBit
= EPRing
->RingPCS
& BIT0
;
317 // For control transfer, create DATA_STAGE_TRB.
319 if (Urb
->DataLen
> 0) {
320 XhcSyncTrsRing (Xhc
, EPRing
);
321 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
322 TrbStart
->TrbCtrData
.TRBPtrLo
= XHC_LOW_32BIT(Urb
->DataPhy
);
323 TrbStart
->TrbCtrData
.TRBPtrHi
= XHC_HIGH_32BIT(Urb
->DataPhy
);
324 TrbStart
->TrbCtrData
.Length
= (UINT32
) Urb
->DataLen
;
325 TrbStart
->TrbCtrData
.TDSize
= 0;
326 TrbStart
->TrbCtrData
.IntTarget
= 0;
327 TrbStart
->TrbCtrData
.ISP
= 1;
328 TrbStart
->TrbCtrData
.IOC
= 1;
329 TrbStart
->TrbCtrData
.IDT
= 0;
330 TrbStart
->TrbCtrData
.CH
= 0;
331 TrbStart
->TrbCtrData
.Type
= TRB_TYPE_DATA_STAGE
;
332 if (Urb
->Ep
.Direction
== EfiUsbDataIn
) {
333 TrbStart
->TrbCtrData
.DIR = 1;
334 } else if (Urb
->Ep
.Direction
== EfiUsbDataOut
) {
335 TrbStart
->TrbCtrData
.DIR = 0;
337 TrbStart
->TrbCtrData
.DIR = 0;
340 // Update the cycle bit
342 TrbStart
->TrbCtrData
.CycleBit
= EPRing
->RingPCS
& BIT0
;
346 // For control transfer, create STATUS_STAGE_TRB.
347 // Get the pointer to next TRB for status stage use
349 XhcSyncTrsRing (Xhc
, EPRing
);
350 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
351 TrbStart
->TrbCtrStatus
.IntTarget
= 0;
352 TrbStart
->TrbCtrStatus
.IOC
= 1;
353 TrbStart
->TrbCtrStatus
.CH
= 0;
354 TrbStart
->TrbCtrStatus
.Type
= TRB_TYPE_STATUS_STAGE
;
355 if (Urb
->Ep
.Direction
== EfiUsbDataIn
) {
356 TrbStart
->TrbCtrStatus
.DIR = 0;
357 } else if (Urb
->Ep
.Direction
== EfiUsbDataOut
) {
358 TrbStart
->TrbCtrStatus
.DIR = 1;
360 TrbStart
->TrbCtrStatus
.DIR = 0;
363 // Update the cycle bit
365 TrbStart
->TrbCtrStatus
.CycleBit
= EPRing
->RingPCS
& BIT0
;
367 // Update the enqueue pointer
369 XhcSyncTrsRing (Xhc
, EPRing
);
371 Urb
->TrbEnd
= (TRB_TEMPLATE
*)(UINTN
)TrbStart
;
380 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
381 while (TotalLen
< Urb
->DataLen
) {
382 if ((TotalLen
+ 0x10000) >= Urb
->DataLen
) {
383 Len
= Urb
->DataLen
- TotalLen
;
387 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
388 TrbStart
->TrbNormal
.TRBPtrLo
= XHC_LOW_32BIT((UINT8
*) Urb
->DataPhy
+ TotalLen
);
389 TrbStart
->TrbNormal
.TRBPtrHi
= XHC_HIGH_32BIT((UINT8
*) Urb
->DataPhy
+ TotalLen
);
390 TrbStart
->TrbNormal
.Length
= (UINT32
) Len
;
391 TrbStart
->TrbNormal
.TDSize
= 0;
392 TrbStart
->TrbNormal
.IntTarget
= 0;
393 TrbStart
->TrbNormal
.ISP
= 1;
394 TrbStart
->TrbNormal
.IOC
= 1;
395 TrbStart
->TrbNormal
.Type
= TRB_TYPE_NORMAL
;
397 // Update the cycle bit
399 TrbStart
->TrbNormal
.CycleBit
= EPRing
->RingPCS
& BIT0
;
401 XhcSyncTrsRing (Xhc
, EPRing
);
406 Urb
->TrbNum
= TrbNum
;
407 Urb
->TrbEnd
= (TRB_TEMPLATE
*)(UINTN
)TrbStart
;
410 case ED_INTERRUPT_OUT
:
411 case ED_INTERRUPT_IN
:
415 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
416 while (TotalLen
< Urb
->DataLen
) {
417 if ((TotalLen
+ 0x10000) >= Urb
->DataLen
) {
418 Len
= Urb
->DataLen
- TotalLen
;
422 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
423 TrbStart
->TrbNormal
.TRBPtrLo
= XHC_LOW_32BIT((UINT8
*) Urb
->DataPhy
+ TotalLen
);
424 TrbStart
->TrbNormal
.TRBPtrHi
= XHC_HIGH_32BIT((UINT8
*) Urb
->DataPhy
+ TotalLen
);
425 TrbStart
->TrbNormal
.Length
= (UINT32
) Len
;
426 TrbStart
->TrbNormal
.TDSize
= 0;
427 TrbStart
->TrbNormal
.IntTarget
= 0;
428 TrbStart
->TrbNormal
.ISP
= 1;
429 TrbStart
->TrbNormal
.IOC
= 1;
430 TrbStart
->TrbNormal
.Type
= TRB_TYPE_NORMAL
;
432 // Update the cycle bit
434 TrbStart
->TrbNormal
.CycleBit
= EPRing
->RingPCS
& BIT0
;
436 XhcSyncTrsRing (Xhc
, EPRing
);
441 Urb
->TrbNum
= TrbNum
;
442 Urb
->TrbEnd
= (TRB_TEMPLATE
*)(UINTN
)TrbStart
;
446 DEBUG ((EFI_D_INFO
, "Not supported EPType 0x%x!\n",EPType
));
456 Initialize the XHCI host controller for schedule.
458 @param Xhc The XHCI Instance to be initialized.
463 IN USB_XHCI_INSTANCE
*Xhc
467 EFI_PHYSICAL_ADDRESS DcbaaPhy
;
469 EFI_PHYSICAL_ADDRESS CmdRingPhy
;
471 UINT32 MaxScratchpadBufs
;
473 EFI_PHYSICAL_ADDRESS ScratchPhy
;
474 UINT64
*ScratchEntry
;
475 EFI_PHYSICAL_ADDRESS ScratchEntryPhy
;
477 UINTN
*ScratchEntryMap
;
481 // Initialize memory management.
483 Xhc
->MemPool
= UsbHcInitMemPool (Xhc
->PciIo
);
484 ASSERT (Xhc
->MemPool
!= NULL
);
487 // Program the Max Device Slots Enabled (MaxSlotsEn) field in the CONFIG register (5.4.7)
488 // to enable the device slots that system software is going to use.
490 Xhc
->MaxSlotsEn
= Xhc
->HcSParams1
.Data
.MaxSlots
;
491 ASSERT (Xhc
->MaxSlotsEn
>= 1 && Xhc
->MaxSlotsEn
<= 255);
492 XhcWriteOpReg (Xhc
, XHC_CONFIG_OFFSET
, Xhc
->MaxSlotsEn
);
495 // The Device Context Base Address Array entry associated with each allocated Device Slot
496 // shall contain a 64-bit pointer to the base of the associated Device Context.
497 // The Device Context Base Address Array shall contain MaxSlotsEn + 1 entries.
498 // Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.
500 Entries
= (Xhc
->MaxSlotsEn
+ 1) * sizeof(UINT64
);
501 Dcbaa
= UsbHcAllocateMem (Xhc
->MemPool
, Entries
);
502 ASSERT (Dcbaa
!= NULL
);
503 ZeroMem (Dcbaa
, Entries
);
506 // A Scratchpad Buffer is a PAGESIZE block of system memory located on a PAGESIZE boundary.
507 // System software shall allocate the Scratchpad Buffer(s) before placing the xHC in to Run
508 // mode (Run/Stop(R/S) ='1').
510 MaxScratchpadBufs
= ((Xhc
->HcSParams2
.Data
.ScratchBufHi
) << 5) | (Xhc
->HcSParams2
.Data
.ScratchBufLo
);
511 Xhc
->MaxScratchpadBufs
= MaxScratchpadBufs
;
512 ASSERT (MaxScratchpadBufs
<= 1023);
513 if (MaxScratchpadBufs
!= 0) {
515 // Allocate the buffer to record the Mapping for each scratch buffer in order to Unmap them
517 ScratchEntryMap
= AllocateZeroPool (sizeof (UINTN
) * MaxScratchpadBufs
);
518 ASSERT (ScratchEntryMap
!= NULL
);
519 Xhc
->ScratchEntryMap
= ScratchEntryMap
;
522 // Allocate the buffer to record the host address for each entry
524 ScratchEntry
= AllocateZeroPool (sizeof (UINT64
) * MaxScratchpadBufs
);
525 ASSERT (ScratchEntry
!= NULL
);
526 Xhc
->ScratchEntry
= ScratchEntry
;
529 Status
= UsbHcAllocateAlignedPages (
531 EFI_SIZE_TO_PAGES (MaxScratchpadBufs
* sizeof (UINT64
)),
533 (VOID
**) &ScratchBuf
,
537 ASSERT_EFI_ERROR (Status
);
539 ZeroMem (ScratchBuf
, MaxScratchpadBufs
* sizeof (UINT64
));
540 Xhc
->ScratchBuf
= ScratchBuf
;
543 // Allocate each scratch buffer
545 for (Index
= 0; Index
< MaxScratchpadBufs
; Index
++) {
547 Status
= UsbHcAllocateAlignedPages (
549 EFI_SIZE_TO_PAGES (Xhc
->PageSize
),
551 (VOID
**) &ScratchEntry
[Index
],
553 (VOID
**) &ScratchEntryMap
[Index
]
555 ASSERT_EFI_ERROR (Status
);
556 ZeroMem ((VOID
*)(UINTN
)ScratchEntry
[Index
], Xhc
->PageSize
);
558 // Fill with the PCI device address
560 *ScratchBuf
++ = ScratchEntryPhy
;
563 // The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the
564 // Device Context Base Address Array points to the Scratchpad Buffer Array.
566 *(UINT64
*)Dcbaa
= (UINT64
)(UINTN
) ScratchPhy
;
570 // Program the Device Context Base Address Array Pointer (DCBAAP) register (5.4.6) with
571 // a 64-bit address pointing to where the Device Context Base Address Array is located.
573 Xhc
->DCBAA
= (UINT64
*)(UINTN
)Dcbaa
;
575 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
576 // So divide it to two 32-bytes width register access.
578 DcbaaPhy
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Dcbaa
, Entries
);
579 XhcWriteOpReg (Xhc
, XHC_DCBAAP_OFFSET
, XHC_LOW_32BIT(DcbaaPhy
));
580 XhcWriteOpReg (Xhc
, XHC_DCBAAP_OFFSET
+ 4, XHC_HIGH_32BIT (DcbaaPhy
));
582 DEBUG ((EFI_D_INFO
, "XhcInitSched:DCBAA=0x%x\n", (UINT64
)(UINTN
)Xhc
->DCBAA
));
585 // Define the Command Ring Dequeue Pointer by programming the Command Ring Control Register
586 // (5.4.5) with a 64-bit address pointing to the starting address of the first TRB of the Command Ring.
587 // Note: The Command Ring is 64 byte aligned, so the low order 6 bits of the Command Ring Pointer shall
590 CreateTransferRing (Xhc
, CMD_RING_TRB_NUMBER
, &Xhc
->CmdRing
);
592 // The xHC uses the Enqueue Pointer to determine when a Transfer Ring is empty. As it fetches TRBs from a
593 // Transfer Ring it checks for a Cycle bit transition. If a transition detected, the ring is empty.
594 // So we set RCS as inverted PCS init value to let Command Ring empty
596 CmdRing
= (UINT64
)(UINTN
)Xhc
->CmdRing
.RingSeg0
;
597 CmdRingPhy
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, (VOID
*)(UINTN
) CmdRing
, sizeof (TRB_TEMPLATE
) * CMD_RING_TRB_NUMBER
);
598 ASSERT ((CmdRingPhy
& 0x3F) == 0);
599 CmdRingPhy
|= XHC_CRCR_RCS
;
601 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
602 // So divide it to two 32-bytes width register access.
604 XhcWriteOpReg (Xhc
, XHC_CRCR_OFFSET
, XHC_LOW_32BIT(CmdRingPhy
));
605 XhcWriteOpReg (Xhc
, XHC_CRCR_OFFSET
+ 4, XHC_HIGH_32BIT (CmdRingPhy
));
607 DEBUG ((EFI_D_INFO
, "XhcInitSched:XHC_CRCR=0x%x\n", Xhc
->CmdRing
.RingSeg0
));
610 // Disable the 'interrupter enable' bit in USB_CMD
611 // and clear IE & IP bit in all Interrupter X Management Registers.
613 XhcClearOpRegBit (Xhc
, XHC_USBCMD_OFFSET
, XHC_USBCMD_INTE
);
614 for (Index
= 0; Index
< (UINT16
)(Xhc
->HcSParams1
.Data
.MaxIntrs
); Index
++) {
615 XhcClearRuntimeRegBit (Xhc
, XHC_IMAN_OFFSET
+ (Index
* 32), XHC_IMAN_IE
);
616 XhcSetRuntimeRegBit (Xhc
, XHC_IMAN_OFFSET
+ (Index
* 32), XHC_IMAN_IP
);
620 // Allocate EventRing for Cmd, Ctrl, Bulk, Interrupt, AsynInterrupt transfer
622 CreateEventRing (Xhc
, &Xhc
->EventRing
);
623 DEBUG ((EFI_D_INFO
, "XhcInitSched:XHC_EVENTRING=0x%x\n", Xhc
->EventRing
.EventRingSeg0
));
627 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted
628 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint
629 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is
630 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the
631 Stopped to the Running state.
633 @param Xhc The XHCI Instance.
634 @param Urb The urb which makes the endpoint halted.
636 @retval EFI_SUCCESS The recovery is successful.
637 @retval Others Failed to recovery halted endpoint.
642 XhcRecoverHaltedEndpoint (
643 IN USB_XHCI_INSTANCE
*Xhc
,
648 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
649 CMD_TRB_RESET_ENDPOINT CmdTrbResetED
;
650 CMD_SET_TR_DEQ_POINTER CmdSetTRDeq
;
653 EFI_PHYSICAL_ADDRESS PhyAddr
;
655 Status
= EFI_SUCCESS
;
656 SlotId
= XhcBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
658 return EFI_DEVICE_ERROR
;
660 Dci
= XhcEndpointToDci (Urb
->Ep
.EpAddr
, (UINT8
)(Urb
->Ep
.Direction
));
663 DEBUG ((EFI_D_INFO
, "Recovery Halted Slot = %x,Dci = %x\n", SlotId
, Dci
));
666 // 1) Send Reset endpoint command to transit from halt to stop state
668 ZeroMem (&CmdTrbResetED
, sizeof (CmdTrbResetED
));
669 CmdTrbResetED
.CycleBit
= 1;
670 CmdTrbResetED
.Type
= TRB_TYPE_RESET_ENDPOINT
;
671 CmdTrbResetED
.EDID
= Dci
;
672 CmdTrbResetED
.SlotId
= SlotId
;
673 Status
= XhcCmdTransfer (
675 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbResetED
,
677 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
679 if (EFI_ERROR(Status
)) {
680 DEBUG ((EFI_D_ERROR
, "XhcRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status
));
685 // 2)Set dequeue pointer
687 ZeroMem (&CmdSetTRDeq
, sizeof (CmdSetTRDeq
));
688 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Urb
->Ring
->RingEnqueue
, sizeof (CMD_SET_TR_DEQ_POINTER
));
689 CmdSetTRDeq
.PtrLo
= XHC_LOW_32BIT (PhyAddr
) | Urb
->Ring
->RingPCS
;
690 CmdSetTRDeq
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
691 CmdSetTRDeq
.CycleBit
= 1;
692 CmdSetTRDeq
.Type
= TRB_TYPE_SET_TR_DEQUE
;
693 CmdSetTRDeq
.Endpoint
= Dci
;
694 CmdSetTRDeq
.SlotId
= SlotId
;
695 Status
= XhcCmdTransfer (
697 (TRB_TEMPLATE
*) (UINTN
) &CmdSetTRDeq
,
699 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
701 if (EFI_ERROR(Status
)) {
702 DEBUG ((EFI_D_ERROR
, "XhcRecoverHaltedEndpoint: Set Dequeue Pointer Failed, Status = %r\n", Status
));
707 // 3)Ring the doorbell to transit from stop to active
709 XhcRingDoorBell (Xhc
, SlotId
, Dci
);
716 Create XHCI event ring.
718 @param Xhc The XHCI Instance.
719 @param EventRing The created event ring.
724 IN USB_XHCI_INSTANCE
*Xhc
,
725 OUT EVENT_RING
*EventRing
729 EVENT_RING_SEG_TABLE_ENTRY
*ERSTBase
;
731 EFI_PHYSICAL_ADDRESS ERSTPhy
;
732 EFI_PHYSICAL_ADDRESS DequeuePhy
;
734 ASSERT (EventRing
!= NULL
);
736 Size
= sizeof (TRB_TEMPLATE
) * EVENT_RING_TRB_NUMBER
;
737 Buf
= UsbHcAllocateMem (Xhc
->MemPool
, Size
);
738 ASSERT (Buf
!= NULL
);
739 ASSERT (((UINTN
) Buf
& 0x3F) == 0);
742 EventRing
->EventRingSeg0
= Buf
;
743 EventRing
->TrbNumber
= EVENT_RING_TRB_NUMBER
;
744 EventRing
->EventRingDequeue
= (TRB_TEMPLATE
*) EventRing
->EventRingSeg0
;
745 EventRing
->EventRingEnqueue
= (TRB_TEMPLATE
*) EventRing
->EventRingSeg0
;
747 DequeuePhy
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Buf
, Size
);
750 // Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'
751 // and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.
753 EventRing
->EventRingCCS
= 1;
755 Size
= sizeof (EVENT_RING_SEG_TABLE_ENTRY
) * ERST_NUMBER
;
756 Buf
= UsbHcAllocateMem (Xhc
->MemPool
, Size
);
757 ASSERT (Buf
!= NULL
);
758 ASSERT (((UINTN
) Buf
& 0x3F) == 0);
761 ERSTBase
= (EVENT_RING_SEG_TABLE_ENTRY
*) Buf
;
762 EventRing
->ERSTBase
= ERSTBase
;
763 ERSTBase
->PtrLo
= XHC_LOW_32BIT (DequeuePhy
);
764 ERSTBase
->PtrHi
= XHC_HIGH_32BIT (DequeuePhy
);
765 ERSTBase
->RingTrbSize
= EVENT_RING_TRB_NUMBER
;
767 ERSTPhy
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, ERSTBase
, Size
);
770 // Program the Interrupter Event Ring Segment Table Size (ERSTSZ) register (5.5.2.3.1)
778 // Program the Interrupter Event Ring Dequeue Pointer (ERDP) register (5.5.2.3.3)
780 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
781 // So divide it to two 32-bytes width register access.
786 XHC_LOW_32BIT((UINT64
)(UINTN
)DequeuePhy
)
791 XHC_HIGH_32BIT((UINT64
)(UINTN
)DequeuePhy
)
794 // Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register(5.5.2.3.2)
796 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
797 // So divide it to two 32-bytes width register access.
802 XHC_LOW_32BIT((UINT64
)(UINTN
)ERSTPhy
)
806 XHC_ERSTBA_OFFSET
+ 4,
807 XHC_HIGH_32BIT((UINT64
)(UINTN
)ERSTPhy
)
810 // Need set IMAN IE bit to enble the ring interrupt
812 XhcSetRuntimeRegBit (Xhc
, XHC_IMAN_OFFSET
, XHC_IMAN_IE
);
816 Create XHCI transfer ring.
818 @param Xhc The XHCI Instance.
819 @param TrbNum The number of TRB in the ring.
820 @param TransferRing The created transfer ring.
825 IN USB_XHCI_INSTANCE
*Xhc
,
827 OUT TRANSFER_RING
*TransferRing
832 EFI_PHYSICAL_ADDRESS PhyAddr
;
834 Buf
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (TRB_TEMPLATE
) * TrbNum
);
835 ASSERT (Buf
!= NULL
);
836 ASSERT (((UINTN
) Buf
& 0x3F) == 0);
837 ZeroMem (Buf
, sizeof (TRB_TEMPLATE
) * TrbNum
);
839 TransferRing
->RingSeg0
= Buf
;
840 TransferRing
->TrbNumber
= TrbNum
;
841 TransferRing
->RingEnqueue
= (TRB_TEMPLATE
*) TransferRing
->RingSeg0
;
842 TransferRing
->RingDequeue
= (TRB_TEMPLATE
*) TransferRing
->RingSeg0
;
843 TransferRing
->RingPCS
= 1;
845 // 4.9.2 Transfer Ring Management
846 // To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to
847 // point to the first TRB in the ring.
849 EndTrb
= (LINK_TRB
*) ((UINTN
)Buf
+ sizeof (TRB_TEMPLATE
) * (TrbNum
- 1));
850 EndTrb
->Type
= TRB_TYPE_LINK
;
851 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Buf
, sizeof (TRB_TEMPLATE
) * TrbNum
);
852 EndTrb
->PtrLo
= XHC_LOW_32BIT (PhyAddr
);
853 EndTrb
->PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
855 // Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
859 // Set Cycle bit as other TRB PCS init value
861 EndTrb
->CycleBit
= 0;
865 Free XHCI event ring.
867 @param Xhc The XHCI Instance.
868 @param EventRing The event ring to be freed.
874 IN USB_XHCI_INSTANCE
*Xhc
,
875 IN EVENT_RING
*EventRing
878 if(EventRing
->EventRingSeg0
== NULL
) {
883 // Free EventRing Segment 0
885 UsbHcFreeMem (Xhc
->MemPool
, EventRing
->EventRingSeg0
, sizeof (TRB_TEMPLATE
) * EVENT_RING_TRB_NUMBER
);
890 UsbHcFreeMem (Xhc
->MemPool
, EventRing
->ERSTBase
, sizeof (EVENT_RING_SEG_TABLE_ENTRY
) * ERST_NUMBER
);
895 Free the resouce allocated at initializing schedule.
897 @param Xhc The XHCI Instance.
902 IN USB_XHCI_INSTANCE
*Xhc
906 UINT64
*ScratchEntry
;
908 if (Xhc
->ScratchBuf
!= NULL
) {
909 ScratchEntry
= Xhc
->ScratchEntry
;
910 for (Index
= 0; Index
< Xhc
->MaxScratchpadBufs
; Index
++) {
912 // Free Scratchpad Buffers
914 UsbHcFreeAlignedPages (Xhc
->PciIo
, (VOID
*)(UINTN
)ScratchEntry
[Index
], EFI_SIZE_TO_PAGES (Xhc
->PageSize
), (VOID
*) Xhc
->ScratchEntryMap
[Index
]);
917 // Free Scratchpad Buffer Array
919 UsbHcFreeAlignedPages (Xhc
->PciIo
, Xhc
->ScratchBuf
, EFI_SIZE_TO_PAGES (Xhc
->MaxScratchpadBufs
* sizeof (UINT64
)), Xhc
->ScratchMap
);
920 FreePool (Xhc
->ScratchEntryMap
);
921 FreePool (Xhc
->ScratchEntry
);
924 if (Xhc
->CmdRing
.RingSeg0
!= NULL
) {
925 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->CmdRing
.RingSeg0
, sizeof (TRB_TEMPLATE
) * CMD_RING_TRB_NUMBER
);
926 Xhc
->CmdRing
.RingSeg0
= NULL
;
929 XhcFreeEventRing (Xhc
,&Xhc
->EventRing
);
931 if (Xhc
->DCBAA
!= NULL
) {
932 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->DCBAA
, (Xhc
->MaxSlotsEn
+ 1) * sizeof(UINT64
));
937 // Free memory pool at last
939 if (Xhc
->MemPool
!= NULL
) {
940 UsbHcFreeMemPool (Xhc
->MemPool
);
946 Check if the Trb is a transaction of the URBs in XHCI's asynchronous transfer list.
948 @param Xhc The XHCI Instance.
949 @param Trb The TRB to be checked.
950 @param Urb The pointer to the matched Urb.
952 @retval TRUE The Trb is matched with a transaction of the URBs in the async list.
953 @retval FALSE The Trb is not matched with any URBs in the async list.
958 IN USB_XHCI_INSTANCE
*Xhc
,
959 IN TRB_TEMPLATE
*Trb
,
965 TRB_TEMPLATE
*CheckedTrb
;
969 EFI_LIST_FOR_EACH_SAFE (Entry
, Next
, &Xhc
->AsyncIntTransfers
) {
970 CheckedUrb
= EFI_LIST_CONTAINER (Entry
, URB
, UrbList
);
971 CheckedTrb
= CheckedUrb
->TrbStart
;
972 for (Index
= 0; Index
< CheckedUrb
->TrbNum
; Index
++) {
973 if (Trb
== CheckedTrb
) {
978 if ((UINTN
)CheckedTrb
>= ((UINTN
) CheckedUrb
->Ring
->RingSeg0
+ sizeof (TRB_TEMPLATE
) * CheckedUrb
->Ring
->TrbNumber
)) {
979 CheckedTrb
= (TRB_TEMPLATE
*) CheckedUrb
->Ring
->RingSeg0
;
988 Check if the Trb is a transaction of the URB.
990 @param Trb The TRB to be checked
991 @param Urb The transfer ring to be checked.
993 @retval TRUE It is a transaction of the URB.
994 @retval FALSE It is not any transaction of the URB.
999 IN TRB_TEMPLATE
*Trb
,
1003 TRB_TEMPLATE
*CheckedTrb
;
1006 CheckedTrb
= Urb
->Ring
->RingSeg0
;
1008 ASSERT (Urb
->Ring
->TrbNumber
== CMD_RING_TRB_NUMBER
|| Urb
->Ring
->TrbNumber
== TR_RING_TRB_NUMBER
);
1010 for (Index
= 0; Index
< Urb
->Ring
->TrbNumber
; Index
++) {
1011 if (Trb
== CheckedTrb
) {
1021 Check the URB's execution result and update the URB's
1024 @param Xhc The XHCI Instance.
1025 @param Urb The URB to check result.
1027 @return Whether the result of URB transfer is finialized.
1032 IN USB_XHCI_INSTANCE
*Xhc
,
1036 EVT_TRB_TRANSFER
*EvtTrb
;
1037 TRB_TEMPLATE
*TRBPtr
;
1046 EFI_PHYSICAL_ADDRESS PhyAddr
;
1048 ASSERT ((Xhc
!= NULL
) && (Urb
!= NULL
));
1050 Status
= EFI_SUCCESS
;
1053 if (Urb
->Finished
) {
1059 if (XhcIsHalt (Xhc
) || XhcIsSysError (Xhc
)) {
1060 Urb
->Result
|= EFI_USB_ERR_SYSTEM
;
1061 Status
= EFI_DEVICE_ERROR
;
1066 // Traverse the event ring to find out all new events from the previous check.
1068 XhcSyncEventRing (Xhc
, &Xhc
->EventRing
);
1069 for (Index
= 0; Index
< Xhc
->EventRing
.TrbNumber
; Index
++) {
1070 Status
= XhcCheckNewEvent (Xhc
, &Xhc
->EventRing
, ((TRB_TEMPLATE
**)&EvtTrb
));
1071 if (Status
== EFI_NOT_READY
) {
1073 // All new events are handled, return directly.
1079 // Only handle COMMAND_COMPLETETION_EVENT and TRANSFER_EVENT.
1081 if ((EvtTrb
->Type
!= TRB_TYPE_COMMAND_COMPLT_EVENT
) && (EvtTrb
->Type
!= TRB_TYPE_TRANS_EVENT
)) {
1086 // Need convert pci device address to host address
1088 PhyAddr
= (EFI_PHYSICAL_ADDRESS
)(EvtTrb
->TRBPtrLo
| LShiftU64 ((UINT64
) EvtTrb
->TRBPtrHi
, 32));
1089 TRBPtr
= (TRB_TEMPLATE
*)(UINTN
) UsbHcGetHostAddrForPciAddr (Xhc
->MemPool
, (VOID
*)(UINTN
) PhyAddr
, sizeof (TRB_TEMPLATE
));
1092 // Update the status of Urb according to the finished event regardless of whether
1093 // the urb is current checked one or in the XHCI's async transfer list.
1094 // This way is used to avoid that those completed async transfer events don't get
1095 // handled in time and are flushed by newer coming events.
1097 if (IsTransferRingTrb (TRBPtr
, Urb
)) {
1099 } else if (IsAsyncIntTrb (Xhc
, TRBPtr
, &AsyncUrb
)) {
1100 CheckedUrb
= AsyncUrb
;
1105 switch (EvtTrb
->Completecode
) {
1106 case TRB_COMPLETION_STALL_ERROR
:
1107 CheckedUrb
->Result
|= EFI_USB_ERR_STALL
;
1108 CheckedUrb
->Finished
= TRUE
;
1109 DEBUG ((EFI_D_ERROR
, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n",EvtTrb
->Completecode
));
1112 case TRB_COMPLETION_BABBLE_ERROR
:
1113 CheckedUrb
->Result
|= EFI_USB_ERR_BABBLE
;
1114 CheckedUrb
->Finished
= TRUE
;
1115 DEBUG ((EFI_D_ERROR
, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n",EvtTrb
->Completecode
));
1118 case TRB_COMPLETION_DATA_BUFFER_ERROR
:
1119 CheckedUrb
->Result
|= EFI_USB_ERR_BUFFER
;
1120 CheckedUrb
->Finished
= TRUE
;
1121 DEBUG ((EFI_D_ERROR
, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n",EvtTrb
->Completecode
));
1124 case TRB_COMPLETION_USB_TRANSACTION_ERROR
:
1125 CheckedUrb
->Result
|= EFI_USB_ERR_TIMEOUT
;
1126 CheckedUrb
->Finished
= TRUE
;
1127 DEBUG ((EFI_D_ERROR
, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n",EvtTrb
->Completecode
));
1130 case TRB_COMPLETION_SHORT_PACKET
:
1131 case TRB_COMPLETION_SUCCESS
:
1132 if (EvtTrb
->Completecode
== TRB_COMPLETION_SHORT_PACKET
) {
1133 DEBUG ((EFI_D_ERROR
, "XhcCheckUrbResult: short packet happens!\n"));
1136 TRBType
= (UINT8
) (TRBPtr
->Type
);
1137 if ((TRBType
== TRB_TYPE_DATA_STAGE
) ||
1138 (TRBType
== TRB_TYPE_NORMAL
) ||
1139 (TRBType
== TRB_TYPE_ISOCH
)) {
1140 CheckedUrb
->Completed
+= (((TRANSFER_TRB_NORMAL
*)TRBPtr
)->Length
- EvtTrb
->Length
);
1146 DEBUG ((EFI_D_ERROR
, "Transfer Default Error Occur! Completecode = 0x%x!\n",EvtTrb
->Completecode
));
1147 CheckedUrb
->Result
|= EFI_USB_ERR_TIMEOUT
;
1148 CheckedUrb
->Finished
= TRUE
;
1153 // Only check first and end Trb event address
1155 if (TRBPtr
== CheckedUrb
->TrbStart
) {
1156 CheckedUrb
->StartDone
= TRUE
;
1159 if (TRBPtr
== CheckedUrb
->TrbEnd
) {
1160 CheckedUrb
->EndDone
= TRUE
;
1163 if (CheckedUrb
->StartDone
&& CheckedUrb
->EndDone
) {
1164 CheckedUrb
->Finished
= TRUE
;
1165 CheckedUrb
->EvtTrb
= (TRB_TEMPLATE
*)EvtTrb
;
1172 // Advance event ring to last available entry
1174 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
1175 // So divide it to two 32-bytes width register access.
1177 Low
= XhcReadRuntimeReg (Xhc
, XHC_ERDP_OFFSET
);
1178 High
= XhcReadRuntimeReg (Xhc
, XHC_ERDP_OFFSET
+ 4);
1179 XhcDequeue
= (UINT64
)(LShiftU64((UINT64
)High
, 32) | Low
);
1181 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Xhc
->EventRing
.EventRingDequeue
, sizeof (TRB_TEMPLATE
));
1183 if ((XhcDequeue
& (~0x0F)) != (PhyAddr
& (~0x0F))) {
1185 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
1186 // So divide it to two 32-bytes width register access.
1188 XhcWriteRuntimeReg (Xhc
, XHC_ERDP_OFFSET
, XHC_LOW_32BIT (PhyAddr
) | BIT3
);
1189 XhcWriteRuntimeReg (Xhc
, XHC_ERDP_OFFSET
+ 4, XHC_HIGH_32BIT (PhyAddr
));
1197 Execute the transfer by polling the URB. This is a synchronous operation.
1199 @param Xhc The XHCI Instance.
1200 @param CmdTransfer The executed URB is for cmd transfer or not.
1201 @param Urb The URB to execute.
1202 @param Timeout The time to wait before abort, in millisecond.
1204 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
1205 @return EFI_TIMEOUT The transfer failed due to time out.
1206 @return EFI_SUCCESS The transfer finished OK.
1211 IN USB_XHCI_INSTANCE
*Xhc
,
1212 IN BOOLEAN CmdTransfer
,
1227 SlotId
= XhcBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
1229 return EFI_DEVICE_ERROR
;
1231 Dci
= XhcEndpointToDci (Urb
->Ep
.EpAddr
, (UINT8
)(Urb
->Ep
.Direction
));
1235 Status
= EFI_SUCCESS
;
1236 Loop
= Timeout
* XHC_1_MILLISECOND
;
1241 XhcRingDoorBell (Xhc
, SlotId
, Dci
);
1243 for (Index
= 0; Index
< Loop
; Index
++) {
1244 Status
= XhcCheckUrbResult (Xhc
, Urb
);
1245 if (Urb
->Finished
) {
1248 gBS
->Stall (XHC_1_MICROSECOND
);
1251 if (Index
== Loop
) {
1252 Urb
->Result
= EFI_USB_ERR_TIMEOUT
;
1259 Delete a single asynchronous interrupt transfer for
1260 the device and endpoint.
1262 @param Xhc The XHCI Instance.
1263 @param BusAddr The logical device address assigned by UsbBus driver.
1264 @param EpNum The endpoint of the target.
1266 @retval EFI_SUCCESS An asynchronous transfer is removed.
1267 @retval EFI_NOT_FOUND No transfer for the device is found.
1271 XhciDelAsyncIntTransfer (
1272 IN USB_XHCI_INSTANCE
*Xhc
,
1280 EFI_USB_DATA_DIRECTION Direction
;
1282 Direction
= ((EpNum
& 0x80) != 0) ? EfiUsbDataIn
: EfiUsbDataOut
;
1287 EFI_LIST_FOR_EACH_SAFE (Entry
, Next
, &Xhc
->AsyncIntTransfers
) {
1288 Urb
= EFI_LIST_CONTAINER (Entry
, URB
, UrbList
);
1289 if ((Urb
->Ep
.BusAddr
== BusAddr
) &&
1290 (Urb
->Ep
.EpAddr
== EpNum
) &&
1291 (Urb
->Ep
.Direction
== Direction
)) {
1292 RemoveEntryList (&Urb
->UrbList
);
1293 FreePool (Urb
->Data
);
1294 XhcFreeUrb (Xhc
, Urb
);
1299 return EFI_NOT_FOUND
;
1303 Remove all the asynchronous interrutp transfers.
1305 @param Xhc The XHCI Instance.
1309 XhciDelAllAsyncIntTransfers (
1310 IN USB_XHCI_INSTANCE
*Xhc
1317 EFI_LIST_FOR_EACH_SAFE (Entry
, Next
, &Xhc
->AsyncIntTransfers
) {
1318 Urb
= EFI_LIST_CONTAINER (Entry
, URB
, UrbList
);
1319 RemoveEntryList (&Urb
->UrbList
);
1320 FreePool (Urb
->Data
);
1321 XhcFreeUrb (Xhc
, Urb
);
1326 Update the queue head for next round of asynchronous transfer
1328 @param Xhc The XHCI Instance.
1329 @param Urb The URB to update
1333 XhcUpdateAsyncRequest (
1334 IN USB_XHCI_INSTANCE
*Xhc
,
1340 if (Urb
->Result
== EFI_USB_NOERROR
) {
1341 Status
= XhcCreateTransferTrb (Xhc
, Urb
);
1342 if (EFI_ERROR (Status
)) {
1345 Status
= RingIntTransferDoorBell (Xhc
, Urb
);
1346 if (EFI_ERROR (Status
)) {
1353 Flush data from PCI controller specific address to mapped system
1356 @param Xhc The XHCI device.
1357 @param Urb The URB to unmap.
1359 @retval EFI_SUCCESS Success to flush data to mapped system memory.
1360 @retval EFI_DEVICE_ERROR Fail to flush data to mapped system memory.
1364 XhcFlushAsyncIntMap (
1365 IN USB_XHCI_INSTANCE
*Xhc
,
1370 EFI_PHYSICAL_ADDRESS PhyAddr
;
1371 EFI_PCI_IO_PROTOCOL_OPERATION MapOp
;
1372 EFI_PCI_IO_PROTOCOL
*PciIo
;
1379 if (Urb
->Ep
.Direction
== EfiUsbDataIn
) {
1380 MapOp
= EfiPciIoOperationBusMasterWrite
;
1382 MapOp
= EfiPciIoOperationBusMasterRead
;
1385 if (Urb
->DataMap
!= NULL
) {
1386 Status
= PciIo
->Unmap (PciIo
, Urb
->DataMap
);
1387 if (EFI_ERROR (Status
)) {
1392 Urb
->DataMap
= NULL
;
1394 Status
= PciIo
->Map (PciIo
, MapOp
, Urb
->Data
, &Len
, &PhyAddr
, &Map
);
1395 if (EFI_ERROR (Status
) || (Len
!= Urb
->DataLen
)) {
1399 Urb
->DataPhy
= (VOID
*) ((UINTN
) PhyAddr
);
1404 return EFI_DEVICE_ERROR
;
1408 Interrupt transfer periodic check handler.
1410 @param Event Interrupt event.
1411 @param Context Pointer to USB_XHCI_INSTANCE.
1416 XhcMonitorAsyncRequests (
1421 USB_XHCI_INSTANCE
*Xhc
;
1430 OldTpl
= gBS
->RaiseTPL (XHC_TPL
);
1432 Xhc
= (USB_XHCI_INSTANCE
*) Context
;
1434 EFI_LIST_FOR_EACH_SAFE (Entry
, Next
, &Xhc
->AsyncIntTransfers
) {
1435 Urb
= EFI_LIST_CONTAINER (Entry
, URB
, UrbList
);
1438 // Make sure that the device is available before every check.
1440 SlotId
= XhcBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
1446 // Check the result of URB execution. If it is still
1447 // active, check the next one.
1449 XhcCheckUrbResult (Xhc
, Urb
);
1451 if (!Urb
->Finished
) {
1456 // Flush any PCI posted write transactions from a PCI host
1457 // bridge to system memory.
1459 Status
= XhcFlushAsyncIntMap (Xhc
, Urb
);
1460 if (EFI_ERROR (Status
)) {
1461 DEBUG ((EFI_D_ERROR
, "XhcMonitorAsyncRequests: Fail to Flush AsyncInt Mapped Memeory\n"));
1465 // Allocate a buffer then copy the transferred data for user.
1466 // If failed to allocate the buffer, update the URB for next
1467 // round of transfer. Ignore the data of this round.
1470 if (Urb
->Result
== EFI_USB_NOERROR
) {
1471 ASSERT (Urb
->Completed
<= Urb
->DataLen
);
1473 ProcBuf
= AllocateZeroPool (Urb
->Completed
);
1475 if (ProcBuf
== NULL
) {
1476 XhcUpdateAsyncRequest (Xhc
, Urb
);
1480 CopyMem (ProcBuf
, Urb
->Data
, Urb
->Completed
);
1484 // Leave error recovery to its related device driver. A
1485 // common case of the error recovery is to re-submit the
1486 // interrupt transfer which is linked to the head of the
1487 // list. This function scans from head to tail. So the
1488 // re-submitted interrupt transfer's callback function
1489 // will not be called again in this round. Don't touch this
1490 // URB after the callback, it may have been removed by the
1493 if (Urb
->Callback
!= NULL
) {
1495 // Restore the old TPL, USB bus maybe connect device in
1496 // his callback. Some drivers may has a lower TPL restriction.
1498 gBS
->RestoreTPL (OldTpl
);
1499 (Urb
->Callback
) (ProcBuf
, Urb
->Completed
, Urb
->Context
, Urb
->Result
);
1500 OldTpl
= gBS
->RaiseTPL (XHC_TPL
);
1503 if (ProcBuf
!= NULL
) {
1504 gBS
->FreePool (ProcBuf
);
1507 XhcUpdateAsyncRequest (Xhc
, Urb
);
1509 gBS
->RestoreTPL (OldTpl
);
1513 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.
1515 @param Xhc The XHCI Instance.
1516 @param ParentRouteChart The route string pointed to the parent device if it exists.
1517 @param Port The port to be polled.
1518 @param PortState The port state.
1520 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.
1521 @retval Others Should not appear.
1526 XhcPollPortStatusChange (
1527 IN USB_XHCI_INSTANCE
*Xhc
,
1528 IN USB_DEV_ROUTE ParentRouteChart
,
1530 IN EFI_USB_PORT_STATUS
*PortState
1536 USB_DEV_ROUTE RouteChart
;
1538 Status
= EFI_SUCCESS
;
1540 if ((PortState
->PortChangeStatus
& (USB_PORT_STAT_C_CONNECTION
| USB_PORT_STAT_C_ENABLE
| USB_PORT_STAT_C_OVERCURRENT
| USB_PORT_STAT_C_RESET
)) == 0) {
1544 if (ParentRouteChart
.Dword
== 0) {
1545 RouteChart
.Route
.RouteString
= 0;
1546 RouteChart
.Route
.RootPortNum
= Port
+ 1;
1547 RouteChart
.Route
.TierNum
= 1;
1550 RouteChart
.Route
.RouteString
= ParentRouteChart
.Route
.RouteString
| (Port
<< (4 * (ParentRouteChart
.Route
.TierNum
- 1)));
1552 RouteChart
.Route
.RouteString
= ParentRouteChart
.Route
.RouteString
| (15 << (4 * (ParentRouteChart
.Route
.TierNum
- 1)));
1554 RouteChart
.Route
.RootPortNum
= ParentRouteChart
.Route
.RootPortNum
;
1555 RouteChart
.Route
.TierNum
= ParentRouteChart
.Route
.TierNum
+ 1;
1558 SlotId
= XhcRouteStringToSlotId (Xhc
, RouteChart
);
1560 if (Xhc
->HcCParams
.Data
.Csz
== 0) {
1561 Status
= XhcDisableSlotCmd (Xhc
, SlotId
);
1563 Status
= XhcDisableSlotCmd64 (Xhc
, SlotId
);
1567 if (((PortState
->PortStatus
& USB_PORT_STAT_ENABLE
) != 0) &&
1568 ((PortState
->PortStatus
& USB_PORT_STAT_CONNECTION
) != 0)) {
1570 // Has a device attached, Identify device speed after port is enabled.
1572 Speed
= EFI_USB_SPEED_FULL
;
1573 if ((PortState
->PortStatus
& USB_PORT_STAT_LOW_SPEED
) != 0) {
1574 Speed
= EFI_USB_SPEED_LOW
;
1575 } else if ((PortState
->PortStatus
& USB_PORT_STAT_HIGH_SPEED
) != 0) {
1576 Speed
= EFI_USB_SPEED_HIGH
;
1577 } else if ((PortState
->PortStatus
& USB_PORT_STAT_SUPER_SPEED
) != 0) {
1578 Speed
= EFI_USB_SPEED_SUPER
;
1581 // Execute Enable_Slot cmd for attached device, initialize device context and assign device address.
1583 SlotId
= XhcRouteStringToSlotId (Xhc
, RouteChart
);
1584 if ((SlotId
== 0) && ((PortState
->PortChangeStatus
& USB_PORT_STAT_C_RESET
) != 0)) {
1585 if (Xhc
->HcCParams
.Data
.Csz
== 0) {
1586 Status
= XhcInitializeDeviceSlot (Xhc
, ParentRouteChart
, Port
, RouteChart
, Speed
);
1588 Status
= XhcInitializeDeviceSlot64 (Xhc
, ParentRouteChart
, Port
, RouteChart
, Speed
);
1598 Calculate the device context index by endpoint address and direction.
1600 @param EpAddr The target endpoint number.
1601 @param Direction The direction of the target endpoint.
1603 @return The device context index of endpoint.
1617 Index
= (UINT8
) (2 * EpAddr
);
1618 if (Direction
== EfiUsbDataIn
) {
1626 Find out the actual device address according to the requested device address from UsbBus.
1628 @param Xhc The XHCI Instance.
1629 @param BusDevAddr The requested device address by UsbBus upper driver.
1631 @return The actual device address assigned to the device.
1636 XhcBusDevAddrToSlotId (
1637 IN USB_XHCI_INSTANCE
*Xhc
,
1643 for (Index
= 0; Index
< 255; Index
++) {
1644 if (Xhc
->UsbDevContext
[Index
+ 1].Enabled
&&
1645 (Xhc
->UsbDevContext
[Index
+ 1].SlotId
!= 0) &&
1646 (Xhc
->UsbDevContext
[Index
+ 1].BusDevAddr
== BusDevAddr
)) {
1655 return Xhc
->UsbDevContext
[Index
+ 1].SlotId
;
1659 Find out the slot id according to the device's route string.
1661 @param Xhc The XHCI Instance.
1662 @param RouteString The route string described the device location.
1664 @return The slot id used by the device.
1669 XhcRouteStringToSlotId (
1670 IN USB_XHCI_INSTANCE
*Xhc
,
1671 IN USB_DEV_ROUTE RouteString
1676 for (Index
= 0; Index
< 255; Index
++) {
1677 if (Xhc
->UsbDevContext
[Index
+ 1].Enabled
&&
1678 (Xhc
->UsbDevContext
[Index
+ 1].SlotId
!= 0) &&
1679 (Xhc
->UsbDevContext
[Index
+ 1].RouteString
.Dword
== RouteString
.Dword
)) {
1688 return Xhc
->UsbDevContext
[Index
+ 1].SlotId
;
1692 Synchronize the specified event ring to update the enqueue and dequeue pointer.
1694 @param Xhc The XHCI Instance.
1695 @param EvtRing The event ring to sync.
1697 @retval EFI_SUCCESS The event ring is synchronized successfully.
1703 IN USB_XHCI_INSTANCE
*Xhc
,
1704 IN EVENT_RING
*EvtRing
1708 TRB_TEMPLATE
*EvtTrb1
;
1710 ASSERT (EvtRing
!= NULL
);
1713 // Calculate the EventRingEnqueue and EventRingCCS.
1714 // Note: only support single Segment
1716 EvtTrb1
= EvtRing
->EventRingDequeue
;
1718 for (Index
= 0; Index
< EvtRing
->TrbNumber
; Index
++) {
1719 if (EvtTrb1
->CycleBit
!= EvtRing
->EventRingCCS
) {
1725 if ((UINTN
)EvtTrb1
>= ((UINTN
) EvtRing
->EventRingSeg0
+ sizeof (TRB_TEMPLATE
) * EvtRing
->TrbNumber
)) {
1726 EvtTrb1
= EvtRing
->EventRingSeg0
;
1727 EvtRing
->EventRingCCS
= (EvtRing
->EventRingCCS
) ? 0 : 1;
1731 if (Index
< EvtRing
->TrbNumber
) {
1732 EvtRing
->EventRingEnqueue
= EvtTrb1
;
1741 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
1743 @param Xhc The XHCI Instance.
1744 @param TrsRing The transfer ring to sync.
1746 @retval EFI_SUCCESS The transfer ring is synchronized successfully.
1752 IN USB_XHCI_INSTANCE
*Xhc
,
1753 IN TRANSFER_RING
*TrsRing
1757 TRB_TEMPLATE
*TrsTrb
;
1759 ASSERT (TrsRing
!= NULL
);
1761 // Calculate the latest RingEnqueue and RingPCS
1763 TrsTrb
= TrsRing
->RingEnqueue
;
1764 ASSERT (TrsTrb
!= NULL
);
1766 for (Index
= 0; Index
< TrsRing
->TrbNumber
; Index
++) {
1767 if (TrsTrb
->CycleBit
!= (TrsRing
->RingPCS
& BIT0
)) {
1771 if ((UINT8
) TrsTrb
->Type
== TRB_TYPE_LINK
) {
1772 ASSERT (((LINK_TRB
*)TrsTrb
)->TC
!= 0);
1774 // set cycle bit in Link TRB as normal
1776 ((LINK_TRB
*)TrsTrb
)->CycleBit
= TrsRing
->RingPCS
& BIT0
;
1778 // Toggle PCS maintained by software
1780 TrsRing
->RingPCS
= (TrsRing
->RingPCS
& BIT0
) ? 0 : 1;
1781 TrsTrb
= (TRB_TEMPLATE
*) TrsRing
->RingSeg0
; // Use host address
1785 ASSERT (Index
!= TrsRing
->TrbNumber
);
1787 if (TrsTrb
!= TrsRing
->RingEnqueue
) {
1788 TrsRing
->RingEnqueue
= TrsTrb
;
1792 // Clear the Trb context for enqueue, but reserve the PCS bit
1794 TrsTrb
->Parameter1
= 0;
1795 TrsTrb
->Parameter2
= 0;
1799 TrsTrb
->Control
= 0;
1805 Check if there is a new generated event.
1807 @param Xhc The XHCI Instance.
1808 @param EvtRing The event ring to check.
1809 @param NewEvtTrb The new event TRB found.
1811 @retval EFI_SUCCESS Found a new event TRB at the event ring.
1812 @retval EFI_NOT_READY The event ring has no new event.
1818 IN USB_XHCI_INSTANCE
*Xhc
,
1819 IN EVENT_RING
*EvtRing
,
1820 OUT TRB_TEMPLATE
**NewEvtTrb
1823 ASSERT (EvtRing
!= NULL
);
1825 *NewEvtTrb
= EvtRing
->EventRingDequeue
;
1827 if (EvtRing
->EventRingDequeue
== EvtRing
->EventRingEnqueue
) {
1828 return EFI_NOT_READY
;
1831 EvtRing
->EventRingDequeue
++;
1833 // If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.
1835 if ((UINTN
)EvtRing
->EventRingDequeue
>= ((UINTN
) EvtRing
->EventRingSeg0
+ sizeof (TRB_TEMPLATE
) * EvtRing
->TrbNumber
)) {
1836 EvtRing
->EventRingDequeue
= EvtRing
->EventRingSeg0
;
1843 Ring the door bell to notify XHCI there is a transaction to be executed.
1845 @param Xhc The XHCI Instance.
1846 @param SlotId The slot id of the target device.
1847 @param Dci The device context index of the target slot or endpoint.
1849 @retval EFI_SUCCESS Successfully ring the door bell.
1855 IN USB_XHCI_INSTANCE
*Xhc
,
1861 XhcWriteDoorBellReg (Xhc
, 0, 0);
1863 XhcWriteDoorBellReg (Xhc
, SlotId
* sizeof (UINT32
), Dci
);
1870 Ring the door bell to notify XHCI there is a transaction to be executed through URB.
1872 @param Xhc The XHCI Instance.
1873 @param Urb The URB to be rung.
1875 @retval EFI_SUCCESS Successfully ring the door bell.
1879 RingIntTransferDoorBell (
1880 IN USB_XHCI_INSTANCE
*Xhc
,
1887 SlotId
= XhcBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
1888 Dci
= XhcEndpointToDci (Urb
->Ep
.EpAddr
, (UINT8
)(Urb
->Ep
.Direction
));
1889 XhcRingDoorBell (Xhc
, SlotId
, Dci
);
1894 Assign and initialize the device slot for a new device.
1896 @param Xhc The XHCI Instance.
1897 @param ParentRouteChart The route string pointed to the parent device.
1898 @param ParentPort The port at which the device is located.
1899 @param RouteChart The route string pointed to the device.
1900 @param DeviceSpeed The device speed.
1902 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1907 XhcInitializeDeviceSlot (
1908 IN USB_XHCI_INSTANCE
*Xhc
,
1909 IN USB_DEV_ROUTE ParentRouteChart
,
1910 IN UINT16 ParentPort
,
1911 IN USB_DEV_ROUTE RouteChart
,
1912 IN UINT8 DeviceSpeed
1916 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
1917 INPUT_CONTEXT
*InputContext
;
1918 DEVICE_CONTEXT
*OutputContext
;
1919 TRANSFER_RING
*EndpointTransferRing
;
1920 CMD_TRB_ADDRESS_DEVICE CmdTrbAddr
;
1921 UINT8 DeviceAddress
;
1922 CMD_TRB_ENABLE_SLOT CmdTrb
;
1925 DEVICE_CONTEXT
*ParentDeviceContext
;
1926 EFI_PHYSICAL_ADDRESS PhyAddr
;
1928 ZeroMem (&CmdTrb
, sizeof (CMD_TRB_ENABLE_SLOT
));
1929 CmdTrb
.CycleBit
= 1;
1930 CmdTrb
.Type
= TRB_TYPE_EN_SLOT
;
1932 Status
= XhcCmdTransfer (
1934 (TRB_TEMPLATE
*) (UINTN
) &CmdTrb
,
1935 XHC_GENERIC_TIMEOUT
,
1936 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
1938 if (EFI_ERROR (Status
)) {
1939 DEBUG ((EFI_D_ERROR
, "XhcInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status
));
1942 ASSERT (EvtTrb
->SlotId
<= Xhc
->MaxSlotsEn
);
1943 DEBUG ((EFI_D_INFO
, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb
->SlotId
));
1944 SlotId
= (UINT8
)EvtTrb
->SlotId
;
1945 ASSERT (SlotId
!= 0);
1947 ZeroMem (&Xhc
->UsbDevContext
[SlotId
], sizeof (USB_DEV_CONTEXT
));
1948 Xhc
->UsbDevContext
[SlotId
].Enabled
= TRUE
;
1949 Xhc
->UsbDevContext
[SlotId
].SlotId
= SlotId
;
1950 Xhc
->UsbDevContext
[SlotId
].RouteString
.Dword
= RouteChart
.Dword
;
1951 Xhc
->UsbDevContext
[SlotId
].ParentRouteString
.Dword
= ParentRouteChart
.Dword
;
1954 // 4.3.3 Device Slot Initialization
1955 // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
1957 InputContext
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (INPUT_CONTEXT
));
1958 ASSERT (InputContext
!= NULL
);
1959 ASSERT (((UINTN
) InputContext
& 0x3F) == 0);
1960 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
1962 Xhc
->UsbDevContext
[SlotId
].InputContext
= (VOID
*) InputContext
;
1965 // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
1966 // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input
1967 // Context are affected by the command.
1969 InputContext
->InputControlContext
.Dword2
|= (BIT0
| BIT1
);
1972 // 3) Initialize the Input Slot Context data structure
1974 InputContext
->Slot
.RouteString
= RouteChart
.Route
.RouteString
;
1975 InputContext
->Slot
.Speed
= DeviceSpeed
+ 1;
1976 InputContext
->Slot
.ContextEntries
= 1;
1977 InputContext
->Slot
.RootHubPortNum
= RouteChart
.Route
.RootPortNum
;
1979 if (RouteChart
.Route
.RouteString
) {
1981 // The device is behind of hub device.
1983 ParentSlotId
= XhcRouteStringToSlotId(Xhc
, ParentRouteChart
);
1984 ASSERT (ParentSlotId
!= 0);
1986 //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
1988 ParentDeviceContext
= (DEVICE_CONTEXT
*)Xhc
->UsbDevContext
[ParentSlotId
].OutputContext
;
1989 if ((ParentDeviceContext
->Slot
.TTPortNum
== 0) &&
1990 (ParentDeviceContext
->Slot
.TTHubSlotId
== 0)) {
1991 if ((ParentDeviceContext
->Slot
.Speed
== (EFI_USB_SPEED_HIGH
+ 1)) && (DeviceSpeed
< EFI_USB_SPEED_HIGH
)) {
1993 // Full/Low device attached to High speed hub port that isolates the high speed signaling
1994 // environment from Full/Low speed signaling environment for a device
1996 InputContext
->Slot
.TTPortNum
= ParentPort
;
1997 InputContext
->Slot
.TTHubSlotId
= ParentSlotId
;
2001 // Inherit the TT parameters from parent device.
2003 InputContext
->Slot
.TTPortNum
= ParentDeviceContext
->Slot
.TTPortNum
;
2004 InputContext
->Slot
.TTHubSlotId
= ParentDeviceContext
->Slot
.TTHubSlotId
;
2006 // If the device is a High speed device then down the speed to be the same as its parent Hub
2008 if (DeviceSpeed
== EFI_USB_SPEED_HIGH
) {
2009 InputContext
->Slot
.Speed
= ParentDeviceContext
->Slot
.Speed
;
2015 // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
2017 EndpointTransferRing
= AllocateZeroPool (sizeof (TRANSFER_RING
));
2018 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0] = EndpointTransferRing
;
2019 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0]);
2021 // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
2023 InputContext
->EP
[0].EPType
= ED_CONTROL_BIDIR
;
2025 if (DeviceSpeed
== EFI_USB_SPEED_SUPER
) {
2026 InputContext
->EP
[0].MaxPacketSize
= 512;
2027 } else if (DeviceSpeed
== EFI_USB_SPEED_HIGH
) {
2028 InputContext
->EP
[0].MaxPacketSize
= 64;
2030 InputContext
->EP
[0].MaxPacketSize
= 8;
2033 // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
2034 // 1KB, and Bulk and Isoch endpoints 3KB.
2036 InputContext
->EP
[0].AverageTRBLength
= 8;
2037 InputContext
->EP
[0].MaxBurstSize
= 0;
2038 InputContext
->EP
[0].Interval
= 0;
2039 InputContext
->EP
[0].MaxPStreams
= 0;
2040 InputContext
->EP
[0].Mult
= 0;
2041 InputContext
->EP
[0].CErr
= 3;
2044 // Init the DCS(dequeue cycle state) as the transfer ring's CCS
2046 PhyAddr
= UsbHcGetPciAddrForHostAddr (
2048 ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0])->RingSeg0
,
2049 sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
2051 InputContext
->EP
[0].PtrLo
= XHC_LOW_32BIT (PhyAddr
) | BIT0
;
2052 InputContext
->EP
[0].PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2055 // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
2057 OutputContext
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (DEVICE_CONTEXT
));
2058 ASSERT (OutputContext
!= NULL
);
2059 ASSERT (((UINTN
) OutputContext
& 0x3F) == 0);
2060 ZeroMem (OutputContext
, sizeof (DEVICE_CONTEXT
));
2062 Xhc
->UsbDevContext
[SlotId
].OutputContext
= OutputContext
;
2064 // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
2065 // a pointer to the Output Device Context data structure (6.2.1).
2067 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, OutputContext
, sizeof (DEVICE_CONTEXT
));
2069 // Fill DCBAA with PCI device address
2071 Xhc
->DCBAA
[SlotId
] = (UINT64
) (UINTN
) PhyAddr
;
2074 // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
2075 // Context data structure described above.
2077 ZeroMem (&CmdTrbAddr
, sizeof (CmdTrbAddr
));
2078 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].InputContext
, sizeof (INPUT_CONTEXT
));
2079 CmdTrbAddr
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2080 CmdTrbAddr
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2081 CmdTrbAddr
.CycleBit
= 1;
2082 CmdTrbAddr
.Type
= TRB_TYPE_ADDRESS_DEV
;
2083 CmdTrbAddr
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
2084 Status
= XhcCmdTransfer (
2086 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbAddr
,
2087 XHC_GENERIC_TIMEOUT
,
2088 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2090 if (!EFI_ERROR (Status
)) {
2091 DeviceAddress
= (UINT8
) ((DEVICE_CONTEXT
*) OutputContext
)->Slot
.DeviceAddress
;
2092 DEBUG ((EFI_D_INFO
, " Address %d assigned successfully\n", DeviceAddress
));
2093 Xhc
->UsbDevContext
[SlotId
].XhciDevAddr
= DeviceAddress
;
2100 Assign and initialize the device slot for a new device.
2102 @param Xhc The XHCI Instance.
2103 @param ParentRouteChart The route string pointed to the parent device.
2104 @param ParentPort The port at which the device is located.
2105 @param RouteChart The route string pointed to the device.
2106 @param DeviceSpeed The device speed.
2108 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
2113 XhcInitializeDeviceSlot64 (
2114 IN USB_XHCI_INSTANCE
*Xhc
,
2115 IN USB_DEV_ROUTE ParentRouteChart
,
2116 IN UINT16 ParentPort
,
2117 IN USB_DEV_ROUTE RouteChart
,
2118 IN UINT8 DeviceSpeed
2122 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
2123 INPUT_CONTEXT_64
*InputContext
;
2124 DEVICE_CONTEXT_64
*OutputContext
;
2125 TRANSFER_RING
*EndpointTransferRing
;
2126 CMD_TRB_ADDRESS_DEVICE CmdTrbAddr
;
2127 UINT8 DeviceAddress
;
2128 CMD_TRB_ENABLE_SLOT CmdTrb
;
2131 DEVICE_CONTEXT_64
*ParentDeviceContext
;
2132 EFI_PHYSICAL_ADDRESS PhyAddr
;
2134 ZeroMem (&CmdTrb
, sizeof (CMD_TRB_ENABLE_SLOT
));
2135 CmdTrb
.CycleBit
= 1;
2136 CmdTrb
.Type
= TRB_TYPE_EN_SLOT
;
2138 Status
= XhcCmdTransfer (
2140 (TRB_TEMPLATE
*) (UINTN
) &CmdTrb
,
2141 XHC_GENERIC_TIMEOUT
,
2142 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2144 if (EFI_ERROR (Status
)) {
2145 DEBUG ((EFI_D_ERROR
, "XhcInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status
));
2148 ASSERT (EvtTrb
->SlotId
<= Xhc
->MaxSlotsEn
);
2149 DEBUG ((EFI_D_INFO
, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb
->SlotId
));
2150 SlotId
= (UINT8
)EvtTrb
->SlotId
;
2151 ASSERT (SlotId
!= 0);
2153 ZeroMem (&Xhc
->UsbDevContext
[SlotId
], sizeof (USB_DEV_CONTEXT
));
2154 Xhc
->UsbDevContext
[SlotId
].Enabled
= TRUE
;
2155 Xhc
->UsbDevContext
[SlotId
].SlotId
= SlotId
;
2156 Xhc
->UsbDevContext
[SlotId
].RouteString
.Dword
= RouteChart
.Dword
;
2157 Xhc
->UsbDevContext
[SlotId
].ParentRouteString
.Dword
= ParentRouteChart
.Dword
;
2160 // 4.3.3 Device Slot Initialization
2161 // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
2163 InputContext
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (INPUT_CONTEXT_64
));
2164 ASSERT (InputContext
!= NULL
);
2165 ASSERT (((UINTN
) InputContext
& 0x3F) == 0);
2166 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
2168 Xhc
->UsbDevContext
[SlotId
].InputContext
= (VOID
*) InputContext
;
2171 // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
2172 // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input
2173 // Context are affected by the command.
2175 InputContext
->InputControlContext
.Dword2
|= (BIT0
| BIT1
);
2178 // 3) Initialize the Input Slot Context data structure
2180 InputContext
->Slot
.RouteString
= RouteChart
.Route
.RouteString
;
2181 InputContext
->Slot
.Speed
= DeviceSpeed
+ 1;
2182 InputContext
->Slot
.ContextEntries
= 1;
2183 InputContext
->Slot
.RootHubPortNum
= RouteChart
.Route
.RootPortNum
;
2185 if (RouteChart
.Route
.RouteString
) {
2187 // The device is behind of hub device.
2189 ParentSlotId
= XhcRouteStringToSlotId(Xhc
, ParentRouteChart
);
2190 ASSERT (ParentSlotId
!= 0);
2192 //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
2194 ParentDeviceContext
= (DEVICE_CONTEXT_64
*)Xhc
->UsbDevContext
[ParentSlotId
].OutputContext
;
2195 if ((ParentDeviceContext
->Slot
.TTPortNum
== 0) &&
2196 (ParentDeviceContext
->Slot
.TTHubSlotId
== 0)) {
2197 if ((ParentDeviceContext
->Slot
.Speed
== (EFI_USB_SPEED_HIGH
+ 1)) && (DeviceSpeed
< EFI_USB_SPEED_HIGH
)) {
2199 // Full/Low device attached to High speed hub port that isolates the high speed signaling
2200 // environment from Full/Low speed signaling environment for a device
2202 InputContext
->Slot
.TTPortNum
= ParentPort
;
2203 InputContext
->Slot
.TTHubSlotId
= ParentSlotId
;
2207 // Inherit the TT parameters from parent device.
2209 InputContext
->Slot
.TTPortNum
= ParentDeviceContext
->Slot
.TTPortNum
;
2210 InputContext
->Slot
.TTHubSlotId
= ParentDeviceContext
->Slot
.TTHubSlotId
;
2212 // If the device is a High speed device then down the speed to be the same as its parent Hub
2214 if (DeviceSpeed
== EFI_USB_SPEED_HIGH
) {
2215 InputContext
->Slot
.Speed
= ParentDeviceContext
->Slot
.Speed
;
2221 // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
2223 EndpointTransferRing
= AllocateZeroPool (sizeof (TRANSFER_RING
));
2224 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0] = EndpointTransferRing
;
2225 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0]);
2227 // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
2229 InputContext
->EP
[0].EPType
= ED_CONTROL_BIDIR
;
2231 if (DeviceSpeed
== EFI_USB_SPEED_SUPER
) {
2232 InputContext
->EP
[0].MaxPacketSize
= 512;
2233 } else if (DeviceSpeed
== EFI_USB_SPEED_HIGH
) {
2234 InputContext
->EP
[0].MaxPacketSize
= 64;
2236 InputContext
->EP
[0].MaxPacketSize
= 8;
2239 // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
2240 // 1KB, and Bulk and Isoch endpoints 3KB.
2242 InputContext
->EP
[0].AverageTRBLength
= 8;
2243 InputContext
->EP
[0].MaxBurstSize
= 0;
2244 InputContext
->EP
[0].Interval
= 0;
2245 InputContext
->EP
[0].MaxPStreams
= 0;
2246 InputContext
->EP
[0].Mult
= 0;
2247 InputContext
->EP
[0].CErr
= 3;
2250 // Init the DCS(dequeue cycle state) as the transfer ring's CCS
2252 PhyAddr
= UsbHcGetPciAddrForHostAddr (
2254 ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0])->RingSeg0
,
2255 sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
2257 InputContext
->EP
[0].PtrLo
= XHC_LOW_32BIT (PhyAddr
) | BIT0
;
2258 InputContext
->EP
[0].PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2261 // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
2263 OutputContext
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (DEVICE_CONTEXT_64
));
2264 ASSERT (OutputContext
!= NULL
);
2265 ASSERT (((UINTN
) OutputContext
& 0x3F) == 0);
2266 ZeroMem (OutputContext
, sizeof (DEVICE_CONTEXT_64
));
2268 Xhc
->UsbDevContext
[SlotId
].OutputContext
= OutputContext
;
2270 // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
2271 // a pointer to the Output Device Context data structure (6.2.1).
2273 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, OutputContext
, sizeof (DEVICE_CONTEXT_64
));
2275 // Fill DCBAA with PCI device address
2277 Xhc
->DCBAA
[SlotId
] = (UINT64
) (UINTN
) PhyAddr
;
2280 // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
2281 // Context data structure described above.
2283 ZeroMem (&CmdTrbAddr
, sizeof (CmdTrbAddr
));
2284 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].InputContext
, sizeof (INPUT_CONTEXT_64
));
2285 CmdTrbAddr
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2286 CmdTrbAddr
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2287 CmdTrbAddr
.CycleBit
= 1;
2288 CmdTrbAddr
.Type
= TRB_TYPE_ADDRESS_DEV
;
2289 CmdTrbAddr
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
2290 Status
= XhcCmdTransfer (
2292 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbAddr
,
2293 XHC_GENERIC_TIMEOUT
,
2294 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2296 if (!EFI_ERROR (Status
)) {
2297 DeviceAddress
= (UINT8
) ((DEVICE_CONTEXT_64
*) OutputContext
)->Slot
.DeviceAddress
;
2298 DEBUG ((EFI_D_INFO
, " Address %d assigned successfully\n", DeviceAddress
));
2299 Xhc
->UsbDevContext
[SlotId
].XhciDevAddr
= DeviceAddress
;
2306 Disable the specified device slot.
2308 @param Xhc The XHCI Instance.
2309 @param SlotId The slot id to be disabled.
2311 @retval EFI_SUCCESS Successfully disable the device slot.
2317 IN USB_XHCI_INSTANCE
*Xhc
,
2322 TRB_TEMPLATE
*EvtTrb
;
2323 CMD_TRB_DISABLE_SLOT CmdTrbDisSlot
;
2328 // Disable the device slots occupied by these devices on its downstream ports.
2329 // Entry 0 is reserved.
2331 for (Index
= 0; Index
< 255; Index
++) {
2332 if (!Xhc
->UsbDevContext
[Index
+ 1].Enabled
||
2333 (Xhc
->UsbDevContext
[Index
+ 1].SlotId
== 0) ||
2334 (Xhc
->UsbDevContext
[Index
+ 1].ParentRouteString
.Dword
!= Xhc
->UsbDevContext
[SlotId
].RouteString
.Dword
)) {
2338 Status
= XhcDisableSlotCmd (Xhc
, Xhc
->UsbDevContext
[Index
+ 1].SlotId
);
2340 if (EFI_ERROR (Status
)) {
2341 DEBUG ((EFI_D_ERROR
, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
2342 Xhc
->UsbDevContext
[Index
+ 1].SlotId
= 0;
2347 // Construct the disable slot command
2349 DEBUG ((EFI_D_INFO
, "Disable device slot %d!\n", SlotId
));
2351 ZeroMem (&CmdTrbDisSlot
, sizeof (CmdTrbDisSlot
));
2352 CmdTrbDisSlot
.CycleBit
= 1;
2353 CmdTrbDisSlot
.Type
= TRB_TYPE_DIS_SLOT
;
2354 CmdTrbDisSlot
.SlotId
= SlotId
;
2355 Status
= XhcCmdTransfer (
2357 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbDisSlot
,
2358 XHC_GENERIC_TIMEOUT
,
2359 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2361 if (EFI_ERROR (Status
)) {
2362 DEBUG ((EFI_D_ERROR
, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status
));
2366 // Free the slot's device context entry
2368 Xhc
->DCBAA
[SlotId
] = 0;
2371 // Free the slot related data structure
2373 for (Index
= 0; Index
< 31; Index
++) {
2374 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
] != NULL
) {
2375 RingSeg
= ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
])->RingSeg0
;
2376 if (RingSeg
!= NULL
) {
2377 UsbHcFreeMem (Xhc
->MemPool
, RingSeg
, sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
);
2379 FreePool (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
]);
2380 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
] = NULL
;
2384 for (Index
= 0; Index
< Xhc
->UsbDevContext
[SlotId
].DevDesc
.NumConfigurations
; Index
++) {
2385 if (Xhc
->UsbDevContext
[SlotId
].ConfDesc
[Index
] != NULL
) {
2386 FreePool (Xhc
->UsbDevContext
[SlotId
].ConfDesc
[Index
]);
2390 if (Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
!= NULL
) {
2391 FreePool (Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
);
2394 if (Xhc
->UsbDevContext
[SlotId
].InputContext
!= NULL
) {
2395 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].InputContext
, sizeof (INPUT_CONTEXT
));
2398 if (Xhc
->UsbDevContext
[SlotId
].OutputContext
!= NULL
) {
2399 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].OutputContext
, sizeof (DEVICE_CONTEXT
));
2402 // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
2403 // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
2404 // remove urb from XHCI's asynchronous transfer list.
2406 Xhc
->UsbDevContext
[SlotId
].Enabled
= FALSE
;
2407 Xhc
->UsbDevContext
[SlotId
].SlotId
= 0;
2413 Disable the specified device slot.
2415 @param Xhc The XHCI Instance.
2416 @param SlotId The slot id to be disabled.
2418 @retval EFI_SUCCESS Successfully disable the device slot.
2423 XhcDisableSlotCmd64 (
2424 IN USB_XHCI_INSTANCE
*Xhc
,
2429 TRB_TEMPLATE
*EvtTrb
;
2430 CMD_TRB_DISABLE_SLOT CmdTrbDisSlot
;
2435 // Disable the device slots occupied by these devices on its downstream ports.
2436 // Entry 0 is reserved.
2438 for (Index
= 0; Index
< 255; Index
++) {
2439 if (!Xhc
->UsbDevContext
[Index
+ 1].Enabled
||
2440 (Xhc
->UsbDevContext
[Index
+ 1].SlotId
== 0) ||
2441 (Xhc
->UsbDevContext
[Index
+ 1].ParentRouteString
.Dword
!= Xhc
->UsbDevContext
[SlotId
].RouteString
.Dword
)) {
2445 Status
= XhcDisableSlotCmd64 (Xhc
, Xhc
->UsbDevContext
[Index
+ 1].SlotId
);
2447 if (EFI_ERROR (Status
)) {
2448 DEBUG ((EFI_D_ERROR
, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
2449 Xhc
->UsbDevContext
[Index
+ 1].SlotId
= 0;
2454 // Construct the disable slot command
2456 DEBUG ((EFI_D_INFO
, "Disable device slot %d!\n", SlotId
));
2458 ZeroMem (&CmdTrbDisSlot
, sizeof (CmdTrbDisSlot
));
2459 CmdTrbDisSlot
.CycleBit
= 1;
2460 CmdTrbDisSlot
.Type
= TRB_TYPE_DIS_SLOT
;
2461 CmdTrbDisSlot
.SlotId
= SlotId
;
2462 Status
= XhcCmdTransfer (
2464 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbDisSlot
,
2465 XHC_GENERIC_TIMEOUT
,
2466 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2468 if (EFI_ERROR (Status
)) {
2469 DEBUG ((EFI_D_ERROR
, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status
));
2473 // Free the slot's device context entry
2475 Xhc
->DCBAA
[SlotId
] = 0;
2478 // Free the slot related data structure
2480 for (Index
= 0; Index
< 31; Index
++) {
2481 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
] != NULL
) {
2482 RingSeg
= ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
])->RingSeg0
;
2483 if (RingSeg
!= NULL
) {
2484 UsbHcFreeMem (Xhc
->MemPool
, RingSeg
, sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
);
2486 FreePool (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
]);
2487 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
] = NULL
;
2491 for (Index
= 0; Index
< Xhc
->UsbDevContext
[SlotId
].DevDesc
.NumConfigurations
; Index
++) {
2492 if (Xhc
->UsbDevContext
[SlotId
].ConfDesc
[Index
] != NULL
) {
2493 FreePool (Xhc
->UsbDevContext
[SlotId
].ConfDesc
[Index
]);
2497 if (Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
!= NULL
) {
2498 FreePool (Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
);
2501 if (Xhc
->UsbDevContext
[SlotId
].InputContext
!= NULL
) {
2502 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].InputContext
, sizeof (INPUT_CONTEXT_64
));
2505 if (Xhc
->UsbDevContext
[SlotId
].OutputContext
!= NULL
) {
2506 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].OutputContext
, sizeof (DEVICE_CONTEXT_64
));
2509 // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
2510 // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
2511 // remove urb from XHCI's asynchronous transfer list.
2513 Xhc
->UsbDevContext
[SlotId
].Enabled
= FALSE
;
2514 Xhc
->UsbDevContext
[SlotId
].SlotId
= 0;
2520 Initialize endpoint context in input context.
2522 @param Xhc The XHCI Instance.
2523 @param SlotId The slot id to be configured.
2524 @param DeviceSpeed The device's speed.
2525 @param InputContext The pointer to the input context.
2526 @param IfDesc The pointer to the usb device interface descriptor.
2528 @return The maximum device context index of endpoint.
2533 XhcInitializeEndpointContext (
2534 IN USB_XHCI_INSTANCE
*Xhc
,
2536 IN UINT8 DeviceSpeed
,
2537 IN INPUT_CONTEXT
*InputContext
,
2538 IN USB_INTERFACE_DESCRIPTOR
*IfDesc
2541 USB_ENDPOINT_DESCRIPTOR
*EpDesc
;
2548 EFI_PHYSICAL_ADDRESS PhyAddr
;
2550 TRANSFER_RING
*EndpointTransferRing
;
2554 NumEp
= IfDesc
->NumEndpoints
;
2556 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)(IfDesc
+ 1);
2557 for (EpIndex
= 0; EpIndex
< NumEp
; EpIndex
++) {
2558 while (EpDesc
->DescriptorType
!= USB_DESC_TYPE_ENDPOINT
) {
2559 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2562 EpAddr
= (UINT8
)(EpDesc
->EndpointAddress
& 0x0F);
2563 Direction
= (UINT8
)((EpDesc
->EndpointAddress
& 0x80) ? EfiUsbDataIn
: EfiUsbDataOut
);
2565 Dci
= XhcEndpointToDci (EpAddr
, Direction
);
2571 InputContext
->InputControlContext
.Dword2
|= (BIT0
<< Dci
);
2572 InputContext
->EP
[Dci
-1].MaxPacketSize
= EpDesc
->MaxPacketSize
;
2574 if (DeviceSpeed
== EFI_USB_SPEED_SUPER
) {
2576 // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
2578 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2580 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2583 switch (EpDesc
->Attributes
& USB_ENDPOINT_TYPE_MASK
) {
2584 case USB_ENDPOINT_BULK
:
2585 if (Direction
== EfiUsbDataIn
) {
2586 InputContext
->EP
[Dci
-1].CErr
= 3;
2587 InputContext
->EP
[Dci
-1].EPType
= ED_BULK_IN
;
2589 InputContext
->EP
[Dci
-1].CErr
= 3;
2590 InputContext
->EP
[Dci
-1].EPType
= ED_BULK_OUT
;
2593 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2594 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] == NULL
) {
2595 EndpointTransferRing
= AllocateZeroPool(sizeof (TRANSFER_RING
));
2596 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] = (VOID
*) EndpointTransferRing
;
2597 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1]);
2601 case USB_ENDPOINT_ISO
:
2602 if (Direction
== EfiUsbDataIn
) {
2603 InputContext
->EP
[Dci
-1].CErr
= 0;
2604 InputContext
->EP
[Dci
-1].EPType
= ED_ISOCH_IN
;
2606 InputContext
->EP
[Dci
-1].CErr
= 0;
2607 InputContext
->EP
[Dci
-1].EPType
= ED_ISOCH_OUT
;
2610 // Do not support isochronous transfer now.
2612 DEBUG ((EFI_D_INFO
, "XhcInitializeEndpointContext: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
2613 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2615 case USB_ENDPOINT_INTERRUPT
:
2616 if (Direction
== EfiUsbDataIn
) {
2617 InputContext
->EP
[Dci
-1].CErr
= 3;
2618 InputContext
->EP
[Dci
-1].EPType
= ED_INTERRUPT_IN
;
2620 InputContext
->EP
[Dci
-1].CErr
= 3;
2621 InputContext
->EP
[Dci
-1].EPType
= ED_INTERRUPT_OUT
;
2623 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2624 InputContext
->EP
[Dci
-1].MaxESITPayload
= EpDesc
->MaxPacketSize
;
2626 // Get the bInterval from descriptor and init the the interval field of endpoint context
2628 if ((DeviceSpeed
== EFI_USB_SPEED_FULL
) || (DeviceSpeed
== EFI_USB_SPEED_LOW
)) {
2629 Interval
= EpDesc
->Interval
;
2631 // Calculate through the bInterval field of Endpoint descriptor.
2633 ASSERT (Interval
!= 0);
2634 InputContext
->EP
[Dci
-1].Interval
= (UINT32
)HighBitSet32((UINT32
)Interval
) + 3;
2635 } else if ((DeviceSpeed
== EFI_USB_SPEED_HIGH
) || (DeviceSpeed
== EFI_USB_SPEED_SUPER
)) {
2636 Interval
= EpDesc
->Interval
;
2637 ASSERT (Interval
>= 1 && Interval
<= 16);
2639 // Refer to XHCI 1.0 spec section 6.2.3.6, table 61
2641 InputContext
->EP
[Dci
-1].Interval
= Interval
- 1;
2642 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2643 InputContext
->EP
[Dci
-1].MaxESITPayload
= 0x0002;
2644 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2645 InputContext
->EP
[Dci
-1].CErr
= 3;
2648 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] == NULL
) {
2649 EndpointTransferRing
= AllocateZeroPool(sizeof (TRANSFER_RING
));
2650 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] = (VOID
*) EndpointTransferRing
;
2651 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1]);
2655 case USB_ENDPOINT_CONTROL
:
2657 // Do not support control transfer now.
2659 DEBUG ((EFI_D_INFO
, "XhcInitializeEndpointContext: Unsupport Control EP found, Transfer ring is not allocated.\n"));
2661 DEBUG ((EFI_D_INFO
, "XhcInitializeEndpointContext: Unknown EP found, Transfer ring is not allocated.\n"));
2662 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2666 PhyAddr
= UsbHcGetPciAddrForHostAddr (
2668 ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1])->RingSeg0
,
2669 sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
2671 PhyAddr
&= ~((EFI_PHYSICAL_ADDRESS
)0x0F);
2672 PhyAddr
|= (EFI_PHYSICAL_ADDRESS
)((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1])->RingPCS
;
2673 InputContext
->EP
[Dci
-1].PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2674 InputContext
->EP
[Dci
-1].PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2676 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2683 Initialize endpoint context in input context.
2685 @param Xhc The XHCI Instance.
2686 @param SlotId The slot id to be configured.
2687 @param DeviceSpeed The device's speed.
2688 @param InputContext The pointer to the input context.
2689 @param IfDesc The pointer to the usb device interface descriptor.
2691 @return The maximum device context index of endpoint.
2696 XhcInitializeEndpointContext64 (
2697 IN USB_XHCI_INSTANCE
*Xhc
,
2699 IN UINT8 DeviceSpeed
,
2700 IN INPUT_CONTEXT_64
*InputContext
,
2701 IN USB_INTERFACE_DESCRIPTOR
*IfDesc
2704 USB_ENDPOINT_DESCRIPTOR
*EpDesc
;
2711 EFI_PHYSICAL_ADDRESS PhyAddr
;
2713 TRANSFER_RING
*EndpointTransferRing
;
2717 NumEp
= IfDesc
->NumEndpoints
;
2719 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)(IfDesc
+ 1);
2720 for (EpIndex
= 0; EpIndex
< NumEp
; EpIndex
++) {
2721 while (EpDesc
->DescriptorType
!= USB_DESC_TYPE_ENDPOINT
) {
2722 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2725 EpAddr
= (UINT8
)(EpDesc
->EndpointAddress
& 0x0F);
2726 Direction
= (UINT8
)((EpDesc
->EndpointAddress
& 0x80) ? EfiUsbDataIn
: EfiUsbDataOut
);
2728 Dci
= XhcEndpointToDci (EpAddr
, Direction
);
2734 InputContext
->InputControlContext
.Dword2
|= (BIT0
<< Dci
);
2735 InputContext
->EP
[Dci
-1].MaxPacketSize
= EpDesc
->MaxPacketSize
;
2737 if (DeviceSpeed
== EFI_USB_SPEED_SUPER
) {
2739 // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
2741 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2743 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2746 switch (EpDesc
->Attributes
& USB_ENDPOINT_TYPE_MASK
) {
2747 case USB_ENDPOINT_BULK
:
2748 if (Direction
== EfiUsbDataIn
) {
2749 InputContext
->EP
[Dci
-1].CErr
= 3;
2750 InputContext
->EP
[Dci
-1].EPType
= ED_BULK_IN
;
2752 InputContext
->EP
[Dci
-1].CErr
= 3;
2753 InputContext
->EP
[Dci
-1].EPType
= ED_BULK_OUT
;
2756 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2757 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] == NULL
) {
2758 EndpointTransferRing
= AllocateZeroPool(sizeof (TRANSFER_RING
));
2759 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] = (VOID
*) EndpointTransferRing
;
2760 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1]);
2764 case USB_ENDPOINT_ISO
:
2765 if (Direction
== EfiUsbDataIn
) {
2766 InputContext
->EP
[Dci
-1].CErr
= 0;
2767 InputContext
->EP
[Dci
-1].EPType
= ED_ISOCH_IN
;
2769 InputContext
->EP
[Dci
-1].CErr
= 0;
2770 InputContext
->EP
[Dci
-1].EPType
= ED_ISOCH_OUT
;
2773 // Do not support isochronous transfer now.
2775 DEBUG ((EFI_D_INFO
, "XhcInitializeEndpointContext64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
2776 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2778 case USB_ENDPOINT_INTERRUPT
:
2779 if (Direction
== EfiUsbDataIn
) {
2780 InputContext
->EP
[Dci
-1].CErr
= 3;
2781 InputContext
->EP
[Dci
-1].EPType
= ED_INTERRUPT_IN
;
2783 InputContext
->EP
[Dci
-1].CErr
= 3;
2784 InputContext
->EP
[Dci
-1].EPType
= ED_INTERRUPT_OUT
;
2786 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2787 InputContext
->EP
[Dci
-1].MaxESITPayload
= EpDesc
->MaxPacketSize
;
2789 // Get the bInterval from descriptor and init the the interval field of endpoint context
2791 if ((DeviceSpeed
== EFI_USB_SPEED_FULL
) || (DeviceSpeed
== EFI_USB_SPEED_LOW
)) {
2792 Interval
= EpDesc
->Interval
;
2794 // Calculate through the bInterval field of Endpoint descriptor.
2796 ASSERT (Interval
!= 0);
2797 InputContext
->EP
[Dci
-1].Interval
= (UINT32
)HighBitSet32((UINT32
)Interval
) + 3;
2798 } else if ((DeviceSpeed
== EFI_USB_SPEED_HIGH
) || (DeviceSpeed
== EFI_USB_SPEED_SUPER
)) {
2799 Interval
= EpDesc
->Interval
;
2800 ASSERT (Interval
>= 1 && Interval
<= 16);
2802 // Refer to XHCI 1.0 spec section 6.2.3.6, table 61
2804 InputContext
->EP
[Dci
-1].Interval
= Interval
- 1;
2805 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2806 InputContext
->EP
[Dci
-1].MaxESITPayload
= 0x0002;
2807 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2808 InputContext
->EP
[Dci
-1].CErr
= 3;
2811 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] == NULL
) {
2812 EndpointTransferRing
= AllocateZeroPool(sizeof (TRANSFER_RING
));
2813 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] = (VOID
*) EndpointTransferRing
;
2814 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1]);
2818 case USB_ENDPOINT_CONTROL
:
2820 // Do not support control transfer now.
2822 DEBUG ((EFI_D_INFO
, "XhcInitializeEndpointContext64: Unsupport Control EP found, Transfer ring is not allocated.\n"));
2824 DEBUG ((EFI_D_INFO
, "XhcInitializeEndpointContext64: Unknown EP found, Transfer ring is not allocated.\n"));
2825 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2829 PhyAddr
= UsbHcGetPciAddrForHostAddr (
2831 ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1])->RingSeg0
,
2832 sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
2834 PhyAddr
&= ~((EFI_PHYSICAL_ADDRESS
)0x0F);
2835 PhyAddr
|= (EFI_PHYSICAL_ADDRESS
)((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1])->RingPCS
;
2836 InputContext
->EP
[Dci
-1].PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2837 InputContext
->EP
[Dci
-1].PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2839 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2846 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
2848 @param Xhc The XHCI Instance.
2849 @param SlotId The slot id to be configured.
2850 @param DeviceSpeed The device's speed.
2851 @param ConfigDesc The pointer to the usb device configuration descriptor.
2853 @retval EFI_SUCCESS Successfully configure all the device endpoints.
2859 IN USB_XHCI_INSTANCE
*Xhc
,
2861 IN UINT8 DeviceSpeed
,
2862 IN USB_CONFIG_DESCRIPTOR
*ConfigDesc
2866 USB_INTERFACE_DESCRIPTOR
*IfDesc
;
2870 EFI_PHYSICAL_ADDRESS PhyAddr
;
2872 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
2873 INPUT_CONTEXT
*InputContext
;
2874 DEVICE_CONTEXT
*OutputContext
;
2875 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
2877 // 4.6.6 Configure Endpoint
2879 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
2880 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
2881 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
2882 CopyMem (&InputContext
->Slot
, &OutputContext
->Slot
, sizeof (SLOT_CONTEXT
));
2884 ASSERT (ConfigDesc
!= NULL
);
2888 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)(ConfigDesc
+ 1);
2889 for (Index
= 0; Index
< ConfigDesc
->NumInterfaces
; Index
++) {
2890 while ((IfDesc
->DescriptorType
!= USB_DESC_TYPE_INTERFACE
) || (IfDesc
->AlternateSetting
!= 0)) {
2891 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
2894 Dci
= XhcInitializeEndpointContext (Xhc
, SlotId
, DeviceSpeed
, InputContext
, IfDesc
);
2899 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
2902 InputContext
->InputControlContext
.Dword2
|= BIT0
;
2903 InputContext
->Slot
.ContextEntries
= MaxDci
;
2905 // configure endpoint
2907 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
2908 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT
));
2909 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2910 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2911 CmdTrbCfgEP
.CycleBit
= 1;
2912 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
2913 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
2914 DEBUG ((EFI_D_INFO
, "Configure Endpoint\n"));
2915 Status
= XhcCmdTransfer (
2917 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
2918 XHC_GENERIC_TIMEOUT
,
2919 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2921 if (EFI_ERROR (Status
)) {
2922 DEBUG ((EFI_D_ERROR
, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status
));
2924 Xhc
->UsbDevContext
[SlotId
].ActiveConfiguration
= ConfigDesc
->ConfigurationValue
;
2931 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
2933 @param Xhc The XHCI Instance.
2934 @param SlotId The slot id to be configured.
2935 @param DeviceSpeed The device's speed.
2936 @param ConfigDesc The pointer to the usb device configuration descriptor.
2938 @retval EFI_SUCCESS Successfully configure all the device endpoints.
2944 IN USB_XHCI_INSTANCE
*Xhc
,
2946 IN UINT8 DeviceSpeed
,
2947 IN USB_CONFIG_DESCRIPTOR
*ConfigDesc
2951 USB_INTERFACE_DESCRIPTOR
*IfDesc
;
2955 EFI_PHYSICAL_ADDRESS PhyAddr
;
2957 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
2958 INPUT_CONTEXT_64
*InputContext
;
2959 DEVICE_CONTEXT_64
*OutputContext
;
2960 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
2962 // 4.6.6 Configure Endpoint
2964 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
2965 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
2966 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
2967 CopyMem (&InputContext
->Slot
, &OutputContext
->Slot
, sizeof (SLOT_CONTEXT_64
));
2969 ASSERT (ConfigDesc
!= NULL
);
2973 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)(ConfigDesc
+ 1);
2974 for (Index
= 0; Index
< ConfigDesc
->NumInterfaces
; Index
++) {
2975 while ((IfDesc
->DescriptorType
!= USB_DESC_TYPE_INTERFACE
) || (IfDesc
->AlternateSetting
!= 0)) {
2976 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
2979 Dci
= XhcInitializeEndpointContext64 (Xhc
, SlotId
, DeviceSpeed
, InputContext
, IfDesc
);
2984 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
2987 InputContext
->InputControlContext
.Dword2
|= BIT0
;
2988 InputContext
->Slot
.ContextEntries
= MaxDci
;
2990 // configure endpoint
2992 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
2993 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT_64
));
2994 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2995 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2996 CmdTrbCfgEP
.CycleBit
= 1;
2997 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
2998 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
2999 DEBUG ((EFI_D_INFO
, "Configure Endpoint\n"));
3000 Status
= XhcCmdTransfer (
3002 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
3003 XHC_GENERIC_TIMEOUT
,
3004 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3006 if (EFI_ERROR (Status
)) {
3007 DEBUG ((EFI_D_ERROR
, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status
));
3009 Xhc
->UsbDevContext
[SlotId
].ActiveConfiguration
= ConfigDesc
->ConfigurationValue
;
3016 Stop endpoint through XHCI's Stop_Endpoint cmd.
3018 @param Xhc The XHCI Instance.
3019 @param SlotId The slot id to be configured.
3020 @param Dci The device context index of endpoint.
3022 @retval EFI_SUCCESS Stop endpoint successfully.
3023 @retval Others Failed to stop endpoint.
3029 IN USB_XHCI_INSTANCE
*Xhc
,
3035 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3036 CMD_TRB_STOP_ENDPOINT CmdTrbStopED
;
3038 DEBUG ((EFI_D_INFO
, "XhcStopEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId
, Dci
));
3041 // Send stop endpoint command to transit Endpoint from running to stop state
3043 ZeroMem (&CmdTrbStopED
, sizeof (CmdTrbStopED
));
3044 CmdTrbStopED
.CycleBit
= 1;
3045 CmdTrbStopED
.Type
= TRB_TYPE_STOP_ENDPOINT
;
3046 CmdTrbStopED
.EDID
= Dci
;
3047 CmdTrbStopED
.SlotId
= SlotId
;
3048 Status
= XhcCmdTransfer (
3050 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbStopED
,
3051 XHC_GENERIC_TIMEOUT
,
3052 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3054 if (EFI_ERROR(Status
)) {
3055 DEBUG ((EFI_D_ERROR
, "XhcStopEndpoint: Stop Endpoint Failed, Status = %r\n", Status
));
3062 Set interface through XHCI's Configure_Endpoint cmd.
3064 @param Xhc The XHCI Instance.
3065 @param SlotId The slot id to be configured.
3066 @param DeviceSpeed The device's speed.
3067 @param ConfigDesc The pointer to the usb device configuration descriptor.
3068 @param Request USB device request to send.
3070 @retval EFI_SUCCESS Successfully set interface.
3076 IN USB_XHCI_INSTANCE
*Xhc
,
3078 IN UINT8 DeviceSpeed
,
3079 IN USB_CONFIG_DESCRIPTOR
*ConfigDesc
,
3080 IN EFI_USB_DEVICE_REQUEST
*Request
3084 USB_INTERFACE_DESCRIPTOR
*IfDescActive
;
3085 USB_INTERFACE_DESCRIPTOR
*IfDescSet
;
3086 USB_INTERFACE_DESCRIPTOR
*IfDesc
;
3087 USB_ENDPOINT_DESCRIPTOR
*EpDesc
;
3094 EFI_PHYSICAL_ADDRESS PhyAddr
;
3097 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
3098 INPUT_CONTEXT
*InputContext
;
3099 DEVICE_CONTEXT
*OutputContext
;
3100 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3102 Status
= EFI_SUCCESS
;
3104 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
3105 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
3107 // XHCI 4.6.6 Configure Endpoint
3108 // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
3109 // Context and Add Context flags as follows:
3110 // 1) If an endpoint is not modified by the Alternate Interface setting, then software shall set the Drop
3111 // Context and Add Context flags to '0'.
3113 // Except the interface indicated by Reqeust->Index, no impact to other interfaces.
3114 // So the default Drop Context and Add Context flags can be '0' to cover 1).
3116 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
3117 CopyMem (&InputContext
->Slot
, &OutputContext
->Slot
, sizeof (SLOT_CONTEXT
));
3119 ASSERT (ConfigDesc
!= NULL
);
3123 IfDescActive
= NULL
;
3126 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)(ConfigDesc
+ 1);
3127 while ((UINTN
) IfDesc
< ((UINTN
) ConfigDesc
+ ConfigDesc
->TotalLength
)) {
3128 if (IfDesc
->DescriptorType
== USB_DESC_TYPE_INTERFACE
) {
3129 if (IfDesc
->InterfaceNumber
== (UINT8
) Request
->Index
) {
3130 if (IfDesc
->AlternateSetting
== Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
[IfDesc
->InterfaceNumber
]) {
3132 // Find out the active interface descriptor.
3134 IfDescActive
= IfDesc
;
3135 } else if (IfDesc
->AlternateSetting
== (UINT8
) Request
->Value
) {
3137 // Find out the interface descriptor to set.
3143 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
3147 // XHCI 4.6.6 Configure Endpoint
3148 // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
3149 // Context and Add Context flags as follows:
3150 // 2) If an endpoint previously disabled, is enabled by the Alternate Interface setting, then software shall set
3151 // the Drop Context flag to '0' and Add Context flag to '1', and initialize the Input Endpoint Context.
3152 // 3) If an endpoint previously enabled, is disabled by the Alternate Interface setting, then software shall set
3153 // the Drop Context flag to '1' and Add Context flag to '0'.
3154 // 4) If a parameter of an enabled endpoint is modified by an Alternate Interface setting, the Drop Context
3155 // and Add Context flags shall be set to '1'.
3157 // Below codes are to cover 2), 3) and 4).
3160 if ((IfDescActive
!= NULL
) && (IfDescSet
!= NULL
)) {
3161 NumEp
= IfDescActive
->NumEndpoints
;
3162 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*) (IfDescActive
+ 1);
3163 for (EpIndex
= 0; EpIndex
< NumEp
; EpIndex
++) {
3164 while (EpDesc
->DescriptorType
!= USB_DESC_TYPE_ENDPOINT
) {
3165 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
3168 EpAddr
= (UINT8
) (EpDesc
->EndpointAddress
& 0x0F);
3169 Direction
= (UINT8
) ((EpDesc
->EndpointAddress
& 0x80) ? EfiUsbDataIn
: EfiUsbDataOut
);
3171 Dci
= XhcEndpointToDci (EpAddr
, Direction
);
3177 // XHCI 4.3.6 - Setting Alternate Interfaces
3178 // 1) Stop any Running Transfer Rings affected by the Alternate Interface setting.
3180 Status
= XhcStopEndpoint (Xhc
, SlotId
, Dci
);
3181 if (EFI_ERROR (Status
)) {
3185 // XHCI 4.3.6 - Setting Alternate Interfaces
3186 // 2) Free Transfer Rings of all endpoints that will be affected by the Alternate Interface setting.
3188 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1] != NULL
) {
3189 RingSeg
= ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1])->RingSeg0
;
3190 if (RingSeg
!= NULL
) {
3191 UsbHcFreeMem (Xhc
->MemPool
, RingSeg
, sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
);
3193 FreePool (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1]);
3194 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1] = NULL
;
3198 // Set the Drop Context flag to '1'.
3200 InputContext
->InputControlContext
.Dword1
|= (BIT0
<< Dci
);
3202 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
3206 // XHCI 4.3.6 - Setting Alternate Interfaces
3207 // 3) Clear all the Endpoint Context fields of each endpoint that will be disabled by the Alternate
3208 // Interface setting, to '0'.
3210 // The step 3) has been covered by the ZeroMem () to InputContext at the start of the function.
3214 // XHCI 4.3.6 - Setting Alternate Interfaces
3215 // 4) For each endpoint enabled by the Configure Endpoint Command:
3216 // a. Allocate a Transfer Ring.
3217 // b. Initialize the Transfer Ring Segment(s) by clearing all fields of all TRBs to '0'.
3218 // c. Initialize the Endpoint Context data structure.
3220 Dci
= XhcInitializeEndpointContext (Xhc
, SlotId
, DeviceSpeed
, InputContext
, IfDescSet
);
3225 InputContext
->InputControlContext
.Dword2
|= BIT0
;
3226 InputContext
->Slot
.ContextEntries
= MaxDci
;
3228 // XHCI 4.3.6 - Setting Alternate Interfaces
3229 // 5) Issue and successfully complete a Configure Endpoint Command.
3231 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
3232 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT
));
3233 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3234 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3235 CmdTrbCfgEP
.CycleBit
= 1;
3236 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
3237 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3238 DEBUG ((EFI_D_INFO
, "SetInterface: Configure Endpoint\n"));
3239 Status
= XhcCmdTransfer (
3241 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
3242 XHC_GENERIC_TIMEOUT
,
3243 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3245 if (EFI_ERROR (Status
)) {
3246 DEBUG ((EFI_D_ERROR
, "SetInterface: Config Endpoint Failed, Status = %r\n", Status
));
3249 // Update the active AlternateSetting.
3251 Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
[(UINT8
) Request
->Index
] = (UINT8
) Request
->Value
;
3259 Set interface through XHCI's Configure_Endpoint cmd.
3261 @param Xhc The XHCI Instance.
3262 @param SlotId The slot id to be configured.
3263 @param DeviceSpeed The device's speed.
3264 @param ConfigDesc The pointer to the usb device configuration descriptor.
3265 @param Request USB device request to send.
3267 @retval EFI_SUCCESS Successfully set interface.
3273 IN USB_XHCI_INSTANCE
*Xhc
,
3275 IN UINT8 DeviceSpeed
,
3276 IN USB_CONFIG_DESCRIPTOR
*ConfigDesc
,
3277 IN EFI_USB_DEVICE_REQUEST
*Request
3281 USB_INTERFACE_DESCRIPTOR
*IfDescActive
;
3282 USB_INTERFACE_DESCRIPTOR
*IfDescSet
;
3283 USB_INTERFACE_DESCRIPTOR
*IfDesc
;
3284 USB_ENDPOINT_DESCRIPTOR
*EpDesc
;
3291 EFI_PHYSICAL_ADDRESS PhyAddr
;
3294 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
3295 INPUT_CONTEXT_64
*InputContext
;
3296 DEVICE_CONTEXT_64
*OutputContext
;
3297 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3299 Status
= EFI_SUCCESS
;
3301 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
3302 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
3304 // XHCI 4.6.6 Configure Endpoint
3305 // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
3306 // Context and Add Context flags as follows:
3307 // 1) If an endpoint is not modified by the Alternate Interface setting, then software shall set the Drop
3308 // Context and Add Context flags to '0'.
3310 // Except the interface indicated by Reqeust->Index, no impact to other interfaces.
3311 // So the default Drop Context and Add Context flags can be '0' to cover 1).
3313 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
3314 CopyMem (&InputContext
->Slot
, &OutputContext
->Slot
, sizeof (SLOT_CONTEXT_64
));
3316 ASSERT (ConfigDesc
!= NULL
);
3320 IfDescActive
= NULL
;
3323 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)(ConfigDesc
+ 1);
3324 while ((UINTN
) IfDesc
< ((UINTN
) ConfigDesc
+ ConfigDesc
->TotalLength
)) {
3325 if (IfDesc
->DescriptorType
== USB_DESC_TYPE_INTERFACE
) {
3326 if (IfDesc
->InterfaceNumber
== (UINT8
) Request
->Index
) {
3327 if (IfDesc
->AlternateSetting
== Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
[IfDesc
->InterfaceNumber
]) {
3329 // Find out the active interface descriptor.
3331 IfDescActive
= IfDesc
;
3332 } else if (IfDesc
->AlternateSetting
== (UINT8
) Request
->Value
) {
3334 // Find out the interface descriptor to set.
3340 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
3344 // XHCI 4.6.6 Configure Endpoint
3345 // When this command is used to "Set an Alternate Interface on a device", software shall set the Drop
3346 // Context and Add Context flags as follows:
3347 // 2) If an endpoint previously disabled, is enabled by the Alternate Interface setting, then software shall set
3348 // the Drop Context flag to '0' and Add Context flag to '1', and initialize the Input Endpoint Context.
3349 // 3) If an endpoint previously enabled, is disabled by the Alternate Interface setting, then software shall set
3350 // the Drop Context flag to '1' and Add Context flag to '0'.
3351 // 4) If a parameter of an enabled endpoint is modified by an Alternate Interface setting, the Drop Context
3352 // and Add Context flags shall be set to '1'.
3354 // Below codes are to cover 2), 3) and 4).
3357 if ((IfDescActive
!= NULL
) && (IfDescSet
!= NULL
)) {
3358 NumEp
= IfDescActive
->NumEndpoints
;
3359 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*) (IfDescActive
+ 1);
3360 for (EpIndex
= 0; EpIndex
< NumEp
; EpIndex
++) {
3361 while (EpDesc
->DescriptorType
!= USB_DESC_TYPE_ENDPOINT
) {
3362 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
3365 EpAddr
= (UINT8
) (EpDesc
->EndpointAddress
& 0x0F);
3366 Direction
= (UINT8
) ((EpDesc
->EndpointAddress
& 0x80) ? EfiUsbDataIn
: EfiUsbDataOut
);
3368 Dci
= XhcEndpointToDci (EpAddr
, Direction
);
3374 // XHCI 4.3.6 - Setting Alternate Interfaces
3375 // 1) Stop any Running Transfer Rings affected by the Alternate Interface setting.
3377 Status
= XhcStopEndpoint (Xhc
, SlotId
, Dci
);
3378 if (EFI_ERROR (Status
)) {
3382 // XHCI 4.3.6 - Setting Alternate Interfaces
3383 // 2) Free Transfer Rings of all endpoints that will be affected by the Alternate Interface setting.
3385 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1] != NULL
) {
3386 RingSeg
= ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1])->RingSeg0
;
3387 if (RingSeg
!= NULL
) {
3388 UsbHcFreeMem (Xhc
->MemPool
, RingSeg
, sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
);
3390 FreePool (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1]);
3391 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
- 1] = NULL
;
3395 // Set the Drop Context flag to '1'.
3397 InputContext
->InputControlContext
.Dword1
|= (BIT0
<< Dci
);
3399 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
3403 // XHCI 4.3.6 - Setting Alternate Interfaces
3404 // 3) Clear all the Endpoint Context fields of each endpoint that will be disabled by the Alternate
3405 // Interface setting, to '0'.
3407 // The step 3) has been covered by the ZeroMem () to InputContext at the start of the function.
3411 // XHCI 4.3.6 - Setting Alternate Interfaces
3412 // 4) For each endpoint enabled by the Configure Endpoint Command:
3413 // a. Allocate a Transfer Ring.
3414 // b. Initialize the Transfer Ring Segment(s) by clearing all fields of all TRBs to '0'.
3415 // c. Initialize the Endpoint Context data structure.
3417 Dci
= XhcInitializeEndpointContext64 (Xhc
, SlotId
, DeviceSpeed
, InputContext
, IfDescSet
);
3422 InputContext
->InputControlContext
.Dword2
|= BIT0
;
3423 InputContext
->Slot
.ContextEntries
= MaxDci
;
3425 // XHCI 4.3.6 - Setting Alternate Interfaces
3426 // 5) Issue and successfully complete a Configure Endpoint Command.
3428 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
3429 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT_64
));
3430 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3431 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3432 CmdTrbCfgEP
.CycleBit
= 1;
3433 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
3434 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3435 DEBUG ((EFI_D_INFO
, "SetInterface64: Configure Endpoint\n"));
3436 Status
= XhcCmdTransfer (
3438 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
3439 XHC_GENERIC_TIMEOUT
,
3440 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3442 if (EFI_ERROR (Status
)) {
3443 DEBUG ((EFI_D_ERROR
, "SetInterface64: Config Endpoint Failed, Status = %r\n", Status
));
3446 // Update the active AlternateSetting.
3448 Xhc
->UsbDevContext
[SlotId
].ActiveAlternateSetting
[(UINT8
) Request
->Index
] = (UINT8
) Request
->Value
;
3456 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
3458 @param Xhc The XHCI Instance.
3459 @param SlotId The slot id to be evaluated.
3460 @param MaxPacketSize The max packet size supported by the device control transfer.
3462 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
3467 XhcEvaluateContext (
3468 IN USB_XHCI_INSTANCE
*Xhc
,
3470 IN UINT32 MaxPacketSize
3474 CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu
;
3475 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3476 INPUT_CONTEXT
*InputContext
;
3477 EFI_PHYSICAL_ADDRESS PhyAddr
;
3479 ASSERT (Xhc
->UsbDevContext
[SlotId
].SlotId
!= 0);
3482 // 4.6.7 Evaluate Context
3484 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
3485 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
3487 InputContext
->InputControlContext
.Dword2
|= BIT1
;
3488 InputContext
->EP
[0].MaxPacketSize
= MaxPacketSize
;
3490 ZeroMem (&CmdTrbEvalu
, sizeof (CmdTrbEvalu
));
3491 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT
));
3492 CmdTrbEvalu
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3493 CmdTrbEvalu
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3494 CmdTrbEvalu
.CycleBit
= 1;
3495 CmdTrbEvalu
.Type
= TRB_TYPE_EVALU_CONTXT
;
3496 CmdTrbEvalu
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3497 DEBUG ((EFI_D_INFO
, "Evaluate context\n"));
3498 Status
= XhcCmdTransfer (
3500 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbEvalu
,
3501 XHC_GENERIC_TIMEOUT
,
3502 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3504 if (EFI_ERROR (Status
)) {
3505 DEBUG ((EFI_D_ERROR
, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status
));
3511 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
3513 @param Xhc The XHCI Instance.
3514 @param SlotId The slot id to be evaluated.
3515 @param MaxPacketSize The max packet size supported by the device control transfer.
3517 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
3522 XhcEvaluateContext64 (
3523 IN USB_XHCI_INSTANCE
*Xhc
,
3525 IN UINT32 MaxPacketSize
3529 CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu
;
3530 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3531 INPUT_CONTEXT_64
*InputContext
;
3532 EFI_PHYSICAL_ADDRESS PhyAddr
;
3534 ASSERT (Xhc
->UsbDevContext
[SlotId
].SlotId
!= 0);
3537 // 4.6.7 Evaluate Context
3539 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
3540 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
3542 InputContext
->InputControlContext
.Dword2
|= BIT1
;
3543 InputContext
->EP
[0].MaxPacketSize
= MaxPacketSize
;
3545 ZeroMem (&CmdTrbEvalu
, sizeof (CmdTrbEvalu
));
3546 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT_64
));
3547 CmdTrbEvalu
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3548 CmdTrbEvalu
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3549 CmdTrbEvalu
.CycleBit
= 1;
3550 CmdTrbEvalu
.Type
= TRB_TYPE_EVALU_CONTXT
;
3551 CmdTrbEvalu
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3552 DEBUG ((EFI_D_INFO
, "Evaluate context\n"));
3553 Status
= XhcCmdTransfer (
3555 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbEvalu
,
3556 XHC_GENERIC_TIMEOUT
,
3557 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3559 if (EFI_ERROR (Status
)) {
3560 DEBUG ((EFI_D_ERROR
, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status
));
3567 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
3569 @param Xhc The XHCI Instance.
3570 @param SlotId The slot id to be configured.
3571 @param PortNum The total number of downstream port supported by the hub.
3572 @param TTT The TT think time of the hub device.
3573 @param MTT The multi-TT of the hub device.
3575 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
3579 XhcConfigHubContext (
3580 IN USB_XHCI_INSTANCE
*Xhc
,
3588 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3589 INPUT_CONTEXT
*InputContext
;
3590 DEVICE_CONTEXT
*OutputContext
;
3591 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
3592 EFI_PHYSICAL_ADDRESS PhyAddr
;
3594 ASSERT (Xhc
->UsbDevContext
[SlotId
].SlotId
!= 0);
3595 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
3596 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
3599 // 4.6.7 Evaluate Context
3601 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
3603 InputContext
->InputControlContext
.Dword2
|= BIT0
;
3606 // Copy the slot context from OutputContext to Input context
3608 CopyMem(&(InputContext
->Slot
), &(OutputContext
->Slot
), sizeof (SLOT_CONTEXT
));
3609 InputContext
->Slot
.Hub
= 1;
3610 InputContext
->Slot
.PortNum
= PortNum
;
3611 InputContext
->Slot
.TTT
= TTT
;
3612 InputContext
->Slot
.MTT
= MTT
;
3614 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
3615 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT
));
3616 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3617 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3618 CmdTrbCfgEP
.CycleBit
= 1;
3619 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
3620 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3621 DEBUG ((EFI_D_INFO
, "Configure Hub Slot Context\n"));
3622 Status
= XhcCmdTransfer (
3624 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
3625 XHC_GENERIC_TIMEOUT
,
3626 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3628 if (EFI_ERROR (Status
)) {
3629 DEBUG ((EFI_D_ERROR
, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status
));
3635 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
3637 @param Xhc The XHCI Instance.
3638 @param SlotId The slot id to be configured.
3639 @param PortNum The total number of downstream port supported by the hub.
3640 @param TTT The TT think time of the hub device.
3641 @param MTT The multi-TT of the hub device.
3643 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
3647 XhcConfigHubContext64 (
3648 IN USB_XHCI_INSTANCE
*Xhc
,
3656 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3657 INPUT_CONTEXT_64
*InputContext
;
3658 DEVICE_CONTEXT_64
*OutputContext
;
3659 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
3660 EFI_PHYSICAL_ADDRESS PhyAddr
;
3662 ASSERT (Xhc
->UsbDevContext
[SlotId
].SlotId
!= 0);
3663 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
3664 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
3667 // 4.6.7 Evaluate Context
3669 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
3671 InputContext
->InputControlContext
.Dword2
|= BIT0
;
3674 // Copy the slot context from OutputContext to Input context
3676 CopyMem(&(InputContext
->Slot
), &(OutputContext
->Slot
), sizeof (SLOT_CONTEXT_64
));
3677 InputContext
->Slot
.Hub
= 1;
3678 InputContext
->Slot
.PortNum
= PortNum
;
3679 InputContext
->Slot
.TTT
= TTT
;
3680 InputContext
->Slot
.MTT
= MTT
;
3682 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
3683 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT_64
));
3684 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3685 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3686 CmdTrbCfgEP
.CycleBit
= 1;
3687 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
3688 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3689 DEBUG ((EFI_D_INFO
, "Configure Hub Slot Context\n"));
3690 Status
= XhcCmdTransfer (
3692 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
3693 XHC_GENERIC_TIMEOUT
,
3694 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3696 if (EFI_ERROR (Status
)) {
3697 DEBUG ((EFI_D_ERROR
, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status
));