3 XHCI transfer scheduling routines.
5 Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 Create a command transfer TRB to support XHCI command interfaces.
21 @param Xhc The XHCI Instance.
22 @param CmdTrb The cmd TRB to be executed.
24 @return Created URB or NULL.
29 IN USB_XHCI_INSTANCE
*Xhc
,
30 IN TRB_TEMPLATE
*CmdTrb
35 Urb
= AllocateZeroPool (sizeof (URB
));
40 Urb
->Signature
= XHC_URB_SIG
;
42 Urb
->Ring
= &Xhc
->CmdRing
;
43 XhcSyncTrsRing (Xhc
, Urb
->Ring
);
45 Urb
->TrbStart
= Urb
->Ring
->RingEnqueue
;
46 CopyMem (Urb
->TrbStart
, CmdTrb
, sizeof (TRB_TEMPLATE
));
47 Urb
->TrbStart
->CycleBit
= Urb
->Ring
->RingPCS
& BIT0
;
48 Urb
->TrbEnd
= Urb
->TrbStart
;
54 Execute a XHCI cmd TRB pointed by CmdTrb.
56 @param Xhc The XHCI Instance.
57 @param CmdTrb The cmd TRB to be executed.
58 @param Timeout Indicates the maximum time, in millisecond, which the
59 transfer is allowed to complete.
60 @param EvtTrb The event TRB corresponding to the cmd TRB.
62 @retval EFI_SUCCESS The transfer was completed successfully.
63 @retval EFI_INVALID_PARAMETER Some parameters are invalid.
64 @retval EFI_TIMEOUT The transfer failed due to timeout.
65 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
71 IN USB_XHCI_INSTANCE
*Xhc
,
72 IN TRB_TEMPLATE
*CmdTrb
,
74 OUT TRB_TEMPLATE
**EvtTrb
81 // Validate the parameters
83 if ((Xhc
== NULL
) || (CmdTrb
== NULL
)) {
84 return EFI_INVALID_PARAMETER
;
87 Status
= EFI_DEVICE_ERROR
;
89 if (XhcIsHalt (Xhc
) || XhcIsSysError (Xhc
)) {
90 DEBUG ((EFI_D_ERROR
, "XhcCmdTransfer: HC is halted\n"));
95 // Create a new URB, then poll the execution status.
97 Urb
= XhcCreateCmdTrb (Xhc
, CmdTrb
);
100 DEBUG ((EFI_D_ERROR
, "XhcCmdTransfer: failed to create URB\n"));
101 Status
= EFI_OUT_OF_RESOURCES
;
105 Status
= XhcExecTransfer (Xhc
, TRUE
, Urb
, Timeout
);
106 *EvtTrb
= Urb
->EvtTrb
;
108 if (Urb
->Result
== EFI_USB_NOERROR
) {
109 Status
= EFI_SUCCESS
;
112 XhcFreeUrb (Xhc
, Urb
);
119 Create a new URB for a new transaction.
121 @param Xhc The XHCI Instance
122 @param BusAddr The logical device address assigned by UsbBus driver
123 @param EpAddr Endpoint addrress
124 @param DevSpeed The device speed
125 @param MaxPacket The max packet length of the endpoint
126 @param Type The transaction type
127 @param Request The standard USB request for control transfer
128 @param Data The user data to transfer
129 @param DataLen The length of data buffer
130 @param Callback The function to call when data is transferred
131 @param Context The context to the callback
133 @return Created URB or NULL
138 IN USB_XHCI_INSTANCE
*Xhc
,
144 IN EFI_USB_DEVICE_REQUEST
*Request
,
147 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback
,
155 Urb
= AllocateZeroPool (sizeof (URB
));
160 Urb
->Signature
= XHC_URB_SIG
;
161 InitializeListHead (&Urb
->UrbList
);
164 Ep
->BusAddr
= BusAddr
;
165 Ep
->EpAddr
= (UINT8
)(EpAddr
& 0x0F);
166 Ep
->Direction
= ((EpAddr
& 0x80) != 0) ? EfiUsbDataIn
: EfiUsbDataOut
;
167 Ep
->DevSpeed
= DevSpeed
;
168 Ep
->MaxPacket
= MaxPacket
;
171 Urb
->Request
= Request
;
173 Urb
->DataLen
= DataLen
;
174 Urb
->Callback
= Callback
;
175 Urb
->Context
= Context
;
177 Status
= XhcCreateTransferTrb (Xhc
, Urb
);
178 ASSERT_EFI_ERROR (Status
);
179 if (EFI_ERROR (Status
)) {
180 DEBUG ((EFI_D_ERROR
, "XhcCreateUrb: XhcCreateTransferTrb Failed, Status = %r\n", Status
));
189 Free an allocated URB.
191 @param Xhc The XHCI device.
192 @param Urb The URB to free.
197 IN USB_XHCI_INSTANCE
*Xhc
,
201 if ((Xhc
== NULL
) || (Urb
== NULL
)) {
205 if (Urb
->DataMap
!= NULL
) {
206 Xhc
->PciIo
->Unmap (Xhc
->PciIo
, Urb
->DataMap
);
213 Create a transfer TRB.
215 @param Xhc The XHCI Instance
216 @param Urb The urb used to construct the transfer TRB.
218 @return Created TRB or NULL
222 XhcCreateTransferTrb (
223 IN USB_XHCI_INSTANCE
*Xhc
,
228 TRANSFER_RING
*EPRing
;
236 EFI_PCI_IO_PROTOCOL_OPERATION MapOp
;
237 EFI_PHYSICAL_ADDRESS PhyAddr
;
241 SlotId
= XhcBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
243 return EFI_DEVICE_ERROR
;
246 Urb
->Finished
= FALSE
;
247 Urb
->StartDone
= FALSE
;
248 Urb
->EndDone
= FALSE
;
250 Urb
->Result
= EFI_USB_NOERROR
;
252 Dci
= XhcEndpointToDci (Urb
->Ep
.EpAddr
, (UINT8
)(Urb
->Ep
.Direction
));
254 EPRing
= (TRANSFER_RING
*)(UINTN
) Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1];
256 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
257 if (Xhc
->HcCParams
.Data
.Csz
== 0) {
258 EPType
= (UINT8
) ((DEVICE_CONTEXT
*)OutputContext
)->EP
[Dci
-1].EPType
;
260 EPType
= (UINT8
) ((DEVICE_CONTEXT_64
*)OutputContext
)->EP
[Dci
-1].EPType
;
263 if (Urb
->Data
!= NULL
) {
264 if (((UINT8
) (Urb
->Ep
.Direction
)) == EfiUsbDataIn
) {
265 MapOp
= EfiPciIoOperationBusMasterWrite
;
267 MapOp
= EfiPciIoOperationBusMasterRead
;
271 Status
= Xhc
->PciIo
->Map (Xhc
->PciIo
, MapOp
, Urb
->Data
, &Len
, &PhyAddr
, &Map
);
273 if (EFI_ERROR (Status
) || (Len
!= Urb
->DataLen
)) {
274 DEBUG ((EFI_D_ERROR
, "XhcCreateTransferTrb: Fail to map Urb->Data.\n"));
275 return EFI_OUT_OF_RESOURCES
;
278 Urb
->DataPhy
= (VOID
*) ((UINTN
) PhyAddr
);
285 XhcSyncTrsRing (Xhc
, EPRing
);
286 Urb
->TrbStart
= EPRing
->RingEnqueue
;
288 case ED_CONTROL_BIDIR
:
290 // For control transfer, create SETUP_STAGE_TRB first.
292 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
293 TrbStart
->TrbCtrSetup
.bmRequestType
= Urb
->Request
->RequestType
;
294 TrbStart
->TrbCtrSetup
.bRequest
= Urb
->Request
->Request
;
295 TrbStart
->TrbCtrSetup
.wValue
= Urb
->Request
->Value
;
296 TrbStart
->TrbCtrSetup
.wIndex
= Urb
->Request
->Index
;
297 TrbStart
->TrbCtrSetup
.wLength
= Urb
->Request
->Length
;
298 TrbStart
->TrbCtrSetup
.Lenth
= 8;
299 TrbStart
->TrbCtrSetup
.IntTarget
= 0;
300 TrbStart
->TrbCtrSetup
.IOC
= 1;
301 TrbStart
->TrbCtrSetup
.IDT
= 1;
302 TrbStart
->TrbCtrSetup
.Type
= TRB_TYPE_SETUP_STAGE
;
303 if (Urb
->Ep
.Direction
== EfiUsbDataIn
) {
304 TrbStart
->TrbCtrSetup
.TRT
= 3;
305 } else if (Urb
->Ep
.Direction
== EfiUsbDataOut
) {
306 TrbStart
->TrbCtrSetup
.TRT
= 2;
308 TrbStart
->TrbCtrSetup
.TRT
= 0;
311 // Update the cycle bit
313 TrbStart
->TrbCtrSetup
.CycleBit
= EPRing
->RingPCS
& BIT0
;
317 // For control transfer, create DATA_STAGE_TRB.
319 if (Urb
->DataLen
> 0) {
320 XhcSyncTrsRing (Xhc
, EPRing
);
321 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
322 TrbStart
->TrbCtrData
.TRBPtrLo
= XHC_LOW_32BIT(Urb
->DataPhy
);
323 TrbStart
->TrbCtrData
.TRBPtrHi
= XHC_HIGH_32BIT(Urb
->DataPhy
);
324 TrbStart
->TrbCtrData
.Lenth
= (UINT32
) Urb
->DataLen
;
325 TrbStart
->TrbCtrData
.TDSize
= 0;
326 TrbStart
->TrbCtrData
.IntTarget
= 0;
327 TrbStart
->TrbCtrData
.ISP
= 1;
328 TrbStart
->TrbCtrData
.IOC
= 1;
329 TrbStart
->TrbCtrData
.IDT
= 0;
330 TrbStart
->TrbCtrData
.CH
= 0;
331 TrbStart
->TrbCtrData
.Type
= TRB_TYPE_DATA_STAGE
;
332 if (Urb
->Ep
.Direction
== EfiUsbDataIn
) {
333 TrbStart
->TrbCtrData
.DIR = 1;
334 } else if (Urb
->Ep
.Direction
== EfiUsbDataOut
) {
335 TrbStart
->TrbCtrData
.DIR = 0;
337 TrbStart
->TrbCtrData
.DIR = 0;
340 // Update the cycle bit
342 TrbStart
->TrbCtrData
.CycleBit
= EPRing
->RingPCS
& BIT0
;
346 // For control transfer, create STATUS_STAGE_TRB.
347 // Get the pointer to next TRB for status stage use
349 XhcSyncTrsRing (Xhc
, EPRing
);
350 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
351 TrbStart
->TrbCtrStatus
.IntTarget
= 0;
352 TrbStart
->TrbCtrStatus
.IOC
= 1;
353 TrbStart
->TrbCtrStatus
.CH
= 0;
354 TrbStart
->TrbCtrStatus
.Type
= TRB_TYPE_STATUS_STAGE
;
355 if (Urb
->Ep
.Direction
== EfiUsbDataIn
) {
356 TrbStart
->TrbCtrStatus
.DIR = 0;
357 } else if (Urb
->Ep
.Direction
== EfiUsbDataOut
) {
358 TrbStart
->TrbCtrStatus
.DIR = 1;
360 TrbStart
->TrbCtrStatus
.DIR = 0;
363 // Update the cycle bit
365 TrbStart
->TrbCtrStatus
.CycleBit
= EPRing
->RingPCS
& BIT0
;
367 // Update the enqueue pointer
369 XhcSyncTrsRing (Xhc
, EPRing
);
371 Urb
->TrbEnd
= (TRB_TEMPLATE
*)(UINTN
)TrbStart
;
380 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
381 while (TotalLen
< Urb
->DataLen
) {
382 if ((TotalLen
+ 0x10000) >= Urb
->DataLen
) {
383 Len
= Urb
->DataLen
- TotalLen
;
387 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
388 TrbStart
->TrbNormal
.TRBPtrLo
= XHC_LOW_32BIT((UINT8
*) Urb
->DataPhy
+ TotalLen
);
389 TrbStart
->TrbNormal
.TRBPtrHi
= XHC_HIGH_32BIT((UINT8
*) Urb
->DataPhy
+ TotalLen
);
390 TrbStart
->TrbNormal
.Lenth
= (UINT32
) Len
;
391 TrbStart
->TrbNormal
.TDSize
= 0;
392 TrbStart
->TrbNormal
.IntTarget
= 0;
393 TrbStart
->TrbNormal
.ISP
= 1;
394 TrbStart
->TrbNormal
.IOC
= 1;
395 TrbStart
->TrbNormal
.Type
= TRB_TYPE_NORMAL
;
397 // Update the cycle bit
399 TrbStart
->TrbNormal
.CycleBit
= EPRing
->RingPCS
& BIT0
;
401 XhcSyncTrsRing (Xhc
, EPRing
);
406 Urb
->TrbNum
= TrbNum
;
407 Urb
->TrbEnd
= (TRB_TEMPLATE
*)(UINTN
)TrbStart
;
410 case ED_INTERRUPT_OUT
:
411 case ED_INTERRUPT_IN
:
415 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
416 while (TotalLen
< Urb
->DataLen
) {
417 if ((TotalLen
+ 0x10000) >= Urb
->DataLen
) {
418 Len
= Urb
->DataLen
- TotalLen
;
422 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
423 TrbStart
->TrbNormal
.TRBPtrLo
= XHC_LOW_32BIT((UINT8
*) Urb
->DataPhy
+ TotalLen
);
424 TrbStart
->TrbNormal
.TRBPtrHi
= XHC_HIGH_32BIT((UINT8
*) Urb
->DataPhy
+ TotalLen
);
425 TrbStart
->TrbNormal
.Lenth
= (UINT32
) Len
;
426 TrbStart
->TrbNormal
.TDSize
= 0;
427 TrbStart
->TrbNormal
.IntTarget
= 0;
428 TrbStart
->TrbNormal
.ISP
= 1;
429 TrbStart
->TrbNormal
.IOC
= 1;
430 TrbStart
->TrbNormal
.Type
= TRB_TYPE_NORMAL
;
432 // Update the cycle bit
434 TrbStart
->TrbNormal
.CycleBit
= EPRing
->RingPCS
& BIT0
;
436 XhcSyncTrsRing (Xhc
, EPRing
);
441 Urb
->TrbNum
= TrbNum
;
442 Urb
->TrbEnd
= (TRB_TEMPLATE
*)(UINTN
)TrbStart
;
446 DEBUG ((EFI_D_INFO
, "Not supported EPType 0x%x!\n",EPType
));
456 Initialize the XHCI host controller for schedule.
458 @param Xhc The XHCI Instance to be initialized.
463 IN USB_XHCI_INSTANCE
*Xhc
467 EFI_PHYSICAL_ADDRESS DcbaaPhy
;
469 EFI_PHYSICAL_ADDRESS CmdRingPhy
;
471 UINT32 MaxScratchpadBufs
;
473 EFI_PHYSICAL_ADDRESS ScratchPhy
;
474 UINT64
*ScratchEntry
;
475 EFI_PHYSICAL_ADDRESS ScratchEntryPhy
;
477 UINTN
*ScratchEntryMap
;
481 // Initialize memory management.
483 Xhc
->MemPool
= UsbHcInitMemPool (Xhc
->PciIo
);
484 ASSERT (Xhc
->MemPool
!= NULL
);
487 // Program the Max Device Slots Enabled (MaxSlotsEn) field in the CONFIG register (5.4.7)
488 // to enable the device slots that system software is going to use.
490 Xhc
->MaxSlotsEn
= Xhc
->HcSParams1
.Data
.MaxSlots
;
491 ASSERT (Xhc
->MaxSlotsEn
>= 1 && Xhc
->MaxSlotsEn
<= 255);
492 XhcWriteOpReg (Xhc
, XHC_CONFIG_OFFSET
, Xhc
->MaxSlotsEn
);
495 // The Device Context Base Address Array entry associated with each allocated Device Slot
496 // shall contain a 64-bit pointer to the base of the associated Device Context.
497 // The Device Context Base Address Array shall contain MaxSlotsEn + 1 entries.
498 // Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.
500 Entries
= (Xhc
->MaxSlotsEn
+ 1) * sizeof(UINT64
);
501 Dcbaa
= UsbHcAllocateMem (Xhc
->MemPool
, Entries
);
502 ASSERT (Dcbaa
!= NULL
);
503 ZeroMem (Dcbaa
, Entries
);
506 // A Scratchpad Buffer is a PAGESIZE block of system memory located on a PAGESIZE boundary.
507 // System software shall allocate the Scratchpad Buffer(s) before placing the xHC in to Run
508 // mode (Run/Stop(R/S) ='1').
510 MaxScratchpadBufs
= ((Xhc
->HcSParams2
.Data
.ScratchBufHi
) << 5) | (Xhc
->HcSParams2
.Data
.ScratchBufLo
);
511 Xhc
->MaxScratchpadBufs
= MaxScratchpadBufs
;
512 ASSERT (MaxScratchpadBufs
<= 1023);
513 if (MaxScratchpadBufs
!= 0) {
515 // Allocate the buffer to record the Mapping for each scratch buffer in order to Unmap them
517 ScratchEntryMap
= AllocateZeroPool (sizeof (UINTN
) * MaxScratchpadBufs
);
518 ASSERT (ScratchEntryMap
!= NULL
);
519 Xhc
->ScratchEntryMap
= ScratchEntryMap
;
522 // Allocate the buffer to record the host address for each entry
524 ScratchEntry
= AllocateZeroPool (sizeof (UINT64
) * MaxScratchpadBufs
);
525 ASSERT (ScratchEntry
!= NULL
);
526 Xhc
->ScratchEntry
= ScratchEntry
;
528 Status
= UsbHcAllocateAlignedPages (
530 EFI_SIZE_TO_PAGES (MaxScratchpadBufs
* sizeof (UINT64
)),
532 (VOID
**) &ScratchBuf
,
536 ASSERT_EFI_ERROR (Status
);
538 ZeroMem (ScratchBuf
, MaxScratchpadBufs
* sizeof (UINT64
));
539 Xhc
->ScratchBuf
= ScratchBuf
;
542 // Allocate each scratch buffer
544 for (Index
= 0; Index
< MaxScratchpadBufs
; Index
++) {
545 Status
= UsbHcAllocateAlignedPages (
547 EFI_SIZE_TO_PAGES (Xhc
->PageSize
),
549 (VOID
**) &ScratchEntry
[Index
],
551 (VOID
**) &ScratchEntryMap
[Index
]
553 ASSERT_EFI_ERROR (Status
);
554 ZeroMem ((VOID
*)(UINTN
)ScratchEntry
[Index
], Xhc
->PageSize
);
556 // Fill with the PCI device address
558 *ScratchBuf
++ = ScratchEntryPhy
;
561 // The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the
562 // Device Context Base Address Array points to the Scratchpad Buffer Array.
564 *(UINT64
*)Dcbaa
= (UINT64
)(UINTN
) ScratchPhy
;
568 // Program the Device Context Base Address Array Pointer (DCBAAP) register (5.4.6) with
569 // a 64-bit address pointing to where the Device Context Base Address Array is located.
571 Xhc
->DCBAA
= (UINT64
*)(UINTN
)Dcbaa
;
573 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
574 // So divide it to two 32-bytes width register access.
576 DcbaaPhy
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Dcbaa
, Entries
);
577 XhcWriteOpReg (Xhc
, XHC_DCBAAP_OFFSET
, XHC_LOW_32BIT(DcbaaPhy
));
578 XhcWriteOpReg (Xhc
, XHC_DCBAAP_OFFSET
+ 4, XHC_HIGH_32BIT (DcbaaPhy
));
580 DEBUG ((EFI_D_INFO
, "XhcInitSched:DCBAA=0x%x\n", (UINT64
)(UINTN
)Xhc
->DCBAA
));
583 // Define the Command Ring Dequeue Pointer by programming the Command Ring Control Register
584 // (5.4.5) with a 64-bit address pointing to the starting address of the first TRB of the Command Ring.
585 // Note: The Command Ring is 64 byte aligned, so the low order 6 bits of the Command Ring Pointer shall
588 CreateTransferRing (Xhc
, CMD_RING_TRB_NUMBER
, &Xhc
->CmdRing
);
590 // The xHC uses the Enqueue Pointer to determine when a Transfer Ring is empty. As it fetches TRBs from a
591 // Transfer Ring it checks for a Cycle bit transition. If a transition detected, the ring is empty.
592 // So we set RCS as inverted PCS init value to let Command Ring empty
594 CmdRing
= (UINT64
)(UINTN
)Xhc
->CmdRing
.RingSeg0
;
595 CmdRingPhy
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, (VOID
*)(UINTN
) CmdRing
, sizeof (TRB_TEMPLATE
) * CMD_RING_TRB_NUMBER
);
596 ASSERT ((CmdRingPhy
& 0x3F) == 0);
597 CmdRingPhy
|= XHC_CRCR_RCS
;
599 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
600 // So divide it to two 32-bytes width register access.
602 XhcWriteOpReg (Xhc
, XHC_CRCR_OFFSET
, XHC_LOW_32BIT(CmdRingPhy
));
603 XhcWriteOpReg (Xhc
, XHC_CRCR_OFFSET
+ 4, XHC_HIGH_32BIT (CmdRingPhy
));
605 DEBUG ((EFI_D_INFO
, "XhcInitSched:XHC_CRCR=0x%x\n", Xhc
->CmdRing
.RingSeg0
));
608 // Disable the 'interrupter enable' bit in USB_CMD
609 // and clear IE & IP bit in all Interrupter X Management Registers.
611 XhcClearOpRegBit (Xhc
, XHC_USBCMD_OFFSET
, XHC_USBCMD_INTE
);
612 for (Index
= 0; Index
< (UINT16
)(Xhc
->HcSParams1
.Data
.MaxIntrs
); Index
++) {
613 XhcClearRuntimeRegBit (Xhc
, XHC_IMAN_OFFSET
+ (Index
* 32), XHC_IMAN_IE
);
614 XhcSetRuntimeRegBit (Xhc
, XHC_IMAN_OFFSET
+ (Index
* 32), XHC_IMAN_IP
);
618 // Allocate EventRing for Cmd, Ctrl, Bulk, Interrupt, AsynInterrupt transfer
620 CreateEventRing (Xhc
, &Xhc
->EventRing
);
621 DEBUG ((EFI_D_INFO
, "XhcInitSched:XHC_EVENTRING=0x%x\n", Xhc
->EventRing
.EventRingSeg0
));
625 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted
626 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint
627 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is
628 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the
629 Stopped to the Running state.
631 @param Xhc The XHCI Instance.
632 @param Urb The urb which makes the endpoint halted.
634 @retval EFI_SUCCESS The recovery is successful.
635 @retval Others Failed to recovery halted endpoint.
640 XhcRecoverHaltedEndpoint (
641 IN USB_XHCI_INSTANCE
*Xhc
,
646 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
647 CMD_TRB_RESET_ENDPOINT CmdTrbResetED
;
648 CMD_SET_TR_DEQ_POINTER CmdSetTRDeq
;
651 EFI_PHYSICAL_ADDRESS PhyAddr
;
653 Status
= EFI_SUCCESS
;
654 SlotId
= XhcBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
656 return EFI_DEVICE_ERROR
;
658 Dci
= XhcEndpointToDci (Urb
->Ep
.EpAddr
, (UINT8
)(Urb
->Ep
.Direction
));
661 DEBUG ((EFI_D_INFO
, "Recovery Halted Slot = %x,Dci = %x\n", SlotId
, Dci
));
664 // 1) Send Reset endpoint command to transit from halt to stop state
666 ZeroMem (&CmdTrbResetED
, sizeof (CmdTrbResetED
));
667 CmdTrbResetED
.CycleBit
= 1;
668 CmdTrbResetED
.Type
= TRB_TYPE_RESET_ENDPOINT
;
669 CmdTrbResetED
.EDID
= Dci
;
670 CmdTrbResetED
.SlotId
= SlotId
;
671 Status
= XhcCmdTransfer (
673 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbResetED
,
675 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
677 if (EFI_ERROR(Status
)) {
678 DEBUG ((EFI_D_ERROR
, "XhcRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status
));
683 // 2)Set dequeue pointer
685 ZeroMem (&CmdSetTRDeq
, sizeof (CmdSetTRDeq
));
686 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Urb
->Ring
->RingEnqueue
, sizeof (CMD_SET_TR_DEQ_POINTER
));
687 CmdSetTRDeq
.PtrLo
= XHC_LOW_32BIT (PhyAddr
) | Urb
->Ring
->RingPCS
;
688 CmdSetTRDeq
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
689 CmdSetTRDeq
.CycleBit
= 1;
690 CmdSetTRDeq
.Type
= TRB_TYPE_SET_TR_DEQUE
;
691 CmdSetTRDeq
.Endpoint
= Dci
;
692 CmdSetTRDeq
.SlotId
= SlotId
;
693 Status
= XhcCmdTransfer (
695 (TRB_TEMPLATE
*) (UINTN
) &CmdSetTRDeq
,
697 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
699 if (EFI_ERROR(Status
)) {
700 DEBUG ((EFI_D_ERROR
, "XhcRecoverHaltedEndpoint: Set Dequeue Pointer Failed, Status = %r\n", Status
));
705 // 3)Ring the doorbell to transit from stop to active
707 XhcRingDoorBell (Xhc
, SlotId
, Dci
);
714 Create XHCI event ring.
716 @param Xhc The XHCI Instance.
717 @param EventRing The created event ring.
722 IN USB_XHCI_INSTANCE
*Xhc
,
723 OUT EVENT_RING
*EventRing
727 EVENT_RING_SEG_TABLE_ENTRY
*ERSTBase
;
729 EFI_PHYSICAL_ADDRESS ERSTPhy
;
730 EFI_PHYSICAL_ADDRESS DequeuePhy
;
732 ASSERT (EventRing
!= NULL
);
734 Size
= sizeof (TRB_TEMPLATE
) * EVENT_RING_TRB_NUMBER
;
735 Buf
= UsbHcAllocateMem (Xhc
->MemPool
, Size
);
736 ASSERT (Buf
!= NULL
);
737 ASSERT (((UINTN
) Buf
& 0x3F) == 0);
740 EventRing
->EventRingSeg0
= Buf
;
741 EventRing
->TrbNumber
= EVENT_RING_TRB_NUMBER
;
742 EventRing
->EventRingDequeue
= (TRB_TEMPLATE
*) EventRing
->EventRingSeg0
;
743 EventRing
->EventRingEnqueue
= (TRB_TEMPLATE
*) EventRing
->EventRingSeg0
;
745 DequeuePhy
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Buf
, Size
);
748 // Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'
749 // and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.
751 EventRing
->EventRingCCS
= 1;
753 Size
= EFI_SIZE_TO_PAGES (sizeof (EVENT_RING_SEG_TABLE_ENTRY
) * ERST_NUMBER
);
754 Buf
= UsbHcAllocateMem (Xhc
->MemPool
, Size
);
755 ASSERT (Buf
!= NULL
);
756 ASSERT (((UINTN
) Buf
& 0x3F) == 0);
759 ERSTBase
= (EVENT_RING_SEG_TABLE_ENTRY
*) Buf
;
760 EventRing
->ERSTBase
= ERSTBase
;
761 ERSTBase
->PtrLo
= XHC_LOW_32BIT (DequeuePhy
);
762 ERSTBase
->PtrHi
= XHC_HIGH_32BIT (DequeuePhy
);
763 ERSTBase
->RingTrbSize
= EVENT_RING_TRB_NUMBER
;
765 ERSTPhy
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, ERSTBase
, Size
);
768 // Program the Interrupter Event Ring Segment Table Size (ERSTSZ) register (5.5.2.3.1)
776 // Program the Interrupter Event Ring Dequeue Pointer (ERDP) register (5.5.2.3.3)
778 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
779 // So divide it to two 32-bytes width register access.
784 XHC_LOW_32BIT((UINT64
)(UINTN
)DequeuePhy
)
789 XHC_HIGH_32BIT((UINT64
)(UINTN
)DequeuePhy
)
792 // Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register(5.5.2.3.2)
794 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
795 // So divide it to two 32-bytes width register access.
800 XHC_LOW_32BIT((UINT64
)(UINTN
)ERSTPhy
)
804 XHC_ERSTBA_OFFSET
+ 4,
805 XHC_HIGH_32BIT((UINT64
)(UINTN
)ERSTPhy
)
808 // Need set IMAN IE bit to enble the ring interrupt
810 XhcSetRuntimeRegBit (Xhc
, XHC_IMAN_OFFSET
, XHC_IMAN_IE
);
814 Create XHCI transfer ring.
816 @param Xhc The XHCI Instance.
817 @param TrbNum The number of TRB in the ring.
818 @param TransferRing The created transfer ring.
823 IN USB_XHCI_INSTANCE
*Xhc
,
825 OUT TRANSFER_RING
*TransferRing
830 EFI_PHYSICAL_ADDRESS PhyAddr
;
832 Buf
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (TRB_TEMPLATE
) * TrbNum
);
833 ASSERT (Buf
!= NULL
);
834 ASSERT (((UINTN
) Buf
& 0x3F) == 0);
835 ZeroMem (Buf
, sizeof (TRB_TEMPLATE
) * TrbNum
);
837 TransferRing
->RingSeg0
= Buf
;
838 TransferRing
->TrbNumber
= TrbNum
;
839 TransferRing
->RingEnqueue
= (TRB_TEMPLATE
*) TransferRing
->RingSeg0
;
840 TransferRing
->RingDequeue
= (TRB_TEMPLATE
*) TransferRing
->RingSeg0
;
841 TransferRing
->RingPCS
= 1;
843 // 4.9.2 Transfer Ring Management
844 // To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to
845 // point to the first TRB in the ring.
847 EndTrb
= (LINK_TRB
*) ((UINTN
)Buf
+ sizeof (TRB_TEMPLATE
) * (TrbNum
- 1));
848 EndTrb
->Type
= TRB_TYPE_LINK
;
849 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Buf
, sizeof (TRB_TEMPLATE
) * TrbNum
);
850 EndTrb
->PtrLo
= XHC_LOW_32BIT (PhyAddr
);
851 EndTrb
->PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
853 // Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
857 // Set Cycle bit as other TRB PCS init value
859 EndTrb
->CycleBit
= 0;
863 Free XHCI event ring.
865 @param Xhc The XHCI Instance.
866 @param EventRing The event ring to be freed.
872 IN USB_XHCI_INSTANCE
*Xhc
,
873 IN EVENT_RING
*EventRing
876 if(EventRing
->EventRingSeg0
== NULL
) {
881 // Free EventRing Segment 0
883 UsbHcFreeMem (Xhc
->MemPool
, EventRing
->EventRingSeg0
, sizeof (TRB_TEMPLATE
) * EVENT_RING_TRB_NUMBER
);
888 UsbHcFreeMem (Xhc
->MemPool
, EventRing
->ERSTBase
, sizeof (EVENT_RING_SEG_TABLE_ENTRY
) * ERST_NUMBER
);
893 Free the resouce allocated at initializing schedule.
895 @param Xhc The XHCI Instance.
900 IN USB_XHCI_INSTANCE
*Xhc
904 UINT64
*ScratchEntry
;
906 if (Xhc
->ScratchBuf
!= NULL
) {
907 ScratchEntry
= Xhc
->ScratchEntry
;
908 for (Index
= 0; Index
< Xhc
->MaxScratchpadBufs
; Index
++) {
910 // Free Scratchpad Buffers
912 UsbHcFreeAlignedPages (Xhc
->PciIo
, (VOID
*)(UINTN
)ScratchEntry
[Index
], EFI_SIZE_TO_PAGES (Xhc
->PageSize
), (VOID
*) Xhc
->ScratchEntryMap
[Index
]);
915 // Free Scratchpad Buffer Array
917 UsbHcFreeAlignedPages (Xhc
->PciIo
, Xhc
->ScratchBuf
, EFI_SIZE_TO_PAGES (Xhc
->MaxScratchpadBufs
* sizeof (UINT64
)), Xhc
->ScratchMap
);
918 FreePool (Xhc
->ScratchEntryMap
);
919 FreePool (Xhc
->ScratchEntry
);
922 if (Xhc
->CmdRing
.RingSeg0
!= NULL
) {
923 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->CmdRing
.RingSeg0
, sizeof (TRB_TEMPLATE
) * CMD_RING_TRB_NUMBER
);
924 Xhc
->CmdRing
.RingSeg0
= NULL
;
927 XhcFreeEventRing (Xhc
,&Xhc
->EventRing
);
929 if (Xhc
->DCBAA
!= NULL
) {
930 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->DCBAA
, (Xhc
->MaxSlotsEn
+ 1) * sizeof(UINT64
));
935 // Free memory pool at last
937 if (Xhc
->MemPool
!= NULL
) {
938 UsbHcFreeMemPool (Xhc
->MemPool
);
944 Check if the Trb is a transaction of the URBs in XHCI's asynchronous transfer list.
946 @param Xhc The XHCI Instance.
947 @param Trb The TRB to be checked.
948 @param Urb The pointer to the matched Urb.
950 @retval TRUE The Trb is matched with a transaction of the URBs in the async list.
951 @retval FALSE The Trb is not matched with any URBs in the async list.
956 IN USB_XHCI_INSTANCE
*Xhc
,
957 IN TRB_TEMPLATE
*Trb
,
963 TRB_TEMPLATE
*CheckedTrb
;
967 EFI_LIST_FOR_EACH_SAFE (Entry
, Next
, &Xhc
->AsyncIntTransfers
) {
968 CheckedUrb
= EFI_LIST_CONTAINER (Entry
, URB
, UrbList
);
969 CheckedTrb
= CheckedUrb
->TrbStart
;
970 for (Index
= 0; Index
< CheckedUrb
->TrbNum
; Index
++) {
971 if (Trb
== CheckedTrb
) {
976 if ((UINTN
)CheckedTrb
>= ((UINTN
) CheckedUrb
->Ring
->RingSeg0
+ sizeof (TRB_TEMPLATE
) * CheckedUrb
->Ring
->TrbNumber
)) {
977 CheckedTrb
= (TRB_TEMPLATE
*) CheckedUrb
->Ring
->RingSeg0
;
986 Check if the Trb is a transaction of the URB.
988 @param Trb The TRB to be checked
989 @param Urb The transfer ring to be checked.
991 @retval TRUE It is a transaction of the URB.
992 @retval FALSE It is not any transaction of the URB.
997 IN TRB_TEMPLATE
*Trb
,
1001 TRB_TEMPLATE
*CheckedTrb
;
1004 CheckedTrb
= Urb
->Ring
->RingSeg0
;
1006 ASSERT (Urb
->Ring
->TrbNumber
== CMD_RING_TRB_NUMBER
|| Urb
->Ring
->TrbNumber
== TR_RING_TRB_NUMBER
);
1008 for (Index
= 0; Index
< Urb
->Ring
->TrbNumber
; Index
++) {
1009 if (Trb
== CheckedTrb
) {
1019 Check the URB's execution result and update the URB's
1022 @param Xhc The XHCI Instance.
1023 @param Urb The URB to check result.
1025 @return Whether the result of URB transfer is finialized.
1030 IN USB_XHCI_INSTANCE
*Xhc
,
1034 EVT_TRB_TRANSFER
*EvtTrb
;
1035 TRB_TEMPLATE
*TRBPtr
;
1044 EFI_PHYSICAL_ADDRESS PhyAddr
;
1046 ASSERT ((Xhc
!= NULL
) && (Urb
!= NULL
));
1048 Status
= EFI_SUCCESS
;
1051 if (Urb
->Finished
) {
1057 if (XhcIsHalt (Xhc
) || XhcIsSysError (Xhc
)) {
1058 Urb
->Result
|= EFI_USB_ERR_SYSTEM
;
1059 Status
= EFI_DEVICE_ERROR
;
1064 // Traverse the event ring to find out all new events from the previous check.
1066 XhcSyncEventRing (Xhc
, &Xhc
->EventRing
);
1067 for (Index
= 0; Index
< Xhc
->EventRing
.TrbNumber
; Index
++) {
1068 Status
= XhcCheckNewEvent (Xhc
, &Xhc
->EventRing
, ((TRB_TEMPLATE
**)&EvtTrb
));
1069 if (Status
== EFI_NOT_READY
) {
1071 // All new events are handled, return directly.
1077 // Only handle COMMAND_COMPLETETION_EVENT and TRANSFER_EVENT.
1079 if ((EvtTrb
->Type
!= TRB_TYPE_COMMAND_COMPLT_EVENT
) && (EvtTrb
->Type
!= TRB_TYPE_TRANS_EVENT
)) {
1084 // Need convert pci device address to host address
1086 PhyAddr
= (EFI_PHYSICAL_ADDRESS
)(EvtTrb
->TRBPtrLo
| LShiftU64 ((UINT64
) EvtTrb
->TRBPtrHi
, 32));
1087 TRBPtr
= (TRB_TEMPLATE
*)(UINTN
) UsbHcGetHostAddrForPciAddr (Xhc
->MemPool
, (VOID
*)(UINTN
) PhyAddr
, sizeof (TRB_TEMPLATE
));
1090 // Update the status of Urb according to the finished event regardless of whether
1091 // the urb is current checked one or in the XHCI's async transfer list.
1092 // This way is used to avoid that those completed async transfer events don't get
1093 // handled in time and are flushed by newer coming events.
1095 if (IsTransferRingTrb (TRBPtr
, Urb
)) {
1097 } else if (IsAsyncIntTrb (Xhc
, TRBPtr
, &AsyncUrb
)) {
1098 CheckedUrb
= AsyncUrb
;
1103 switch (EvtTrb
->Completecode
) {
1104 case TRB_COMPLETION_STALL_ERROR
:
1105 CheckedUrb
->Result
|= EFI_USB_ERR_STALL
;
1106 CheckedUrb
->Finished
= TRUE
;
1107 DEBUG ((EFI_D_ERROR
, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n",EvtTrb
->Completecode
));
1110 case TRB_COMPLETION_BABBLE_ERROR
:
1111 CheckedUrb
->Result
|= EFI_USB_ERR_BABBLE
;
1112 CheckedUrb
->Finished
= TRUE
;
1113 DEBUG ((EFI_D_ERROR
, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n",EvtTrb
->Completecode
));
1116 case TRB_COMPLETION_DATA_BUFFER_ERROR
:
1117 CheckedUrb
->Result
|= EFI_USB_ERR_BUFFER
;
1118 CheckedUrb
->Finished
= TRUE
;
1119 DEBUG ((EFI_D_ERROR
, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n",EvtTrb
->Completecode
));
1122 case TRB_COMPLETION_USB_TRANSACTION_ERROR
:
1123 CheckedUrb
->Result
|= EFI_USB_ERR_TIMEOUT
;
1124 CheckedUrb
->Finished
= TRUE
;
1125 DEBUG ((EFI_D_ERROR
, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n",EvtTrb
->Completecode
));
1128 case TRB_COMPLETION_SHORT_PACKET
:
1129 case TRB_COMPLETION_SUCCESS
:
1130 if (EvtTrb
->Completecode
== TRB_COMPLETION_SHORT_PACKET
) {
1131 DEBUG ((EFI_D_ERROR
, "XhcCheckUrbResult: short packet happens!\n"));
1134 TRBType
= (UINT8
) (TRBPtr
->Type
);
1135 if ((TRBType
== TRB_TYPE_DATA_STAGE
) ||
1136 (TRBType
== TRB_TYPE_NORMAL
) ||
1137 (TRBType
== TRB_TYPE_ISOCH
)) {
1138 CheckedUrb
->Completed
+= (CheckedUrb
->DataLen
- EvtTrb
->Lenth
);
1144 DEBUG ((EFI_D_ERROR
, "Transfer Default Error Occur! Completecode = 0x%x!\n",EvtTrb
->Completecode
));
1145 CheckedUrb
->Result
|= EFI_USB_ERR_TIMEOUT
;
1146 CheckedUrb
->Finished
= TRUE
;
1151 // Only check first and end Trb event address
1153 if (TRBPtr
== CheckedUrb
->TrbStart
) {
1154 CheckedUrb
->StartDone
= TRUE
;
1157 if (TRBPtr
== CheckedUrb
->TrbEnd
) {
1158 CheckedUrb
->EndDone
= TRUE
;
1161 if (CheckedUrb
->StartDone
&& CheckedUrb
->EndDone
) {
1162 CheckedUrb
->Finished
= TRUE
;
1163 CheckedUrb
->EvtTrb
= (TRB_TEMPLATE
*)EvtTrb
;
1170 // Advance event ring to last available entry
1172 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
1173 // So divide it to two 32-bytes width register access.
1175 Low
= XhcReadRuntimeReg (Xhc
, XHC_ERDP_OFFSET
);
1176 High
= XhcReadRuntimeReg (Xhc
, XHC_ERDP_OFFSET
+ 4);
1177 XhcDequeue
= (UINT64
)(LShiftU64((UINT64
)High
, 32) | Low
);
1179 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Xhc
->EventRing
.EventRingDequeue
, sizeof (TRB_TEMPLATE
));
1181 if ((XhcDequeue
& (~0x0F)) != (PhyAddr
& (~0x0F))) {
1183 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
1184 // So divide it to two 32-bytes width register access.
1186 XhcWriteRuntimeReg (Xhc
, XHC_ERDP_OFFSET
, XHC_LOW_32BIT (PhyAddr
) | BIT3
);
1187 XhcWriteRuntimeReg (Xhc
, XHC_ERDP_OFFSET
+ 4, XHC_HIGH_32BIT (PhyAddr
));
1195 Execute the transfer by polling the URB. This is a synchronous operation.
1197 @param Xhc The XHCI Instance.
1198 @param CmdTransfer The executed URB is for cmd transfer or not.
1199 @param Urb The URB to execute.
1200 @param Timeout The time to wait before abort, in millisecond.
1202 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
1203 @return EFI_TIMEOUT The transfer failed due to time out.
1204 @return EFI_SUCCESS The transfer finished OK.
1209 IN USB_XHCI_INSTANCE
*Xhc
,
1210 IN BOOLEAN CmdTransfer
,
1225 SlotId
= XhcBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
1227 return EFI_DEVICE_ERROR
;
1229 Dci
= XhcEndpointToDci (Urb
->Ep
.EpAddr
, (UINT8
)(Urb
->Ep
.Direction
));
1233 Status
= EFI_SUCCESS
;
1234 Loop
= Timeout
* XHC_1_MILLISECOND
;
1239 XhcRingDoorBell (Xhc
, SlotId
, Dci
);
1241 for (Index
= 0; Index
< Loop
; Index
++) {
1242 Status
= XhcCheckUrbResult (Xhc
, Urb
);
1243 if (Urb
->Finished
) {
1246 gBS
->Stall (XHC_1_MICROSECOND
);
1249 if (Index
== Loop
) {
1250 Urb
->Result
= EFI_USB_ERR_TIMEOUT
;
1257 Delete a single asynchronous interrupt transfer for
1258 the device and endpoint.
1260 @param Xhc The XHCI Instance.
1261 @param BusAddr The logical device address assigned by UsbBus driver.
1262 @param EpNum The endpoint of the target.
1264 @retval EFI_SUCCESS An asynchronous transfer is removed.
1265 @retval EFI_NOT_FOUND No transfer for the device is found.
1269 XhciDelAsyncIntTransfer (
1270 IN USB_XHCI_INSTANCE
*Xhc
,
1278 EFI_USB_DATA_DIRECTION Direction
;
1280 Direction
= ((EpNum
& 0x80) != 0) ? EfiUsbDataIn
: EfiUsbDataOut
;
1285 EFI_LIST_FOR_EACH_SAFE (Entry
, Next
, &Xhc
->AsyncIntTransfers
) {
1286 Urb
= EFI_LIST_CONTAINER (Entry
, URB
, UrbList
);
1287 if ((Urb
->Ep
.BusAddr
== BusAddr
) &&
1288 (Urb
->Ep
.EpAddr
== EpNum
) &&
1289 (Urb
->Ep
.Direction
== Direction
)) {
1290 RemoveEntryList (&Urb
->UrbList
);
1291 FreePool (Urb
->Data
);
1292 XhcFreeUrb (Xhc
, Urb
);
1297 return EFI_NOT_FOUND
;
1301 Remove all the asynchronous interrutp transfers.
1303 @param Xhc The XHCI Instance.
1307 XhciDelAllAsyncIntTransfers (
1308 IN USB_XHCI_INSTANCE
*Xhc
1315 EFI_LIST_FOR_EACH_SAFE (Entry
, Next
, &Xhc
->AsyncIntTransfers
) {
1316 Urb
= EFI_LIST_CONTAINER (Entry
, URB
, UrbList
);
1317 RemoveEntryList (&Urb
->UrbList
);
1318 FreePool (Urb
->Data
);
1319 XhcFreeUrb (Xhc
, Urb
);
1324 Update the queue head for next round of asynchronous transfer
1326 @param Xhc The XHCI Instance.
1327 @param Urb The URB to update
1331 XhcUpdateAsyncRequest (
1332 IN USB_XHCI_INSTANCE
*Xhc
,
1338 if (Urb
->Result
== EFI_USB_NOERROR
) {
1339 Status
= XhcCreateTransferTrb (Xhc
, Urb
);
1340 if (EFI_ERROR (Status
)) {
1343 Status
= RingIntTransferDoorBell (Xhc
, Urb
);
1344 if (EFI_ERROR (Status
)) {
1351 Flush data from PCI controller specific address to mapped system
1354 @param Xhc The XHCI device.
1355 @param Urb The URB to unmap.
1357 @retval EFI_SUCCESS Success to flush data to mapped system memory.
1358 @retval EFI_DEVICE_ERROR Fail to flush data to mapped system memory.
1362 XhcFlushAsyncIntMap (
1363 IN USB_XHCI_INSTANCE
*Xhc
,
1368 EFI_PHYSICAL_ADDRESS PhyAddr
;
1369 EFI_PCI_IO_PROTOCOL_OPERATION MapOp
;
1370 EFI_PCI_IO_PROTOCOL
*PciIo
;
1377 if (Urb
->Ep
.Direction
== EfiUsbDataIn
) {
1378 MapOp
= EfiPciIoOperationBusMasterWrite
;
1380 MapOp
= EfiPciIoOperationBusMasterRead
;
1383 if (Urb
->DataMap
!= NULL
) {
1384 Status
= PciIo
->Unmap (PciIo
, Urb
->DataMap
);
1385 if (EFI_ERROR (Status
)) {
1390 Urb
->DataMap
= NULL
;
1392 Status
= PciIo
->Map (PciIo
, MapOp
, Urb
->Data
, &Len
, &PhyAddr
, &Map
);
1393 if (EFI_ERROR (Status
) || (Len
!= Urb
->DataLen
)) {
1397 Urb
->DataPhy
= (VOID
*) ((UINTN
) PhyAddr
);
1402 return EFI_DEVICE_ERROR
;
1406 Interrupt transfer periodic check handler.
1408 @param Event Interrupt event.
1409 @param Context Pointer to USB_XHCI_INSTANCE.
1414 XhcMonitorAsyncRequests (
1419 USB_XHCI_INSTANCE
*Xhc
;
1428 OldTpl
= gBS
->RaiseTPL (XHC_TPL
);
1430 Xhc
= (USB_XHCI_INSTANCE
*) Context
;
1432 EFI_LIST_FOR_EACH_SAFE (Entry
, Next
, &Xhc
->AsyncIntTransfers
) {
1433 Urb
= EFI_LIST_CONTAINER (Entry
, URB
, UrbList
);
1436 // Make sure that the device is available before every check.
1438 SlotId
= XhcBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
1444 // Check the result of URB execution. If it is still
1445 // active, check the next one.
1447 XhcCheckUrbResult (Xhc
, Urb
);
1449 if (!Urb
->Finished
) {
1454 // Flush any PCI posted write transactions from a PCI host
1455 // bridge to system memory.
1457 Status
= XhcFlushAsyncIntMap (Xhc
, Urb
);
1458 if (EFI_ERROR (Status
)) {
1459 DEBUG ((EFI_D_ERROR
, "XhcMonitorAsyncRequests: Fail to Flush AsyncInt Mapped Memeory\n"));
1463 // Allocate a buffer then copy the transferred data for user.
1464 // If failed to allocate the buffer, update the URB for next
1465 // round of transfer. Ignore the data of this round.
1468 if (Urb
->Result
== EFI_USB_NOERROR
) {
1469 ASSERT (Urb
->Completed
<= Urb
->DataLen
);
1471 ProcBuf
= AllocateZeroPool (Urb
->Completed
);
1473 if (ProcBuf
== NULL
) {
1474 XhcUpdateAsyncRequest (Xhc
, Urb
);
1478 CopyMem (ProcBuf
, Urb
->Data
, Urb
->Completed
);
1482 // Leave error recovery to its related device driver. A
1483 // common case of the error recovery is to re-submit the
1484 // interrupt transfer which is linked to the head of the
1485 // list. This function scans from head to tail. So the
1486 // re-submitted interrupt transfer's callback function
1487 // will not be called again in this round. Don't touch this
1488 // URB after the callback, it may have been removed by the
1491 if (Urb
->Callback
!= NULL
) {
1493 // Restore the old TPL, USB bus maybe connect device in
1494 // his callback. Some drivers may has a lower TPL restriction.
1496 gBS
->RestoreTPL (OldTpl
);
1497 (Urb
->Callback
) (ProcBuf
, Urb
->Completed
, Urb
->Context
, Urb
->Result
);
1498 OldTpl
= gBS
->RaiseTPL (XHC_TPL
);
1501 if (ProcBuf
!= NULL
) {
1502 gBS
->FreePool (ProcBuf
);
1505 XhcUpdateAsyncRequest (Xhc
, Urb
);
1507 gBS
->RestoreTPL (OldTpl
);
1511 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.
1513 @param Xhc The XHCI Instance.
1514 @param ParentRouteChart The route string pointed to the parent device if it exists.
1515 @param Port The port to be polled.
1516 @param PortState The port state.
1518 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.
1519 @retval Others Should not appear.
1524 XhcPollPortStatusChange (
1525 IN USB_XHCI_INSTANCE
*Xhc
,
1526 IN USB_DEV_ROUTE ParentRouteChart
,
1528 IN EFI_USB_PORT_STATUS
*PortState
1534 USB_DEV_ROUTE RouteChart
;
1536 Status
= EFI_SUCCESS
;
1538 if ((PortState
->PortChangeStatus
& (USB_PORT_STAT_C_CONNECTION
| USB_PORT_STAT_C_ENABLE
| USB_PORT_STAT_C_OVERCURRENT
| USB_PORT_STAT_C_RESET
)) == 0) {
1542 if (ParentRouteChart
.Dword
== 0) {
1543 RouteChart
.Route
.RouteString
= 0;
1544 RouteChart
.Route
.RootPortNum
= Port
+ 1;
1545 RouteChart
.Route
.TierNum
= 1;
1548 RouteChart
.Route
.RouteString
= ParentRouteChart
.Route
.RouteString
| (Port
<< (4 * (ParentRouteChart
.Route
.TierNum
- 1)));
1550 RouteChart
.Route
.RouteString
= ParentRouteChart
.Route
.RouteString
| (15 << (4 * (ParentRouteChart
.Route
.TierNum
- 1)));
1552 RouteChart
.Route
.RootPortNum
= ParentRouteChart
.Route
.RootPortNum
;
1553 RouteChart
.Route
.TierNum
= ParentRouteChart
.Route
.TierNum
+ 1;
1556 SlotId
= XhcRouteStringToSlotId (Xhc
, RouteChart
);
1558 if (Xhc
->HcCParams
.Data
.Csz
== 0) {
1559 Status
= XhcDisableSlotCmd (Xhc
, SlotId
);
1561 Status
= XhcDisableSlotCmd64 (Xhc
, SlotId
);
1565 if (((PortState
->PortStatus
& USB_PORT_STAT_ENABLE
) != 0) &&
1566 ((PortState
->PortStatus
& USB_PORT_STAT_CONNECTION
) != 0)) {
1568 // Has a device attached, Identify device speed after port is enabled.
1570 Speed
= EFI_USB_SPEED_FULL
;
1571 if ((PortState
->PortStatus
& USB_PORT_STAT_LOW_SPEED
) != 0) {
1572 Speed
= EFI_USB_SPEED_LOW
;
1573 } else if ((PortState
->PortStatus
& USB_PORT_STAT_HIGH_SPEED
) != 0) {
1574 Speed
= EFI_USB_SPEED_HIGH
;
1575 } else if ((PortState
->PortStatus
& USB_PORT_STAT_SUPER_SPEED
) != 0) {
1576 Speed
= EFI_USB_SPEED_SUPER
;
1579 // Execute Enable_Slot cmd for attached device, initialize device context and assign device address.
1581 SlotId
= XhcRouteStringToSlotId (Xhc
, RouteChart
);
1582 if ((SlotId
== 0) && ((PortState
->PortChangeStatus
& USB_PORT_STAT_C_RESET
) != 0)) {
1583 if (Xhc
->HcCParams
.Data
.Csz
== 0) {
1584 Status
= XhcInitializeDeviceSlot (Xhc
, ParentRouteChart
, Port
, RouteChart
, Speed
);
1586 Status
= XhcInitializeDeviceSlot64 (Xhc
, ParentRouteChart
, Port
, RouteChart
, Speed
);
1596 Calculate the device context index by endpoint address and direction.
1598 @param EpAddr The target endpoint number.
1599 @param Direction The direction of the target endpoint.
1601 @return The device context index of endpoint.
1615 Index
= (UINT8
) (2 * EpAddr
);
1616 if (Direction
== EfiUsbDataIn
) {
1624 Find out the actual device address according to the requested device address from UsbBus.
1626 @param Xhc The XHCI Instance.
1627 @param BusDevAddr The requested device address by UsbBus upper driver.
1629 @return The actual device address assigned to the device.
1634 XhcBusDevAddrToSlotId (
1635 IN USB_XHCI_INSTANCE
*Xhc
,
1641 for (Index
= 0; Index
< 255; Index
++) {
1642 if (Xhc
->UsbDevContext
[Index
+ 1].Enabled
&&
1643 (Xhc
->UsbDevContext
[Index
+ 1].SlotId
!= 0) &&
1644 (Xhc
->UsbDevContext
[Index
+ 1].BusDevAddr
== BusDevAddr
)) {
1653 return Xhc
->UsbDevContext
[Index
+ 1].SlotId
;
1657 Find out the slot id according to the device's route string.
1659 @param Xhc The XHCI Instance.
1660 @param RouteString The route string described the device location.
1662 @return The slot id used by the device.
1667 XhcRouteStringToSlotId (
1668 IN USB_XHCI_INSTANCE
*Xhc
,
1669 IN USB_DEV_ROUTE RouteString
1674 for (Index
= 0; Index
< 255; Index
++) {
1675 if (Xhc
->UsbDevContext
[Index
+ 1].Enabled
&&
1676 (Xhc
->UsbDevContext
[Index
+ 1].SlotId
!= 0) &&
1677 (Xhc
->UsbDevContext
[Index
+ 1].RouteString
.Dword
== RouteString
.Dword
)) {
1686 return Xhc
->UsbDevContext
[Index
+ 1].SlotId
;
1690 Synchronize the specified event ring to update the enqueue and dequeue pointer.
1692 @param Xhc The XHCI Instance.
1693 @param EvtRing The event ring to sync.
1695 @retval EFI_SUCCESS The event ring is synchronized successfully.
1701 IN USB_XHCI_INSTANCE
*Xhc
,
1702 IN EVENT_RING
*EvtRing
1706 TRB_TEMPLATE
*EvtTrb1
;
1708 ASSERT (EvtRing
!= NULL
);
1711 // Calculate the EventRingEnqueue and EventRingCCS.
1712 // Note: only support single Segment
1714 EvtTrb1
= EvtRing
->EventRingDequeue
;
1716 for (Index
= 0; Index
< EvtRing
->TrbNumber
; Index
++) {
1717 if (EvtTrb1
->CycleBit
!= EvtRing
->EventRingCCS
) {
1723 if ((UINTN
)EvtTrb1
>= ((UINTN
) EvtRing
->EventRingSeg0
+ sizeof (TRB_TEMPLATE
) * EvtRing
->TrbNumber
)) {
1724 EvtTrb1
= EvtRing
->EventRingSeg0
;
1725 EvtRing
->EventRingCCS
= (EvtRing
->EventRingCCS
) ? 0 : 1;
1729 if (Index
< EvtRing
->TrbNumber
) {
1730 EvtRing
->EventRingEnqueue
= EvtTrb1
;
1739 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
1741 @param Xhc The XHCI Instance.
1742 @param TrsRing The transfer ring to sync.
1744 @retval EFI_SUCCESS The transfer ring is synchronized successfully.
1750 IN USB_XHCI_INSTANCE
*Xhc
,
1751 IN TRANSFER_RING
*TrsRing
1755 TRB_TEMPLATE
*TrsTrb
;
1757 ASSERT (TrsRing
!= NULL
);
1759 // Calculate the latest RingEnqueue and RingPCS
1761 TrsTrb
= TrsRing
->RingEnqueue
;
1762 ASSERT (TrsTrb
!= NULL
);
1764 for (Index
= 0; Index
< TrsRing
->TrbNumber
; Index
++) {
1765 if (TrsTrb
->CycleBit
!= (TrsRing
->RingPCS
& BIT0
)) {
1769 if ((UINT8
) TrsTrb
->Type
== TRB_TYPE_LINK
) {
1770 ASSERT (((LINK_TRB
*)TrsTrb
)->TC
!= 0);
1772 // set cycle bit in Link TRB as normal
1774 ((LINK_TRB
*)TrsTrb
)->CycleBit
= TrsRing
->RingPCS
& BIT0
;
1776 // Toggle PCS maintained by software
1778 TrsRing
->RingPCS
= (TrsRing
->RingPCS
& BIT0
) ? 0 : 1;
1779 TrsTrb
= (TRB_TEMPLATE
*) TrsRing
->RingSeg0
; // Use host address
1783 ASSERT (Index
!= TrsRing
->TrbNumber
);
1785 if (TrsTrb
!= TrsRing
->RingEnqueue
) {
1786 TrsRing
->RingEnqueue
= TrsTrb
;
1790 // Clear the Trb context for enqueue, but reserve the PCS bit
1792 TrsTrb
->Parameter1
= 0;
1793 TrsTrb
->Parameter2
= 0;
1797 TrsTrb
->Control
= 0;
1803 Check if there is a new generated event.
1805 @param Xhc The XHCI Instance.
1806 @param EvtRing The event ring to check.
1807 @param NewEvtTrb The new event TRB found.
1809 @retval EFI_SUCCESS Found a new event TRB at the event ring.
1810 @retval EFI_NOT_READY The event ring has no new event.
1816 IN USB_XHCI_INSTANCE
*Xhc
,
1817 IN EVENT_RING
*EvtRing
,
1818 OUT TRB_TEMPLATE
**NewEvtTrb
1821 ASSERT (EvtRing
!= NULL
);
1823 *NewEvtTrb
= EvtRing
->EventRingDequeue
;
1825 if (EvtRing
->EventRingDequeue
== EvtRing
->EventRingEnqueue
) {
1826 return EFI_NOT_READY
;
1829 EvtRing
->EventRingDequeue
++;
1831 // If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.
1833 if ((UINTN
)EvtRing
->EventRingDequeue
>= ((UINTN
) EvtRing
->EventRingSeg0
+ sizeof (TRB_TEMPLATE
) * EvtRing
->TrbNumber
)) {
1834 EvtRing
->EventRingDequeue
= EvtRing
->EventRingSeg0
;
1841 Ring the door bell to notify XHCI there is a transaction to be executed.
1843 @param Xhc The XHCI Instance.
1844 @param SlotId The slot id of the target device.
1845 @param Dci The device context index of the target slot or endpoint.
1847 @retval EFI_SUCCESS Successfully ring the door bell.
1853 IN USB_XHCI_INSTANCE
*Xhc
,
1859 XhcWriteDoorBellReg (Xhc
, 0, 0);
1861 XhcWriteDoorBellReg (Xhc
, SlotId
* sizeof (UINT32
), Dci
);
1868 Ring the door bell to notify XHCI there is a transaction to be executed through URB.
1870 @param Xhc The XHCI Instance.
1871 @param Urb The URB to be rung.
1873 @retval EFI_SUCCESS Successfully ring the door bell.
1877 RingIntTransferDoorBell (
1878 IN USB_XHCI_INSTANCE
*Xhc
,
1885 SlotId
= XhcBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
1886 Dci
= XhcEndpointToDci (Urb
->Ep
.EpAddr
, (UINT8
)(Urb
->Ep
.Direction
));
1887 XhcRingDoorBell (Xhc
, SlotId
, Dci
);
1892 Assign and initialize the device slot for a new device.
1894 @param Xhc The XHCI Instance.
1895 @param ParentRouteChart The route string pointed to the parent device.
1896 @param ParentPort The port at which the device is located.
1897 @param RouteChart The route string pointed to the device.
1898 @param DeviceSpeed The device speed.
1900 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1905 XhcInitializeDeviceSlot (
1906 IN USB_XHCI_INSTANCE
*Xhc
,
1907 IN USB_DEV_ROUTE ParentRouteChart
,
1908 IN UINT16 ParentPort
,
1909 IN USB_DEV_ROUTE RouteChart
,
1910 IN UINT8 DeviceSpeed
1914 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
1915 INPUT_CONTEXT
*InputContext
;
1916 DEVICE_CONTEXT
*OutputContext
;
1917 TRANSFER_RING
*EndpointTransferRing
;
1918 CMD_TRB_ADDRESS_DEVICE CmdTrbAddr
;
1919 UINT8 DeviceAddress
;
1920 CMD_TRB_ENABLE_SLOT CmdTrb
;
1923 DEVICE_CONTEXT
*ParentDeviceContext
;
1924 EFI_PHYSICAL_ADDRESS PhyAddr
;
1926 ZeroMem (&CmdTrb
, sizeof (CMD_TRB_ENABLE_SLOT
));
1927 CmdTrb
.CycleBit
= 1;
1928 CmdTrb
.Type
= TRB_TYPE_EN_SLOT
;
1930 Status
= XhcCmdTransfer (
1932 (TRB_TEMPLATE
*) (UINTN
) &CmdTrb
,
1933 XHC_GENERIC_TIMEOUT
,
1934 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
1936 if (EFI_ERROR (Status
)) {
1937 DEBUG ((EFI_D_ERROR
, "XhcInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status
));
1940 ASSERT (EvtTrb
->SlotId
<= Xhc
->MaxSlotsEn
);
1941 DEBUG ((EFI_D_INFO
, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb
->SlotId
));
1942 SlotId
= (UINT8
)EvtTrb
->SlotId
;
1943 ASSERT (SlotId
!= 0);
1945 ZeroMem (&Xhc
->UsbDevContext
[SlotId
], sizeof (USB_DEV_CONTEXT
));
1946 Xhc
->UsbDevContext
[SlotId
].Enabled
= TRUE
;
1947 Xhc
->UsbDevContext
[SlotId
].SlotId
= SlotId
;
1948 Xhc
->UsbDevContext
[SlotId
].RouteString
.Dword
= RouteChart
.Dword
;
1949 Xhc
->UsbDevContext
[SlotId
].ParentRouteString
.Dword
= ParentRouteChart
.Dword
;
1952 // 4.3.3 Device Slot Initialization
1953 // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
1955 InputContext
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (INPUT_CONTEXT
));
1956 ASSERT (InputContext
!= NULL
);
1957 ASSERT (((UINTN
) InputContext
& 0x3F) == 0);
1958 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
1960 Xhc
->UsbDevContext
[SlotId
].InputContext
= (VOID
*) InputContext
;
1963 // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
1964 // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input
1965 // Context are affected by the command.
1967 InputContext
->InputControlContext
.Dword2
|= (BIT0
| BIT1
);
1970 // 3) Initialize the Input Slot Context data structure
1972 InputContext
->Slot
.RouteString
= RouteChart
.Route
.RouteString
;
1973 InputContext
->Slot
.Speed
= DeviceSpeed
+ 1;
1974 InputContext
->Slot
.ContextEntries
= 1;
1975 InputContext
->Slot
.RootHubPortNum
= RouteChart
.Route
.RootPortNum
;
1977 if (RouteChart
.Route
.RouteString
) {
1979 // The device is behind of hub device.
1981 ParentSlotId
= XhcRouteStringToSlotId(Xhc
, ParentRouteChart
);
1982 ASSERT (ParentSlotId
!= 0);
1984 //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
1986 ParentDeviceContext
= (DEVICE_CONTEXT
*)Xhc
->UsbDevContext
[ParentSlotId
].OutputContext
;
1987 if ((ParentDeviceContext
->Slot
.TTPortNum
== 0) &&
1988 (ParentDeviceContext
->Slot
.TTHubSlotId
== 0)) {
1989 if ((ParentDeviceContext
->Slot
.Speed
== (EFI_USB_SPEED_HIGH
+ 1)) && (DeviceSpeed
< EFI_USB_SPEED_HIGH
)) {
1991 // Full/Low device attached to High speed hub port that isolates the high speed signaling
1992 // environment from Full/Low speed signaling environment for a device
1994 InputContext
->Slot
.TTPortNum
= ParentPort
;
1995 InputContext
->Slot
.TTHubSlotId
= ParentSlotId
;
1999 // Inherit the TT parameters from parent device.
2001 InputContext
->Slot
.TTPortNum
= ParentDeviceContext
->Slot
.TTPortNum
;
2002 InputContext
->Slot
.TTHubSlotId
= ParentDeviceContext
->Slot
.TTHubSlotId
;
2004 // If the device is a High speed device then down the speed to be the same as its parent Hub
2006 if (DeviceSpeed
== EFI_USB_SPEED_HIGH
) {
2007 InputContext
->Slot
.Speed
= ParentDeviceContext
->Slot
.Speed
;
2013 // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
2015 EndpointTransferRing
= AllocateZeroPool (sizeof (TRANSFER_RING
));
2016 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0] = EndpointTransferRing
;
2017 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0]);
2019 // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
2021 InputContext
->EP
[0].EPType
= ED_CONTROL_BIDIR
;
2023 if (DeviceSpeed
== EFI_USB_SPEED_SUPER
) {
2024 InputContext
->EP
[0].MaxPacketSize
= 512;
2025 } else if (DeviceSpeed
== EFI_USB_SPEED_HIGH
) {
2026 InputContext
->EP
[0].MaxPacketSize
= 64;
2028 InputContext
->EP
[0].MaxPacketSize
= 8;
2031 // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
2032 // 1KB, and Bulk and Isoch endpoints 3KB.
2034 InputContext
->EP
[0].AverageTRBLength
= 8;
2035 InputContext
->EP
[0].MaxBurstSize
= 0;
2036 InputContext
->EP
[0].Interval
= 0;
2037 InputContext
->EP
[0].MaxPStreams
= 0;
2038 InputContext
->EP
[0].Mult
= 0;
2039 InputContext
->EP
[0].CErr
= 3;
2042 // Init the DCS(dequeue cycle state) as the transfer ring's CCS
2044 PhyAddr
= UsbHcGetPciAddrForHostAddr (
2046 ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0])->RingSeg0
,
2047 sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
2049 InputContext
->EP
[0].PtrLo
= XHC_LOW_32BIT (PhyAddr
) | BIT0
;
2050 InputContext
->EP
[0].PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2053 // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
2055 OutputContext
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (DEVICE_CONTEXT
));
2056 ASSERT (OutputContext
!= NULL
);
2057 ASSERT (((UINTN
) OutputContext
& 0x3F) == 0);
2058 ZeroMem (OutputContext
, sizeof (DEVICE_CONTEXT
));
2060 Xhc
->UsbDevContext
[SlotId
].OutputContext
= OutputContext
;
2062 // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
2063 // a pointer to the Output Device Context data structure (6.2.1).
2065 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, OutputContext
, sizeof (DEVICE_CONTEXT
));
2067 // Fill DCBAA with PCI device address
2069 Xhc
->DCBAA
[SlotId
] = (UINT64
) (UINTN
) PhyAddr
;
2072 // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
2073 // Context data structure described above.
2075 ZeroMem (&CmdTrbAddr
, sizeof (CmdTrbAddr
));
2076 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].InputContext
, sizeof (INPUT_CONTEXT
));
2077 CmdTrbAddr
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2078 CmdTrbAddr
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2079 CmdTrbAddr
.CycleBit
= 1;
2080 CmdTrbAddr
.Type
= TRB_TYPE_ADDRESS_DEV
;
2081 CmdTrbAddr
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
2082 Status
= XhcCmdTransfer (
2084 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbAddr
,
2085 XHC_GENERIC_TIMEOUT
,
2086 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2088 if (!EFI_ERROR (Status
)) {
2089 DeviceAddress
= (UINT8
) ((DEVICE_CONTEXT
*) OutputContext
)->Slot
.DeviceAddress
;
2090 DEBUG ((EFI_D_INFO
, " Address %d assigned successfully\n", DeviceAddress
));
2091 Xhc
->UsbDevContext
[SlotId
].XhciDevAddr
= DeviceAddress
;
2098 Assign and initialize the device slot for a new device.
2100 @param Xhc The XHCI Instance.
2101 @param ParentRouteChart The route string pointed to the parent device.
2102 @param ParentPort The port at which the device is located.
2103 @param RouteChart The route string pointed to the device.
2104 @param DeviceSpeed The device speed.
2106 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
2111 XhcInitializeDeviceSlot64 (
2112 IN USB_XHCI_INSTANCE
*Xhc
,
2113 IN USB_DEV_ROUTE ParentRouteChart
,
2114 IN UINT16 ParentPort
,
2115 IN USB_DEV_ROUTE RouteChart
,
2116 IN UINT8 DeviceSpeed
2120 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
2121 INPUT_CONTEXT_64
*InputContext
;
2122 DEVICE_CONTEXT_64
*OutputContext
;
2123 TRANSFER_RING
*EndpointTransferRing
;
2124 CMD_TRB_ADDRESS_DEVICE CmdTrbAddr
;
2125 UINT8 DeviceAddress
;
2126 CMD_TRB_ENABLE_SLOT CmdTrb
;
2129 DEVICE_CONTEXT_64
*ParentDeviceContext
;
2130 EFI_PHYSICAL_ADDRESS PhyAddr
;
2132 ZeroMem (&CmdTrb
, sizeof (CMD_TRB_ENABLE_SLOT
));
2133 CmdTrb
.CycleBit
= 1;
2134 CmdTrb
.Type
= TRB_TYPE_EN_SLOT
;
2136 Status
= XhcCmdTransfer (
2138 (TRB_TEMPLATE
*) (UINTN
) &CmdTrb
,
2139 XHC_GENERIC_TIMEOUT
,
2140 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2142 if (EFI_ERROR (Status
)) {
2143 DEBUG ((EFI_D_ERROR
, "XhcInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status
));
2146 ASSERT (EvtTrb
->SlotId
<= Xhc
->MaxSlotsEn
);
2147 DEBUG ((EFI_D_INFO
, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb
->SlotId
));
2148 SlotId
= (UINT8
)EvtTrb
->SlotId
;
2149 ASSERT (SlotId
!= 0);
2151 ZeroMem (&Xhc
->UsbDevContext
[SlotId
], sizeof (USB_DEV_CONTEXT
));
2152 Xhc
->UsbDevContext
[SlotId
].Enabled
= TRUE
;
2153 Xhc
->UsbDevContext
[SlotId
].SlotId
= SlotId
;
2154 Xhc
->UsbDevContext
[SlotId
].RouteString
.Dword
= RouteChart
.Dword
;
2155 Xhc
->UsbDevContext
[SlotId
].ParentRouteString
.Dword
= ParentRouteChart
.Dword
;
2158 // 4.3.3 Device Slot Initialization
2159 // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
2161 InputContext
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (INPUT_CONTEXT_64
));
2162 ASSERT (InputContext
!= NULL
);
2163 ASSERT (((UINTN
) InputContext
& 0x3F) == 0);
2164 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
2166 Xhc
->UsbDevContext
[SlotId
].InputContext
= (VOID
*) InputContext
;
2169 // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
2170 // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input
2171 // Context are affected by the command.
2173 InputContext
->InputControlContext
.Dword2
|= (BIT0
| BIT1
);
2176 // 3) Initialize the Input Slot Context data structure
2178 InputContext
->Slot
.RouteString
= RouteChart
.Route
.RouteString
;
2179 InputContext
->Slot
.Speed
= DeviceSpeed
+ 1;
2180 InputContext
->Slot
.ContextEntries
= 1;
2181 InputContext
->Slot
.RootHubPortNum
= RouteChart
.Route
.RootPortNum
;
2183 if (RouteChart
.Route
.RouteString
) {
2185 // The device is behind of hub device.
2187 ParentSlotId
= XhcRouteStringToSlotId(Xhc
, ParentRouteChart
);
2188 ASSERT (ParentSlotId
!= 0);
2190 //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
2192 ParentDeviceContext
= (DEVICE_CONTEXT_64
*)Xhc
->UsbDevContext
[ParentSlotId
].OutputContext
;
2193 if ((ParentDeviceContext
->Slot
.TTPortNum
== 0) &&
2194 (ParentDeviceContext
->Slot
.TTHubSlotId
== 0)) {
2195 if ((ParentDeviceContext
->Slot
.Speed
== (EFI_USB_SPEED_HIGH
+ 1)) && (DeviceSpeed
< EFI_USB_SPEED_HIGH
)) {
2197 // Full/Low device attached to High speed hub port that isolates the high speed signaling
2198 // environment from Full/Low speed signaling environment for a device
2200 InputContext
->Slot
.TTPortNum
= ParentPort
;
2201 InputContext
->Slot
.TTHubSlotId
= ParentSlotId
;
2205 // Inherit the TT parameters from parent device.
2207 InputContext
->Slot
.TTPortNum
= ParentDeviceContext
->Slot
.TTPortNum
;
2208 InputContext
->Slot
.TTHubSlotId
= ParentDeviceContext
->Slot
.TTHubSlotId
;
2210 // If the device is a High speed device then down the speed to be the same as its parent Hub
2212 if (DeviceSpeed
== EFI_USB_SPEED_HIGH
) {
2213 InputContext
->Slot
.Speed
= ParentDeviceContext
->Slot
.Speed
;
2219 // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
2221 EndpointTransferRing
= AllocateZeroPool (sizeof (TRANSFER_RING
));
2222 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0] = EndpointTransferRing
;
2223 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0]);
2225 // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
2227 InputContext
->EP
[0].EPType
= ED_CONTROL_BIDIR
;
2229 if (DeviceSpeed
== EFI_USB_SPEED_SUPER
) {
2230 InputContext
->EP
[0].MaxPacketSize
= 512;
2231 } else if (DeviceSpeed
== EFI_USB_SPEED_HIGH
) {
2232 InputContext
->EP
[0].MaxPacketSize
= 64;
2234 InputContext
->EP
[0].MaxPacketSize
= 8;
2237 // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
2238 // 1KB, and Bulk and Isoch endpoints 3KB.
2240 InputContext
->EP
[0].AverageTRBLength
= 8;
2241 InputContext
->EP
[0].MaxBurstSize
= 0;
2242 InputContext
->EP
[0].Interval
= 0;
2243 InputContext
->EP
[0].MaxPStreams
= 0;
2244 InputContext
->EP
[0].Mult
= 0;
2245 InputContext
->EP
[0].CErr
= 3;
2248 // Init the DCS(dequeue cycle state) as the transfer ring's CCS
2250 PhyAddr
= UsbHcGetPciAddrForHostAddr (
2252 ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0])->RingSeg0
,
2253 sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
2255 InputContext
->EP
[0].PtrLo
= XHC_LOW_32BIT (PhyAddr
) | BIT0
;
2256 InputContext
->EP
[0].PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2259 // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
2261 OutputContext
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (DEVICE_CONTEXT_64
));
2262 ASSERT (OutputContext
!= NULL
);
2263 ASSERT (((UINTN
) OutputContext
& 0x3F) == 0);
2264 ZeroMem (OutputContext
, sizeof (DEVICE_CONTEXT_64
));
2266 Xhc
->UsbDevContext
[SlotId
].OutputContext
= OutputContext
;
2268 // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
2269 // a pointer to the Output Device Context data structure (6.2.1).
2271 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, OutputContext
, sizeof (DEVICE_CONTEXT_64
));
2273 // Fill DCBAA with PCI device address
2275 Xhc
->DCBAA
[SlotId
] = (UINT64
) (UINTN
) PhyAddr
;
2278 // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
2279 // Context data structure described above.
2281 ZeroMem (&CmdTrbAddr
, sizeof (CmdTrbAddr
));
2282 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].InputContext
, sizeof (INPUT_CONTEXT_64
));
2283 CmdTrbAddr
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2284 CmdTrbAddr
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2285 CmdTrbAddr
.CycleBit
= 1;
2286 CmdTrbAddr
.Type
= TRB_TYPE_ADDRESS_DEV
;
2287 CmdTrbAddr
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
2288 Status
= XhcCmdTransfer (
2290 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbAddr
,
2291 XHC_GENERIC_TIMEOUT
,
2292 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2294 if (!EFI_ERROR (Status
)) {
2295 DeviceAddress
= (UINT8
) ((DEVICE_CONTEXT_64
*) OutputContext
)->Slot
.DeviceAddress
;
2296 DEBUG ((EFI_D_INFO
, " Address %d assigned successfully\n", DeviceAddress
));
2297 Xhc
->UsbDevContext
[SlotId
].XhciDevAddr
= DeviceAddress
;
2304 Disable the specified device slot.
2306 @param Xhc The XHCI Instance.
2307 @param SlotId The slot id to be disabled.
2309 @retval EFI_SUCCESS Successfully disable the device slot.
2315 IN USB_XHCI_INSTANCE
*Xhc
,
2320 TRB_TEMPLATE
*EvtTrb
;
2321 CMD_TRB_DISABLE_SLOT CmdTrbDisSlot
;
2326 // Disable the device slots occupied by these devices on its downstream ports.
2327 // Entry 0 is reserved.
2329 for (Index
= 0; Index
< 255; Index
++) {
2330 if (!Xhc
->UsbDevContext
[Index
+ 1].Enabled
||
2331 (Xhc
->UsbDevContext
[Index
+ 1].SlotId
== 0) ||
2332 (Xhc
->UsbDevContext
[Index
+ 1].ParentRouteString
.Dword
!= Xhc
->UsbDevContext
[SlotId
].RouteString
.Dword
)) {
2336 Status
= XhcDisableSlotCmd (Xhc
, Xhc
->UsbDevContext
[Index
+ 1].SlotId
);
2338 if (EFI_ERROR (Status
)) {
2339 DEBUG ((EFI_D_ERROR
, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
2340 Xhc
->UsbDevContext
[Index
+ 1].SlotId
= 0;
2345 // Construct the disable slot command
2347 DEBUG ((EFI_D_INFO
, "Disable device slot %d!\n", SlotId
));
2349 ZeroMem (&CmdTrbDisSlot
, sizeof (CmdTrbDisSlot
));
2350 CmdTrbDisSlot
.CycleBit
= 1;
2351 CmdTrbDisSlot
.Type
= TRB_TYPE_DIS_SLOT
;
2352 CmdTrbDisSlot
.SlotId
= SlotId
;
2353 Status
= XhcCmdTransfer (
2355 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbDisSlot
,
2356 XHC_GENERIC_TIMEOUT
,
2357 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2359 if (EFI_ERROR (Status
)) {
2360 DEBUG ((EFI_D_ERROR
, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status
));
2364 // Free the slot's device context entry
2366 Xhc
->DCBAA
[SlotId
] = 0;
2369 // Free the slot related data structure
2371 for (Index
= 0; Index
< 31; Index
++) {
2372 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
] != NULL
) {
2373 RingSeg
= ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
])->RingSeg0
;
2374 if (RingSeg
!= NULL
) {
2375 UsbHcFreeMem (Xhc
->MemPool
, RingSeg
, sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
);
2377 FreePool (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
]);
2378 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
] = NULL
;
2382 for (Index
= 0; Index
< Xhc
->UsbDevContext
[SlotId
].DevDesc
.NumConfigurations
; Index
++) {
2383 if (Xhc
->UsbDevContext
[SlotId
].ConfDesc
[Index
] != NULL
) {
2384 FreePool (Xhc
->UsbDevContext
[SlotId
].ConfDesc
[Index
]);
2388 if (Xhc
->UsbDevContext
[SlotId
].InputContext
!= NULL
) {
2389 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].InputContext
, sizeof (INPUT_CONTEXT
));
2392 if (Xhc
->UsbDevContext
[SlotId
].OutputContext
!= NULL
) {
2393 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].OutputContext
, sizeof (DEVICE_CONTEXT
));
2396 // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
2397 // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
2398 // remove urb from XHCI's asynchronous transfer list.
2400 Xhc
->UsbDevContext
[SlotId
].Enabled
= FALSE
;
2401 Xhc
->UsbDevContext
[SlotId
].SlotId
= 0;
2407 Disable the specified device slot.
2409 @param Xhc The XHCI Instance.
2410 @param SlotId The slot id to be disabled.
2412 @retval EFI_SUCCESS Successfully disable the device slot.
2417 XhcDisableSlotCmd64 (
2418 IN USB_XHCI_INSTANCE
*Xhc
,
2423 TRB_TEMPLATE
*EvtTrb
;
2424 CMD_TRB_DISABLE_SLOT CmdTrbDisSlot
;
2429 // Disable the device slots occupied by these devices on its downstream ports.
2430 // Entry 0 is reserved.
2432 for (Index
= 0; Index
< 255; Index
++) {
2433 if (!Xhc
->UsbDevContext
[Index
+ 1].Enabled
||
2434 (Xhc
->UsbDevContext
[Index
+ 1].SlotId
== 0) ||
2435 (Xhc
->UsbDevContext
[Index
+ 1].ParentRouteString
.Dword
!= Xhc
->UsbDevContext
[SlotId
].RouteString
.Dword
)) {
2439 Status
= XhcDisableSlotCmd64 (Xhc
, Xhc
->UsbDevContext
[Index
+ 1].SlotId
);
2441 if (EFI_ERROR (Status
)) {
2442 DEBUG ((EFI_D_ERROR
, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
2443 Xhc
->UsbDevContext
[Index
+ 1].SlotId
= 0;
2448 // Construct the disable slot command
2450 DEBUG ((EFI_D_INFO
, "Disable device slot %d!\n", SlotId
));
2452 ZeroMem (&CmdTrbDisSlot
, sizeof (CmdTrbDisSlot
));
2453 CmdTrbDisSlot
.CycleBit
= 1;
2454 CmdTrbDisSlot
.Type
= TRB_TYPE_DIS_SLOT
;
2455 CmdTrbDisSlot
.SlotId
= SlotId
;
2456 Status
= XhcCmdTransfer (
2458 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbDisSlot
,
2459 XHC_GENERIC_TIMEOUT
,
2460 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2462 if (EFI_ERROR (Status
)) {
2463 DEBUG ((EFI_D_ERROR
, "XhcDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status
));
2467 // Free the slot's device context entry
2469 Xhc
->DCBAA
[SlotId
] = 0;
2472 // Free the slot related data structure
2474 for (Index
= 0; Index
< 31; Index
++) {
2475 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
] != NULL
) {
2476 RingSeg
= ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
])->RingSeg0
;
2477 if (RingSeg
!= NULL
) {
2478 UsbHcFreeMem (Xhc
->MemPool
, RingSeg
, sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
);
2480 FreePool (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
]);
2481 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
] = NULL
;
2485 for (Index
= 0; Index
< Xhc
->UsbDevContext
[SlotId
].DevDesc
.NumConfigurations
; Index
++) {
2486 if (Xhc
->UsbDevContext
[SlotId
].ConfDesc
[Index
] != NULL
) {
2487 FreePool (Xhc
->UsbDevContext
[SlotId
].ConfDesc
[Index
]);
2491 if (Xhc
->UsbDevContext
[SlotId
].InputContext
!= NULL
) {
2492 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].InputContext
, sizeof (INPUT_CONTEXT_64
));
2495 if (Xhc
->UsbDevContext
[SlotId
].OutputContext
!= NULL
) {
2496 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].OutputContext
, sizeof (DEVICE_CONTEXT_64
));
2499 // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
2500 // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
2501 // remove urb from XHCI's asynchronous transfer list.
2503 Xhc
->UsbDevContext
[SlotId
].Enabled
= FALSE
;
2504 Xhc
->UsbDevContext
[SlotId
].SlotId
= 0;
2511 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
2513 @param Xhc The XHCI Instance.
2514 @param SlotId The slot id to be configured.
2515 @param DeviceSpeed The device's speed.
2516 @param ConfigDesc The pointer to the usb device configuration descriptor.
2518 @retval EFI_SUCCESS Successfully configure all the device endpoints.
2524 IN USB_XHCI_INSTANCE
*Xhc
,
2526 IN UINT8 DeviceSpeed
,
2527 IN USB_CONFIG_DESCRIPTOR
*ConfigDesc
2531 USB_INTERFACE_DESCRIPTOR
*IfDesc
;
2532 USB_ENDPOINT_DESCRIPTOR
*EpDesc
;
2540 EFI_PHYSICAL_ADDRESS PhyAddr
;
2543 TRANSFER_RING
*EndpointTransferRing
;
2544 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
2545 INPUT_CONTEXT
*InputContext
;
2546 DEVICE_CONTEXT
*OutputContext
;
2547 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
2549 // 4.6.6 Configure Endpoint
2551 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
2552 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
2553 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
2554 CopyMem (&InputContext
->Slot
, &OutputContext
->Slot
, sizeof (SLOT_CONTEXT
));
2556 ASSERT (ConfigDesc
!= NULL
);
2560 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)(ConfigDesc
+ 1);
2561 for (Index
= 0; Index
< ConfigDesc
->NumInterfaces
; Index
++) {
2562 while (IfDesc
->DescriptorType
!= USB_DESC_TYPE_INTERFACE
) {
2563 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
2566 NumEp
= IfDesc
->NumEndpoints
;
2568 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)(IfDesc
+ 1);
2569 for (EpIndex
= 0; EpIndex
< NumEp
; EpIndex
++) {
2570 while (EpDesc
->DescriptorType
!= USB_DESC_TYPE_ENDPOINT
) {
2571 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2574 EpAddr
= (UINT8
)(EpDesc
->EndpointAddress
& 0x0F);
2575 Direction
= (UINT8
)((EpDesc
->EndpointAddress
& 0x80) ? EfiUsbDataIn
: EfiUsbDataOut
);
2577 Dci
= XhcEndpointToDci (EpAddr
, Direction
);
2583 InputContext
->InputControlContext
.Dword2
|= (BIT0
<< Dci
);
2584 InputContext
->EP
[Dci
-1].MaxPacketSize
= EpDesc
->MaxPacketSize
;
2586 if (DeviceSpeed
== EFI_USB_SPEED_SUPER
) {
2588 // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
2590 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2592 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2595 switch (EpDesc
->Attributes
& USB_ENDPOINT_TYPE_MASK
) {
2596 case USB_ENDPOINT_BULK
:
2597 if (Direction
== EfiUsbDataIn
) {
2598 InputContext
->EP
[Dci
-1].CErr
= 3;
2599 InputContext
->EP
[Dci
-1].EPType
= ED_BULK_IN
;
2601 InputContext
->EP
[Dci
-1].CErr
= 3;
2602 InputContext
->EP
[Dci
-1].EPType
= ED_BULK_OUT
;
2605 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2606 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] == NULL
) {
2607 EndpointTransferRing
= AllocateZeroPool(sizeof (TRANSFER_RING
));
2608 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] = (VOID
*) EndpointTransferRing
;
2609 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1]);
2613 case USB_ENDPOINT_ISO
:
2614 if (Direction
== EfiUsbDataIn
) {
2615 InputContext
->EP
[Dci
-1].CErr
= 0;
2616 InputContext
->EP
[Dci
-1].EPType
= ED_ISOCH_IN
;
2618 InputContext
->EP
[Dci
-1].CErr
= 0;
2619 InputContext
->EP
[Dci
-1].EPType
= ED_ISOCH_OUT
;
2622 case USB_ENDPOINT_INTERRUPT
:
2623 if (Direction
== EfiUsbDataIn
) {
2624 InputContext
->EP
[Dci
-1].CErr
= 3;
2625 InputContext
->EP
[Dci
-1].EPType
= ED_INTERRUPT_IN
;
2627 InputContext
->EP
[Dci
-1].CErr
= 3;
2628 InputContext
->EP
[Dci
-1].EPType
= ED_INTERRUPT_OUT
;
2630 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2631 InputContext
->EP
[Dci
-1].MaxESITPayload
= EpDesc
->MaxPacketSize
;
2633 // Get the bInterval from descriptor and init the the interval field of endpoint context
2635 if ((DeviceSpeed
== EFI_USB_SPEED_FULL
) || (DeviceSpeed
== EFI_USB_SPEED_LOW
)) {
2636 Interval
= EpDesc
->Interval
;
2638 // Calculate through the bInterval field of Endpoint descriptor.
2640 ASSERT (Interval
!= 0);
2641 InputContext
->EP
[Dci
-1].Interval
= (UINT32
)HighBitSet32((UINT32
)Interval
) + 3;
2642 } else if ((DeviceSpeed
== EFI_USB_SPEED_HIGH
) || (DeviceSpeed
== EFI_USB_SPEED_SUPER
)) {
2643 Interval
= EpDesc
->Interval
;
2644 ASSERT (Interval
>= 1 && Interval
<= 16);
2646 // Refer to XHCI 1.0 spec section 6.2.3.6, table 61
2648 InputContext
->EP
[Dci
-1].Interval
= Interval
- 1;
2649 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2650 InputContext
->EP
[Dci
-1].MaxESITPayload
= 0x0002;
2651 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2652 InputContext
->EP
[Dci
-1].CErr
= 3;
2655 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] == NULL
) {
2656 EndpointTransferRing
= AllocateZeroPool(sizeof (TRANSFER_RING
));
2657 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] = (VOID
*) EndpointTransferRing
;
2658 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1]);
2662 case USB_ENDPOINT_CONTROL
:
2668 PhyAddr
= UsbHcGetPciAddrForHostAddr (
2670 ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1])->RingSeg0
,
2671 sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
2674 PhyAddr
|= ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1])->RingPCS
;
2675 InputContext
->EP
[Dci
-1].PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2676 InputContext
->EP
[Dci
-1].PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2678 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2680 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
2683 InputContext
->InputControlContext
.Dword2
|= BIT0
;
2684 InputContext
->Slot
.ContextEntries
= MaxDci
;
2686 // configure endpoint
2688 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
2689 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT
));
2690 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2691 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2692 CmdTrbCfgEP
.CycleBit
= 1;
2693 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
2694 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
2695 DEBUG ((EFI_D_INFO
, "Configure Endpoint\n"));
2696 Status
= XhcCmdTransfer (
2698 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
2699 XHC_GENERIC_TIMEOUT
,
2700 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2702 if (EFI_ERROR (Status
)) {
2703 DEBUG ((EFI_D_ERROR
, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status
));
2709 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
2711 @param Xhc The XHCI Instance.
2712 @param SlotId The slot id to be configured.
2713 @param DeviceSpeed The device's speed.
2714 @param ConfigDesc The pointer to the usb device configuration descriptor.
2716 @retval EFI_SUCCESS Successfully configure all the device endpoints.
2722 IN USB_XHCI_INSTANCE
*Xhc
,
2724 IN UINT8 DeviceSpeed
,
2725 IN USB_CONFIG_DESCRIPTOR
*ConfigDesc
2729 USB_INTERFACE_DESCRIPTOR
*IfDesc
;
2730 USB_ENDPOINT_DESCRIPTOR
*EpDesc
;
2738 EFI_PHYSICAL_ADDRESS PhyAddr
;
2741 TRANSFER_RING
*EndpointTransferRing
;
2742 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
2743 INPUT_CONTEXT_64
*InputContext
;
2744 DEVICE_CONTEXT_64
*OutputContext
;
2745 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
2747 // 4.6.6 Configure Endpoint
2749 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
2750 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
2751 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
2752 CopyMem (&InputContext
->Slot
, &OutputContext
->Slot
, sizeof (SLOT_CONTEXT_64
));
2754 ASSERT (ConfigDesc
!= NULL
);
2758 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)(ConfigDesc
+ 1);
2759 for (Index
= 0; Index
< ConfigDesc
->NumInterfaces
; Index
++) {
2760 while (IfDesc
->DescriptorType
!= USB_DESC_TYPE_INTERFACE
) {
2761 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
2764 NumEp
= IfDesc
->NumEndpoints
;
2766 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)(IfDesc
+ 1);
2767 for (EpIndex
= 0; EpIndex
< NumEp
; EpIndex
++) {
2768 while (EpDesc
->DescriptorType
!= USB_DESC_TYPE_ENDPOINT
) {
2769 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2772 EpAddr
= (UINT8
)(EpDesc
->EndpointAddress
& 0x0F);
2773 Direction
= (UINT8
)((EpDesc
->EndpointAddress
& 0x80) ? EfiUsbDataIn
: EfiUsbDataOut
);
2775 Dci
= XhcEndpointToDci (EpAddr
, Direction
);
2781 InputContext
->InputControlContext
.Dword2
|= (BIT0
<< Dci
);
2782 InputContext
->EP
[Dci
-1].MaxPacketSize
= EpDesc
->MaxPacketSize
;
2784 if (DeviceSpeed
== EFI_USB_SPEED_SUPER
) {
2786 // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
2788 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2790 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2793 switch (EpDesc
->Attributes
& USB_ENDPOINT_TYPE_MASK
) {
2794 case USB_ENDPOINT_BULK
:
2795 if (Direction
== EfiUsbDataIn
) {
2796 InputContext
->EP
[Dci
-1].CErr
= 3;
2797 InputContext
->EP
[Dci
-1].EPType
= ED_BULK_IN
;
2799 InputContext
->EP
[Dci
-1].CErr
= 3;
2800 InputContext
->EP
[Dci
-1].EPType
= ED_BULK_OUT
;
2803 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2804 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] == NULL
) {
2805 EndpointTransferRing
= AllocateZeroPool(sizeof (TRANSFER_RING
));
2806 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] = (VOID
*) EndpointTransferRing
;
2807 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1]);
2811 case USB_ENDPOINT_ISO
:
2812 if (Direction
== EfiUsbDataIn
) {
2813 InputContext
->EP
[Dci
-1].CErr
= 0;
2814 InputContext
->EP
[Dci
-1].EPType
= ED_ISOCH_IN
;
2816 InputContext
->EP
[Dci
-1].CErr
= 0;
2817 InputContext
->EP
[Dci
-1].EPType
= ED_ISOCH_OUT
;
2820 case USB_ENDPOINT_INTERRUPT
:
2821 if (Direction
== EfiUsbDataIn
) {
2822 InputContext
->EP
[Dci
-1].CErr
= 3;
2823 InputContext
->EP
[Dci
-1].EPType
= ED_INTERRUPT_IN
;
2825 InputContext
->EP
[Dci
-1].CErr
= 3;
2826 InputContext
->EP
[Dci
-1].EPType
= ED_INTERRUPT_OUT
;
2828 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2829 InputContext
->EP
[Dci
-1].MaxESITPayload
= EpDesc
->MaxPacketSize
;
2831 // Get the bInterval from descriptor and init the the interval field of endpoint context
2833 if ((DeviceSpeed
== EFI_USB_SPEED_FULL
) || (DeviceSpeed
== EFI_USB_SPEED_LOW
)) {
2834 Interval
= EpDesc
->Interval
;
2836 // Calculate through the bInterval field of Endpoint descriptor.
2838 ASSERT (Interval
!= 0);
2839 InputContext
->EP
[Dci
-1].Interval
= (UINT32
)HighBitSet32((UINT32
)Interval
) + 3;
2840 } else if ((DeviceSpeed
== EFI_USB_SPEED_HIGH
) || (DeviceSpeed
== EFI_USB_SPEED_SUPER
)) {
2841 Interval
= EpDesc
->Interval
;
2842 ASSERT (Interval
>= 1 && Interval
<= 16);
2844 // Refer to XHCI 1.0 spec section 6.2.3.6, table 61
2846 InputContext
->EP
[Dci
-1].Interval
= Interval
- 1;
2847 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
2848 InputContext
->EP
[Dci
-1].MaxESITPayload
= 0x0002;
2849 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
2850 InputContext
->EP
[Dci
-1].CErr
= 3;
2853 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] == NULL
) {
2854 EndpointTransferRing
= AllocateZeroPool(sizeof (TRANSFER_RING
));
2855 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] = (VOID
*) EndpointTransferRing
;
2856 CreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1]);
2860 case USB_ENDPOINT_CONTROL
:
2866 PhyAddr
= UsbHcGetPciAddrForHostAddr (
2868 ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1])->RingSeg0
,
2869 sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
2873 PhyAddr
|= ((TRANSFER_RING
*)(UINTN
)Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1])->RingPCS
;
2875 InputContext
->EP
[Dci
-1].PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2876 InputContext
->EP
[Dci
-1].PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2878 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
2880 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*)((UINTN
)IfDesc
+ IfDesc
->Length
);
2883 InputContext
->InputControlContext
.Dword2
|= BIT0
;
2884 InputContext
->Slot
.ContextEntries
= MaxDci
;
2886 // configure endpoint
2888 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
2889 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT_64
));
2890 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2891 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2892 CmdTrbCfgEP
.CycleBit
= 1;
2893 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
2894 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
2895 DEBUG ((EFI_D_INFO
, "Configure Endpoint\n"));
2896 Status
= XhcCmdTransfer (
2898 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
2899 XHC_GENERIC_TIMEOUT
,
2900 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2902 if (EFI_ERROR (Status
)) {
2903 DEBUG ((EFI_D_ERROR
, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status
));
2911 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
2913 @param Xhc The XHCI Instance.
2914 @param SlotId The slot id to be evaluated.
2915 @param MaxPacketSize The max packet size supported by the device control transfer.
2917 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
2922 XhcEvaluateContext (
2923 IN USB_XHCI_INSTANCE
*Xhc
,
2925 IN UINT32 MaxPacketSize
2929 CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu
;
2930 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
2931 INPUT_CONTEXT
*InputContext
;
2932 EFI_PHYSICAL_ADDRESS PhyAddr
;
2934 ASSERT (Xhc
->UsbDevContext
[SlotId
].SlotId
!= 0);
2937 // 4.6.7 Evaluate Context
2939 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
2940 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
2942 InputContext
->InputControlContext
.Dword2
|= BIT1
;
2943 InputContext
->EP
[0].MaxPacketSize
= MaxPacketSize
;
2945 ZeroMem (&CmdTrbEvalu
, sizeof (CmdTrbEvalu
));
2946 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT
));
2947 CmdTrbEvalu
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2948 CmdTrbEvalu
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2949 CmdTrbEvalu
.CycleBit
= 1;
2950 CmdTrbEvalu
.Type
= TRB_TYPE_EVALU_CONTXT
;
2951 CmdTrbEvalu
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
2952 DEBUG ((EFI_D_INFO
, "Evaluate context\n"));
2953 Status
= XhcCmdTransfer (
2955 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbEvalu
,
2956 XHC_GENERIC_TIMEOUT
,
2957 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2959 if (EFI_ERROR (Status
)) {
2960 DEBUG ((EFI_D_ERROR
, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status
));
2966 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
2968 @param Xhc The XHCI Instance.
2969 @param SlotId The slot id to be evaluated.
2970 @param MaxPacketSize The max packet size supported by the device control transfer.
2972 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
2977 XhcEvaluateContext64 (
2978 IN USB_XHCI_INSTANCE
*Xhc
,
2980 IN UINT32 MaxPacketSize
2984 CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu
;
2985 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
2986 INPUT_CONTEXT_64
*InputContext
;
2987 EFI_PHYSICAL_ADDRESS PhyAddr
;
2989 ASSERT (Xhc
->UsbDevContext
[SlotId
].SlotId
!= 0);
2992 // 4.6.7 Evaluate Context
2994 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
2995 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
2997 InputContext
->InputControlContext
.Dword2
|= BIT1
;
2998 InputContext
->EP
[0].MaxPacketSize
= MaxPacketSize
;
3000 ZeroMem (&CmdTrbEvalu
, sizeof (CmdTrbEvalu
));
3001 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT_64
));
3002 CmdTrbEvalu
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3003 CmdTrbEvalu
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3004 CmdTrbEvalu
.CycleBit
= 1;
3005 CmdTrbEvalu
.Type
= TRB_TYPE_EVALU_CONTXT
;
3006 CmdTrbEvalu
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3007 DEBUG ((EFI_D_INFO
, "Evaluate context\n"));
3008 Status
= XhcCmdTransfer (
3010 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbEvalu
,
3011 XHC_GENERIC_TIMEOUT
,
3012 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3014 if (EFI_ERROR (Status
)) {
3015 DEBUG ((EFI_D_ERROR
, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status
));
3022 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
3024 @param Xhc The XHCI Instance.
3025 @param SlotId The slot id to be configured.
3026 @param PortNum The total number of downstream port supported by the hub.
3027 @param TTT The TT think time of the hub device.
3028 @param MTT The multi-TT of the hub device.
3030 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
3034 XhcConfigHubContext (
3035 IN USB_XHCI_INSTANCE
*Xhc
,
3043 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3044 INPUT_CONTEXT
*InputContext
;
3045 DEVICE_CONTEXT
*OutputContext
;
3046 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
3047 EFI_PHYSICAL_ADDRESS PhyAddr
;
3049 ASSERT (Xhc
->UsbDevContext
[SlotId
].SlotId
!= 0);
3050 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
3051 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
3054 // 4.6.7 Evaluate Context
3056 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
3058 InputContext
->InputControlContext
.Dword2
|= BIT0
;
3061 // Copy the slot context from OutputContext to Input context
3063 CopyMem(&(InputContext
->Slot
), &(OutputContext
->Slot
), sizeof (SLOT_CONTEXT
));
3064 InputContext
->Slot
.Hub
= 1;
3065 InputContext
->Slot
.PortNum
= PortNum
;
3066 InputContext
->Slot
.TTT
= TTT
;
3067 InputContext
->Slot
.MTT
= MTT
;
3069 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
3070 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT
));
3071 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3072 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3073 CmdTrbCfgEP
.CycleBit
= 1;
3074 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
3075 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3076 DEBUG ((EFI_D_INFO
, "Configure Hub Slot Context\n"));
3077 Status
= XhcCmdTransfer (
3079 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
3080 XHC_GENERIC_TIMEOUT
,
3081 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3083 if (EFI_ERROR (Status
)) {
3084 DEBUG ((EFI_D_ERROR
, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status
));
3090 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
3092 @param Xhc The XHCI Instance.
3093 @param SlotId The slot id to be configured.
3094 @param PortNum The total number of downstream port supported by the hub.
3095 @param TTT The TT think time of the hub device.
3096 @param MTT The multi-TT of the hub device.
3098 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
3102 XhcConfigHubContext64 (
3103 IN USB_XHCI_INSTANCE
*Xhc
,
3111 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
3112 INPUT_CONTEXT_64
*InputContext
;
3113 DEVICE_CONTEXT_64
*OutputContext
;
3114 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
3115 EFI_PHYSICAL_ADDRESS PhyAddr
;
3117 ASSERT (Xhc
->UsbDevContext
[SlotId
].SlotId
!= 0);
3118 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
3119 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
3122 // 4.6.7 Evaluate Context
3124 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
3126 InputContext
->InputControlContext
.Dword2
|= BIT0
;
3129 // Copy the slot context from OutputContext to Input context
3131 CopyMem(&(InputContext
->Slot
), &(OutputContext
->Slot
), sizeof (SLOT_CONTEXT_64
));
3132 InputContext
->Slot
.Hub
= 1;
3133 InputContext
->Slot
.PortNum
= PortNum
;
3134 InputContext
->Slot
.TTT
= TTT
;
3135 InputContext
->Slot
.MTT
= MTT
;
3137 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
3138 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT_64
));
3139 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
3140 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
3141 CmdTrbCfgEP
.CycleBit
= 1;
3142 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
3143 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
3144 DEBUG ((EFI_D_INFO
, "Configure Hub Slot Context\n"));
3145 Status
= XhcCmdTransfer (
3147 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
3148 XHC_GENERIC_TIMEOUT
,
3149 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
3151 if (EFI_ERROR (Status
)) {
3152 DEBUG ((EFI_D_ERROR
, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status
));