]> git.proxmox.com Git - mirror_edk2.git/blob - MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h
projects / mirror_edk2.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
MdeModulePkg: Clean up source files
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciSched.h
1 /** @file
2
3 This file contains the definition for XHCI host controller schedule routines.
4
5 Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #ifndef _EFI_XHCI_SCHED_H_
17 #define _EFI_XHCI_SCHED_H_
18
19 #define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
20
21 //
22 // Transfer types, used in URB to identify the transfer type
23 //
24 #define XHC_CTRL_TRANSFER 0x01
25 #define XHC_BULK_TRANSFER 0x02
26 #define XHC_INT_TRANSFER_SYNC 0x04
27 #define XHC_INT_TRANSFER_ASYNC 0x08
28 #define XHC_INT_ONLY_TRANSFER_ASYNC 0x10
29
30 //
31 // 6.4.6 TRB Types
32 //
33 #define TRB_TYPE_NORMAL 1
34 #define TRB_TYPE_SETUP_STAGE 2
35 #define TRB_TYPE_DATA_STAGE 3
36 #define TRB_TYPE_STATUS_STAGE 4
37 #define TRB_TYPE_ISOCH 5
38 #define TRB_TYPE_LINK 6
39 #define TRB_TYPE_EVENT_DATA 7
40 #define TRB_TYPE_NO_OP 8
41 #define TRB_TYPE_EN_SLOT 9
42 #define TRB_TYPE_DIS_SLOT 10
43 #define TRB_TYPE_ADDRESS_DEV 11
44 #define TRB_TYPE_CON_ENDPOINT 12
45 #define TRB_TYPE_EVALU_CONTXT 13
46 #define TRB_TYPE_RESET_ENDPOINT 14
47 #define TRB_TYPE_STOP_ENDPOINT 15
48 #define TRB_TYPE_SET_TR_DEQUE 16
49 #define TRB_TYPE_RESET_DEV 17
50 #define TRB_TYPE_GET_PORT_BANW 21
51 #define TRB_TYPE_FORCE_HEADER 22
52 #define TRB_TYPE_NO_OP_COMMAND 23
53 #define TRB_TYPE_TRANS_EVENT 32
54 #define TRB_TYPE_COMMAND_COMPLT_EVENT 33
55 #define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
56 #define TRB_TYPE_HOST_CONTROLLER_EVENT 37
57 #define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
58 #define TRB_TYPE_MFINDEX_WRAP_EVENT 39
59
60 //
61 // Endpoint Type (EP Type).
62 //
63 #define ED_NOT_VALID 0
64 #define ED_ISOCH_OUT 1
65 #define ED_BULK_OUT 2
66 #define ED_INTERRUPT_OUT 3
67 #define ED_CONTROL_BIDIR 4
68 #define ED_ISOCH_IN 5
69 #define ED_BULK_IN 6
70 #define ED_INTERRUPT_IN 7
71
72 //
73 // 6.4.5 TRB Completion Codes
74 //
75 #define TRB_COMPLETION_INVALID 0
76 #define TRB_COMPLETION_SUCCESS 1
77 #define TRB_COMPLETION_DATA_BUFFER_ERROR 2
78 #define TRB_COMPLETION_BABBLE_ERROR 3
79 #define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
80 #define TRB_COMPLETION_TRB_ERROR 5
81 #define TRB_COMPLETION_STALL_ERROR 6
82 #define TRB_COMPLETION_SHORT_PACKET 13
83 #define TRB_COMPLETION_STOPPED 26
84 #define TRB_COMPLETION_STOPPED_LENGTH_INVALID 27
85
86 //
87 // The topology string used to present usb device location
88 //
89 typedef struct _USB_DEV_TOPOLOGY {
90 //
91 // The tier concatenation of down stream port.
92 //
93 UINT32 RouteString:20;
94 //
95 // The root port number of the chain.
96 //
97 UINT32 RootPortNum:8;
98 //
99 // The Tier the device reside.
100 //
101 UINT32 TierNum:4;
102 } USB_DEV_TOPOLOGY;
103
104 //
105 // USB Device's RouteChart
106 //
107 typedef union _USB_DEV_ROUTE {
108 UINT32 Dword;
109 USB_DEV_TOPOLOGY Route;
110 } USB_DEV_ROUTE;
111
112 //
113 // Endpoint address and its capabilities
114 //
115 typedef struct _USB_ENDPOINT {
116 //
117 // Store logical device address assigned by UsbBus
118 // It's because some XHCI host controllers may assign the same physcial device
119 // address for those devices inserted at different root port.
120 //
121 UINT8 BusAddr;
122 UINT8 DevAddr;
123 UINT8 EpAddr;
124 EFI_USB_DATA_DIRECTION Direction;
125 UINT8 DevSpeed;
126 UINTN MaxPacket;
127 UINTN Type;
128 } USB_ENDPOINT;
129
130 //
131 // TRB Template
132 //
133 typedef struct _TRB_TEMPLATE {
134 UINT32 Parameter1;
135
136 UINT32 Parameter2;
137
138 UINT32 Status;
139
140 UINT32 CycleBit:1;
141 UINT32 RsvdZ1:9;
142 UINT32 Type:6;
143 UINT32 Control:16;
144 } TRB_TEMPLATE;
145
146 typedef struct _TRANSFER_RING {
147 VOID *RingSeg0;
148 UINTN TrbNumber;
149 TRB_TEMPLATE *RingEnqueue;
150 TRB_TEMPLATE *RingDequeue;
151 UINT32 RingPCS;
152 } TRANSFER_RING;
153
154 typedef struct _EVENT_RING {
155 VOID *ERSTBase;
156 VOID *EventRingSeg0;
157 UINTN TrbNumber;
158 TRB_TEMPLATE *EventRingEnqueue;
159 TRB_TEMPLATE *EventRingDequeue;
160 UINT32 EventRingCCS;
161 } EVENT_RING;
162
163 //
164 // URB (Usb Request Block) contains information for all kinds of
165 // usb requests.
166 //
167 typedef struct _URB {
168 UINT32 Signature;
169 LIST_ENTRY UrbList;
170 //
171 // Usb Device URB related information
172 //
173 USB_ENDPOINT Ep;
174 EFI_USB_DEVICE_REQUEST *Request;
175 VOID *Data;
176 UINTN DataLen;
177 VOID *DataPhy;
178 VOID *DataMap;
179 EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
180 VOID *Context;
181 //
182 // Execute result
183 //
184 UINT32 Result;
185 //
186 // completed data length
187 //
188 UINTN Completed;
189 //
190 // Command/Tranfer Ring info
191 //
192 TRANSFER_RING *Ring;
193 TRB_TEMPLATE *TrbStart;
194 TRB_TEMPLATE *TrbEnd;
195 UINTN TrbNum;
196 BOOLEAN StartDone;
197 BOOLEAN EndDone;
198 BOOLEAN Finished;
199
200 TRB_TEMPLATE *EvtTrb;
201 } URB;
202
203 //
204 // 6.5 Event Ring Segment Table
205 // The Event Ring Segment Table is used to define multi-segment Event Rings and to enable runtime
206 // expansion and shrinking of the Event Ring. The location of the Event Ring Segment Table is defined by the
207 // Event Ring Segment Table Base Address Register (5.5.2.3.2). The size of the Event Ring Segment Table
208 // is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).
209 //
210 typedef struct _EVENT_RING_SEG_TABLE_ENTRY {
211 UINT32 PtrLo;
212 UINT32 PtrHi;
213 UINT32 RingTrbSize:16;
214 UINT32 RsvdZ1:16;
215 UINT32 RsvdZ2;
216 } EVENT_RING_SEG_TABLE_ENTRY;
217
218 //
219 // 6.4.1.1 Normal TRB
220 // A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and
221 // Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer
222 // Rings, and to define the Data stage information for Control Transfer Rings.
223 //
224 typedef struct _TRANSFER_TRB_NORMAL {
225 UINT32 TRBPtrLo;
226
227 UINT32 TRBPtrHi;
228
229 UINT32 Length:17;
230 UINT32 TDSize:5;
231 UINT32 IntTarget:10;
232
233 UINT32 CycleBit:1;
234 UINT32 ENT:1;
235 UINT32 ISP:1;
236 UINT32 NS:1;
237 UINT32 CH:1;
238 UINT32 IOC:1;
239 UINT32 IDT:1;
240 UINT32 RsvdZ1:2;
241 UINT32 BEI:1;
242 UINT32 Type:6;
243 UINT32 RsvdZ2:16;
244 } TRANSFER_TRB_NORMAL;
245
246 //
247 // 6.4.1.2.1 Setup Stage TRB
248 // A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.
249 //
250 typedef struct _TRANSFER_TRB_CONTROL_SETUP {
251 UINT32 bmRequestType:8;
252 UINT32 bRequest:8;
253 UINT32 wValue:16;
254
255 UINT32 wIndex:16;
256 UINT32 wLength:16;
257
258 UINT32 Length:17;
259 UINT32 RsvdZ1:5;
260 UINT32 IntTarget:10;
261
262 UINT32 CycleBit:1;
263 UINT32 RsvdZ2:4;
264 UINT32 IOC:1;
265 UINT32 IDT:1;
266 UINT32 RsvdZ3:3;
267 UINT32 Type:6;
268 UINT32 TRT:2;
269 UINT32 RsvdZ4:14;
270 } TRANSFER_TRB_CONTROL_SETUP;
271
272 //
273 // 6.4.1.2.2 Data Stage TRB
274 // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
275 //
276 typedef struct _TRANSFER_TRB_CONTROL_DATA {
277 UINT32 TRBPtrLo;
278
279 UINT32 TRBPtrHi;
280
281 UINT32 Length:17;
282 UINT32 TDSize:5;
283 UINT32 IntTarget:10;
284
285 UINT32 CycleBit:1;
286 UINT32 ENT:1;
287 UINT32 ISP:1;
288 UINT32 NS:1;
289 UINT32 CH:1;
290 UINT32 IOC:1;
291 UINT32 IDT:1;
292 UINT32 RsvdZ1:3;
293 UINT32 Type:6;
294 UINT32 DIR:1;
295 UINT32 RsvdZ2:15;
296 } TRANSFER_TRB_CONTROL_DATA;
297
298 //
299 // 6.4.1.2.2 Data Stage TRB
300 // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
301 //
302 typedef struct _TRANSFER_TRB_CONTROL_STATUS {
303 UINT32 RsvdZ1;
304 UINT32 RsvdZ2;
305
306 UINT32 RsvdZ3:22;
307 UINT32 IntTarget:10;
308
309 UINT32 CycleBit:1;
310 UINT32 ENT:1;
311 UINT32 RsvdZ4:2;
312 UINT32 CH:1;
313 UINT32 IOC:1;
314 UINT32 RsvdZ5:4;
315 UINT32 Type:6;
316 UINT32 DIR:1;
317 UINT32 RsvdZ6:15;
318 } TRANSFER_TRB_CONTROL_STATUS;
319
320 //
321 // 6.4.2.1 Transfer Event TRB
322 // A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1
323 // for more information on the use and operation of Transfer Events.
324 //
325 typedef struct _EVT_TRB_TRANSFER {
326 UINT32 TRBPtrLo;
327
328 UINT32 TRBPtrHi;
329
330 UINT32 Length:24;
331 UINT32 Completecode:8;
332
333 UINT32 CycleBit:1;
334 UINT32 RsvdZ1:1;
335 UINT32 ED:1;
336 UINT32 RsvdZ2:7;
337 UINT32 Type:6;
338 UINT32 EndpointId:5;
339 UINT32 RsvdZ3:3;
340 UINT32 SlotId:8;
341 } EVT_TRB_TRANSFER;
342
343 //
344 // 6.4.2.2 Command Completion Event TRB
345 // A Command Completion Event TRB shall be generated by the xHC when a command completes on the
346 // Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.
347 //
348 typedef struct _EVT_TRB_COMMAND_COMPLETION {
349 UINT32 TRBPtrLo;
350
351 UINT32 TRBPtrHi;
352
353 UINT32 RsvdZ2:24;
354 UINT32 Completecode:8;
355
356 UINT32 CycleBit:1;
357 UINT32 RsvdZ3:9;
358 UINT32 Type:6;
359 UINT32 VFID:8;
360 UINT32 SlotId:8;
361 } EVT_TRB_COMMAND_COMPLETION;
362
363 typedef union _TRB {
364 TRB_TEMPLATE TrbTemplate;
365 TRANSFER_TRB_NORMAL TrbNormal;
366 TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;
367 TRANSFER_TRB_CONTROL_DATA TrbCtrData;
368 TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;
369 } TRB;
370
371 //
372 // 6.4.3.1 No Op Command TRB
373 // The No Op Command TRB provides a simple means for verifying the operation of the Command Ring
374 // mechanisms offered by the xHCI.
375 //
376 typedef struct _CMD_TRB_NO_OP {
377 UINT32 RsvdZ0;
378 UINT32 RsvdZ1;
379 UINT32 RsvdZ2;
380
381 UINT32 CycleBit:1;
382 UINT32 RsvdZ3:9;
383 UINT32 Type:6;
384 UINT32 RsvdZ4:16;
385 } CMD_TRB_NO_OP;
386
387 //
388 // 6.4.3.2 Enable Slot Command TRB
389 // The Enable Slot Command TRB causes the xHC to select an available Device Slot and return the ID of the
390 // selected slot to the host in a Command Completion Event.
391 //
392 typedef struct _CMD_TRB_ENABLE_SLOT {
393 UINT32 RsvdZ0;
394 UINT32 RsvdZ1;
395 UINT32 RsvdZ2;
396
397 UINT32 CycleBit:1;
398 UINT32 RsvdZ3:9;
399 UINT32 Type:6;
400 UINT32 RsvdZ4:16;
401 } CMD_TRB_ENABLE_SLOT;
402
403 //
404 // 6.4.3.3 Disable Slot Command TRB
405 // The Disable Slot Command TRB releases any bandwidth assigned to the disabled slot and frees any
406 // internal xHC resources assigned to the slot.
407 //
408 typedef struct _CMD_TRB_DISABLE_SLOT {
409 UINT32 RsvdZ0;
410 UINT32 RsvdZ1;
411 UINT32 RsvdZ2;
412
413 UINT32 CycleBit:1;
414 UINT32 RsvdZ3:9;
415 UINT32 Type:6;
416 UINT32 RsvdZ4:8;
417 UINT32 SlotId:8;
418 } CMD_TRB_DISABLE_SLOT;
419
420 //
421 // 6.4.3.4 Address Device Command TRB
422 // The Address Device Command TRB transitions the selected Device Context from the Default to the
423 // Addressed state and causes the xHC to select an address for the USB device in the Default State and
424 // issue a SET_ADDRESS request to the USB device.
425 //
426 typedef struct _CMD_TRB_ADDRESS_DEVICE {
427 UINT32 PtrLo;
428
429 UINT32 PtrHi;
430
431 UINT32 RsvdZ1;
432
433 UINT32 CycleBit:1;
434 UINT32 RsvdZ2:8;
435 UINT32 BSR:1;
436 UINT32 Type:6;
437 UINT32 RsvdZ3:8;
438 UINT32 SlotId:8;
439 } CMD_TRB_ADDRESS_DEVICE;
440
441 //
442 // 6.4.3.5 Configure Endpoint Command TRB
443 // The Configure Endpoint Command TRB evaluates the bandwidth and resource requirements of the
444 // endpoints selected by the command.
445 //
446 typedef struct _CMD_TRB_CONFIG_ENDPOINT {
447 UINT32 PtrLo;
448
449 UINT32 PtrHi;
450
451 UINT32 RsvdZ1;
452
453 UINT32 CycleBit:1;
454 UINT32 RsvdZ2:8;
455 UINT32 DC:1;
456 UINT32 Type:6;
457 UINT32 RsvdZ3:8;
458 UINT32 SlotId:8;
459 } CMD_TRB_CONFIG_ENDPOINT;
460
461 //
462 // 6.4.3.6 Evaluate Context Command TRB
463 // The Evaluate Context Command TRB is used by system software to inform the xHC that the selected
464 // Context data structures in the Device Context have been modified by system software and that the xHC
465 // shall evaluate any changes
466 //
467 typedef struct _CMD_TRB_EVALUATE_CONTEXT {
468 UINT32 PtrLo;
469
470 UINT32 PtrHi;
471
472 UINT32 RsvdZ1;
473
474 UINT32 CycleBit:1;
475 UINT32 RsvdZ2:9;
476 UINT32 Type:6;
477 UINT32 RsvdZ3:8;
478 UINT32 SlotId:8;
479 } CMD_TRB_EVALUATE_CONTEXT;
480
481 //
482 // 6.4.3.7 Reset Endpoint Command TRB
483 // The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring
484 //
485 typedef struct _CMD_TRB_RESET_ENDPOINT {
486 UINT32 RsvdZ0;
487 UINT32 RsvdZ1;
488 UINT32 RsvdZ2;
489
490 UINT32 CycleBit:1;
491 UINT32 RsvdZ3:8;
492 UINT32 TSP:1;
493 UINT32 Type:6;
494 UINT32 EDID:5;
495 UINT32 RsvdZ4:3;
496 UINT32 SlotId:8;
497 } CMD_TRB_RESET_ENDPOINT;
498
499 //
500 // 6.4.3.8 Stop Endpoint Command TRB
501 // The Stop Endpoint Command TRB command allows software to stop the xHC execution of the TDs on a
502 // Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.
503 //
504 typedef struct _CMD_TRB_STOP_ENDPOINT {
505 UINT32 RsvdZ0;
506 UINT32 RsvdZ1;
507 UINT32 RsvdZ2;
508
509 UINT32 CycleBit:1;
510 UINT32 RsvdZ3:9;
511 UINT32 Type:6;
512 UINT32 EDID:5;
513 UINT32 RsvdZ4:2;
514 UINT32 SP:1;
515 UINT32 SlotId:8;
516 } CMD_TRB_STOP_ENDPOINT;
517
518 //
519 // 6.4.3.9 Set TR Dequeue Pointer Command TRB
520 // The Set TR Dequeue Pointer Command TRB is used by system software to modify the TR Dequeue
521 // Pointer and DCS fields of an Endpoint or Stream Context.
522 //
523 typedef struct _CMD_SET_TR_DEQ_POINTER {
524 UINT32 PtrLo;
525
526 UINT32 PtrHi;
527
528 UINT32 RsvdZ1:16;
529 UINT32 StreamID:16;
530
531 UINT32 CycleBit:1;
532 UINT32 RsvdZ2:9;
533 UINT32 Type:6;
534 UINT32 Endpoint:5;
535 UINT32 RsvdZ3:3;
536 UINT32 SlotId:8;
537 } CMD_SET_TR_DEQ_POINTER;
538
539 //
540 // 6.4.4.1 Link TRB
541 // A Link TRB provides support for non-contiguous TRB Rings.
542 //
543 typedef struct _LINK_TRB {
544 UINT32 PtrLo;
545
546 UINT32 PtrHi;
547
548 UINT32 RsvdZ1:22;
549 UINT32 InterTarget:10;
550
551 UINT32 CycleBit:1;
552 UINT32 TC:1;
553 UINT32 RsvdZ2:2;
554 UINT32 CH:1;
555 UINT32 IOC:1;
556 UINT32 RsvdZ3:4;
557 UINT32 Type:6;
558 UINT32 RsvdZ4:16;
559 } LINK_TRB;
560
561 //
562 // 6.2.2 Slot Context
563 //
564 typedef struct _SLOT_CONTEXT {
565 UINT32 RouteString:20;
566 UINT32 Speed:4;
567 UINT32 RsvdZ1:1;
568 UINT32 MTT:1;
569 UINT32 Hub:1;
570 UINT32 ContextEntries:5;
571
572 UINT32 MaxExitLatency:16;
573 UINT32 RootHubPortNum:8;
574 UINT32 PortNum:8;
575
576 UINT32 TTHubSlotId:8;
577 UINT32 TTPortNum:8;
578 UINT32 TTT:2;
579 UINT32 RsvdZ2:4;
580 UINT32 InterTarget:10;
581
582 UINT32 DeviceAddress:8;
583 UINT32 RsvdZ3:19;
584 UINT32 SlotState:5;
585
586 UINT32 RsvdZ4;
587 UINT32 RsvdZ5;
588 UINT32 RsvdZ6;
589 UINT32 RsvdZ7;
590 } SLOT_CONTEXT;
591
592 typedef struct _SLOT_CONTEXT_64 {
593 UINT32 RouteString:20;
594 UINT32 Speed:4;
595 UINT32 RsvdZ1:1;
596 UINT32 MTT:1;
597 UINT32 Hub:1;
598 UINT32 ContextEntries:5;
599
600 UINT32 MaxExitLatency:16;
601 UINT32 RootHubPortNum:8;
602 UINT32 PortNum:8;
603
604 UINT32 TTHubSlotId:8;
605 UINT32 TTPortNum:8;
606 UINT32 TTT:2;
607 UINT32 RsvdZ2:4;
608 UINT32 InterTarget:10;
609
610 UINT32 DeviceAddress:8;
611 UINT32 RsvdZ3:19;
612 UINT32 SlotState:5;
613
614 UINT32 RsvdZ4;
615 UINT32 RsvdZ5;
616 UINT32 RsvdZ6;
617 UINT32 RsvdZ7;
618
619 UINT32 RsvdZ8;
620 UINT32 RsvdZ9;
621 UINT32 RsvdZ10;
622 UINT32 RsvdZ11;
623
624 UINT32 RsvdZ12;
625 UINT32 RsvdZ13;
626 UINT32 RsvdZ14;
627 UINT32 RsvdZ15;
628
629 } SLOT_CONTEXT_64;
630
631
632 //
633 // 6.2.3 Endpoint Context
634 //
635 typedef struct _ENDPOINT_CONTEXT {
636 UINT32 EPState:3;
637 UINT32 RsvdZ1:5;
638 UINT32 Mult:2;
639 UINT32 MaxPStreams:5;
640 UINT32 LSA:1;
641 UINT32 Interval:8;
642 UINT32 RsvdZ2:8;
643
644 UINT32 RsvdZ3:1;
645 UINT32 CErr:2;
646 UINT32 EPType:3;
647 UINT32 RsvdZ4:1;
648 UINT32 HID:1;
649 UINT32 MaxBurstSize:8;
650 UINT32 MaxPacketSize:16;
651
652 UINT32 PtrLo;
653
654 UINT32 PtrHi;
655
656 UINT32 AverageTRBLength:16;
657 UINT32 MaxESITPayload:16;
658
659 UINT32 RsvdZ5;
660 UINT32 RsvdZ6;
661 UINT32 RsvdZ7;
662 } ENDPOINT_CONTEXT;
663
664 typedef struct _ENDPOINT_CONTEXT_64 {
665 UINT32 EPState:3;
666 UINT32 RsvdZ1:5;
667 UINT32 Mult:2;
668 UINT32 MaxPStreams:5;
669 UINT32 LSA:1;
670 UINT32 Interval:8;
671 UINT32 RsvdZ2:8;
672
673 UINT32 RsvdZ3:1;
674 UINT32 CErr:2;
675 UINT32 EPType:3;
676 UINT32 RsvdZ4:1;
677 UINT32 HID:1;
678 UINT32 MaxBurstSize:8;
679 UINT32 MaxPacketSize:16;
680
681 UINT32 PtrLo;
682
683 UINT32 PtrHi;
684
685 UINT32 AverageTRBLength:16;
686 UINT32 MaxESITPayload:16;
687
688 UINT32 RsvdZ5;
689 UINT32 RsvdZ6;
690 UINT32 RsvdZ7;
691
692 UINT32 RsvdZ8;
693 UINT32 RsvdZ9;
694 UINT32 RsvdZ10;
695 UINT32 RsvdZ11;
696
697 UINT32 RsvdZ12;
698 UINT32 RsvdZ13;
699 UINT32 RsvdZ14;
700 UINT32 RsvdZ15;
701
702 } ENDPOINT_CONTEXT_64;
703
704
705 //
706 // 6.2.5.1 Input Control Context
707 //
708 typedef struct _INPUT_CONTRL_CONTEXT {
709 UINT32 Dword1;
710 UINT32 Dword2;
711 UINT32 RsvdZ1;
712 UINT32 RsvdZ2;
713 UINT32 RsvdZ3;
714 UINT32 RsvdZ4;
715 UINT32 RsvdZ5;
716 UINT32 RsvdZ6;
717 } INPUT_CONTRL_CONTEXT;
718
719 typedef struct _INPUT_CONTRL_CONTEXT_64 {
720 UINT32 Dword1;
721 UINT32 Dword2;
722 UINT32 RsvdZ1;
723 UINT32 RsvdZ2;
724 UINT32 RsvdZ3;
725 UINT32 RsvdZ4;
726 UINT32 RsvdZ5;
727 UINT32 RsvdZ6;
728 UINT32 RsvdZ7;
729 UINT32 RsvdZ8;
730 UINT32 RsvdZ9;
731 UINT32 RsvdZ10;
732 UINT32 RsvdZ11;
733 UINT32 RsvdZ12;
734 UINT32 RsvdZ13;
735 UINT32 RsvdZ14;
736 } INPUT_CONTRL_CONTEXT_64;
737
738 //
739 // 6.2.1 Device Context
740 //
741 typedef struct _DEVICE_CONTEXT {
742 SLOT_CONTEXT Slot;
743 ENDPOINT_CONTEXT EP[31];
744 } DEVICE_CONTEXT;
745
746 typedef struct _DEVICE_CONTEXT_64 {
747 SLOT_CONTEXT_64 Slot;
748 ENDPOINT_CONTEXT_64 EP[31];
749 } DEVICE_CONTEXT_64;
750
751 //
752 // 6.2.5 Input Context
753 //
754 typedef struct _INPUT_CONTEXT {
755 INPUT_CONTRL_CONTEXT InputControlContext;
756 SLOT_CONTEXT Slot;
757 ENDPOINT_CONTEXT EP[31];
758 } INPUT_CONTEXT;
759
760 typedef struct _INPUT_CONTEXT_64 {
761 INPUT_CONTRL_CONTEXT_64 InputControlContext;
762 SLOT_CONTEXT_64 Slot;
763 ENDPOINT_CONTEXT_64 EP[31];
764 } INPUT_CONTEXT_64;
765
766
767 /**
768 Initialize the XHCI host controller for schedule.
769
770 @param Xhc The XHCI Instance to be initialized.
771
772 **/
773 VOID
774 XhcInitSched (
775 IN USB_XHCI_INSTANCE *Xhc
776 );
777
778 /**
779 Free the resouce allocated at initializing schedule.
780
781 @param Xhc The XHCI Instance.
782
783 **/
784 VOID
785 XhcFreeSched (
786 IN USB_XHCI_INSTANCE *Xhc
787 );
788
789 /**
790 Ring the door bell to notify XHCI there is a transaction to be executed through URB.
791
792 @param Xhc The XHCI Instance.
793 @param Urb The URB to be rung.
794
795 @retval EFI_SUCCESS Successfully ring the door bell.
796
797 **/
798 EFI_STATUS
799 RingIntTransferDoorBell (
800 IN USB_XHCI_INSTANCE *Xhc,
801 IN URB *Urb
802 );
803
804 /**
805 Execute the transfer by polling the URB. This is a synchronous operation.
806
807 @param Xhc The XHCI Instance.
808 @param CmdTransfer The executed URB is for cmd transfer or not.
809 @param Urb The URB to execute.
810 @param Timeout The time to wait before abort, in millisecond.
811
812 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
813 @return EFI_TIMEOUT The transfer failed due to time out.
814 @return EFI_SUCCESS The transfer finished OK.
815
816 **/
817 EFI_STATUS
818 XhcExecTransfer (
819 IN USB_XHCI_INSTANCE *Xhc,
820 IN BOOLEAN CmdTransfer,
821 IN URB *Urb,
822 IN UINTN Timeout
823 );
824
825 /**
826 Delete a single asynchronous interrupt transfer for
827 the device and endpoint.
828
829 @param Xhc The XHCI Instance.
830 @param BusAddr The logical device address assigned by UsbBus driver.
831 @param EpNum The endpoint of the target.
832
833 @retval EFI_SUCCESS An asynchronous transfer is removed.
834 @retval EFI_NOT_FOUND No transfer for the device is found.
835
836 **/
837 EFI_STATUS
838 XhciDelAsyncIntTransfer (
839 IN USB_XHCI_INSTANCE *Xhc,
840 IN UINT8 BusAddr,
841 IN UINT8 EpNum
842 );
843
844 /**
845 Remove all the asynchronous interrupt transfers.
846
847 @param Xhc The XHCI Instance.
848
849 **/
850 VOID
851 XhciDelAllAsyncIntTransfers (
852 IN USB_XHCI_INSTANCE *Xhc
853 );
854
855 /**
856 Set Bios Ownership
857
858 @param Xhc The XHCI Instance.
859
860 **/
861 VOID
862 XhcSetBiosOwnership (
863 IN USB_XHCI_INSTANCE *Xhc
864 );
865
866 /**
867 Clear Bios Ownership
868
869 @param Xhc The XHCI Instance.
870
871 **/
872 VOID
873 XhcClearBiosOwnership (
874 IN USB_XHCI_INSTANCE *Xhc
875 );
876
877 /**
878 Find out the slot id according to the device's route string.
879
880 @param Xhc The XHCI Instance.
881 @param RouteString The route string described the device location.
882
883 @return The slot id used by the device.
884
885 **/
886 UINT8
887 EFIAPI
888 XhcRouteStringToSlotId (
889 IN USB_XHCI_INSTANCE *Xhc,
890 IN USB_DEV_ROUTE RouteString
891 );
892
893 /**
894 Calculate the device context index by endpoint address and direction.
895
896 @param EpAddr The target endpoint number.
897 @param Direction The direction of the target endpoint.
898
899 @return The device context index of endpoint.
900
901 **/
902 UINT8
903 XhcEndpointToDci (
904 IN UINT8 EpAddr,
905 IN UINT8 Direction
906 );
907
908 /**
909 Ring the door bell to notify XHCI there is a transaction to be executed.
910
911 @param Xhc The XHCI Instance.
912 @param SlotId The slot id of the target device.
913 @param Dci The device context index of the target slot or endpoint.
914
915 @retval EFI_SUCCESS Successfully ring the door bell.
916
917 **/
918 EFI_STATUS
919 EFIAPI
920 XhcRingDoorBell (
921 IN USB_XHCI_INSTANCE *Xhc,
922 IN UINT8 SlotId,
923 IN UINT8 Dci
924 );
925
926 /**
927 Interrupt transfer periodic check handler.
928
929 @param Event Interrupt event.
930 @param Context Pointer to USB_XHCI_INSTANCE.
931
932 **/
933 VOID
934 EFIAPI
935 XhcMonitorAsyncRequests (
936 IN EFI_EVENT Event,
937 IN VOID *Context
938 );
939
940 /**
941 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.
942
943 @param Xhc The XHCI Instance.
944 @param ParentRouteChart The route string pointed to the parent device if it exists.
945 @param Port The port to be polled.
946 @param PortState The port state.
947
948 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.
949 @retval Others Should not appear.
950
951 **/
952 EFI_STATUS
953 EFIAPI
954 XhcPollPortStatusChange (
955 IN USB_XHCI_INSTANCE *Xhc,
956 IN USB_DEV_ROUTE ParentRouteChart,
957 IN UINT8 Port,
958 IN EFI_USB_PORT_STATUS *PortState
959 );
960
961 /**
962 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
963
964 @param Xhc The XHCI Instance.
965 @param SlotId The slot id to be configured.
966 @param PortNum The total number of downstream port supported by the hub.
967 @param TTT The TT think time of the hub device.
968 @param MTT The multi-TT of the hub device.
969
970 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
971
972 **/
973 EFI_STATUS
974 XhcConfigHubContext (
975 IN USB_XHCI_INSTANCE *Xhc,
976 IN UINT8 SlotId,
977 IN UINT8 PortNum,
978 IN UINT8 TTT,
979 IN UINT8 MTT
980 );
981
982
983 /**
984 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
985
986 @param Xhc The XHCI Instance.
987 @param SlotId The slot id to be configured.
988 @param PortNum The total number of downstream port supported by the hub.
989 @param TTT The TT think time of the hub device.
990 @param MTT The multi-TT of the hub device.
991
992 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
993
994 **/
995 EFI_STATUS
996 XhcConfigHubContext64 (
997 IN USB_XHCI_INSTANCE *Xhc,
998 IN UINT8 SlotId,
999 IN UINT8 PortNum,
1000 IN UINT8 TTT,
1001 IN UINT8 MTT
1002 );
1003
1004
1005 /**
1006 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
1007
1008 @param Xhc The XHCI Instance.
1009 @param SlotId The slot id to be configured.
1010 @param DeviceSpeed The device's speed.
1011 @param ConfigDesc The pointer to the usb device configuration descriptor.
1012
1013 @retval EFI_SUCCESS Successfully configure all the device endpoints.
1014
1015 **/
1016 EFI_STATUS
1017 EFIAPI
1018 XhcSetConfigCmd (
1019 IN USB_XHCI_INSTANCE *Xhc,
1020 IN UINT8 SlotId,
1021 IN UINT8 DeviceSpeed,
1022 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
1023 );
1024
1025
1026 /**
1027 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
1028
1029 @param Xhc The XHCI Instance.
1030 @param SlotId The slot id to be configured.
1031 @param DeviceSpeed The device's speed.
1032 @param ConfigDesc The pointer to the usb device configuration descriptor.
1033
1034 @retval EFI_SUCCESS Successfully configure all the device endpoints.
1035
1036 **/
1037 EFI_STATUS
1038 EFIAPI
1039 XhcSetConfigCmd64 (
1040 IN USB_XHCI_INSTANCE *Xhc,
1041 IN UINT8 SlotId,
1042 IN UINT8 DeviceSpeed,
1043 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
1044 );
1045
1046 /**
1047 Set interface through XHCI's Configure_Endpoint cmd.
1048
1049 @param Xhc The XHCI Instance.
1050 @param SlotId The slot id to be configured.
1051 @param DeviceSpeed The device's speed.
1052 @param ConfigDesc The pointer to the usb device configuration descriptor.
1053 @param Request USB device request to send.
1054
1055 @retval EFI_SUCCESS Successfully set interface.
1056
1057 **/
1058 EFI_STATUS
1059 EFIAPI
1060 XhcSetInterface (
1061 IN USB_XHCI_INSTANCE *Xhc,
1062 IN UINT8 SlotId,
1063 IN UINT8 DeviceSpeed,
1064 IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
1065 IN EFI_USB_DEVICE_REQUEST *Request
1066 );
1067
1068 /**
1069 Set interface through XHCI's Configure_Endpoint cmd.
1070
1071 @param Xhc The XHCI Instance.
1072 @param SlotId The slot id to be configured.
1073 @param DeviceSpeed The device's speed.
1074 @param ConfigDesc The pointer to the usb device configuration descriptor.
1075 @param Request USB device request to send.
1076
1077 @retval EFI_SUCCESS Successfully set interface.
1078
1079 **/
1080 EFI_STATUS
1081 EFIAPI
1082 XhcSetInterface64 (
1083 IN USB_XHCI_INSTANCE *Xhc,
1084 IN UINT8 SlotId,
1085 IN UINT8 DeviceSpeed,
1086 IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
1087 IN EFI_USB_DEVICE_REQUEST *Request
1088 );
1089
1090 /**
1091 Find out the actual device address according to the requested device address from UsbBus.
1092
1093 @param Xhc The XHCI Instance.
1094 @param BusDevAddr The requested device address by UsbBus upper driver.
1095
1096 @return The actual device address assigned to the device.
1097
1098 **/
1099 UINT8
1100 EFIAPI
1101 XhcBusDevAddrToSlotId (
1102 IN USB_XHCI_INSTANCE *Xhc,
1103 IN UINT8 BusDevAddr
1104 );
1105
1106 /**
1107 Assign and initialize the device slot for a new device.
1108
1109 @param Xhc The XHCI Instance.
1110 @param ParentRouteChart The route string pointed to the parent device.
1111 @param ParentPort The port at which the device is located.
1112 @param RouteChart The route string pointed to the device.
1113 @param DeviceSpeed The device speed.
1114
1115 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1116
1117 **/
1118 EFI_STATUS
1119 EFIAPI
1120 XhcInitializeDeviceSlot (
1121 IN USB_XHCI_INSTANCE *Xhc,
1122 IN USB_DEV_ROUTE ParentRouteChart,
1123 IN UINT16 ParentPort,
1124 IN USB_DEV_ROUTE RouteChart,
1125 IN UINT8 DeviceSpeed
1126 );
1127
1128 /**
1129 Assign and initialize the device slot for a new device.
1130
1131 @param Xhc The XHCI Instance.
1132 @param ParentRouteChart The route string pointed to the parent device.
1133 @param ParentPort The port at which the device is located.
1134 @param RouteChart The route string pointed to the device.
1135 @param DeviceSpeed The device speed.
1136
1137 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1138
1139 **/
1140 EFI_STATUS
1141 EFIAPI
1142 XhcInitializeDeviceSlot64 (
1143 IN USB_XHCI_INSTANCE *Xhc,
1144 IN USB_DEV_ROUTE ParentRouteChart,
1145 IN UINT16 ParentPort,
1146 IN USB_DEV_ROUTE RouteChart,
1147 IN UINT8 DeviceSpeed
1148 );
1149
1150 /**
1151 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
1152
1153 @param Xhc The XHCI Instance.
1154 @param SlotId The slot id to be evaluated.
1155 @param MaxPacketSize The max packet size supported by the device control transfer.
1156
1157 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
1158
1159 **/
1160 EFI_STATUS
1161 EFIAPI
1162 XhcEvaluateContext (
1163 IN USB_XHCI_INSTANCE *Xhc,
1164 IN UINT8 SlotId,
1165 IN UINT32 MaxPacketSize
1166 );
1167
1168
1169 /**
1170 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
1171
1172 @param Xhc The XHCI Instance.
1173 @param SlotId The slot id to be evaluated.
1174 @param MaxPacketSize The max packet size supported by the device control transfer.
1175
1176 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
1177
1178 **/
1179 EFI_STATUS
1180 EFIAPI
1181 XhcEvaluateContext64 (
1182 IN USB_XHCI_INSTANCE *Xhc,
1183 IN UINT8 SlotId,
1184 IN UINT32 MaxPacketSize
1185 );
1186
1187
1188 /**
1189 Disable the specified device slot.
1190
1191 @param Xhc The XHCI Instance.
1192 @param SlotId The slot id to be disabled.
1193
1194 @retval EFI_SUCCESS Successfully disable the device slot.
1195
1196 **/
1197 EFI_STATUS
1198 EFIAPI
1199 XhcDisableSlotCmd (
1200 IN USB_XHCI_INSTANCE *Xhc,
1201 IN UINT8 SlotId
1202 );
1203
1204
1205 /**
1206 Disable the specified device slot.
1207
1208 @param Xhc The XHCI Instance.
1209 @param SlotId The slot id to be disabled.
1210
1211 @retval EFI_SUCCESS Successfully disable the device slot.
1212
1213 **/
1214 EFI_STATUS
1215 EFIAPI
1216 XhcDisableSlotCmd64 (
1217 IN USB_XHCI_INSTANCE *Xhc,
1218 IN UINT8 SlotId
1219 );
1220
1221
1222 /**
1223 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
1224
1225 @param Xhc The XHCI Instance.
1226 @param TrsRing The transfer ring to sync.
1227
1228 @retval EFI_SUCCESS The transfer ring is synchronized successfully.
1229
1230 **/
1231 EFI_STATUS
1232 EFIAPI
1233 XhcSyncTrsRing (
1234 IN USB_XHCI_INSTANCE *Xhc,
1235 TRANSFER_RING *TrsRing
1236 );
1237
1238 /**
1239 Synchronize the specified event ring to update the enqueue and dequeue pointer.
1240
1241 @param Xhc The XHCI Instance.
1242 @param EvtRing The event ring to sync.
1243
1244 @retval EFI_SUCCESS The event ring is synchronized successfully.
1245
1246 **/
1247 EFI_STATUS
1248 EFIAPI
1249 XhcSyncEventRing (
1250 IN USB_XHCI_INSTANCE *Xhc,
1251 EVENT_RING *EvtRing
1252 );
1253
1254 /**
1255 Check if there is a new generated event.
1256
1257 @param Xhc The XHCI Instance.
1258 @param EvtRing The event ring to check.
1259 @param NewEvtTrb The new event TRB found.
1260
1261 @retval EFI_SUCCESS Found a new event TRB at the event ring.
1262 @retval EFI_NOT_READY The event ring has no new event.
1263
1264 **/
1265 EFI_STATUS
1266 EFIAPI
1267 XhcCheckNewEvent (
1268 IN USB_XHCI_INSTANCE *Xhc,
1269 IN EVENT_RING *EvtRing,
1270 OUT TRB_TEMPLATE **NewEvtTrb
1271 );
1272
1273 /**
1274 Create XHCI transfer ring.
1275
1276 @param Xhc The XHCI Instance.
1277 @param TrbNum The number of TRB in the ring.
1278 @param TransferRing The created transfer ring.
1279
1280 **/
1281 VOID
1282 CreateTransferRing (
1283 IN USB_XHCI_INSTANCE *Xhc,
1284 IN UINTN TrbNum,
1285 OUT TRANSFER_RING *TransferRing
1286 );
1287
1288 /**
1289 Create XHCI event ring.
1290
1291 @param Xhc The XHCI Instance.
1292 @param EventRing The created event ring.
1293
1294 **/
1295 VOID
1296 CreateEventRing (
1297 IN USB_XHCI_INSTANCE *Xhc,
1298 OUT EVENT_RING *EventRing
1299 );
1300
1301 /**
1302 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted
1303 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint
1304 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is
1305 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the
1306 Stopped to the Running state.
1307
1308 @param Xhc The XHCI Instance.
1309 @param Urb The urb which makes the endpoint halted.
1310
1311 @retval EFI_SUCCESS The recovery is successful.
1312 @retval Others Failed to recovery halted endpoint.
1313
1314 **/
1315 EFI_STATUS
1316 EFIAPI
1317 XhcRecoverHaltedEndpoint (
1318 IN USB_XHCI_INSTANCE *Xhc,
1319 IN URB *Urb
1320 );
1321
1322 /**
1323 System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer
1324 Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to
1325 the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running
1326 state.
1327
1328 @param Xhc The XHCI Instance.
1329 @param Urb The urb which doesn't get completed in a specified timeout range.
1330
1331 @retval EFI_SUCCESS The dequeuing of the TDs is successful.
1332 @retval Others Failed to stop the endpoint and dequeue the TDs.
1333
1334 **/
1335 EFI_STATUS
1336 EFIAPI
1337 XhcDequeueTrbFromEndpoint (
1338 IN USB_XHCI_INSTANCE *Xhc,
1339 IN URB *Urb
1340 );
1341
1342 /**
1343 Stop endpoint through XHCI's Stop_Endpoint cmd.
1344
1345 @param Xhc The XHCI Instance.
1346 @param SlotId The slot id to be configured.
1347 @param Dci The device context index of endpoint.
1348 @param PendingUrb The pending URB to check completion status when stopping the end point.
1349
1350 @retval EFI_SUCCESS Stop endpoint successfully.
1351 @retval Others Failed to stop endpoint.
1352
1353 **/
1354 EFI_STATUS
1355 EFIAPI
1356 XhcStopEndpoint (
1357 IN USB_XHCI_INSTANCE *Xhc,
1358 IN UINT8 SlotId,
1359 IN UINT8 Dci,
1360 IN URB *PendingUrb OPTIONAL
1361 );
1362
1363 /**
1364 Reset endpoint through XHCI's Reset_Endpoint cmd.
1365
1366 @param Xhc The XHCI Instance.
1367 @param SlotId The slot id to be configured.
1368 @param Dci The device context index of endpoint.
1369
1370 @retval EFI_SUCCESS Reset endpoint successfully.
1371 @retval Others Failed to reset endpoint.
1372
1373 **/
1374 EFI_STATUS
1375 EFIAPI
1376 XhcResetEndpoint (
1377 IN USB_XHCI_INSTANCE *Xhc,
1378 IN UINT8 SlotId,
1379 IN UINT8 Dci
1380 );
1381
1382 /**
1383 Set transfer ring dequeue pointer through XHCI's Set_Tr_Dequeue_Pointer cmd.
1384
1385 @param Xhc The XHCI Instance.
1386 @param SlotId The slot id to be configured.
1387 @param Dci The device context index of endpoint.
1388 @param Urb The dequeue pointer of the transfer ring specified
1389 by the urb to be updated.
1390
1391 @retval EFI_SUCCESS Set transfer ring dequeue pointer succeeds.
1392 @retval Others Failed to set transfer ring dequeue pointer.
1393
1394 **/
1395 EFI_STATUS
1396 EFIAPI
1397 XhcSetTrDequeuePointer (
1398 IN USB_XHCI_INSTANCE *Xhc,
1399 IN UINT8 SlotId,
1400 IN UINT8 Dci,
1401 IN URB *Urb
1402 );
1403
1404 /**
1405 Create a new URB for a new transaction.
1406
1407 @param Xhc The XHCI Instance
1408 @param DevAddr The device address
1409 @param EpAddr Endpoint addrress
1410 @param DevSpeed The device speed
1411 @param MaxPacket The max packet length of the endpoint
1412 @param Type The transaction type
1413 @param Request The standard USB request for control transfer
1414 @param Data The user data to transfer
1415 @param DataLen The length of data buffer
1416 @param Callback The function to call when data is transferred
1417 @param Context The context to the callback
1418
1419 @return Created URB or NULL
1420
1421 **/
1422 URB*
1423 XhcCreateUrb (
1424 IN USB_XHCI_INSTANCE *Xhc,
1425 IN UINT8 DevAddr,
1426 IN UINT8 EpAddr,
1427 IN UINT8 DevSpeed,
1428 IN UINTN MaxPacket,
1429 IN UINTN Type,
1430 IN EFI_USB_DEVICE_REQUEST *Request,
1431 IN VOID *Data,
1432 IN UINTN DataLen,
1433 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
1434 IN VOID *Context
1435 );
1436
1437 /**
1438 Free an allocated URB.
1439
1440 @param Xhc The XHCI device.
1441 @param Urb The URB to free.
1442
1443 **/
1444 VOID
1445 XhcFreeUrb (
1446 IN USB_XHCI_INSTANCE *Xhc,
1447 IN URB *Urb
1448 );
1449
1450 /**
1451 Create a transfer TRB.
1452
1453 @param Xhc The XHCI Instance
1454 @param Urb The urb used to construct the transfer TRB.
1455
1456 @return Created TRB or NULL
1457
1458 **/
1459 EFI_STATUS
1460 XhcCreateTransferTrb (
1461 IN USB_XHCI_INSTANCE *Xhc,
1462 IN URB *Urb
1463 );
1464
1465 #endif
EFI Development Kit II mirror for PVE