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1 /** @file
2
3 This file contains the definition for XHCI host controller schedule routines.
4
5 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #ifndef _EFI_XHCI_SCHED_H_
17 #define _EFI_XHCI_SCHED_H_
18
19 #define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
20
21 //
22 // Transfer types, used in URB to identify the transfer type
23 //
24 #define XHC_CTRL_TRANSFER 0x01
25 #define XHC_BULK_TRANSFER 0x02
26 #define XHC_INT_TRANSFER_SYNC 0x04
27 #define XHC_INT_TRANSFER_ASYNC 0x08
28 #define XHC_INT_ONLY_TRANSFER_ASYNC 0x10
29
30 //
31 // 6.4.6 TRB Types
32 //
33 #define TRB_TYPE_NORMAL 1
34 #define TRB_TYPE_SETUP_STAGE 2
35 #define TRB_TYPE_DATA_STAGE 3
36 #define TRB_TYPE_STATUS_STAGE 4
37 #define TRB_TYPE_ISOCH 5
38 #define TRB_TYPE_LINK 6
39 #define TRB_TYPE_EVENT_DATA 7
40 #define TRB_TYPE_NO_OP 8
41 #define TRB_TYPE_EN_SLOT 9
42 #define TRB_TYPE_DIS_SLOT 10
43 #define TRB_TYPE_ADDRESS_DEV 11
44 #define TRB_TYPE_CON_ENDPOINT 12
45 #define TRB_TYPE_EVALU_CONTXT 13
46 #define TRB_TYPE_RESET_ENDPOINT 14
47 #define TRB_TYPE_STOP_ENDPOINT 15
48 #define TRB_TYPE_SET_TR_DEQUE 16
49 #define TRB_TYPE_RESET_DEV 17
50 #define TRB_TYPE_GET_PORT_BANW 21
51 #define TRB_TYPE_FORCE_HEADER 22
52 #define TRB_TYPE_NO_OP_COMMAND 23
53 #define TRB_TYPE_TRANS_EVENT 32
54 #define TRB_TYPE_COMMAND_COMPLT_EVENT 33
55 #define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
56 #define TRB_TYPE_HOST_CONTROLLER_EVENT 37
57 #define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
58 #define TRB_TYPE_MFINDEX_WRAP_EVENT 39
59
60 //
61 // Endpoint Type (EP Type).
62 //
63 #define ED_NOT_VALID 0
64 #define ED_ISOCH_OUT 1
65 #define ED_BULK_OUT 2
66 #define ED_INTERRUPT_OUT 3
67 #define ED_CONTROL_BIDIR 4
68 #define ED_ISOCH_IN 5
69 #define ED_BULK_IN 6
70 #define ED_INTERRUPT_IN 7
71
72 //
73 // 6.4.5 TRB Completion Codes
74 //
75 #define TRB_COMPLETION_INVALID 0
76 #define TRB_COMPLETION_SUCCESS 1
77 #define TRB_COMPLETION_DATA_BUFFER_ERROR 2
78 #define TRB_COMPLETION_BABBLE_ERROR 3
79 #define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
80 #define TRB_COMPLETION_TRB_ERROR 5
81 #define TRB_COMPLETION_STALL_ERROR 6
82 #define TRB_COMPLETION_SHORT_PACKET 13
83
84 //
85 // The topology string used to present usb device location
86 //
87 typedef struct _USB_DEV_TOPOLOGY {
88 //
89 // The tier concatenation of down stream port.
90 //
91 UINT32 RouteString:20;
92 //
93 // The root port number of the chain.
94 //
95 UINT32 RootPortNum:8;
96 //
97 // The Tier the device reside.
98 //
99 UINT32 TierNum:4;
100 } USB_DEV_TOPOLOGY;
101
102 //
103 // USB Device's RouteChart
104 //
105 typedef union _USB_DEV_ROUTE {
106 UINT32 Dword;
107 USB_DEV_TOPOLOGY Route;
108 } USB_DEV_ROUTE;
109
110 //
111 // Endpoint address and its capabilities
112 //
113 typedef struct _USB_ENDPOINT {
114 //
115 // Store logical device address assigned by UsbBus
116 // It's because some XHCI host controllers may assign the same physcial device
117 // address for those devices inserted at different root port.
118 //
119 UINT8 BusAddr;
120 UINT8 DevAddr;
121 UINT8 EpAddr;
122 EFI_USB_DATA_DIRECTION Direction;
123 UINT8 DevSpeed;
124 UINTN MaxPacket;
125 UINTN Type;
126 } USB_ENDPOINT;
127
128 //
129 // TRB Template
130 //
131 typedef struct _TRB_TEMPLATE {
132 UINT32 Parameter1;
133
134 UINT32 Parameter2;
135
136 UINT32 Status;
137
138 UINT32 CycleBit:1;
139 UINT32 RsvdZ1:9;
140 UINT32 Type:6;
141 UINT32 Control:16;
142 } TRB_TEMPLATE;
143
144 typedef struct _TRANSFER_RING {
145 VOID *RingSeg0;
146 UINTN TrbNumber;
147 TRB_TEMPLATE *RingEnqueue;
148 TRB_TEMPLATE *RingDequeue;
149 UINT32 RingPCS;
150 } TRANSFER_RING;
151
152 typedef struct _EVENT_RING {
153 VOID *ERSTBase;
154 VOID *EventRingSeg0;
155 UINTN TrbNumber;
156 TRB_TEMPLATE *EventRingEnqueue;
157 TRB_TEMPLATE *EventRingDequeue;
158 UINT32 EventRingCCS;
159 } EVENT_RING;
160
161 //
162 // URB (Usb Request Block) contains information for all kinds of
163 // usb requests.
164 //
165 typedef struct _URB {
166 UINT32 Signature;
167 LIST_ENTRY UrbList;
168 //
169 // Usb Device URB related information
170 //
171 USB_ENDPOINT Ep;
172 EFI_USB_DEVICE_REQUEST *Request;
173 VOID *Data;
174 UINTN DataLen;
175 EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
176 VOID *Context;
177 //
178 // Execute result
179 //
180 UINT32 Result;
181 //
182 // completed data length
183 //
184 UINTN Completed;
185 //
186 // Command/Tranfer Ring info
187 //
188 TRANSFER_RING *Ring;
189 TRB_TEMPLATE *TrbStart;
190 TRB_TEMPLATE *TrbEnd;
191 UINTN TrbNum;
192 EVENT_RING *EvtRing;
193 TRB_TEMPLATE *EvtTrbStart;
194 } URB;
195
196 //
197 // 6.5 Event Ring Segment Table
198 // The Event Ring Segment Table is used to define multi-segment Event Rings and to enable runtime
199 // expansion and shrinking of the Event Ring. The location of the Event Ring Segment Table is defined by the
200 // Event Ring Segment Table Base Address Register (5.5.2.3.2). The size of the Event Ring Segment Table
201 // is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).
202 //
203 typedef struct _EVENT_RING_SEG_TABLE_ENTRY {
204 UINT32 PtrLo;
205 UINT32 PtrHi;
206 UINT32 RingTrbSize:16;
207 UINT32 RsvdZ1:16;
208 UINT32 RsvdZ2;
209 } EVENT_RING_SEG_TABLE_ENTRY;
210
211 //
212 // 6.4.1.1 Normal TRB
213 // A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and
214 // Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer
215 // Rings, and to define the Data stage information for Control Transfer Rings.
216 //
217 typedef struct _TRANSFER_TRB_NORMAL {
218 UINT32 TRBPtrLo;
219
220 UINT32 TRBPtrHi;
221
222 UINT32 Lenth:17;
223 UINT32 TDSize:5;
224 UINT32 IntTarget:10;
225
226 UINT32 CycleBit:1;
227 UINT32 ENT:1;
228 UINT32 ISP:1;
229 UINT32 NS:1;
230 UINT32 CH:1;
231 UINT32 IOC:1;
232 UINT32 IDT:1;
233 UINT32 RsvdZ1:2;
234 UINT32 BEI:1;
235 UINT32 Type:6;
236 UINT32 RsvdZ2:16;
237 } TRANSFER_TRB_NORMAL;
238
239 //
240 // 6.4.1.2.1 Setup Stage TRB
241 // A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.
242 //
243 typedef struct _TRANSFER_TRB_CONTROL_SETUP {
244 UINT32 bmRequestType:8;
245 UINT32 bRequest:8;
246 UINT32 wValue:16;
247
248 UINT32 wIndex:16;
249 UINT32 wLength:16;
250
251 UINT32 Lenth:17;
252 UINT32 RsvdZ1:5;
253 UINT32 IntTarget:10;
254
255 UINT32 CycleBit:1;
256 UINT32 RsvdZ2:4;
257 UINT32 IOC:1;
258 UINT32 IDT:1;
259 UINT32 RsvdZ3:3;
260 UINT32 Type:6;
261 UINT32 TRT:2;
262 UINT32 RsvdZ4:14;
263 } TRANSFER_TRB_CONTROL_SETUP;
264
265 //
266 // 6.4.1.2.2 Data Stage TRB
267 // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
268 //
269 typedef struct _TRANSFER_TRB_CONTROL_DATA {
270 UINT32 TRBPtrLo;
271
272 UINT32 TRBPtrHi;
273
274 UINT32 Lenth:17;
275 UINT32 TDSize:5;
276 UINT32 IntTarget:10;
277
278 UINT32 CycleBit:1;
279 UINT32 ENT:1;
280 UINT32 ISP:1;
281 UINT32 NS:1;
282 UINT32 CH:1;
283 UINT32 IOC:1;
284 UINT32 IDT:1;
285 UINT32 RsvdZ1:3;
286 UINT32 Type:6;
287 UINT32 DIR:1;
288 UINT32 RsvdZ2:15;
289 } TRANSFER_TRB_CONTROL_DATA;
290
291 //
292 // 6.4.1.2.2 Data Stage TRB
293 // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
294 //
295 typedef struct _TRANSFER_TRB_CONTROL_STATUS {
296 UINT32 RsvdZ1;
297 UINT32 RsvdZ2;
298
299 UINT32 RsvdZ3:22;
300 UINT32 IntTarget:10;
301
302 UINT32 CycleBit:1;
303 UINT32 ENT:1;
304 UINT32 RsvdZ4:2;
305 UINT32 CH:1;
306 UINT32 IOC:1;
307 UINT32 RsvdZ5:4;
308 UINT32 Type:6;
309 UINT32 DIR:1;
310 UINT32 RsvdZ6:15;
311 } TRANSFER_TRB_CONTROL_STATUS;
312
313 //
314 // 6.4.2.1 Transfer Event TRB
315 // A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1
316 // for more information on the use and operation of Transfer Events.
317 //
318 typedef struct _EVT_TRB_TRANSFER {
319 UINT32 TRBPtrLo;
320
321 UINT32 TRBPtrHi;
322
323 UINT32 Lenth:24;
324 UINT32 Completecode:8;
325
326 UINT32 CycleBit:1;
327 UINT32 RsvdZ1:1;
328 UINT32 ED:1;
329 UINT32 RsvdZ2:7;
330 UINT32 Type:6;
331 UINT32 EndpointId:5;
332 UINT32 RsvdZ3:3;
333 UINT32 SlotId:8;
334 } EVT_TRB_TRANSFER;
335
336 //
337 // 6.4.2.2 Command Completion Event TRB
338 // A Command Completion Event TRB shall be generated by the xHC when a command completes on the
339 // Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.
340 //
341 typedef struct _EVT_TRB_COMMAND_COMPLETION {
342 UINT32 TRBPtrLo;
343
344 UINT32 TRBPtrHi;
345
346 UINT32 RsvdZ2:24;
347 UINT32 Completecode:8;
348
349 UINT32 CycleBit:1;
350 UINT32 RsvdZ3:9;
351 UINT32 Type:6;
352 UINT32 VFID:8;
353 UINT32 SlotId:8;
354 } EVT_TRB_COMMAND_COMPLETION;
355
356 typedef union _TRB {
357 TRB_TEMPLATE TrbTemplate;
358 TRANSFER_TRB_NORMAL TrbNormal;
359 TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;
360 TRANSFER_TRB_CONTROL_DATA TrbCtrData;
361 TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;
362 } TRB;
363
364 //
365 // 6.4.3.1 No Op Command TRB
366 // The No Op Command TRB provides a simple means for verifying the operation of the Command Ring
367 // mechanisms offered by the xHCI.
368 //
369 typedef struct _CMD_TRB_NO_OP {
370 UINT32 RsvdZ0;
371 UINT32 RsvdZ1;
372 UINT32 RsvdZ2;
373
374 UINT32 CycleBit:1;
375 UINT32 RsvdZ3:9;
376 UINT32 Type:6;
377 UINT32 RsvdZ4:16;
378 } CMD_TRB_NO_OP;
379
380 //
381 // 6.4.3.2 Enable Slot Command TRB
382 // The Enable Slot Command TRB causes the xHC to select an available Device Slot and return the ID of the
383 // selected slot to the host in a Command Completion Event.
384 //
385 typedef struct _CMD_TRB_ENABLE_SLOT {
386 UINT32 RsvdZ0;
387 UINT32 RsvdZ1;
388 UINT32 RsvdZ2;
389
390 UINT32 CycleBit:1;
391 UINT32 RsvdZ3:9;
392 UINT32 Type:6;
393 UINT32 RsvdZ4:16;
394 } CMD_TRB_ENABLE_SLOT;
395
396 //
397 // 6.4.3.3 Disable Slot Command TRB
398 // The Disable Slot Command TRB releases any bandwidth assigned to the disabled slot and frees any
399 // internal xHC resources assigned to the slot.
400 //
401 typedef struct _CMD_TRB_DISABLE_SLOT {
402 UINT32 RsvdZ0;
403 UINT32 RsvdZ1;
404 UINT32 RsvdZ2;
405
406 UINT32 CycleBit:1;
407 UINT32 RsvdZ3:9;
408 UINT32 Type:6;
409 UINT32 RsvdZ4:8;
410 UINT32 SlotId:8;
411 } CMD_TRB_DISABLE_SLOT;
412
413 //
414 // 6.4.3.4 Address Device Command TRB
415 // The Address Device Command TRB transitions the selected Device Context from the Default to the
416 // Addressed state and causes the xHC to select an address for the USB device in the Default State and
417 // issue a SET_ADDRESS request to the USB device.
418 //
419 typedef struct _CMD_TRB_ADDRESS_DEVICE {
420 UINT32 PtrLo;
421
422 UINT32 PtrHi;
423
424 UINT32 RsvdZ1;
425
426 UINT32 CycleBit:1;
427 UINT32 RsvdZ2:8;
428 UINT32 BSR:1;
429 UINT32 Type:6;
430 UINT32 RsvdZ3:8;
431 UINT32 SlotId:8;
432 } CMD_TRB_ADDRESS_DEVICE;
433
434 //
435 // 6.4.3.5 Configure Endpoint Command TRB
436 // The Configure Endpoint Command TRB evaluates the bandwidth and resource requirements of the
437 // endpoints selected by the command.
438 //
439 typedef struct _CMD_TRB_CONFIG_ENDPOINT {
440 UINT32 PtrLo;
441
442 UINT32 PtrHi;
443
444 UINT32 RsvdZ1;
445
446 UINT32 CycleBit:1;
447 UINT32 RsvdZ2:8;
448 UINT32 DC:1;
449 UINT32 Type:6;
450 UINT32 RsvdZ3:8;
451 UINT32 SlotId:8;
452 } CMD_TRB_CONFIG_ENDPOINT;
453
454 //
455 // 6.4.3.6 Evaluate Context Command TRB
456 // The Evaluate Context Command TRB is used by system software to inform the xHC that the selected
457 // Context data structures in the Device Context have been modified by system software and that the xHC
458 // shall evaluate any changes
459 //
460 typedef struct _CMD_TRB_EVALUATE_CONTEXT {
461 UINT32 PtrLo;
462
463 UINT32 PtrHi;
464
465 UINT32 RsvdZ1;
466
467 UINT32 CycleBit:1;
468 UINT32 RsvdZ2:9;
469 UINT32 Type:6;
470 UINT32 RsvdZ3:8;
471 UINT32 SlotId:8;
472 } CMD_TRB_EVALUATE_CONTEXT;
473
474 //
475 // 6.4.3.7 Reset Endpoint Command TRB
476 // The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring
477 //
478 typedef struct _CMD_TRB_RESET_ENDPOINT {
479 UINT32 RsvdZ0;
480 UINT32 RsvdZ1;
481 UINT32 RsvdZ2;
482
483 UINT32 CycleBit:1;
484 UINT32 RsvdZ3:8;
485 UINT32 TSP:1;
486 UINT32 Type:6;
487 UINT32 EDID:5;
488 UINT32 RsvdZ4:3;
489 UINT32 SlotId:8;
490 } CMD_TRB_RESET_ENDPOINT;
491
492 //
493 // 6.4.3.8 Stop Endpoint Command TRB
494 // The Stop Endpoint Command TRB command allows software to stop the xHC execution of the TDs on a
495 // Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.
496 //
497 typedef struct _CMD_TRB_STOP_ENDPOINT {
498 UINT32 RsvdZ0;
499 UINT32 RsvdZ1;
500 UINT32 RsvdZ2;
501
502 UINT32 CycleBit:1;
503 UINT32 RsvdZ3:9;
504 UINT32 Type:6;
505 UINT32 EDID:5;
506 UINT32 RsvdZ4:2;
507 UINT32 SP:1;
508 UINT32 SlotId:8;
509 } CMD_TRB_STOP_ENDPOINT;
510
511 //
512 // 6.4.3.9 Set TR Dequeue Pointer Command TRB
513 // The Set TR Dequeue Pointer Command TRB is used by system software to modify the TR Dequeue
514 // Pointer and DCS fields of an Endpoint or Stream Context.
515 //
516 typedef struct _CMD_SET_TR_DEQ_POINTER {
517 UINT32 PtrLo;
518
519 UINT32 PtrHi;
520
521 UINT32 RsvdZ1:16;
522 UINT32 StreamID:16;
523
524 UINT32 CycleBit:1;
525 UINT32 RsvdZ2:9;
526 UINT32 Type:6;
527 UINT32 Endpoint:5;
528 UINT32 RsvdZ3:3;
529 UINT32 SlotId:8;
530 } CMD_SET_TR_DEQ_POINTER;
531
532 //
533 // 6.4.4.1 Link TRB
534 // A Link TRB provides support for non-contiguous TRB Rings.
535 //
536 typedef struct _LINK_TRB {
537 UINT32 PtrLo;
538
539 UINT32 PtrHi;
540
541 UINT32 RsvdZ1:22;
542 UINT32 InterTarget:10;
543
544 UINT32 CycleBit:1;
545 UINT32 TC:1;
546 UINT32 RsvdZ2:2;
547 UINT32 CH:1;
548 UINT32 IOC:1;
549 UINT32 RsvdZ3:4;
550 UINT32 Type:6;
551 UINT32 RsvdZ4:16;
552 } LINK_TRB;
553
554 //
555 // 6.2.2 Slot Context
556 //
557 typedef struct _SLOT_CONTEXT {
558 UINT32 RouteString:20;
559 UINT32 Speed:4;
560 UINT32 RsvdZ1:1;
561 UINT32 MTT:1;
562 UINT32 Hub:1;
563 UINT32 ContextEntries:5;
564
565 UINT32 MaxExitLatency:16;
566 UINT32 RootHubPortNum:8;
567 UINT32 PortNum:8;
568
569 UINT32 TTHubSlotId:8;
570 UINT32 TTPortNum:8;
571 UINT32 TTT:2;
572 UINT32 RsvdZ2:4;
573 UINT32 InterTarget:10;
574
575 UINT32 DeviceAddress:8;
576 UINT32 RsvdZ3:19;
577 UINT32 SlotState:5;
578
579 UINT32 RsvdZ4;
580 UINT32 RsvdZ5;
581 UINT32 RsvdZ6;
582 UINT32 RsvdZ7;
583 } SLOT_CONTEXT;
584
585 typedef struct _SLOT_CONTEXT_64 {
586 UINT32 RouteString:20;
587 UINT32 Speed:4;
588 UINT32 RsvdZ1:1;
589 UINT32 MTT:1;
590 UINT32 Hub:1;
591 UINT32 ContextEntries:5;
592
593 UINT32 MaxExitLatency:16;
594 UINT32 RootHubPortNum:8;
595 UINT32 PortNum:8;
596
597 UINT32 TTHubSlotId:8;
598 UINT32 TTPortNum:8;
599 UINT32 TTT:2;
600 UINT32 RsvdZ2:4;
601 UINT32 InterTarget:10;
602
603 UINT32 DeviceAddress:8;
604 UINT32 RsvdZ3:19;
605 UINT32 SlotState:5;
606
607 UINT32 RsvdZ4;
608 UINT32 RsvdZ5;
609 UINT32 RsvdZ6;
610 UINT32 RsvdZ7;
611
612 UINT32 RsvdZ8;
613 UINT32 RsvdZ9;
614 UINT32 RsvdZ10;
615 UINT32 RsvdZ11;
616
617 UINT32 RsvdZ12;
618 UINT32 RsvdZ13;
619 UINT32 RsvdZ14;
620 UINT32 RsvdZ15;
621
622 } SLOT_CONTEXT_64;
623
624
625 //
626 // 6.2.3 Endpoint Context
627 //
628 typedef struct _ENDPOINT_CONTEXT {
629 UINT32 EPState:3;
630 UINT32 RsvdZ1:5;
631 UINT32 Mult:2;
632 UINT32 MaxPStreams:5;
633 UINT32 LSA:1;
634 UINT32 Interval:8;
635 UINT32 RsvdZ2:8;
636
637 UINT32 RsvdZ3:1;
638 UINT32 CErr:2;
639 UINT32 EPType:3;
640 UINT32 RsvdZ4:1;
641 UINT32 HID:1;
642 UINT32 MaxBurstSize:8;
643 UINT32 MaxPacketSize:16;
644
645 UINT32 PtrLo;
646
647 UINT32 PtrHi;
648
649 UINT32 AverageTRBLength:16;
650 UINT32 MaxESITPayload:16;
651
652 UINT32 RsvdZ5;
653 UINT32 RsvdZ6;
654 UINT32 RsvdZ7;
655 } ENDPOINT_CONTEXT;
656
657 typedef struct _ENDPOINT_CONTEXT_64 {
658 UINT32 EPState:3;
659 UINT32 RsvdZ1:5;
660 UINT32 Mult:2;
661 UINT32 MaxPStreams:5;
662 UINT32 LSA:1;
663 UINT32 Interval:8;
664 UINT32 RsvdZ2:8;
665
666 UINT32 RsvdZ3:1;
667 UINT32 CErr:2;
668 UINT32 EPType:3;
669 UINT32 RsvdZ4:1;
670 UINT32 HID:1;
671 UINT32 MaxBurstSize:8;
672 UINT32 MaxPacketSize:16;
673
674 UINT32 PtrLo;
675
676 UINT32 PtrHi;
677
678 UINT32 AverageTRBLength:16;
679 UINT32 MaxESITPayload:16;
680
681 UINT32 RsvdZ5;
682 UINT32 RsvdZ6;
683 UINT32 RsvdZ7;
684
685 UINT32 RsvdZ8;
686 UINT32 RsvdZ9;
687 UINT32 RsvdZ10;
688 UINT32 RsvdZ11;
689
690 UINT32 RsvdZ12;
691 UINT32 RsvdZ13;
692 UINT32 RsvdZ14;
693 UINT32 RsvdZ15;
694
695 } ENDPOINT_CONTEXT_64;
696
697
698 //
699 // 6.2.5.1 Input Control Context
700 //
701 typedef struct _INPUT_CONTRL_CONTEXT {
702 UINT32 Dword1;
703 UINT32 Dword2;
704 UINT32 RsvdZ1;
705 UINT32 RsvdZ2;
706 UINT32 RsvdZ3;
707 UINT32 RsvdZ4;
708 UINT32 RsvdZ5;
709 UINT32 RsvdZ6;
710 } INPUT_CONTRL_CONTEXT;
711
712 typedef struct _INPUT_CONTRL_CONTEXT_64 {
713 UINT32 Dword1;
714 UINT32 Dword2;
715 UINT32 RsvdZ1;
716 UINT32 RsvdZ2;
717 UINT32 RsvdZ3;
718 UINT32 RsvdZ4;
719 UINT32 RsvdZ5;
720 UINT32 RsvdZ6;
721 UINT32 RsvdZ7;
722 UINT32 RsvdZ8;
723 UINT32 RsvdZ9;
724 UINT32 RsvdZ10;
725 UINT32 RsvdZ11;
726 UINT32 RsvdZ12;
727 UINT32 RsvdZ13;
728 UINT32 RsvdZ14;
729 } INPUT_CONTRL_CONTEXT_64;
730
731 //
732 // 6.2.1 Device Context
733 //
734 typedef struct _DEVICE_CONTEXT {
735 SLOT_CONTEXT Slot;
736 ENDPOINT_CONTEXT EP[31];
737 } DEVICE_CONTEXT;
738
739 typedef struct _DEVICE_CONTEXT_64 {
740 SLOT_CONTEXT_64 Slot;
741 ENDPOINT_CONTEXT_64 EP[31];
742 } DEVICE_CONTEXT_64;
743
744 //
745 // 6.2.5 Input Context
746 //
747 typedef struct _INPUT_CONTEXT {
748 INPUT_CONTRL_CONTEXT InputControlContext;
749 SLOT_CONTEXT Slot;
750 ENDPOINT_CONTEXT EP[31];
751 } INPUT_CONTEXT;
752
753 typedef struct _INPUT_CONTEXT_64 {
754 INPUT_CONTRL_CONTEXT_64 InputControlContext;
755 SLOT_CONTEXT_64 Slot;
756 ENDPOINT_CONTEXT_64 EP[31];
757 } INPUT_CONTEXT_64;
758
759
760 /**
761 Initialize the XHCI host controller for schedule.
762
763 @param Xhc The XHCI Instance to be initialized.
764
765 **/
766 VOID
767 XhcInitSched (
768 IN USB_XHCI_INSTANCE *Xhc
769 );
770
771 /**
772 Free the resouce allocated at initializing schedule.
773
774 @param Xhc The XHCI Instance.
775
776 **/
777 VOID
778 XhcFreeSched (
779 IN USB_XHCI_INSTANCE *Xhc
780 );
781
782 /**
783 Ring the door bell to notify XHCI there is a transaction to be executed through URB.
784
785 @param Xhc The XHCI Instance.
786 @param Urb The URB to be rung.
787
788 @retval EFI_SUCCESS Successfully ring the door bell.
789
790 **/
791 EFI_STATUS
792 RingIntTransferDoorBell (
793 IN USB_XHCI_INSTANCE *Xhc,
794 IN URB *Urb
795 );
796
797 /**
798 Execute the transfer by polling the URB. This is a synchronous operation.
799
800 @param Xhc The XHCI Instance.
801 @param CmdTransfer The executed URB is for cmd transfer or not.
802 @param Urb The URB to execute.
803 @param Timeout The time to wait before abort, in millisecond.
804
805 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
806 @return EFI_TIMEOUT The transfer failed due to time out.
807 @return EFI_SUCCESS The transfer finished OK.
808
809 **/
810 EFI_STATUS
811 XhcExecTransfer (
812 IN USB_XHCI_INSTANCE *Xhc,
813 IN BOOLEAN CmdTransfer,
814 IN URB *Urb,
815 IN UINTN Timeout
816 );
817
818 /**
819 Delete a single asynchronous interrupt transfer for
820 the device and endpoint.
821
822 @param Xhc The XHCI Instance.
823 @param BusAddr The logical device address assigned by UsbBus driver.
824 @param EpNum The endpoint of the target.
825
826 @retval EFI_SUCCESS An asynchronous transfer is removed.
827 @retval EFI_NOT_FOUND No transfer for the device is found.
828
829 **/
830 EFI_STATUS
831 XhciDelAsyncIntTransfer (
832 IN USB_XHCI_INSTANCE *Xhc,
833 IN UINT8 BusAddr,
834 IN UINT8 EpNum
835 );
836
837 /**
838 Remove all the asynchronous interrupt transfers.
839
840 @param Xhc The XHCI Instance.
841
842 **/
843 VOID
844 XhciDelAllAsyncIntTransfers (
845 IN USB_XHCI_INSTANCE *Xhc
846 );
847
848 /**
849 Set Bios Ownership
850
851 @param Xhc The XHCI Instance.
852
853 **/
854 VOID
855 XhcSetBiosOwnership (
856 IN USB_XHCI_INSTANCE *Xhc
857 );
858
859 /**
860 Clear Bios Ownership
861
862 @param Xhc The XHCI Instance.
863
864 **/
865 VOID
866 XhcClearBiosOwnership (
867 IN USB_XHCI_INSTANCE *Xhc
868 );
869
870 /**
871 Find out the slot id according to the device's route string.
872
873 @param Xhc The XHCI Instance.
874 @param RouteString The route string described the device location.
875
876 @return The slot id used by the device.
877
878 **/
879 UINT8
880 EFIAPI
881 XhcRouteStringToSlotId (
882 IN USB_XHCI_INSTANCE *Xhc,
883 IN USB_DEV_ROUTE RouteString
884 );
885
886 /**
887 Calculate the device context index by endpoint address and direction.
888
889 @param EpAddr The target endpoint number.
890 @param Direction The direction of the target endpoint.
891
892 @return The device context index of endpoint.
893
894 **/
895 UINT8
896 XhcEndpointToDci (
897 IN UINT8 EpAddr,
898 IN UINT8 Direction
899 );
900
901 /**
902 Ring the door bell to notify XHCI there is a transaction to be executed.
903
904 @param Xhc The XHCI Instance.
905 @param SlotId The slot id of the target device.
906 @param Dci The device context index of the target slot or endpoint.
907
908 @retval EFI_SUCCESS Successfully ring the door bell.
909
910 **/
911 EFI_STATUS
912 EFIAPI
913 XhcRingDoorBell (
914 IN USB_XHCI_INSTANCE *Xhc,
915 IN UINT8 SlotId,
916 IN UINT8 Dci
917 );
918
919 /**
920 Interrupt transfer periodic check handler.
921
922 @param Event Interrupt event.
923 @param Context Pointer to USB_XHCI_INSTANCE.
924
925 **/
926 VOID
927 EFIAPI
928 XhcMonitorAsyncRequests (
929 IN EFI_EVENT Event,
930 IN VOID *Context
931 );
932
933 /**
934 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.
935
936 @param Xhc The XHCI Instance.
937 @param ParentRouteChart The route string pointed to the parent device if it exists.
938 @param Port The port to be polled.
939 @param PortState The port state.
940
941 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.
942 @retval Others Should not appear.
943
944 **/
945 EFI_STATUS
946 EFIAPI
947 XhcPollPortStatusChange (
948 IN USB_XHCI_INSTANCE *Xhc,
949 IN USB_DEV_ROUTE ParentRouteChart,
950 IN UINT8 Port,
951 IN EFI_USB_PORT_STATUS *PortState
952 );
953
954 /**
955 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
956
957 @param Xhc The XHCI Instance.
958 @param SlotId The slot id to be configured.
959 @param PortNum The total number of downstream port supported by the hub.
960 @param TTT The TT think time of the hub device.
961 @param MTT The multi-TT of the hub device.
962
963 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
964
965 **/
966 EFI_STATUS
967 XhcConfigHubContext (
968 IN USB_XHCI_INSTANCE *Xhc,
969 IN UINT8 SlotId,
970 IN UINT8 PortNum,
971 IN UINT8 TTT,
972 IN UINT8 MTT
973 );
974
975
976 /**
977 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
978
979 @param Xhc The XHCI Instance.
980 @param SlotId The slot id to be configured.
981 @param PortNum The total number of downstream port supported by the hub.
982 @param TTT The TT think time of the hub device.
983 @param MTT The multi-TT of the hub device.
984
985 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
986
987 **/
988 EFI_STATUS
989 XhcConfigHubContext64 (
990 IN USB_XHCI_INSTANCE *Xhc,
991 IN UINT8 SlotId,
992 IN UINT8 PortNum,
993 IN UINT8 TTT,
994 IN UINT8 MTT
995 );
996
997
998 /**
999 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
1000
1001 @param Xhc The XHCI Instance.
1002 @param SlotId The slot id to be configured.
1003 @param DeviceSpeed The device's speed.
1004 @param ConfigDesc The pointer to the usb device configuration descriptor.
1005
1006 @retval EFI_SUCCESS Successfully configure all the device endpoints.
1007
1008 **/
1009 EFI_STATUS
1010 EFIAPI
1011 XhcSetConfigCmd (
1012 IN USB_XHCI_INSTANCE *Xhc,
1013 IN UINT8 SlotId,
1014 IN UINT8 DeviceSpeed,
1015 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
1016 );
1017
1018
1019 /**
1020 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
1021
1022 @param Xhc The XHCI Instance.
1023 @param SlotId The slot id to be configured.
1024 @param DeviceSpeed The device's speed.
1025 @param ConfigDesc The pointer to the usb device configuration descriptor.
1026
1027 @retval EFI_SUCCESS Successfully configure all the device endpoints.
1028
1029 **/
1030 EFI_STATUS
1031 EFIAPI
1032 XhcSetConfigCmd64 (
1033 IN USB_XHCI_INSTANCE *Xhc,
1034 IN UINT8 SlotId,
1035 IN UINT8 DeviceSpeed,
1036 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
1037 );
1038
1039
1040 /**
1041 Find out the actual device address according to the requested device address from UsbBus.
1042
1043 @param Xhc The XHCI Instance.
1044 @param BusDevAddr The requested device address by UsbBus upper driver.
1045
1046 @return The actual device address assigned to the device.
1047
1048 **/
1049 UINT8
1050 EFIAPI
1051 XhcBusDevAddrToSlotId (
1052 IN USB_XHCI_INSTANCE *Xhc,
1053 IN UINT8 BusDevAddr
1054 );
1055
1056 /**
1057 Assign and initialize the device slot for a new device.
1058
1059 @param Xhc The XHCI Instance.
1060 @param ParentRouteChart The route string pointed to the parent device.
1061 @param ParentPort The port at which the device is located.
1062 @param RouteChart The route string pointed to the device.
1063 @param DeviceSpeed The device speed.
1064
1065 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1066
1067 **/
1068 EFI_STATUS
1069 EFIAPI
1070 XhcInitializeDeviceSlot (
1071 IN USB_XHCI_INSTANCE *Xhc,
1072 IN USB_DEV_ROUTE ParentRouteChart,
1073 IN UINT16 ParentPort,
1074 IN USB_DEV_ROUTE RouteChart,
1075 IN UINT8 DeviceSpeed
1076 );
1077
1078 /**
1079 Assign and initialize the device slot for a new device.
1080
1081 @param Xhc The XHCI Instance.
1082 @param ParentRouteChart The route string pointed to the parent device.
1083 @param ParentPort The port at which the device is located.
1084 @param RouteChart The route string pointed to the device.
1085 @param DeviceSpeed The device speed.
1086
1087 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1088
1089 **/
1090 EFI_STATUS
1091 EFIAPI
1092 XhcInitializeDeviceSlot64 (
1093 IN USB_XHCI_INSTANCE *Xhc,
1094 IN USB_DEV_ROUTE ParentRouteChart,
1095 IN UINT16 ParentPort,
1096 IN USB_DEV_ROUTE RouteChart,
1097 IN UINT8 DeviceSpeed
1098 );
1099
1100 /**
1101 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
1102
1103 @param Xhc The XHCI Instance.
1104 @param SlotId The slot id to be evaluated.
1105 @param MaxPacketSize The max packet size supported by the device control transfer.
1106
1107 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
1108
1109 **/
1110 EFI_STATUS
1111 EFIAPI
1112 XhcEvaluateContext (
1113 IN USB_XHCI_INSTANCE *Xhc,
1114 IN UINT8 SlotId,
1115 IN UINT32 MaxPacketSize
1116 );
1117
1118
1119 /**
1120 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
1121
1122 @param Xhc The XHCI Instance.
1123 @param SlotId The slot id to be evaluated.
1124 @param MaxPacketSize The max packet size supported by the device control transfer.
1125
1126 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
1127
1128 **/
1129 EFI_STATUS
1130 EFIAPI
1131 XhcEvaluateContext64 (
1132 IN USB_XHCI_INSTANCE *Xhc,
1133 IN UINT8 SlotId,
1134 IN UINT32 MaxPacketSize
1135 );
1136
1137
1138 /**
1139 Disable the specified device slot.
1140
1141 @param Xhc The XHCI Instance.
1142 @param SlotId The slot id to be disabled.
1143
1144 @retval EFI_SUCCESS Successfully disable the device slot.
1145
1146 **/
1147 EFI_STATUS
1148 EFIAPI
1149 XhcDisableSlotCmd (
1150 IN USB_XHCI_INSTANCE *Xhc,
1151 IN UINT8 SlotId
1152 );
1153
1154
1155 /**
1156 Disable the specified device slot.
1157
1158 @param Xhc The XHCI Instance.
1159 @param SlotId The slot id to be disabled.
1160
1161 @retval EFI_SUCCESS Successfully disable the device slot.
1162
1163 **/
1164 EFI_STATUS
1165 EFIAPI
1166 XhcDisableSlotCmd64 (
1167 IN USB_XHCI_INSTANCE *Xhc,
1168 IN UINT8 SlotId
1169 );
1170
1171
1172 /**
1173 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
1174
1175 @param Xhc The XHCI Instance.
1176 @param TrsRing The transfer ring to sync.
1177
1178 @retval EFI_SUCCESS The transfer ring is synchronized successfully.
1179
1180 **/
1181 EFI_STATUS
1182 EFIAPI
1183 XhcSyncTrsRing (
1184 IN USB_XHCI_INSTANCE *Xhc,
1185 TRANSFER_RING *TrsRing
1186 );
1187
1188 /**
1189 Synchronize the specified event ring to update the enqueue and dequeue pointer.
1190
1191 @param Xhc The XHCI Instance.
1192 @param EvtRing The event ring to sync.
1193
1194 @retval EFI_SUCCESS The event ring is synchronized successfully.
1195
1196 **/
1197 EFI_STATUS
1198 EFIAPI
1199 XhcSyncEventRing (
1200 IN USB_XHCI_INSTANCE *Xhc,
1201 EVENT_RING *EvtRing
1202 );
1203
1204 /**
1205 Check if there is a new generated event.
1206
1207 @param Xhc The XHCI Instance.
1208 @param EvtRing The event ring to check.
1209 @param NewEvtTrb The new event TRB found.
1210
1211 @retval EFI_SUCCESS Found a new event TRB at the event ring.
1212 @retval EFI_NOT_READY The event ring has no new event.
1213
1214 **/
1215 EFI_STATUS
1216 EFIAPI
1217 XhcCheckNewEvent (
1218 IN USB_XHCI_INSTANCE *Xhc,
1219 IN EVENT_RING *EvtRing,
1220 OUT TRB_TEMPLATE **NewEvtTrb
1221 );
1222
1223 /**
1224 Create XHCI transfer ring.
1225
1226 @param Xhc The XHCI Instance.
1227 @param TrbNum The number of TRB in the ring.
1228 @param TransferRing The created transfer ring.
1229
1230 **/
1231 VOID
1232 CreateTransferRing (
1233 IN USB_XHCI_INSTANCE *Xhc,
1234 IN UINTN TrbNum,
1235 OUT TRANSFER_RING *TransferRing
1236 );
1237
1238 /**
1239 Create XHCI event ring.
1240
1241 @param Xhc The XHCI Instance.
1242 @param EventRing The created event ring.
1243
1244 **/
1245 VOID
1246 CreateEventRing (
1247 IN USB_XHCI_INSTANCE *Xhc,
1248 OUT EVENT_RING *EventRing
1249 );
1250
1251 /**
1252 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted
1253 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint
1254 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is
1255 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the
1256 Stopped to the Running state.
1257
1258 @param Xhc The XHCI Instance.
1259 @param Urb The urb which makes the endpoint halted.
1260
1261 @retval EFI_SUCCESS The recovery is successful.
1262 @retval Others Failed to recovery halted endpoint.
1263
1264 **/
1265 EFI_STATUS
1266 EFIAPI
1267 XhcRecoverHaltedEndpoint (
1268 IN USB_XHCI_INSTANCE *Xhc,
1269 IN URB *Urb
1270 );
1271
1272 /**
1273 Create a new URB for a new transaction.
1274
1275 @param Xhc The XHCI Instance
1276 @param DevAddr The device address
1277 @param EpAddr Endpoint addrress
1278 @param DevSpeed The device speed
1279 @param MaxPacket The max packet length of the endpoint
1280 @param Type The transaction type
1281 @param Request The standard USB request for control transfer
1282 @param Data The user data to transfer
1283 @param DataLen The length of data buffer
1284 @param Callback The function to call when data is transferred
1285 @param Context The context to the callback
1286
1287 @return Created URB or NULL
1288
1289 **/
1290 URB*
1291 XhcCreateUrb (
1292 IN USB_XHCI_INSTANCE *Xhc,
1293 IN UINT8 DevAddr,
1294 IN UINT8 EpAddr,
1295 IN UINT8 DevSpeed,
1296 IN UINTN MaxPacket,
1297 IN UINTN Type,
1298 IN EFI_USB_DEVICE_REQUEST *Request,
1299 IN VOID *Data,
1300 IN UINTN DataLen,
1301 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
1302 IN VOID *Context
1303 );
1304
1305 /**
1306 Create a transfer TRB.
1307
1308 @param Xhc The XHCI Instance
1309 @param Urb The urb used to construct the transfer TRB.
1310
1311 @return Created TRB or NULL
1312
1313 **/
1314 EFI_STATUS
1315 XhcCreateTransferTrb (
1316 IN USB_XHCI_INSTANCE *Xhc,
1317 IN URB *Urb
1318 );
1319
1320 #endif
EFI Development Kit II mirror for PVE