MdeModulePkg XhciPei: Fix build failure "conversion from 'UINT32' to 'UINT8', possibl...
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciPei / XhcPeim.c
1 /** @file
2 PEIM to produce gPeiUsb2HostControllerPpiGuid based on gPeiUsbControllerPpiGuid
3 which is used to enable recovery function from USB Drivers.
4
5 Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
6
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions
9 of the BSD License which accompanies this distribution. The
10 full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
12
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15
16 **/
17
18 #include "XhcPeim.h"
19
20 //
21 // Two arrays used to translate the XHCI port state (change)
22 // to the UEFI protocol's port state (change).
23 //
24 USB_PORT_STATE_MAP mUsbPortStateMap[] = {
25 {XHC_PORTSC_CCS, USB_PORT_STAT_CONNECTION},
26 {XHC_PORTSC_PED, USB_PORT_STAT_ENABLE},
27 {XHC_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT},
28 {XHC_PORTSC_PP, USB_PORT_STAT_POWER},
29 {XHC_PORTSC_RESET, USB_PORT_STAT_RESET}
30 };
31
32 USB_PORT_STATE_MAP mUsbPortChangeMap[] = {
33 {XHC_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION},
34 {XHC_PORTSC_PEC, USB_PORT_STAT_C_ENABLE},
35 {XHC_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT},
36 {XHC_PORTSC_PRC, USB_PORT_STAT_C_RESET}
37 };
38
39 USB_CLEAR_PORT_MAP mUsbClearPortChangeMap[] = {
40 {XHC_PORTSC_CSC, EfiUsbPortConnectChange},
41 {XHC_PORTSC_PEC, EfiUsbPortEnableChange},
42 {XHC_PORTSC_OCC, EfiUsbPortOverCurrentChange},
43 {XHC_PORTSC_PRC, EfiUsbPortResetChange}
44 };
45
46 USB_PORT_STATE_MAP mUsbHubPortStateMap[] = {
47 {XHC_HUB_PORTSC_CCS, USB_PORT_STAT_CONNECTION},
48 {XHC_HUB_PORTSC_PED, USB_PORT_STAT_ENABLE},
49 {XHC_HUB_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT},
50 {XHC_HUB_PORTSC_PP, USB_PORT_STAT_POWER},
51 {XHC_HUB_PORTSC_RESET, USB_PORT_STAT_RESET}
52 };
53
54 USB_PORT_STATE_MAP mUsbHubPortChangeMap[] = {
55 {XHC_HUB_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION},
56 {XHC_HUB_PORTSC_PEC, USB_PORT_STAT_C_ENABLE},
57 {XHC_HUB_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT},
58 {XHC_HUB_PORTSC_PRC, USB_PORT_STAT_C_RESET}
59 };
60
61 USB_CLEAR_PORT_MAP mUsbHubClearPortChangeMap[] = {
62 {XHC_HUB_PORTSC_CSC, EfiUsbPortConnectChange},
63 {XHC_HUB_PORTSC_PEC, EfiUsbPortEnableChange},
64 {XHC_HUB_PORTSC_OCC, EfiUsbPortOverCurrentChange},
65 {XHC_HUB_PORTSC_PRC, EfiUsbPortResetChange},
66 {XHC_HUB_PORTSC_BHRC, Usb3PortBHPortResetChange}
67 };
68
69 /**
70 Read XHCI Operation register.
71
72 @param Xhc The XHCI device.
73 @param Offset The operation register offset.
74
75 @retval the register content read.
76
77 **/
78 UINT32
79 XhcPeiReadOpReg (
80 IN PEI_XHC_DEV *Xhc,
81 IN UINT32 Offset
82 )
83 {
84 UINT32 Data;
85
86 ASSERT (Xhc->CapLength != 0);
87
88 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset);
89 return Data;
90 }
91
92 /**
93 Write the data to the XHCI operation register.
94
95 @param Xhc The XHCI device.
96 @param Offset The operation register offset.
97 @param Data The data to write.
98
99 **/
100 VOID
101 XhcPeiWriteOpReg (
102 IN PEI_XHC_DEV *Xhc,
103 IN UINT32 Offset,
104 IN UINT32 Data
105 )
106 {
107 ASSERT (Xhc->CapLength != 0);
108
109 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data);
110 }
111
112 /**
113 Set one bit of the operational register while keeping other bits.
114
115 @param Xhc The XHCI device.
116 @param Offset The offset of the operational register.
117 @param Bit The bit mask of the register to set.
118
119 **/
120 VOID
121 XhcPeiSetOpRegBit (
122 IN PEI_XHC_DEV *Xhc,
123 IN UINT32 Offset,
124 IN UINT32 Bit
125 )
126 {
127 UINT32 Data;
128
129 Data = XhcPeiReadOpReg (Xhc, Offset);
130 Data |= Bit;
131 XhcPeiWriteOpReg (Xhc, Offset, Data);
132 }
133
134 /**
135 Clear one bit of the operational register while keeping other bits.
136
137 @param Xhc The XHCI device.
138 @param Offset The offset of the operational register.
139 @param Bit The bit mask of the register to clear.
140
141 **/
142 VOID
143 XhcPeiClearOpRegBit (
144 IN PEI_XHC_DEV *Xhc,
145 IN UINT32 Offset,
146 IN UINT32 Bit
147 )
148 {
149 UINT32 Data;
150
151 Data = XhcPeiReadOpReg (Xhc, Offset);
152 Data &= ~Bit;
153 XhcPeiWriteOpReg (Xhc, Offset, Data);
154 }
155
156 /**
157 Wait the operation register's bit as specified by Bit
158 to become set (or clear).
159
160 @param Xhc The XHCI device.
161 @param Offset The offset of the operational register.
162 @param Bit The bit mask of the register to wait for.
163 @param WaitToSet Wait the bit to set or clear.
164 @param Timeout The time to wait before abort (in microsecond, us).
165
166 @retval EFI_SUCCESS The bit successfully changed by host controller.
167 @retval EFI_TIMEOUT The time out occurred.
168
169 **/
170 EFI_STATUS
171 XhcPeiWaitOpRegBit (
172 IN PEI_XHC_DEV *Xhc,
173 IN UINT32 Offset,
174 IN UINT32 Bit,
175 IN BOOLEAN WaitToSet,
176 IN UINT32 Timeout
177 )
178 {
179 UINT32 Index;
180
181 for (Index = 0; Index < Timeout / XHC_POLL_DELAY + 1; Index++) {
182 if (XHC_REG_BIT_IS_SET (Xhc, Offset, Bit) == WaitToSet) {
183 return EFI_SUCCESS;
184 }
185
186 MicroSecondDelay (XHC_POLL_DELAY);
187 }
188
189 return EFI_TIMEOUT;
190 }
191
192 /**
193 Read XHCI capability register.
194
195 @param Xhc The XHCI device.
196 @param Offset Capability register address.
197
198 @retval the register content read.
199
200 **/
201 UINT32
202 XhcPeiReadCapRegister (
203 IN PEI_XHC_DEV *Xhc,
204 IN UINT32 Offset
205 )
206 {
207 UINT32 Data;
208
209 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Offset);
210
211 return Data;
212 }
213
214 /**
215 Read XHCI door bell register.
216
217 @param Xhc The XHCI device.
218 @param Offset The offset of the door bell register.
219
220 @return The register content read
221
222 **/
223 UINT32
224 XhcPeiReadDoorBellReg (
225 IN PEI_XHC_DEV *Xhc,
226 IN UINT32 Offset
227 )
228 {
229 UINT32 Data;
230
231 ASSERT (Xhc->DBOff != 0);
232
233 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->DBOff + Offset);
234
235 return Data;
236 }
237
238 /**
239 Write the data to the XHCI door bell register.
240
241 @param Xhc The XHCI device.
242 @param Offset The offset of the door bell register.
243 @param Data The data to write.
244
245 **/
246 VOID
247 XhcPeiWriteDoorBellReg (
248 IN PEI_XHC_DEV *Xhc,
249 IN UINT32 Offset,
250 IN UINT32 Data
251 )
252 {
253 ASSERT (Xhc->DBOff != 0);
254
255 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->DBOff + Offset, Data);
256 }
257
258 /**
259 Read XHCI runtime register.
260
261 @param Xhc The XHCI device.
262 @param Offset The offset of the runtime register.
263
264 @return The register content read
265
266 **/
267 UINT32
268 XhcPeiReadRuntimeReg (
269 IN PEI_XHC_DEV *Xhc,
270 IN UINT32 Offset
271 )
272 {
273 UINT32 Data;
274
275 ASSERT (Xhc->RTSOff != 0);
276
277 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset);
278
279 return Data;
280 }
281
282 /**
283 Write the data to the XHCI runtime register.
284
285 @param Xhc The XHCI device.
286 @param Offset The offset of the runtime register.
287 @param Data The data to write.
288
289 **/
290 VOID
291 XhcPeiWriteRuntimeReg (
292 IN PEI_XHC_DEV *Xhc,
293 IN UINT32 Offset,
294 IN UINT32 Data
295 )
296 {
297 ASSERT (Xhc->RTSOff != 0);
298
299 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset, Data);
300 }
301
302 /**
303 Set one bit of the runtime register while keeping other bits.
304
305 @param Xhc The XHCI device.
306 @param Offset The offset of the runtime register.
307 @param Bit The bit mask of the register to set.
308
309 **/
310 VOID
311 XhcPeiSetRuntimeRegBit (
312 IN PEI_XHC_DEV *Xhc,
313 IN UINT32 Offset,
314 IN UINT32 Bit
315 )
316 {
317 UINT32 Data;
318
319 Data = XhcPeiReadRuntimeReg (Xhc, Offset);
320 Data |= Bit;
321 XhcPeiWriteRuntimeReg (Xhc, Offset, Data);
322 }
323
324 /**
325 Clear one bit of the runtime register while keeping other bits.
326
327 @param Xhc The XHCI device.
328 @param Offset The offset of the runtime register.
329 @param Bit The bit mask of the register to set.
330
331 **/
332 VOID
333 XhcPeiClearRuntimeRegBit (
334 IN PEI_XHC_DEV *Xhc,
335 IN UINT32 Offset,
336 IN UINT32 Bit
337 )
338 {
339 UINT32 Data;
340
341 Data = XhcPeiReadRuntimeReg (Xhc, Offset);
342 Data &= ~Bit;
343 XhcPeiWriteRuntimeReg (Xhc, Offset, Data);
344 }
345
346 /**
347 Check whether Xhc is halted.
348
349 @param Xhc The XHCI device.
350
351 @retval TRUE The controller is halted.
352 @retval FALSE The controller isn't halted.
353
354 **/
355 BOOLEAN
356 XhcPeiIsHalt (
357 IN PEI_XHC_DEV *Xhc
358 )
359 {
360 return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT);
361 }
362
363 /**
364 Check whether system error occurred.
365
366 @param Xhc The XHCI device.
367
368 @retval TRUE System error happened.
369 @retval FALSE No system error.
370
371 **/
372 BOOLEAN
373 XhcPeiIsSysError (
374 IN PEI_XHC_DEV *Xhc
375 )
376 {
377 return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE);
378 }
379
380 /**
381 Reset the host controller.
382
383 @param Xhc The XHCI device.
384 @param Timeout Time to wait before abort (in microsecond, us).
385
386 @retval EFI_TIMEOUT The transfer failed due to time out.
387 @retval Others Failed to reset the host.
388
389 **/
390 EFI_STATUS
391 XhcPeiResetHC (
392 IN PEI_XHC_DEV *Xhc,
393 IN UINT32 Timeout
394 )
395 {
396 EFI_STATUS Status;
397
398 //
399 // Host can only be reset when it is halt. If not so, halt it
400 //
401 if (!XhcPeiIsHalt (Xhc)) {
402 Status = XhcPeiHaltHC (Xhc, Timeout);
403
404 if (EFI_ERROR (Status)) {
405 goto ON_EXIT;
406 }
407 }
408
409 XhcPeiSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);
410 Status = XhcPeiWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);
411 ON_EXIT:
412 DEBUG ((EFI_D_INFO, "XhcPeiResetHC: %r\n", Status));
413 return Status;
414 }
415
416 /**
417 Halt the host controller.
418
419 @param Xhc The XHCI device.
420 @param Timeout Time to wait before abort.
421
422 @retval EFI_TIMEOUT Failed to halt the controller before Timeout.
423 @retval EFI_SUCCESS The XHCI is halt.
424
425 **/
426 EFI_STATUS
427 XhcPeiHaltHC (
428 IN PEI_XHC_DEV *Xhc,
429 IN UINT32 Timeout
430 )
431 {
432 EFI_STATUS Status;
433
434 XhcPeiClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);
435 Status = XhcPeiWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, TRUE, Timeout);
436 DEBUG ((EFI_D_INFO, "XhcPeiHaltHC: %r\n", Status));
437 return Status;
438 }
439
440 /**
441 Set the XHCI to run.
442
443 @param Xhc The XHCI device.
444 @param Timeout Time to wait before abort.
445
446 @retval EFI_SUCCESS The XHCI is running.
447 @retval Others Failed to set the XHCI to run.
448
449 **/
450 EFI_STATUS
451 XhcPeiRunHC (
452 IN PEI_XHC_DEV *Xhc,
453 IN UINT32 Timeout
454 )
455 {
456 EFI_STATUS Status;
457
458 XhcPeiSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);
459 Status = XhcPeiWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, FALSE, Timeout);
460 DEBUG ((EFI_D_INFO, "XhcPeiRunHC: %r\n", Status));
461 return Status;
462 }
463
464 /**
465 Submits control transfer to a target USB device.
466
467 @param PeiServices The pointer of EFI_PEI_SERVICES.
468 @param This The pointer of PEI_USB2_HOST_CONTROLLER_PPI.
469 @param DeviceAddress The target device address.
470 @param DeviceSpeed Target device speed.
471 @param MaximumPacketLength Maximum packet size the default control transfer
472 endpoint is capable of sending or receiving.
473 @param Request USB device request to send.
474 @param TransferDirection Specifies the data direction for the data stage.
475 @param Data Data buffer to be transmitted or received from USB device.
476 @param DataLength The size (in bytes) of the data buffer.
477 @param TimeOut Indicates the maximum timeout, in millisecond.
478 If Timeout is 0, then the caller must wait for the function
479 to be completed until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
480 @param Translator Transaction translator to be used by this device.
481 @param TransferResult Return the result of this control transfer.
482
483 @retval EFI_SUCCESS Transfer was completed successfully.
484 @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resources.
485 @retval EFI_INVALID_PARAMETER Some parameters are invalid.
486 @retval EFI_TIMEOUT Transfer failed due to timeout.
487 @retval EFI_DEVICE_ERROR Transfer failed due to host controller or device error.
488
489 **/
490 EFI_STATUS
491 EFIAPI
492 XhcPeiControlTransfer (
493 IN EFI_PEI_SERVICES **PeiServices,
494 IN PEI_USB2_HOST_CONTROLLER_PPI *This,
495 IN UINT8 DeviceAddress,
496 IN UINT8 DeviceSpeed,
497 IN UINTN MaximumPacketLength,
498 IN EFI_USB_DEVICE_REQUEST *Request,
499 IN EFI_USB_DATA_DIRECTION TransferDirection,
500 IN OUT VOID *Data,
501 IN OUT UINTN *DataLength,
502 IN UINTN TimeOut,
503 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
504 OUT UINT32 *TransferResult
505 )
506 {
507 PEI_XHC_DEV *Xhc;
508 URB *Urb;
509 UINT8 Endpoint;
510 UINT8 Index;
511 UINT8 DescriptorType;
512 UINT8 SlotId;
513 UINT8 TTT;
514 UINT8 MTT;
515 UINT32 MaxPacket0;
516 EFI_USB_HUB_DESCRIPTOR *HubDesc;
517 EFI_STATUS Status;
518 EFI_STATUS RecoveryStatus;
519 UINTN MapSize;
520 EFI_USB_PORT_STATUS PortStatus;
521 UINT32 State;
522 EFI_USB_DEVICE_REQUEST ClearPortRequest;
523 UINTN Len;
524
525 //
526 // Validate parameters
527 //
528 if ((Request == NULL) || (TransferResult == NULL)) {
529 return EFI_INVALID_PARAMETER;
530 }
531
532 if ((TransferDirection != EfiUsbDataIn) &&
533 (TransferDirection != EfiUsbDataOut) &&
534 (TransferDirection != EfiUsbNoData)) {
535 return EFI_INVALID_PARAMETER;
536 }
537
538 if ((TransferDirection == EfiUsbNoData) &&
539 ((Data != NULL) || (*DataLength != 0))) {
540 return EFI_INVALID_PARAMETER;
541 }
542
543 if ((TransferDirection != EfiUsbNoData) &&
544 ((Data == NULL) || (*DataLength == 0))) {
545 return EFI_INVALID_PARAMETER;
546 }
547
548 if ((MaximumPacketLength != 8) && (MaximumPacketLength != 16) &&
549 (MaximumPacketLength != 32) && (MaximumPacketLength != 64) &&
550 (MaximumPacketLength != 512)
551 ) {
552 return EFI_INVALID_PARAMETER;
553 }
554
555 if ((DeviceSpeed == EFI_USB_SPEED_LOW) && (MaximumPacketLength != 8)) {
556 return EFI_INVALID_PARAMETER;
557 }
558
559 if ((DeviceSpeed == EFI_USB_SPEED_SUPER) && (MaximumPacketLength != 512)) {
560 return EFI_INVALID_PARAMETER;
561 }
562
563 Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);
564
565 Status = EFI_DEVICE_ERROR;
566 *TransferResult = EFI_USB_ERR_SYSTEM;
567 Len = 0;
568
569 if (XhcPeiIsHalt (Xhc) || XhcPeiIsSysError (Xhc)) {
570 DEBUG ((EFI_D_ERROR, "XhcPeiControlTransfer: HC is halted or has system error\n"));
571 goto ON_EXIT;
572 }
573
574 //
575 // Check if the device is still enabled before every transaction.
576 //
577 SlotId = XhcPeiBusDevAddrToSlotId (Xhc, DeviceAddress);
578 if (SlotId == 0) {
579 goto ON_EXIT;
580 }
581
582 //
583 // Hook the Set_Address request from UsbBus.
584 // According to XHCI 1.0 spec, the Set_Address request is replaced by XHCI's Address_Device cmd.
585 //
586 if ((Request->Request == USB_REQ_SET_ADDRESS) &&
587 (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE))) {
588 //
589 // Reset the BusDevAddr field of all disabled entries in UsbDevContext array firstly.
590 // This way is used to clean the history to avoid using wrong device address afterwards.
591 //
592 for (Index = 0; Index < 255; Index++) {
593 if (!Xhc->UsbDevContext[Index + 1].Enabled &&
594 (Xhc->UsbDevContext[Index + 1].SlotId == 0) &&
595 (Xhc->UsbDevContext[Index + 1].BusDevAddr == (UINT8) Request->Value)) {
596 Xhc->UsbDevContext[Index + 1].BusDevAddr = 0;
597 }
598 }
599
600 if (Xhc->UsbDevContext[SlotId].XhciDevAddr == 0) {
601 goto ON_EXIT;
602 }
603 //
604 // The actual device address has been assigned by XHCI during initializing the device slot.
605 // So we just need establish the mapping relationship between the device address requested from UsbBus
606 // and the actual device address assigned by XHCI. The following invocations through EFI_USB2_HC_PROTOCOL interface
607 // can find out the actual device address by it.
608 //
609 Xhc->UsbDevContext[SlotId].BusDevAddr = (UINT8) Request->Value;
610 Status = EFI_SUCCESS;
611 goto ON_EXIT;
612 }
613
614 //
615 // Create a new URB, insert it into the asynchronous
616 // schedule list, then poll the execution status.
617 // Note that we encode the direction in address although default control
618 // endpoint is bidirectional. XhcPeiCreateUrb expects this
619 // combination of Ep addr and its direction.
620 //
621 Endpoint = (UINT8) (0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));
622 Urb = XhcPeiCreateUrb (
623 Xhc,
624 DeviceAddress,
625 Endpoint,
626 DeviceSpeed,
627 MaximumPacketLength,
628 XHC_CTRL_TRANSFER,
629 Request,
630 Data,
631 *DataLength,
632 NULL,
633 NULL
634 );
635
636 if (Urb == NULL) {
637 DEBUG ((EFI_D_ERROR, "XhcPeiControlTransfer: failed to create URB"));
638 Status = EFI_OUT_OF_RESOURCES;
639 goto ON_EXIT;
640 }
641
642 Status = XhcPeiExecTransfer (Xhc, FALSE, Urb, TimeOut);
643
644 //
645 // Get the status from URB. The result is updated in XhcPeiCheckUrbResult
646 // which is called by XhcPeiExecTransfer
647 //
648 *TransferResult = Urb->Result;
649 *DataLength = Urb->Completed;
650
651 if (*TransferResult == EFI_USB_NOERROR) {
652 Status = EFI_SUCCESS;
653 } else if (*TransferResult == EFI_USB_ERR_STALL) {
654 RecoveryStatus = XhcPeiRecoverHaltedEndpoint(Xhc, Urb);
655 if (EFI_ERROR (RecoveryStatus)) {
656 DEBUG ((EFI_D_ERROR, "XhcPeiControlTransfer: XhcPeiRecoverHaltedEndpoint failed\n"));
657 }
658 Status = EFI_DEVICE_ERROR;
659 goto FREE_URB;
660 } else {
661 goto FREE_URB;
662 }
663
664 //
665 // Hook Get_Descriptor request from UsbBus as we need evaluate context and configure endpoint.
666 // Hook Get_Status request form UsbBus as we need trace device attach/detach event happened at hub.
667 // Hook Set_Config request from UsbBus as we need configure device endpoint.
668 //
669 if ((Request->Request == USB_REQ_GET_DESCRIPTOR) &&
670 ((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE)) ||
671 ((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_DEVICE))))) {
672 DescriptorType = (UINT8) (Request->Value >> 8);
673 if ((DescriptorType == USB_DESC_TYPE_DEVICE) && ((*DataLength == sizeof (EFI_USB_DEVICE_DESCRIPTOR)) || ((DeviceSpeed == EFI_USB_SPEED_FULL) && (*DataLength == 8)))) {
674 ASSERT (Data != NULL);
675 //
676 // Store a copy of device scriptor as hub device need this info to configure endpoint.
677 //
678 CopyMem (&Xhc->UsbDevContext[SlotId].DevDesc, Data, *DataLength);
679 if (Xhc->UsbDevContext[SlotId].DevDesc.BcdUSB == 0x0300) {
680 //
681 // If it's a usb3.0 device, then its max packet size is a 2^n.
682 //
683 MaxPacket0 = 1 << Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;
684 } else {
685 MaxPacket0 = Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;
686 }
687 Xhc->UsbDevContext[SlotId].ConfDesc = AllocateZeroPool (Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations * sizeof (EFI_USB_CONFIG_DESCRIPTOR *));
688 if (Xhc->UsbDevContext[SlotId].ConfDesc == NULL) {
689 Status = EFI_OUT_OF_RESOURCES;
690 goto FREE_URB;
691 }
692 if (Xhc->HcCParams.Data.Csz == 0) {
693 Status = XhcPeiEvaluateContext (Xhc, SlotId, MaxPacket0);
694 } else {
695 Status = XhcPeiEvaluateContext64 (Xhc, SlotId, MaxPacket0);
696 }
697 } else if (DescriptorType == USB_DESC_TYPE_CONFIG) {
698 ASSERT (Data != NULL);
699 if (*DataLength == ((UINT16 *) Data)[1]) {
700 //
701 // Get configuration value from request, store the configuration descriptor for Configure_Endpoint cmd.
702 //
703 Index = (UINT8) Request->Value;
704 ASSERT (Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations);
705 Xhc->UsbDevContext[SlotId].ConfDesc[Index] = AllocateZeroPool (*DataLength);
706 if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] == NULL) {
707 Status = EFI_OUT_OF_RESOURCES;
708 goto FREE_URB;
709 }
710 CopyMem (Xhc->UsbDevContext[SlotId].ConfDesc[Index], Data, *DataLength);
711 }
712 } else if (((DescriptorType == USB_DESC_TYPE_HUB) ||
713 (DescriptorType == USB_DESC_TYPE_HUB_SUPER_SPEED)) && (*DataLength > 2)) {
714 ASSERT (Data != NULL);
715 HubDesc = (EFI_USB_HUB_DESCRIPTOR *) Data;
716 ASSERT (HubDesc->NumPorts <= 15);
717 //
718 // The bit 5,6 of HubCharacter field of Hub Descriptor is TTT.
719 //
720 TTT = (UINT8) ((HubDesc->HubCharacter & (BIT5 | BIT6)) >> 5);
721 if (Xhc->UsbDevContext[SlotId].DevDesc.DeviceProtocol == 2) {
722 //
723 // Don't support multi-TT feature for super speed hub now.
724 //
725 MTT = 0;
726 DEBUG ((EFI_D_ERROR, "XHCI: Don't support multi-TT feature for Hub now. (force to disable MTT)\n"));
727 } else {
728 MTT = 0;
729 }
730
731 if (Xhc->HcCParams.Data.Csz == 0) {
732 Status = XhcPeiConfigHubContext (Xhc, SlotId, HubDesc->NumPorts, TTT, MTT);
733 } else {
734 Status = XhcPeiConfigHubContext64 (Xhc, SlotId, HubDesc->NumPorts, TTT, MTT);
735 }
736 }
737 } else if ((Request->Request == USB_REQ_SET_CONFIG) &&
738 (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE))) {
739 //
740 // Hook Set_Config request from UsbBus as we need configure device endpoint.
741 //
742 for (Index = 0; Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {
743 if (Xhc->UsbDevContext[SlotId].ConfDesc[Index]->ConfigurationValue == (UINT8)Request->Value) {
744 if (Xhc->HcCParams.Data.Csz == 0) {
745 Status = XhcPeiSetConfigCmd (Xhc, SlotId, DeviceSpeed, Xhc->UsbDevContext[SlotId].ConfDesc[Index]);
746 } else {
747 Status = XhcPeiSetConfigCmd64 (Xhc, SlotId, DeviceSpeed, Xhc->UsbDevContext[SlotId].ConfDesc[Index]);
748 }
749 break;
750 }
751 }
752 } else if ((Request->Request == USB_REQ_GET_STATUS) &&
753 (Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER))) {
754 ASSERT (Data != NULL);
755 //
756 // Hook Get_Status request from UsbBus to keep track of the port status change.
757 //
758 State = *(UINT32 *) Data;
759 PortStatus.PortStatus = 0;
760 PortStatus.PortChangeStatus = 0;
761
762 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
763 //
764 // For super speed hub, its bit10~12 presents the attached device speed.
765 //
766 if ((State & XHC_PORTSC_PS) >> 10 == 0) {
767 PortStatus.PortStatus |= USB_PORT_STAT_SUPER_SPEED;
768 }
769 } else {
770 //
771 // For high or full/low speed hub, its bit9~10 presents the attached device speed.
772 //
773 if (XHC_BIT_IS_SET (State, BIT9)) {
774 PortStatus.PortStatus |= USB_PORT_STAT_LOW_SPEED;
775 } else if (XHC_BIT_IS_SET (State, BIT10)) {
776 PortStatus.PortStatus |= USB_PORT_STAT_HIGH_SPEED;
777 }
778 }
779
780 //
781 // Convert the XHCI port/port change state to UEFI status
782 //
783 MapSize = sizeof (mUsbHubPortStateMap) / sizeof (USB_PORT_STATE_MAP);
784 for (Index = 0; Index < MapSize; Index++) {
785 if (XHC_BIT_IS_SET (State, mUsbHubPortStateMap[Index].HwState)) {
786 PortStatus.PortStatus = (UINT16) (PortStatus.PortStatus | mUsbHubPortStateMap[Index].UefiState);
787 }
788 }
789
790 MapSize = sizeof (mUsbHubPortChangeMap) / sizeof (USB_PORT_STATE_MAP);
791 for (Index = 0; Index < MapSize; Index++) {
792 if (XHC_BIT_IS_SET (State, mUsbHubPortChangeMap[Index].HwState)) {
793 PortStatus.PortChangeStatus = (UINT16) (PortStatus.PortChangeStatus | mUsbHubPortChangeMap[Index].UefiState);
794 }
795 }
796
797 MapSize = sizeof (mUsbHubClearPortChangeMap) / sizeof (USB_CLEAR_PORT_MAP);
798
799 for (Index = 0; Index < MapSize; Index++) {
800 if (XHC_BIT_IS_SET (State, mUsbHubClearPortChangeMap[Index].HwState)) {
801 ZeroMem (&ClearPortRequest, sizeof (EFI_USB_DEVICE_REQUEST));
802 ClearPortRequest.RequestType = USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER);
803 ClearPortRequest.Request = (UINT8) USB_REQ_CLEAR_FEATURE;
804 ClearPortRequest.Value = mUsbHubClearPortChangeMap[Index].Selector;
805 ClearPortRequest.Index = Request->Index;
806 ClearPortRequest.Length = 0;
807
808 XhcPeiControlTransfer (
809 PeiServices,
810 This,
811 DeviceAddress,
812 DeviceSpeed,
813 MaximumPacketLength,
814 &ClearPortRequest,
815 EfiUsbNoData,
816 NULL,
817 &Len,
818 TimeOut,
819 Translator,
820 TransferResult
821 );
822 }
823 }
824
825 XhcPeiPollPortStatusChange (Xhc, Xhc->UsbDevContext[SlotId].RouteString, (UINT8)Request->Index, &PortStatus);
826
827 *(UINT32 *) Data = *(UINT32 *) &PortStatus;
828 }
829
830 FREE_URB:
831 XhcPeiFreeUrb (Xhc, Urb);
832
833 ON_EXIT:
834
835 if (EFI_ERROR (Status)) {
836 DEBUG ((EFI_D_ERROR, "XhcPeiControlTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
837 }
838
839 return Status;
840 }
841
842 /**
843 Submits bulk transfer to a bulk endpoint of a USB device.
844
845 @param PeiServices The pointer of EFI_PEI_SERVICES.
846 @param This The pointer of PEI_USB2_HOST_CONTROLLER_PPI.
847 @param DeviceAddress Target device address.
848 @param EndPointAddress Endpoint number and its direction in bit 7.
849 @param DeviceSpeed Device speed, Low speed device doesn't support
850 bulk transfer.
851 @param MaximumPacketLength Maximum packet size the endpoint is capable of
852 sending or receiving.
853 @param Data Array of pointers to the buffers of data to transmit
854 from or receive into.
855 @param DataLength The lenght of the data buffer.
856 @param DataToggle On input, the initial data toggle for the transfer;
857 On output, it is updated to to next data toggle to use of
858 the subsequent bulk transfer.
859 @param TimeOut Indicates the maximum time, in millisecond, which the
860 transfer is allowed to complete.
861 If Timeout is 0, then the caller must wait for the function
862 to be completed until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
863 @param Translator A pointr to the transaction translator data.
864 @param TransferResult A pointer to the detailed result information of the
865 bulk transfer.
866
867 @retval EFI_SUCCESS The transfer was completed successfully.
868 @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.
869 @retval EFI_INVALID_PARAMETER Parameters are invalid.
870 @retval EFI_TIMEOUT The transfer failed due to timeout.
871 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
872
873 **/
874 EFI_STATUS
875 EFIAPI
876 XhcPeiBulkTransfer (
877 IN EFI_PEI_SERVICES **PeiServices,
878 IN PEI_USB2_HOST_CONTROLLER_PPI *This,
879 IN UINT8 DeviceAddress,
880 IN UINT8 EndPointAddress,
881 IN UINT8 DeviceSpeed,
882 IN UINTN MaximumPacketLength,
883 IN OUT VOID *Data[EFI_USB_MAX_BULK_BUFFER_NUM],
884 IN OUT UINTN *DataLength,
885 IN OUT UINT8 *DataToggle,
886 IN UINTN TimeOut,
887 IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,
888 OUT UINT32 *TransferResult
889 )
890 {
891 PEI_XHC_DEV *Xhc;
892 URB *Urb;
893 UINT8 SlotId;
894 EFI_STATUS Status;
895 EFI_STATUS RecoveryStatus;
896
897 //
898 // Validate the parameters
899 //
900 if ((DataLength == NULL) || (*DataLength == 0) ||
901 (Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL)) {
902 return EFI_INVALID_PARAMETER;
903 }
904
905 if ((*DataToggle != 0) && (*DataToggle != 1)) {
906 return EFI_INVALID_PARAMETER;
907 }
908
909 if ((DeviceSpeed == EFI_USB_SPEED_LOW) ||
910 ((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||
911 ((DeviceSpeed == EFI_USB_SPEED_HIGH) && (MaximumPacketLength > 512)) ||
912 ((DeviceSpeed == EFI_USB_SPEED_SUPER) && (MaximumPacketLength > 1024))) {
913 return EFI_INVALID_PARAMETER;
914 }
915
916 Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);
917
918 *TransferResult = EFI_USB_ERR_SYSTEM;
919 Status = EFI_DEVICE_ERROR;
920
921 if (XhcPeiIsHalt (Xhc) || XhcPeiIsSysError (Xhc)) {
922 DEBUG ((EFI_D_ERROR, "XhcPeiBulkTransfer: HC is halted or has system error\n"));
923 goto ON_EXIT;
924 }
925
926 //
927 // Check if the device is still enabled before every transaction.
928 //
929 SlotId = XhcPeiBusDevAddrToSlotId (Xhc, DeviceAddress);
930 if (SlotId == 0) {
931 goto ON_EXIT;
932 }
933
934 //
935 // Create a new URB, insert it into the asynchronous
936 // schedule list, then poll the execution status.
937 //
938 Urb = XhcPeiCreateUrb (
939 Xhc,
940 DeviceAddress,
941 EndPointAddress,
942 DeviceSpeed,
943 MaximumPacketLength,
944 XHC_BULK_TRANSFER,
945 NULL,
946 Data[0],
947 *DataLength,
948 NULL,
949 NULL
950 );
951
952 if (Urb == NULL) {
953 DEBUG ((EFI_D_ERROR, "XhcPeiBulkTransfer: failed to create URB\n"));
954 Status = EFI_OUT_OF_RESOURCES;
955 goto ON_EXIT;
956 }
957
958 Status = XhcPeiExecTransfer (Xhc, FALSE, Urb, TimeOut);
959
960 *TransferResult = Urb->Result;
961 *DataLength = Urb->Completed;
962
963 if (*TransferResult == EFI_USB_NOERROR) {
964 Status = EFI_SUCCESS;
965 } else if (*TransferResult == EFI_USB_ERR_STALL) {
966 RecoveryStatus = XhcPeiRecoverHaltedEndpoint(Xhc, Urb);
967 if (EFI_ERROR (RecoveryStatus)) {
968 DEBUG ((EFI_D_ERROR, "XhcPeiBulkTransfer: XhcPeiRecoverHaltedEndpoint failed\n"));
969 }
970 Status = EFI_DEVICE_ERROR;
971 }
972
973 XhcPeiFreeUrb (Xhc, Urb);
974
975 ON_EXIT:
976
977 if (EFI_ERROR (Status)) {
978 DEBUG ((EFI_D_ERROR, "XhcPeiBulkTransfer: error - %r, transfer - %x\n", Status, *TransferResult));
979 }
980
981 return Status;
982 }
983
984 /**
985 Retrieves the number of root hub ports.
986
987 @param[in] PeiServices The pointer to the PEI Services Table.
988 @param[in] This The pointer to this instance of the
989 PEI_USB2_HOST_CONTROLLER_PPI.
990 @param[out] PortNumber The pointer to the number of the root hub ports.
991
992 @retval EFI_SUCCESS The port number was retrieved successfully.
993 @retval EFI_INVALID_PARAMETER PortNumber is NULL.
994
995 **/
996 EFI_STATUS
997 EFIAPI
998 XhcPeiGetRootHubPortNumber (
999 IN EFI_PEI_SERVICES **PeiServices,
1000 IN PEI_USB2_HOST_CONTROLLER_PPI *This,
1001 OUT UINT8 *PortNumber
1002 )
1003 {
1004 PEI_XHC_DEV *XhcDev;
1005 XhcDev = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);
1006
1007 if (PortNumber == NULL) {
1008 return EFI_INVALID_PARAMETER;
1009 }
1010
1011 *PortNumber = XhcDev->HcSParams1.Data.MaxPorts;
1012 DEBUG ((EFI_D_INFO, "XhcPeiGetRootHubPortNumber: PortNumber = %x\n", *PortNumber));
1013 return EFI_SUCCESS;
1014 }
1015
1016 /**
1017 Clears a feature for the specified root hub port.
1018
1019 @param PeiServices The pointer of EFI_PEI_SERVICES.
1020 @param This The pointer of PEI_USB2_HOST_CONTROLLER_PPI.
1021 @param PortNumber Specifies the root hub port whose feature
1022 is requested to be cleared.
1023 @param PortFeature Indicates the feature selector associated with the
1024 feature clear request.
1025
1026 @retval EFI_SUCCESS The feature specified by PortFeature was cleared
1027 for the USB root hub port specified by PortNumber.
1028 @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid.
1029
1030 **/
1031 EFI_STATUS
1032 EFIAPI
1033 XhcPeiClearRootHubPortFeature (
1034 IN EFI_PEI_SERVICES **PeiServices,
1035 IN PEI_USB2_HOST_CONTROLLER_PPI *This,
1036 IN UINT8 PortNumber,
1037 IN EFI_USB_PORT_FEATURE PortFeature
1038 )
1039 {
1040 PEI_XHC_DEV *Xhc;
1041 UINT32 Offset;
1042 UINT32 State;
1043 EFI_STATUS Status;
1044
1045 Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);
1046 Status = EFI_SUCCESS;
1047
1048 if (PortNumber >= Xhc->HcSParams1.Data.MaxPorts) {
1049 Status = EFI_INVALID_PARAMETER;
1050 goto ON_EXIT;
1051 }
1052
1053 Offset = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));
1054 State = XhcPeiReadOpReg (Xhc, Offset);
1055 DEBUG ((EFI_D_INFO, "XhcPeiClearRootHubPortFeature: Port: %x State: %x\n", PortNumber, State));
1056
1057 //
1058 // Mask off the port status change bits, these bits are
1059 // write clean bits
1060 //
1061 State &= ~ (BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);
1062
1063 switch (PortFeature) {
1064 case EfiUsbPortEnable:
1065 //
1066 // Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag.
1067 // A port may be disabled by software writing a '1' to this flag.
1068 //
1069 State |= XHC_PORTSC_PED;
1070 State &= ~XHC_PORTSC_RESET;
1071 XhcPeiWriteOpReg (Xhc, Offset, State);
1072 break;
1073
1074 case EfiUsbPortSuspend:
1075 State |= XHC_PORTSC_LWS;
1076 XhcPeiWriteOpReg (Xhc, Offset, State);
1077 State &= ~XHC_PORTSC_PLS;
1078 XhcPeiWriteOpReg (Xhc, Offset, State);
1079 break;
1080
1081 case EfiUsbPortReset:
1082 //
1083 // PORTSC_RESET BIT(4) bit is RW1S attribute, which means Write-1-to-set status:
1084 // Register bits indicate status when read, a clear bit may be set by
1085 // writing a '1'. Writing a '0' to RW1S bits has no effect.
1086 //
1087 break;
1088
1089 case EfiUsbPortPower:
1090 if (Xhc->HcCParams.Data.Ppc) {
1091 //
1092 // Port Power Control supported
1093 //
1094 State &= ~XHC_PORTSC_PP;
1095 XhcPeiWriteOpReg (Xhc, Offset, State);
1096 }
1097 break;
1098
1099 case EfiUsbPortOwner:
1100 //
1101 // XHCI root hub port don't has the owner bit, ignore the operation
1102 //
1103 break;
1104
1105 case EfiUsbPortConnectChange:
1106 //
1107 // Clear connect status change
1108 //
1109 State |= XHC_PORTSC_CSC;
1110 XhcPeiWriteOpReg (Xhc, Offset, State);
1111 break;
1112
1113 case EfiUsbPortEnableChange:
1114 //
1115 // Clear enable status change
1116 //
1117 State |= XHC_PORTSC_PEC;
1118 XhcPeiWriteOpReg (Xhc, Offset, State);
1119 break;
1120
1121 case EfiUsbPortOverCurrentChange:
1122 //
1123 // Clear PortOverCurrent change
1124 //
1125 State |= XHC_PORTSC_OCC;
1126 XhcPeiWriteOpReg (Xhc, Offset, State);
1127 break;
1128
1129 case EfiUsbPortResetChange:
1130 //
1131 // Clear Port Reset change
1132 //
1133 State |= XHC_PORTSC_PRC;
1134 XhcPeiWriteOpReg (Xhc, Offset, State);
1135 break;
1136
1137 case EfiUsbPortSuspendChange:
1138 //
1139 // Not supported or not related operation
1140 //
1141 break;
1142
1143 default:
1144 Status = EFI_INVALID_PARAMETER;
1145 break;
1146 }
1147
1148 ON_EXIT:
1149 DEBUG ((EFI_D_INFO, "XhcPeiClearRootHubPortFeature: PortFeature: %x Status = %r\n", PortFeature, Status));
1150 return Status;
1151 }
1152
1153 /**
1154 Sets a feature for the specified root hub port.
1155
1156 @param PeiServices The pointer of EFI_PEI_SERVICES
1157 @param This The pointer of PEI_USB2_HOST_CONTROLLER_PPI
1158 @param PortNumber Root hub port to set.
1159 @param PortFeature Feature to set.
1160
1161 @retval EFI_SUCCESS The feature specified by PortFeature was set.
1162 @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid.
1163 @retval EFI_TIMEOUT The time out occurred.
1164
1165 **/
1166 EFI_STATUS
1167 EFIAPI
1168 XhcPeiSetRootHubPortFeature (
1169 IN EFI_PEI_SERVICES **PeiServices,
1170 IN PEI_USB2_HOST_CONTROLLER_PPI *This,
1171 IN UINT8 PortNumber,
1172 IN EFI_USB_PORT_FEATURE PortFeature
1173 )
1174 {
1175 PEI_XHC_DEV *Xhc;
1176 UINT32 Offset;
1177 UINT32 State;
1178 EFI_STATUS Status;
1179
1180 Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);
1181 Status = EFI_SUCCESS;
1182
1183 if (PortNumber >= Xhc->HcSParams1.Data.MaxPorts) {
1184 Status = EFI_INVALID_PARAMETER;
1185 goto ON_EXIT;
1186 }
1187
1188 Offset = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));
1189 State = XhcPeiReadOpReg (Xhc, Offset);
1190 DEBUG ((EFI_D_INFO, "XhcPeiSetRootHubPortFeature: Port: %x State: %x\n", PortNumber, State));
1191
1192 //
1193 // Mask off the port status change bits, these bits are
1194 // write clean bits
1195 //
1196 State &= ~ (BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);
1197
1198 switch (PortFeature) {
1199 case EfiUsbPortEnable:
1200 //
1201 // Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag.
1202 // A port may be disabled by software writing a '1' to this flag.
1203 //
1204 break;
1205
1206 case EfiUsbPortSuspend:
1207 State |= XHC_PORTSC_LWS;
1208 XhcPeiWriteOpReg (Xhc, Offset, State);
1209 State &= ~XHC_PORTSC_PLS;
1210 State |= (3 << 5) ;
1211 XhcPeiWriteOpReg (Xhc, Offset, State);
1212 break;
1213
1214 case EfiUsbPortReset:
1215 //
1216 // Make sure Host Controller not halt before reset it
1217 //
1218 if (XhcPeiIsHalt (Xhc)) {
1219 Status = XhcPeiRunHC (Xhc, XHC_GENERIC_TIMEOUT);
1220 if (EFI_ERROR (Status)) {
1221 break;
1222 }
1223 }
1224
1225 //
1226 // 4.3.1 Resetting a Root Hub Port
1227 // 1) Write the PORTSC register with the Port Reset (PR) bit set to '1'.
1228 // 2) Wait for a successful Port Status Change Event for the port, where the Port Reset Change (PRC)
1229 // bit in the PORTSC field is set to '1'.
1230 //
1231 State |= XHC_PORTSC_RESET;
1232 XhcPeiWriteOpReg (Xhc, Offset, State);
1233 XhcPeiWaitOpRegBit(Xhc, Offset, XHC_PORTSC_PRC, TRUE, XHC_GENERIC_TIMEOUT);
1234 break;
1235
1236 case EfiUsbPortPower:
1237 if (Xhc->HcCParams.Data.Ppc) {
1238 //
1239 // Port Power Control supported
1240 //
1241 State |= XHC_PORTSC_PP;
1242 XhcPeiWriteOpReg (Xhc, Offset, State);
1243 }
1244 break;
1245
1246 case EfiUsbPortOwner:
1247 //
1248 // XHCI root hub port don't has the owner bit, ignore the operation
1249 //
1250 break;
1251
1252 default:
1253 Status = EFI_INVALID_PARAMETER;
1254 }
1255
1256 ON_EXIT:
1257 DEBUG ((EFI_D_INFO, "XhcPeiSetRootHubPortFeature: PortFeature: %x Status = %r\n", PortFeature, Status));
1258 return Status;
1259 }
1260
1261 /**
1262 Retrieves the current status of a USB root hub port.
1263
1264 @param PeiServices The pointer of EFI_PEI_SERVICES.
1265 @param This The pointer of PEI_USB2_HOST_CONTROLLER_PPI.
1266 @param PortNumber The root hub port to retrieve the state from.
1267 @param PortStatus Variable to receive the port state.
1268
1269 @retval EFI_SUCCESS The status of the USB root hub port specified.
1270 by PortNumber was returned in PortStatus.
1271 @retval EFI_INVALID_PARAMETER PortNumber is invalid.
1272
1273 **/
1274 EFI_STATUS
1275 EFIAPI
1276 XhcPeiGetRootHubPortStatus (
1277 IN EFI_PEI_SERVICES **PeiServices,
1278 IN PEI_USB2_HOST_CONTROLLER_PPI *This,
1279 IN UINT8 PortNumber,
1280 OUT EFI_USB_PORT_STATUS *PortStatus
1281 )
1282 {
1283 PEI_XHC_DEV *Xhc;
1284 UINT32 Offset;
1285 UINT32 State;
1286 UINTN Index;
1287 UINTN MapSize;
1288 USB_DEV_ROUTE ParentRouteChart;
1289
1290 if (PortStatus == NULL) {
1291 return EFI_INVALID_PARAMETER;
1292 }
1293
1294 Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);
1295
1296 if (PortNumber >= Xhc->HcSParams1.Data.MaxPorts) {
1297 return EFI_INVALID_PARAMETER;
1298 }
1299
1300 //
1301 // Clear port status.
1302 //
1303 PortStatus->PortStatus = 0;
1304 PortStatus->PortChangeStatus = 0;
1305
1306 Offset = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));
1307 State = XhcPeiReadOpReg (Xhc, Offset);
1308 DEBUG ((EFI_D_INFO, "XhcPeiGetRootHubPortStatus: Port: %x State: %x\n", PortNumber, State));
1309
1310 //
1311 // According to XHCI 1.0 spec, bit 10~13 of the root port status register identifies the speed of the attached device.
1312 //
1313 switch ((State & XHC_PORTSC_PS) >> 10) {
1314 case 2:
1315 PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;
1316 break;
1317
1318 case 3:
1319 PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED;
1320 break;
1321
1322 case 4:
1323 PortStatus->PortStatus |= USB_PORT_STAT_SUPER_SPEED;
1324 break;
1325
1326 default:
1327 break;
1328 }
1329
1330 //
1331 // Convert the XHCI port/port change state to UEFI status
1332 //
1333 MapSize = sizeof (mUsbPortStateMap) / sizeof (USB_PORT_STATE_MAP);
1334
1335 for (Index = 0; Index < MapSize; Index++) {
1336 if (XHC_BIT_IS_SET (State, mUsbPortStateMap[Index].HwState)) {
1337 PortStatus->PortStatus = (UINT16) (PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);
1338 }
1339 }
1340 //
1341 // Bit5~8 reflects its current link state.
1342 //
1343 if ((State & XHC_PORTSC_PLS) >> 5 == 3) {
1344 PortStatus->PortStatus |= USB_PORT_STAT_SUSPEND;
1345 }
1346
1347 MapSize = sizeof (mUsbPortChangeMap) / sizeof (USB_PORT_STATE_MAP);
1348
1349 for (Index = 0; Index < MapSize; Index++) {
1350 if (XHC_BIT_IS_SET (State, mUsbPortChangeMap[Index].HwState)) {
1351 PortStatus->PortChangeStatus = (UINT16) (PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);
1352 }
1353 }
1354
1355 MapSize = sizeof (mUsbClearPortChangeMap) / sizeof (USB_CLEAR_PORT_MAP);
1356
1357 for (Index = 0; Index < MapSize; Index++) {
1358 if (XHC_BIT_IS_SET (State, mUsbClearPortChangeMap[Index].HwState)) {
1359 XhcPeiClearRootHubPortFeature (PeiServices, This, PortNumber, (EFI_USB_PORT_FEATURE)mUsbClearPortChangeMap[Index].Selector);
1360 }
1361 }
1362
1363 //
1364 // Poll the root port status register to enable/disable corresponding device slot if there is a device attached/detached.
1365 // For those devices behind hub, we get its attach/detach event by hooking Get_Port_Status request at control transfer for those hub.
1366 //
1367 ParentRouteChart.Dword = 0;
1368 XhcPeiPollPortStatusChange (Xhc, ParentRouteChart, PortNumber, PortStatus);
1369
1370 DEBUG ((EFI_D_INFO, "XhcPeiGetRootHubPortStatus: PortChangeStatus: %x PortStatus: %x\n", PortStatus->PortChangeStatus, PortStatus->PortStatus));
1371 return EFI_SUCCESS;
1372 }
1373
1374 /**
1375 @param FileHandle Handle of the file being invoked.
1376 @param PeiServices Describes the list of possible PEI Services.
1377
1378 @retval EFI_SUCCESS PPI successfully installed.
1379
1380 **/
1381 EFI_STATUS
1382 EFIAPI
1383 XhcPeimEntry (
1384 IN EFI_PEI_FILE_HANDLE FileHandle,
1385 IN CONST EFI_PEI_SERVICES **PeiServices
1386 )
1387 {
1388 PEI_USB_CONTROLLER_PPI *UsbControllerPpi;
1389 EFI_STATUS Status;
1390 UINT8 Index;
1391 UINTN ControllerType;
1392 UINTN BaseAddress;
1393 UINTN MemPages;
1394 PEI_XHC_DEV *XhcDev;
1395 EFI_PHYSICAL_ADDRESS TempPtr;
1396 UINT32 PageSize;
1397
1398 //
1399 // Shadow this PEIM to run from memory.
1400 //
1401 if (!EFI_ERROR (PeiServicesRegisterForShadow (FileHandle))) {
1402 return EFI_SUCCESS;
1403 }
1404
1405 Status = PeiServicesLocatePpi (
1406 &gPeiUsbControllerPpiGuid,
1407 0,
1408 NULL,
1409 (VOID **) &UsbControllerPpi
1410 );
1411 if (EFI_ERROR (Status)) {
1412 return EFI_UNSUPPORTED;
1413 }
1414
1415 Index = 0;
1416 while (TRUE) {
1417 Status = UsbControllerPpi->GetUsbController (
1418 (EFI_PEI_SERVICES **) PeiServices,
1419 UsbControllerPpi,
1420 Index,
1421 &ControllerType,
1422 &BaseAddress
1423 );
1424 //
1425 // When status is error, it means no controller is found.
1426 //
1427 if (EFI_ERROR (Status)) {
1428 break;
1429 }
1430
1431 //
1432 // This PEIM is for XHC type controller.
1433 //
1434 if (ControllerType != PEI_XHCI_CONTROLLER) {
1435 Index++;
1436 continue;
1437 }
1438
1439 MemPages = EFI_SIZE_TO_PAGES (sizeof (PEI_XHC_DEV));
1440 Status = PeiServicesAllocatePages (
1441 EfiBootServicesData,
1442 MemPages,
1443 &TempPtr
1444 );
1445 if (EFI_ERROR (Status)) {
1446 return EFI_OUT_OF_RESOURCES;
1447 }
1448 ZeroMem ((VOID *) (UINTN) TempPtr, EFI_PAGES_TO_SIZE (MemPages));
1449 XhcDev = (PEI_XHC_DEV *) ((UINTN) TempPtr);
1450
1451 XhcDev->Signature = USB_XHC_DEV_SIGNATURE;
1452 XhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress;
1453 XhcDev->CapLength = (UINT8) (XhcPeiReadCapRegister (XhcDev, XHC_CAPLENGTH_OFFSET) & 0x0FF);
1454 XhcDev->HcSParams1.Dword = XhcPeiReadCapRegister (XhcDev, XHC_HCSPARAMS1_OFFSET);
1455 XhcDev->HcSParams2.Dword = XhcPeiReadCapRegister (XhcDev, XHC_HCSPARAMS2_OFFSET);
1456 XhcDev->HcCParams.Dword = XhcPeiReadCapRegister (XhcDev, XHC_HCCPARAMS_OFFSET);
1457 XhcDev->DBOff = XhcPeiReadCapRegister (XhcDev, XHC_DBOFF_OFFSET);
1458 XhcDev->RTSOff = XhcPeiReadCapRegister (XhcDev, XHC_RTSOFF_OFFSET);
1459
1460 //
1461 // This PageSize field defines the page size supported by the xHC implementation.
1462 // This xHC supports a page size of 2^(n+12) if bit n is Set. For example,
1463 // if bit 0 is Set, the xHC supports 4k byte page sizes.
1464 //
1465 PageSize = XhcPeiReadOpReg (XhcDev, XHC_PAGESIZE_OFFSET) & XHC_PAGESIZE_MASK;
1466 XhcDev->PageSize = 1 << (HighBitSet32 (PageSize) + 12);
1467
1468 DEBUG ((EFI_D_INFO, "XhciPei: UsbHostControllerBaseAddress: %x\n", XhcDev->UsbHostControllerBaseAddress));
1469 DEBUG ((EFI_D_INFO, "XhciPei: CapLength: %x\n", XhcDev->CapLength));
1470 DEBUG ((EFI_D_INFO, "XhciPei: HcSParams1: %x\n", XhcDev->HcSParams1.Dword));
1471 DEBUG ((EFI_D_INFO, "XhciPei: HcSParams2: %x\n", XhcDev->HcSParams2.Dword));
1472 DEBUG ((EFI_D_INFO, "XhciPei: HcCParams: %x\n", XhcDev->HcCParams.Dword));
1473 DEBUG ((EFI_D_INFO, "XhciPei: DBOff: %x\n", XhcDev->DBOff));
1474 DEBUG ((EFI_D_INFO, "XhciPei: RTSOff: %x\n", XhcDev->RTSOff));
1475 DEBUG ((EFI_D_INFO, "XhciPei: PageSize: %x\n", XhcDev->PageSize));
1476
1477 XhcPeiResetHC (XhcDev, XHC_RESET_TIMEOUT);
1478 ASSERT (XhcPeiIsHalt (XhcDev));
1479
1480 //
1481 // Initialize the schedule
1482 //
1483 XhcPeiInitSched (XhcDev);
1484
1485 //
1486 // Start the Host Controller
1487 //
1488 XhcPeiRunHC (XhcDev, XHC_GENERIC_TIMEOUT);
1489
1490 //
1491 // Wait for root port state stable
1492 //
1493 MicroSecondDelay (XHC_ROOT_PORT_STATE_STABLE);
1494
1495 XhcDev->Usb2HostControllerPpi.ControlTransfer = XhcPeiControlTransfer;
1496 XhcDev->Usb2HostControllerPpi.BulkTransfer = XhcPeiBulkTransfer;
1497 XhcDev->Usb2HostControllerPpi.GetRootHubPortNumber = XhcPeiGetRootHubPortNumber;
1498 XhcDev->Usb2HostControllerPpi.GetRootHubPortStatus = XhcPeiGetRootHubPortStatus;
1499 XhcDev->Usb2HostControllerPpi.SetRootHubPortFeature = XhcPeiSetRootHubPortFeature;
1500 XhcDev->Usb2HostControllerPpi.ClearRootHubPortFeature = XhcPeiClearRootHubPortFeature;
1501
1502 XhcDev->PpiDescriptor.Flags = (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
1503 XhcDev->PpiDescriptor.Guid = &gPeiUsb2HostControllerPpiGuid;
1504 XhcDev->PpiDescriptor.Ppi = &XhcDev->Usb2HostControllerPpi;
1505
1506 PeiServicesInstallPpi (&XhcDev->PpiDescriptor);
1507
1508 Index++;
1509 }
1510
1511 return EFI_SUCCESS;
1512 }
1513