2 Private Header file for Usb Host Controller PEIM
4 Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions
8 of the BSD License which accompanies this distribution. The
9 full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #ifndef _RECOVERY_XHC_H_
18 #define _RECOVERY_XHC_H_
22 #include <Ppi/UsbController.h>
23 #include <Ppi/Usb2HostController.h>
25 #include <Library/DebugLib.h>
26 #include <Library/PeimEntryPoint.h>
27 #include <Library/PeiServicesLib.h>
28 #include <Library/BaseMemoryLib.h>
29 #include <Library/TimerLib.h>
30 #include <Library/IoLib.h>
31 #include <Library/MemoryAllocationLib.h>
33 typedef struct _PEI_XHC_DEV PEI_XHC_DEV
;
34 typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT
;
38 #include "XhciSched.h"
40 #define CMD_RING_TRB_NUMBER 0x100
41 #define TR_RING_TRB_NUMBER 0x100
42 #define ERST_NUMBER 0x01
43 #define EVENT_RING_TRB_NUMBER 0x200
45 #define XHC_1_MICROSECOND 1
46 #define XHC_1_MILLISECOND (1000 * XHC_1_MICROSECOND)
47 #define XHC_1_SECOND (1000 * XHC_1_MILLISECOND)
50 // XHC reset timeout experience values.
51 // The unit is microsecond, setting it as 1s.
53 #define XHC_RESET_TIMEOUT (1 * XHC_1_SECOND)
55 // XHC delay experience value for polling operation.
56 // The unit is microsecond, set it as 1ms.
58 #define XHC_POLL_DELAY (1 * XHC_1_MILLISECOND)
61 // Wait for root port state stable.
63 #define XHC_ROOT_PORT_STATE_STABLE (200 * XHC_1_MILLISECOND)
65 #define XHC_GENERIC_TIMEOUT (10 * XHC_1_MILLISECOND)
67 #define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
68 #define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
69 #define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
71 #define XHC_REG_BIT_IS_SET(XHC, Offset, Bit) \
72 (XHC_BIT_IS_SET(XhcPeiReadOpReg ((XHC), (Offset)), (Bit)))
74 #define USB_DESC_TYPE_HUB 0x29
75 #define USB_DESC_TYPE_HUB_SUPER_SPEED 0x2a
78 // The RequestType in EFI_USB_DEVICE_REQUEST is composed of
79 // three fields: One bit direction, 2 bit type, and 5 bit
82 #define USB_REQUEST_TYPE(Dir, Type, Target) \
83 ((UINT8)((((Dir) == EfiUsbDataIn ? 0x01 : 0) << 7) | (Type) | (Target)))
85 struct _USB_DEV_CONTEXT
{
87 // Whether this entry in UsbDevContext array is used or not.
91 // The slot id assigned to the new device through XHCI's Enable_Slot cmd.
95 // The route string presented an attached usb device.
97 USB_DEV_ROUTE RouteString
;
99 // The route string of parent device if it exists. Otherwise it's zero.
101 USB_DEV_ROUTE ParentRouteString
;
103 // The actual device address assigned by XHCI through Address_Device command.
107 // The requested device address from UsbBus driver through Set_Address standard usb request.
108 // As XHCI spec replaces this request with Address_Device command, we have to record the
109 // requested device address and establish a mapping relationship with the actual device address.
110 // Then UsbBus driver just need to be aware of the requested device address to access usb device
111 // through EFI_USB2_HC_PROTOCOL. Xhci driver would be responsible for translating it to actual
112 // device address and access the actual device.
116 // The pointer to the input device context.
120 // The pointer to the output device context.
124 // The transfer queue for every endpoint.
126 VOID
*EndpointTransferRing
[31];
128 // The device descriptor which is stored to support XHCI's Evaluate_Context cmd.
130 EFI_USB_DEVICE_DESCRIPTOR DevDesc
;
132 // As a usb device may include multiple configuration descriptors, we dynamically allocate an array
134 // Note that every configuration descriptor stored here includes those lower level descriptors,
135 // such as Interface descriptor, Endpoint descriptor, and so on.
136 // These information is used to support XHCI's Config_Endpoint cmd.
138 EFI_USB_CONFIG_DESCRIPTOR
**ConfDesc
;
141 #define USB_XHC_DEV_SIGNATURE SIGNATURE_32 ('x', 'h', 'c', 'i')
143 struct _PEI_XHC_DEV
{
145 PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi
;
146 EFI_PEI_PPI_DESCRIPTOR PpiDescriptor
;
147 UINT32 UsbHostControllerBaseAddress
;
148 USBHC_MEM_POOL
*MemPool
;
151 // XHCI configuration data
153 UINT8 CapLength
; ///< Capability Register Length
154 XHC_HCSPARAMS1 HcSParams1
; ///< Structural Parameters 1
155 XHC_HCSPARAMS2 HcSParams2
; ///< Structural Parameters 2
156 XHC_HCCPARAMS HcCParams
; ///< Capability Parameters
157 UINT32 DBOff
; ///< Doorbell Offset
158 UINT32 RTSOff
; ///< Runtime Register Space Offset
160 UINT32 MaxScratchpadBufs
;
162 UINT64
*ScratchEntry
;
168 TRANSFER_RING CmdRing
;
172 EVENT_RING EventRing
;
175 // Store device contexts managed by XHCI device
176 // The array supports up to 255 devices, entry 0 is reserved and should not be used.
178 USB_DEV_CONTEXT UsbDevContext
[256];
181 #define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS(a) CR (a, PEI_XHC_DEV, Usb2HostControllerPpi, USB_XHC_DEV_SIGNATURE)
184 Initialize the memory management pool for the host controller.
186 @return Pointer to the allocated memory pool or NULL if failed.
196 Release the memory management pool.
198 @param Pool The USB memory pool to free.
203 IN USBHC_MEM_POOL
*Pool
208 Allocate some memory from the host controller's memory pool
209 which can be used to communicate with host controller.
211 @param Pool The host controller's memory pool.
212 @param Size Size of the memory to allocate.
214 @return The allocated memory or NULL.
219 IN USBHC_MEM_POOL
*Pool
,
225 Free the allocated memory back to the memory pool.
227 @param Pool The memory pool of the host controller.
228 @param Mem The memory to free.
229 @param Size The size of the memory to free.
234 IN USBHC_MEM_POOL
*Pool
,