1a62560665990389c32d915b268d07039935b349
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciPei / XhciReg.h
1 /** @file
2 Private Header file for Usb Host Controller PEIM
3
4 Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
5
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions
8 of the BSD License which accompanies this distribution. The
9 full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #ifndef _EFI_PEI_XHCI_REG_H_
18 #define _EFI_PEI_XHCI_REG_H_
19
20 //
21 // Capability registers offset
22 //
23 #define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset
24 #define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h
25 #define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1
26 #define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2
27 #define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3
28 #define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters
29 #define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset
30 #define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset
31
32 //
33 // Operational registers offset
34 //
35 #define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset
36 #define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset
37 #define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset
38 #define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset
39 #define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset
40 #define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset
41 #define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset
42 #define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset
43
44 //
45 // Runtime registers offset
46 //
47 #define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset
48 #define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset
49 #define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset
50 #define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset
51 #define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset
52 #define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset
53
54 //
55 // Register Bit Definition
56 //
57 #define XHC_USBCMD_RUN BIT0 // Run/Stop
58 #define XHC_USBCMD_RESET BIT1 // Host Controller Reset
59 #define XHC_USBCMD_INTE BIT2 // Interrupter Enable
60 #define XHC_USBCMD_HSEE BIT3 // Host System Error Enable
61
62 #define XHC_USBSTS_HALT BIT0 // Host Controller Halted
63 #define XHC_USBSTS_HSE BIT2 // Host System Error
64 #define XHC_USBSTS_EINT BIT3 // Event Interrupt
65 #define XHC_USBSTS_PCD BIT4 // Port Change Detect
66 #define XHC_USBSTS_SSS BIT8 // Save State Status
67 #define XHC_USBSTS_RSS BIT9 // Restore State Status
68 #define XHC_USBSTS_SRE BIT10 // Save/Restore Error
69 #define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready
70 #define XHC_USBSTS_HCE BIT12 // Host Controller Error
71
72 #define XHC_PAGESIZE_MASK 0xFFFF // Page Size
73
74 #define XHC_CRCR_RCS BIT0 // Ring Cycle State
75 #define XHC_CRCR_CS BIT1 // Command Stop
76 #define XHC_CRCR_CA BIT2 // Command Abort
77 #define XHC_CRCR_CRR BIT3 // Command Ring Running
78
79 #define XHC_CONFIG_MASK 0xFF // Max Device Slots Enabled
80
81 #define XHC_PORTSC_CCS BIT0 // Current Connect Status
82 #define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled
83 #define XHC_PORTSC_OCA BIT3 // Over-current Active
84 #define XHC_PORTSC_RESET BIT4 // Port Reset
85 #define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State
86 #define XHC_PORTSC_PP BIT9 // Port Power
87 #define XHC_PORTSC_PS (BIT10|BIT11|BIT12) // Port Speed
88 #define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
89 #define XHC_PORTSC_CSC BIT17 // Connect Status Change
90 #define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
91 #define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
92 #define XHC_PORTSC_OCC BIT20 // Over-Current Change
93 #define XHC_PORTSC_PRC BIT21 // Port Reset Change
94 #define XHC_PORTSC_PLC BIT22 // Port Link State Change
95 #define XHC_PORTSC_CEC BIT23 // Port Config Error Change
96 #define XHC_PORTSC_CAS BIT24 // Cold Attach Status
97
98 #define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status
99 #define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled
100 #define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
101 #define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset
102 #define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power
103 #define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
104 #define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change
105 #define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
106 #define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
107 #define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
108
109 #define XHC_IMAN_IP BIT0 // Interrupt Pending
110 #define XHC_IMAN_IE BIT1 // Interrupt Enable
111
112 #define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval
113 #define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter
114
115
116 #pragma pack (1)
117 typedef struct {
118 UINT8 MaxSlots; // Number of Device Slots
119 UINT16 MaxIntrs:11; // Number of Interrupters
120 UINT16 Rsvd:5;
121 UINT8 MaxPorts; // Number of Ports
122 } HCSPARAMS1;
123
124 //
125 // Structural Parameters 1 Register Bitmap Definition
126 //
127 typedef union {
128 UINT32 Dword;
129 HCSPARAMS1 Data;
130 } XHC_HCSPARAMS1;
131
132 typedef struct {
133 UINT32 Ist:4; // Isochronous Scheduling Threshold
134 UINT32 Erst:4; // Event Ring Segment Table Max
135 UINT32 Rsvd:13;
136 UINT32 ScratchBufHi:5; // Max Scratchpad Buffers Hi
137 UINT32 Spr:1; // Scratchpad Restore
138 UINT32 ScratchBufLo:5; // Max Scratchpad Buffers Lo
139 } HCSPARAMS2;
140
141 //
142 // Structural Parameters 2 Register Bitmap Definition
143 //
144 typedef union {
145 UINT32 Dword;
146 HCSPARAMS2 Data;
147 } XHC_HCSPARAMS2;
148
149 typedef struct {
150 UINT16 Ac64:1; // 64-bit Addressing Capability
151 UINT16 Bnc:1; // BW Negotiation Capability
152 UINT16 Csz:1; // Context Size
153 UINT16 Ppc:1; // Port Power Control
154 UINT16 Pind:1; // Port Indicators
155 UINT16 Lhrc:1; // Light HC Reset Capability
156 UINT16 Ltc:1; // Latency Tolerance Messaging Capability
157 UINT16 Nss:1; // No Secondary SID Support
158 UINT16 Pae:1; // Parse All Event Data
159 UINT16 Rsvd:3;
160 UINT16 MaxPsaSize:4; // Maximum Primary Stream Array Size
161 UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer
162 } HCCPARAMS;
163
164 //
165 // Capability Parameters Register Bitmap Definition
166 //
167 typedef union {
168 UINT32 Dword;
169 HCCPARAMS Data;
170 } XHC_HCCPARAMS;
171
172 #pragma pack ()
173
174 //
175 // XHCi Data and Ctrl Structures
176 //
177 #pragma pack(1)
178 typedef struct {
179 UINT8 Pi;
180 UINT8 SubClassCode;
181 UINT8 BaseCode;
182 } USB_CLASSC;
183
184 typedef struct {
185 UINT8 Length;
186 UINT8 DescType;
187 UINT8 NumPorts;
188 UINT16 HubCharacter;
189 UINT8 PwrOn2PwrGood;
190 UINT8 HubContrCurrent;
191 UINT8 Filler[16];
192 } EFI_USB_HUB_DESCRIPTOR;
193 #pragma pack()
194
195 //
196 // Hub Class Feature Selector for Clear Port Feature Request
197 // It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.
198 // For more details, Please refer to USB 3.0 Spec Table 10-7.
199 //
200 typedef enum {
201 Usb3PortBHPortReset = 28,
202 Usb3PortBHPortResetChange = 29
203 } XHC_PORT_FEATURE;
204
205 //
206 // Structure to map the hardware port states to the
207 // UEFI's port states.
208 //
209 typedef struct {
210 UINT32 HwState;
211 UINT16 UefiState;
212 } USB_PORT_STATE_MAP;
213
214 //
215 // Structure to map the hardware port states to feature selector for clear port feature request.
216 //
217 typedef struct {
218 UINT32 HwState;
219 UINT16 Selector;
220 } USB_CLEAR_PORT_MAP;
221
222 /**
223 Read XHCI Operation register.
224
225 @param Xhc The XHCI device.
226 @param Offset The operation register offset.
227
228 @retval the register content read.
229
230 **/
231 UINT32
232 XhcPeiReadOpReg (
233 IN PEI_XHC_DEV *Xhc,
234 IN UINT32 Offset
235 );
236
237 /**
238 Write the data to the XHCI operation register.
239
240 @param Xhc The XHCI device.
241 @param Offset The operation register offset.
242 @param Data The data to write.
243
244 **/
245 VOID
246 XhcPeiWriteOpReg (
247 IN PEI_XHC_DEV *Xhc,
248 IN UINT32 Offset,
249 IN UINT32 Data
250 );
251
252 /**
253 Set one bit of the operational register while keeping other bits.
254
255 @param Xhc The XHCI device.
256 @param Offset The offset of the operational register.
257 @param Bit The bit mask of the register to set.
258
259 **/
260 VOID
261 XhcPeiSetOpRegBit (
262 IN PEI_XHC_DEV *Xhc,
263 IN UINT32 Offset,
264 IN UINT32 Bit
265 );
266
267 /**
268 Clear one bit of the operational register while keeping other bits.
269
270 @param Xhc The XHCI device.
271 @param Offset The offset of the operational register.
272 @param Bit The bit mask of the register to clear.
273
274 **/
275 VOID
276 XhcPeiClearOpRegBit (
277 IN PEI_XHC_DEV *Xhc,
278 IN UINT32 Offset,
279 IN UINT32 Bit
280 );
281
282 /**
283 Wait the operation register's bit as specified by Bit
284 to be set (or clear).
285
286 @param Xhc The XHCI device.
287 @param Offset The offset of the operational register.
288 @param Bit The bit of the register to wait for.
289 @param WaitToSet Wait the bit to set or clear.
290 @param Timeout The time to wait before abort (in microsecond, us).
291
292 @retval EFI_SUCCESS The bit successfully changed by host controller.
293 @retval EFI_TIMEOUT The time out occurred.
294
295 **/
296 EFI_STATUS
297 XhcPeiWaitOpRegBit (
298 IN PEI_XHC_DEV *Xhc,
299 IN UINT32 Offset,
300 IN UINT32 Bit,
301 IN BOOLEAN WaitToSet,
302 IN UINT32 Timeout
303 );
304
305 /**
306 Read XHCI door bell register.
307
308 @param Xhc The XHCI device.
309 @param Offset The offset of the door bell register.
310
311 @return The register content read
312
313 **/
314 UINT32
315 XhcPeiReadDoorBellReg (
316 IN PEI_XHC_DEV *Xhc,
317 IN UINT32 Offset
318 );
319
320 /**
321 Write the data to the XHCI door bell register.
322
323 @param Xhc The XHCI device.
324 @param Offset The offset of the door bell register.
325 @param Data The data to write.
326
327 **/
328 VOID
329 XhcPeiWriteDoorBellReg (
330 IN PEI_XHC_DEV *Xhc,
331 IN UINT32 Offset,
332 IN UINT32 Data
333 );
334
335 /**
336 Read XHCI runtime register.
337
338 @param Xhc The XHCI device.
339 @param Offset The offset of the runtime register.
340
341 @return The register content read
342
343 **/
344 UINT32
345 XhcPeiReadRuntimeReg (
346 IN PEI_XHC_DEV *Xhc,
347 IN UINT32 Offset
348 );
349
350 /**
351 Write the data to the XHCI runtime register.
352
353 @param Xhc The XHCI device.
354 @param Offset The offset of the runtime register.
355 @param Data The data to write.
356
357 **/
358 VOID
359 XhcPeiWriteRuntimeReg (
360 IN PEI_XHC_DEV *Xhc,
361 IN UINT32 Offset,
362 IN UINT32 Data
363 );
364
365 /**
366 Set one bit of the runtime register while keeping other bits.
367
368 @param Xhc The XHCI device.
369 @param Offset The offset of the runtime register.
370 @param Bit The bit mask of the register to set.
371
372 **/
373 VOID
374 XhcPeiSetRuntimeRegBit (
375 IN PEI_XHC_DEV *Xhc,
376 IN UINT32 Offset,
377 IN UINT32 Bit
378 );
379
380 /**
381 Clear one bit of the runtime register while keeping other bits.
382
383 @param Xhc The XHCI device.
384 @param Offset The offset of the runtime register.
385 @param Bit The bit mask of the register to set.
386
387 **/
388 VOID
389 XhcPeiClearRuntimeRegBit (
390 IN PEI_XHC_DEV *Xhc,
391 IN UINT32 Offset,
392 IN UINT32 Bit
393 );
394
395 /**
396 Check whether Xhc is halted.
397
398 @param Xhc The XHCI device.
399
400 @retval TRUE The controller is halted.
401 @retval FALSE The controller isn't halted.
402
403 **/
404 BOOLEAN
405 XhcPeiIsHalt (
406 IN PEI_XHC_DEV *Xhc
407 );
408
409 /**
410 Check whether system error occurred.
411
412 @param Xhc The XHCI device.
413
414 @retval TRUE System error happened.
415 @retval FALSE No system error.
416
417 **/
418 BOOLEAN
419 XhcPeiIsSysError (
420 IN PEI_XHC_DEV *Xhc
421 );
422
423 /**
424 Reset the host controller.
425
426 @param Xhc The XHCI device.
427 @param Timeout Time to wait before abort (in millisecond, ms).
428
429 @retval EFI_TIMEOUT The transfer failed due to time out.
430 @retval Others Failed to reset the host.
431
432 **/
433 EFI_STATUS
434 XhcPeiResetHC (
435 IN PEI_XHC_DEV *Xhc,
436 IN UINT32 Timeout
437 );
438
439 /**
440 Halt the host controller.
441
442 @param Xhc The XHCI device.
443 @param Timeout Time to wait before abort.
444
445 @retval EFI_TIMEOUT Failed to halt the controller before Timeout.
446 @retval EFI_SUCCESS The XHCI is halt.
447
448 **/
449 EFI_STATUS
450 XhcPeiHaltHC (
451 IN PEI_XHC_DEV *Xhc,
452 IN UINT32 Timeout
453 );
454
455 /**
456 Set the XHCI to run.
457
458 @param Xhc The XHCI device.
459 @param Timeout Time to wait before abort.
460
461 @retval EFI_SUCCESS The XHCI is running.
462 @retval Others Failed to set the XHCI to run.
463
464 **/
465 EFI_STATUS
466 XhcPeiRunHC (
467 IN PEI_XHC_DEV *Xhc,
468 IN UINT32 Timeout
469 );
470
471 #endif