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MdeModulePkg/XhciPei: Support IoMmu.
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciPei / XhciSched.c
1 /** @file
2 PEIM to produce gPeiUsb2HostControllerPpiGuid based on gPeiUsbControllerPpiGuid
3 which is used to enable recovery function from USB Drivers.
4
5 Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
6
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions
9 of the BSD License which accompanies this distribution. The
10 full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
12
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15
16 **/
17
18 #include "XhcPeim.h"
19
20 /**
21 Create a command transfer TRB to support XHCI command interfaces.
22
23 @param Xhc The XHCI device.
24 @param CmdTrb The cmd TRB to be executed.
25
26 @return Created URB or NULL.
27
28 **/
29 URB*
30 XhcPeiCreateCmdTrb (
31 IN PEI_XHC_DEV *Xhc,
32 IN TRB_TEMPLATE *CmdTrb
33 )
34 {
35 URB *Urb;
36
37 Urb = AllocateZeroPool (sizeof (URB));
38 if (Urb == NULL) {
39 return NULL;
40 }
41
42 Urb->Signature = XHC_URB_SIG;
43
44 Urb->Ring = &Xhc->CmdRing;
45 XhcPeiSyncTrsRing (Xhc, Urb->Ring);
46 Urb->TrbNum = 1;
47 Urb->TrbStart = Urb->Ring->RingEnqueue;
48 CopyMem (Urb->TrbStart, CmdTrb, sizeof (TRB_TEMPLATE));
49 Urb->TrbStart->CycleBit = Urb->Ring->RingPCS & BIT0;
50 Urb->TrbEnd = Urb->TrbStart;
51
52 return Urb;
53 }
54
55 /**
56 Execute a XHCI cmd TRB pointed by CmdTrb.
57
58 @param Xhc The XHCI device.
59 @param CmdTrb The cmd TRB to be executed.
60 @param Timeout Indicates the maximum time, in millisecond, which the
61 transfer is allowed to complete.
62 @param EvtTrb The event TRB corresponding to the cmd TRB.
63
64 @retval EFI_SUCCESS The transfer was completed successfully.
65 @retval EFI_INVALID_PARAMETER Some parameters are invalid.
66 @retval EFI_TIMEOUT The transfer failed due to timeout.
67 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
68
69 **/
70 EFI_STATUS
71 XhcPeiCmdTransfer (
72 IN PEI_XHC_DEV *Xhc,
73 IN TRB_TEMPLATE *CmdTrb,
74 IN UINTN Timeout,
75 OUT TRB_TEMPLATE **EvtTrb
76 )
77 {
78 EFI_STATUS Status;
79 URB *Urb;
80
81 //
82 // Validate the parameters
83 //
84 if ((Xhc == NULL) || (CmdTrb == NULL)) {
85 return EFI_INVALID_PARAMETER;
86 }
87
88 Status = EFI_DEVICE_ERROR;
89
90 if (XhcPeiIsHalt (Xhc) || XhcPeiIsSysError (Xhc)) {
91 DEBUG ((EFI_D_ERROR, "XhcPeiCmdTransfer: HC is halted or has system error\n"));
92 goto ON_EXIT;
93 }
94
95 //
96 // Create a new URB, then poll the execution status.
97 //
98 Urb = XhcPeiCreateCmdTrb (Xhc, CmdTrb);
99 if (Urb == NULL) {
100 DEBUG ((EFI_D_ERROR, "XhcPeiCmdTransfer: failed to create URB\n"));
101 Status = EFI_OUT_OF_RESOURCES;
102 goto ON_EXIT;
103 }
104
105 Status = XhcPeiExecTransfer (Xhc, TRUE, Urb, Timeout);
106 *EvtTrb = Urb->EvtTrb;
107
108 if (Urb->Result == EFI_USB_NOERROR) {
109 Status = EFI_SUCCESS;
110 }
111
112 XhcPeiFreeUrb (Xhc, Urb);
113
114 ON_EXIT:
115 return Status;
116 }
117
118 /**
119 Create a new URB for a new transaction.
120
121 @param Xhc The XHCI device
122 @param BusAddr The logical device address assigned by UsbBus driver
123 @param EpAddr Endpoint addrress
124 @param DevSpeed The device speed
125 @param MaxPacket The max packet length of the endpoint
126 @param Type The transaction type
127 @param Request The standard USB request for control transfer
128 @param Data The user data to transfer
129 @param DataLen The length of data buffer
130 @param Callback The function to call when data is transferred
131 @param Context The context to the callback
132
133 @return Created URB or NULL
134
135 **/
136 URB*
137 XhcPeiCreateUrb (
138 IN PEI_XHC_DEV *Xhc,
139 IN UINT8 BusAddr,
140 IN UINT8 EpAddr,
141 IN UINT8 DevSpeed,
142 IN UINTN MaxPacket,
143 IN UINTN Type,
144 IN EFI_USB_DEVICE_REQUEST *Request,
145 IN VOID *Data,
146 IN UINTN DataLen,
147 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
148 IN VOID *Context
149 )
150 {
151 USB_ENDPOINT *Ep;
152 EFI_STATUS Status;
153 URB *Urb;
154
155 Urb = AllocateZeroPool (sizeof (URB));
156 if (Urb == NULL) {
157 return NULL;
158 }
159
160 Urb->Signature = XHC_URB_SIG;
161
162 Ep = &Urb->Ep;
163 Ep->BusAddr = BusAddr;
164 Ep->EpAddr = (UINT8) (EpAddr & 0x0F);
165 Ep->Direction = ((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;
166 Ep->DevSpeed = DevSpeed;
167 Ep->MaxPacket = MaxPacket;
168 Ep->Type = Type;
169
170 Urb->Request = Request;
171 Urb->Data = Data;
172 Urb->DataLen = DataLen;
173 Urb->Callback = Callback;
174 Urb->Context = Context;
175
176 Status = XhcPeiCreateTransferTrb (Xhc, Urb);
177 if (EFI_ERROR (Status)) {
178 DEBUG ((EFI_D_ERROR, "XhcPeiCreateUrb: XhcPeiCreateTransferTrb Failed, Status = %r\n", Status));
179 FreePool (Urb);
180 Urb = NULL;
181 }
182
183 return Urb;
184 }
185
186 /**
187 Free an allocated URB.
188
189 @param Xhc The XHCI device.
190 @param Urb The URB to free.
191
192 **/
193 VOID
194 XhcPeiFreeUrb (
195 IN PEI_XHC_DEV *Xhc,
196 IN URB *Urb
197 )
198 {
199 if ((Xhc == NULL) || (Urb == NULL)) {
200 return;
201 }
202
203 IoMmuUnmap (Urb->DataMap);
204
205 FreePool (Urb);
206 }
207
208 /**
209 Create a transfer TRB.
210
211 @param Xhc The XHCI device
212 @param Urb The urb used to construct the transfer TRB.
213
214 @return Created TRB or NULL
215
216 **/
217 EFI_STATUS
218 XhcPeiCreateTransferTrb (
219 IN PEI_XHC_DEV *Xhc,
220 IN URB *Urb
221 )
222 {
223 VOID *OutputContext;
224 TRANSFER_RING *EPRing;
225 UINT8 EPType;
226 UINT8 SlotId;
227 UINT8 Dci;
228 TRB *TrbStart;
229 UINTN TotalLen;
230 UINTN Len;
231 UINTN TrbNum;
232 EDKII_IOMMU_OPERATION MapOp;
233 EFI_PHYSICAL_ADDRESS PhyAddr;
234 VOID *Map;
235 EFI_STATUS Status;
236
237 SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
238 if (SlotId == 0) {
239 return EFI_DEVICE_ERROR;
240 }
241
242 Urb->Finished = FALSE;
243 Urb->StartDone = FALSE;
244 Urb->EndDone = FALSE;
245 Urb->Completed = 0;
246 Urb->Result = EFI_USB_NOERROR;
247
248 Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
249 EPRing = (TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];
250 Urb->Ring = EPRing;
251 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
252 if (Xhc->HcCParams.Data.Csz == 0) {
253 EPType = (UINT8) ((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;
254 } else {
255 EPType = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;
256 }
257
258 //
259 // No need to remap.
260 //
261 if ((Urb->Data != NULL) && (Urb->DataMap == NULL)) {
262 if (((UINT8) (Urb->Ep.Direction)) == EfiUsbDataIn) {
263 MapOp = EdkiiIoMmuOperationBusMasterWrite;
264 } else {
265 MapOp = EdkiiIoMmuOperationBusMasterRead;
266 }
267
268 Len = Urb->DataLen;
269 Status = IoMmuMap (MapOp, Urb->Data, &Len, &PhyAddr, &Map);
270
271 if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {
272 DEBUG ((DEBUG_ERROR, "XhcCreateTransferTrb: Fail to map Urb->Data.\n"));
273 return EFI_OUT_OF_RESOURCES;
274 }
275
276 Urb->DataPhy = (VOID *) ((UINTN) PhyAddr);
277 Urb->DataMap = Map;
278 }
279
280 //
281 // Construct the TRB
282 //
283 XhcPeiSyncTrsRing (Xhc, EPRing);
284 Urb->TrbStart = EPRing->RingEnqueue;
285 switch (EPType) {
286 case ED_CONTROL_BIDIR:
287 //
288 // For control transfer, create SETUP_STAGE_TRB first.
289 //
290 TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;
291 TrbStart->TrbCtrSetup.bmRequestType = Urb->Request->RequestType;
292 TrbStart->TrbCtrSetup.bRequest = Urb->Request->Request;
293 TrbStart->TrbCtrSetup.wValue = Urb->Request->Value;
294 TrbStart->TrbCtrSetup.wIndex = Urb->Request->Index;
295 TrbStart->TrbCtrSetup.wLength = Urb->Request->Length;
296 TrbStart->TrbCtrSetup.Length = 8;
297 TrbStart->TrbCtrSetup.IntTarget = 0;
298 TrbStart->TrbCtrSetup.IOC = 1;
299 TrbStart->TrbCtrSetup.IDT = 1;
300 TrbStart->TrbCtrSetup.Type = TRB_TYPE_SETUP_STAGE;
301 if (Urb->Ep.Direction == EfiUsbDataIn) {
302 TrbStart->TrbCtrSetup.TRT = 3;
303 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
304 TrbStart->TrbCtrSetup.TRT = 2;
305 } else {
306 TrbStart->TrbCtrSetup.TRT = 0;
307 }
308 //
309 // Update the cycle bit
310 //
311 TrbStart->TrbCtrSetup.CycleBit = EPRing->RingPCS & BIT0;
312 Urb->TrbNum++;
313
314 //
315 // For control transfer, create DATA_STAGE_TRB.
316 //
317 if (Urb->DataLen > 0) {
318 XhcPeiSyncTrsRing (Xhc, EPRing);
319 TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;
320 TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT (Urb->DataPhy);
321 TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT (Urb->DataPhy);
322 TrbStart->TrbCtrData.Length = (UINT32) Urb->DataLen;
323 TrbStart->TrbCtrData.TDSize = 0;
324 TrbStart->TrbCtrData.IntTarget = 0;
325 TrbStart->TrbCtrData.ISP = 1;
326 TrbStart->TrbCtrData.IOC = 1;
327 TrbStart->TrbCtrData.IDT = 0;
328 TrbStart->TrbCtrData.CH = 0;
329 TrbStart->TrbCtrData.Type = TRB_TYPE_DATA_STAGE;
330 if (Urb->Ep.Direction == EfiUsbDataIn) {
331 TrbStart->TrbCtrData.DIR = 1;
332 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
333 TrbStart->TrbCtrData.DIR = 0;
334 } else {
335 TrbStart->TrbCtrData.DIR = 0;
336 }
337 //
338 // Update the cycle bit
339 //
340 TrbStart->TrbCtrData.CycleBit = EPRing->RingPCS & BIT0;
341 Urb->TrbNum++;
342 }
343 //
344 // For control transfer, create STATUS_STAGE_TRB.
345 // Get the pointer to next TRB for status stage use
346 //
347 XhcPeiSyncTrsRing (Xhc, EPRing);
348 TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;
349 TrbStart->TrbCtrStatus.IntTarget = 0;
350 TrbStart->TrbCtrStatus.IOC = 1;
351 TrbStart->TrbCtrStatus.CH = 0;
352 TrbStart->TrbCtrStatus.Type = TRB_TYPE_STATUS_STAGE;
353 if (Urb->Ep.Direction == EfiUsbDataIn) {
354 TrbStart->TrbCtrStatus.DIR = 0;
355 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
356 TrbStart->TrbCtrStatus.DIR = 1;
357 } else {
358 TrbStart->TrbCtrStatus.DIR = 0;
359 }
360 //
361 // Update the cycle bit
362 //
363 TrbStart->TrbCtrStatus.CycleBit = EPRing->RingPCS & BIT0;
364 //
365 // Update the enqueue pointer
366 //
367 XhcPeiSyncTrsRing (Xhc, EPRing);
368 Urb->TrbNum++;
369 Urb->TrbEnd = (TRB_TEMPLATE *) (UINTN) TrbStart;
370
371 break;
372
373 case ED_BULK_OUT:
374 case ED_BULK_IN:
375 TotalLen = 0;
376 Len = 0;
377 TrbNum = 0;
378 TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;
379 while (TotalLen < Urb->DataLen) {
380 if ((TotalLen + 0x10000) >= Urb->DataLen) {
381 Len = Urb->DataLen - TotalLen;
382 } else {
383 Len = 0x10000;
384 }
385 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
386 TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
387 TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
388 TrbStart->TrbNormal.Length = (UINT32) Len;
389 TrbStart->TrbNormal.TDSize = 0;
390 TrbStart->TrbNormal.IntTarget = 0;
391 TrbStart->TrbNormal.ISP = 1;
392 TrbStart->TrbNormal.IOC = 1;
393 TrbStart->TrbNormal.Type = TRB_TYPE_NORMAL;
394 //
395 // Update the cycle bit
396 //
397 TrbStart->TrbNormal.CycleBit = EPRing->RingPCS & BIT0;
398
399 XhcPeiSyncTrsRing (Xhc, EPRing);
400 TrbNum++;
401 TotalLen += Len;
402 }
403
404 Urb->TrbNum = TrbNum;
405 Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;
406 break;
407
408 case ED_INTERRUPT_OUT:
409 case ED_INTERRUPT_IN:
410 TotalLen = 0;
411 Len = 0;
412 TrbNum = 0;
413 TrbStart = (TRB *) (UINTN) EPRing->RingEnqueue;
414 while (TotalLen < Urb->DataLen) {
415 if ((TotalLen + 0x10000) >= Urb->DataLen) {
416 Len = Urb->DataLen - TotalLen;
417 } else {
418 Len = 0x10000;
419 }
420 TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
421 TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
422 TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
423 TrbStart->TrbNormal.Length = (UINT32) Len;
424 TrbStart->TrbNormal.TDSize = 0;
425 TrbStart->TrbNormal.IntTarget = 0;
426 TrbStart->TrbNormal.ISP = 1;
427 TrbStart->TrbNormal.IOC = 1;
428 TrbStart->TrbNormal.Type = TRB_TYPE_NORMAL;
429 //
430 // Update the cycle bit
431 //
432 TrbStart->TrbNormal.CycleBit = EPRing->RingPCS & BIT0;
433
434 XhcPeiSyncTrsRing (Xhc, EPRing);
435 TrbNum++;
436 TotalLen += Len;
437 }
438
439 Urb->TrbNum = TrbNum;
440 Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;
441 break;
442
443 default:
444 DEBUG ((EFI_D_INFO, "Not supported EPType 0x%x!\n",EPType));
445 ASSERT (FALSE);
446 break;
447 }
448
449 return EFI_SUCCESS;
450 }
451
452 /**
453 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted
454 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint
455 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is
456 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the
457 Stopped to the Running state.
458
459 @param Xhc The XHCI device.
460 @param Urb The urb which makes the endpoint halted.
461
462 @retval EFI_SUCCESS The recovery is successful.
463 @retval Others Failed to recovery halted endpoint.
464
465 **/
466 EFI_STATUS
467 XhcPeiRecoverHaltedEndpoint (
468 IN PEI_XHC_DEV *Xhc,
469 IN URB *Urb
470 )
471 {
472 EFI_STATUS Status;
473 UINT8 Dci;
474 UINT8 SlotId;
475
476 Status = EFI_SUCCESS;
477 SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
478 if (SlotId == 0) {
479 return EFI_DEVICE_ERROR;
480 }
481 Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8) (Urb->Ep.Direction));
482
483 DEBUG ((EFI_D_INFO, "XhcPeiRecoverHaltedEndpoint: Recovery Halted Slot = %x, Dci = %x\n", SlotId, Dci));
484
485 //
486 // 1) Send Reset endpoint command to transit from halt to stop state
487 //
488 Status = XhcPeiResetEndpoint (Xhc, SlotId, Dci);
489 if (EFI_ERROR(Status)) {
490 DEBUG ((EFI_D_ERROR, "XhcPeiRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
491 goto Done;
492 }
493
494 //
495 // 2) Set dequeue pointer
496 //
497 Status = XhcPeiSetTrDequeuePointer (Xhc, SlotId, Dci, Urb);
498 if (EFI_ERROR(Status)) {
499 DEBUG ((EFI_D_ERROR, "XhcPeiRecoverHaltedEndpoint: Set Dequeue Pointer Failed, Status = %r\n", Status));
500 goto Done;
501 }
502
503 //
504 // 3) Ring the doorbell to transit from stop to active
505 //
506 XhcPeiRingDoorBell (Xhc, SlotId, Dci);
507
508 Done:
509 return Status;
510 }
511
512 /**
513 System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer
514 Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to
515 the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running
516 state.
517
518 @param Xhc The XHCI device.
519 @param Urb The urb which doesn't get completed in a specified timeout range.
520
521 @retval EFI_SUCCESS The dequeuing of the TDs is successful.
522 @retval Others Failed to stop the endpoint and dequeue the TDs.
523
524 **/
525 EFI_STATUS
526 XhcPeiDequeueTrbFromEndpoint (
527 IN PEI_XHC_DEV *Xhc,
528 IN URB *Urb
529 )
530 {
531 EFI_STATUS Status;
532 UINT8 Dci;
533 UINT8 SlotId;
534
535 Status = EFI_SUCCESS;
536 SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
537 if (SlotId == 0) {
538 return EFI_DEVICE_ERROR;
539 }
540 Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8) (Urb->Ep.Direction));
541
542 DEBUG ((EFI_D_INFO, "XhcPeiDequeueTrbFromEndpoint: Stop Slot = %x, Dci = %x\n", SlotId, Dci));
543
544 //
545 // 1) Send Stop endpoint command to stop endpoint.
546 //
547 Status = XhcPeiStopEndpoint (Xhc, SlotId, Dci);
548 if (EFI_ERROR(Status)) {
549 DEBUG ((EFI_D_ERROR, "XhcPeiDequeueTrbFromEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
550 goto Done;
551 }
552
553 //
554 // 2) Set dequeue pointer
555 //
556 Status = XhcPeiSetTrDequeuePointer (Xhc, SlotId, Dci, Urb);
557 if (EFI_ERROR(Status)) {
558 DEBUG ((EFI_D_ERROR, "XhcPeiDequeueTrbFromEndpoint: Set Dequeue Pointer Failed, Status = %r\n", Status));
559 goto Done;
560 }
561
562 //
563 // 3) Ring the doorbell to transit from stop to active
564 //
565 XhcPeiRingDoorBell (Xhc, SlotId, Dci);
566
567 Done:
568 return Status;
569 }
570
571 /**
572 Check if the Trb is a transaction of the URB.
573
574 @param Trb The TRB to be checked
575 @param Urb The transfer ring to be checked.
576
577 @retval TRUE It is a transaction of the URB.
578 @retval FALSE It is not any transaction of the URB.
579
580 **/
581 BOOLEAN
582 XhcPeiIsTransferRingTrb (
583 IN TRB_TEMPLATE *Trb,
584 IN URB *Urb
585 )
586 {
587 TRB_TEMPLATE *CheckedTrb;
588 UINTN Index;
589
590 CheckedTrb = Urb->Ring->RingSeg0;
591
592 ASSERT (Urb->Ring->TrbNumber == CMD_RING_TRB_NUMBER || Urb->Ring->TrbNumber == TR_RING_TRB_NUMBER);
593
594 for (Index = 0; Index < Urb->Ring->TrbNumber; Index++) {
595 if (Trb == CheckedTrb) {
596 return TRUE;
597 }
598 CheckedTrb++;
599 }
600
601 return FALSE;
602 }
603
604 /**
605 Check the URB's execution result and update the URB's
606 result accordingly.
607
608 @param Xhc The XHCI device.
609 @param Urb The URB to check result.
610
611 @return Whether the result of URB transfer is finialized.
612
613 **/
614 BOOLEAN
615 XhcPeiCheckUrbResult (
616 IN PEI_XHC_DEV *Xhc,
617 IN URB *Urb
618 )
619 {
620 EVT_TRB_TRANSFER *EvtTrb;
621 TRB_TEMPLATE *TRBPtr;
622 UINTN Index;
623 UINT8 TRBType;
624 EFI_STATUS Status;
625 URB *CheckedUrb;
626 UINT64 XhcDequeue;
627 UINT32 High;
628 UINT32 Low;
629 EFI_PHYSICAL_ADDRESS PhyAddr;
630
631 ASSERT ((Xhc != NULL) && (Urb != NULL));
632
633 Status = EFI_SUCCESS;
634
635 if (Urb->Finished) {
636 goto EXIT;
637 }
638
639 EvtTrb = NULL;
640
641 if (XhcPeiIsHalt (Xhc) || XhcPeiIsSysError (Xhc)) {
642 Urb->Result |= EFI_USB_ERR_SYSTEM;
643 goto EXIT;
644 }
645
646 //
647 // Traverse the event ring to find out all new events from the previous check.
648 //
649 XhcPeiSyncEventRing (Xhc, &Xhc->EventRing);
650 for (Index = 0; Index < Xhc->EventRing.TrbNumber; Index++) {
651 Status = XhcPeiCheckNewEvent (Xhc, &Xhc->EventRing, ((TRB_TEMPLATE **) &EvtTrb));
652 if (Status == EFI_NOT_READY) {
653 //
654 // All new events are handled, return directly.
655 //
656 goto EXIT;
657 }
658
659 //
660 // Only handle COMMAND_COMPLETETION_EVENT and TRANSFER_EVENT.
661 //
662 if ((EvtTrb->Type != TRB_TYPE_COMMAND_COMPLT_EVENT) && (EvtTrb->Type != TRB_TYPE_TRANS_EVENT)) {
663 continue;
664 }
665
666 //
667 // Need convert pci device address to host address
668 //
669 PhyAddr = (EFI_PHYSICAL_ADDRESS) (EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));
670 TRBPtr = (TRB_TEMPLATE *) (UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *) (UINTN) PhyAddr, sizeof (TRB_TEMPLATE));
671
672 //
673 // Update the status of Urb according to the finished event regardless of whether
674 // the urb is current checked one or in the XHCI's async transfer list.
675 // This way is used to avoid that those completed async transfer events don't get
676 // handled in time and are flushed by newer coming events.
677 //
678 if (XhcPeiIsTransferRingTrb (TRBPtr, Urb)) {
679 CheckedUrb = Urb;
680 } else {
681 continue;
682 }
683
684 switch (EvtTrb->Completecode) {
685 case TRB_COMPLETION_STALL_ERROR:
686 CheckedUrb->Result |= EFI_USB_ERR_STALL;
687 CheckedUrb->Finished = TRUE;
688 DEBUG ((EFI_D_ERROR, "XhcPeiCheckUrbResult: STALL_ERROR! Completecode = %x\n", EvtTrb->Completecode));
689 goto EXIT;
690
691 case TRB_COMPLETION_BABBLE_ERROR:
692 CheckedUrb->Result |= EFI_USB_ERR_BABBLE;
693 CheckedUrb->Finished = TRUE;
694 DEBUG ((EFI_D_ERROR, "XhcPeiCheckUrbResult: BABBLE_ERROR! Completecode = %x\n", EvtTrb->Completecode));
695 goto EXIT;
696
697 case TRB_COMPLETION_DATA_BUFFER_ERROR:
698 CheckedUrb->Result |= EFI_USB_ERR_BUFFER;
699 CheckedUrb->Finished = TRUE;
700 DEBUG ((EFI_D_ERROR, "XhcPeiCheckUrbResult: ERR_BUFFER! Completecode = %x\n", EvtTrb->Completecode));
701 goto EXIT;
702
703 case TRB_COMPLETION_USB_TRANSACTION_ERROR:
704 CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
705 CheckedUrb->Finished = TRUE;
706 DEBUG ((EFI_D_ERROR, "XhcPeiCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n", EvtTrb->Completecode));
707 goto EXIT;
708
709 case TRB_COMPLETION_SHORT_PACKET:
710 case TRB_COMPLETION_SUCCESS:
711 if (EvtTrb->Completecode == TRB_COMPLETION_SHORT_PACKET) {
712 DEBUG ((EFI_D_VERBOSE, "XhcPeiCheckUrbResult: short packet happens!\n"));
713 }
714
715 TRBType = (UINT8) (TRBPtr->Type);
716 if ((TRBType == TRB_TYPE_DATA_STAGE) ||
717 (TRBType == TRB_TYPE_NORMAL) ||
718 (TRBType == TRB_TYPE_ISOCH)) {
719 CheckedUrb->Completed += (((TRANSFER_TRB_NORMAL*)TRBPtr)->Length - EvtTrb->Length);
720 }
721
722 break;
723
724 default:
725 DEBUG ((EFI_D_ERROR, "XhcPeiCheckUrbResult: Transfer Default Error Occur! Completecode = 0x%x!\n", EvtTrb->Completecode));
726 CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;
727 CheckedUrb->Finished = TRUE;
728 goto EXIT;
729 }
730
731 //
732 // Only check first and end Trb event address
733 //
734 if (TRBPtr == CheckedUrb->TrbStart) {
735 CheckedUrb->StartDone = TRUE;
736 }
737
738 if (TRBPtr == CheckedUrb->TrbEnd) {
739 CheckedUrb->EndDone = TRUE;
740 }
741
742 if (CheckedUrb->StartDone && CheckedUrb->EndDone) {
743 CheckedUrb->Finished = TRUE;
744 CheckedUrb->EvtTrb = (TRB_TEMPLATE *) EvtTrb;
745 }
746 }
747
748 EXIT:
749
750 //
751 // Advance event ring to last available entry
752 //
753 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
754 // So divide it to two 32-bytes width register access.
755 //
756 Low = XhcPeiReadRuntimeReg (Xhc, XHC_ERDP_OFFSET);
757 High = XhcPeiReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);
758 XhcDequeue = (UINT64) (LShiftU64((UINT64) High, 32) | Low);
759
760 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE));
761
762 if ((XhcDequeue & (~0x0F)) != (PhyAddr & (~0x0F))) {
763 //
764 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
765 // So divide it to two 32-bytes width register access.
766 //
767 XhcPeiWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET, XHC_LOW_32BIT (PhyAddr) | BIT3);
768 XhcPeiWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4, XHC_HIGH_32BIT (PhyAddr));
769 }
770
771 return Urb->Finished;
772 }
773
774 /**
775 Execute the transfer by polling the URB. This is a synchronous operation.
776
777 @param Xhc The XHCI device.
778 @param CmdTransfer The executed URB is for cmd transfer or not.
779 @param Urb The URB to execute.
780 @param Timeout The time to wait before abort, in millisecond.
781
782 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
783 @return EFI_TIMEOUT The transfer failed due to time out.
784 @return EFI_SUCCESS The transfer finished OK.
785
786 **/
787 EFI_STATUS
788 XhcPeiExecTransfer (
789 IN PEI_XHC_DEV *Xhc,
790 IN BOOLEAN CmdTransfer,
791 IN URB *Urb,
792 IN UINTN Timeout
793 )
794 {
795 EFI_STATUS Status;
796 UINTN Index;
797 UINT64 Loop;
798 UINT8 SlotId;
799 UINT8 Dci;
800 BOOLEAN Finished;
801
802 if (CmdTransfer) {
803 SlotId = 0;
804 Dci = 0;
805 } else {
806 SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
807 if (SlotId == 0) {
808 return EFI_DEVICE_ERROR;
809 }
810 Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
811 }
812
813 Status = EFI_SUCCESS;
814 Loop = Timeout * XHC_1_MILLISECOND;
815 if (Timeout == 0) {
816 Loop = 0xFFFFFFFF;
817 }
818
819 XhcPeiRingDoorBell (Xhc, SlotId, Dci);
820
821 for (Index = 0; Index < Loop; Index++) {
822 Finished = XhcPeiCheckUrbResult (Xhc, Urb);
823 if (Finished) {
824 break;
825 }
826 MicroSecondDelay (XHC_1_MICROSECOND);
827 }
828
829 if (Index == Loop) {
830 Urb->Result = EFI_USB_ERR_TIMEOUT;
831 Status = EFI_TIMEOUT;
832 } else if (Urb->Result != EFI_USB_NOERROR) {
833 Status = EFI_DEVICE_ERROR;
834 }
835
836 return Status;
837 }
838
839 /**
840 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.
841
842 @param Xhc The XHCI device.
843 @param ParentRouteChart The route string pointed to the parent device if it exists.
844 @param Port The port to be polled.
845 @param PortState The port state.
846
847 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.
848 @retval Others Should not appear.
849
850 **/
851 EFI_STATUS
852 XhcPeiPollPortStatusChange (
853 IN PEI_XHC_DEV *Xhc,
854 IN USB_DEV_ROUTE ParentRouteChart,
855 IN UINT8 Port,
856 IN EFI_USB_PORT_STATUS *PortState
857 )
858 {
859 EFI_STATUS Status;
860 UINT8 Speed;
861 UINT8 SlotId;
862 USB_DEV_ROUTE RouteChart;
863
864 DEBUG ((EFI_D_INFO, "XhcPeiPollPortStatusChange: PortChangeStatus: %x PortStatus: %x\n", PortState->PortChangeStatus, PortState->PortStatus));
865
866 Status = EFI_SUCCESS;
867
868 if ((PortState->PortChangeStatus & (USB_PORT_STAT_C_CONNECTION | USB_PORT_STAT_C_ENABLE | USB_PORT_STAT_C_OVERCURRENT | USB_PORT_STAT_C_RESET)) == 0) {
869 return EFI_SUCCESS;
870 }
871
872 if (ParentRouteChart.Dword == 0) {
873 RouteChart.Route.RouteString = 0;
874 RouteChart.Route.RootPortNum = Port + 1;
875 RouteChart.Route.TierNum = 1;
876 } else {
877 if(Port < 14) {
878 RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (Port << (4 * (ParentRouteChart.Route.TierNum - 1)));
879 } else {
880 RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (15 << (4 * (ParentRouteChart.Route.TierNum - 1)));
881 }
882 RouteChart.Route.RootPortNum = ParentRouteChart.Route.RootPortNum;
883 RouteChart.Route.TierNum = ParentRouteChart.Route.TierNum + 1;
884 }
885
886 SlotId = XhcPeiRouteStringToSlotId (Xhc, RouteChart);
887 if (SlotId != 0) {
888 if (Xhc->HcCParams.Data.Csz == 0) {
889 Status = XhcPeiDisableSlotCmd (Xhc, SlotId);
890 } else {
891 Status = XhcPeiDisableSlotCmd64 (Xhc, SlotId);
892 }
893 }
894
895 if (((PortState->PortStatus & USB_PORT_STAT_ENABLE) != 0) &&
896 ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0)) {
897 //
898 // Has a device attached, Identify device speed after port is enabled.
899 //
900 Speed = EFI_USB_SPEED_FULL;
901 if ((PortState->PortStatus & USB_PORT_STAT_LOW_SPEED) != 0) {
902 Speed = EFI_USB_SPEED_LOW;
903 } else if ((PortState->PortStatus & USB_PORT_STAT_HIGH_SPEED) != 0) {
904 Speed = EFI_USB_SPEED_HIGH;
905 } else if ((PortState->PortStatus & USB_PORT_STAT_SUPER_SPEED) != 0) {
906 Speed = EFI_USB_SPEED_SUPER;
907 }
908 //
909 // Execute Enable_Slot cmd for attached device, initialize device context and assign device address.
910 //
911 SlotId = XhcPeiRouteStringToSlotId (Xhc, RouteChart);
912 if ((SlotId == 0) && ((PortState->PortChangeStatus & USB_PORT_STAT_C_RESET) != 0)) {
913 if (Xhc->HcCParams.Data.Csz == 0) {
914 Status = XhcPeiInitializeDeviceSlot (Xhc, ParentRouteChart, Port, RouteChart, Speed);
915 } else {
916 Status = XhcPeiInitializeDeviceSlot64 (Xhc, ParentRouteChart, Port, RouteChart, Speed);
917 }
918 }
919 }
920
921 return Status;
922 }
923
924 /**
925 Calculate the device context index by endpoint address and direction.
926
927 @param EpAddr The target endpoint number.
928 @param Direction The direction of the target endpoint.
929
930 @return The device context index of endpoint.
931
932 **/
933 UINT8
934 XhcPeiEndpointToDci (
935 IN UINT8 EpAddr,
936 IN EFI_USB_DATA_DIRECTION Direction
937 )
938 {
939 UINT8 Index;
940
941 ASSERT (EpAddr <= 15);
942
943 if (EpAddr == 0) {
944 return 1;
945 } else {
946 Index = (UINT8) (2 * EpAddr);
947 if (Direction == EfiUsbDataIn) {
948 Index += 1;
949 }
950 return Index;
951 }
952 }
953
954 /**
955 Find out the actual device address according to the requested device address from UsbBus.
956
957 @param Xhc The XHCI device.
958 @param BusDevAddr The requested device address by UsbBus upper driver.
959
960 @return The actual device address assigned to the device.
961
962 **/
963 UINT8
964 XhcPeiBusDevAddrToSlotId (
965 IN PEI_XHC_DEV *Xhc,
966 IN UINT8 BusDevAddr
967 )
968 {
969 UINT8 Index;
970
971 for (Index = 0; Index < 255; Index++) {
972 if (Xhc->UsbDevContext[Index + 1].Enabled &&
973 (Xhc->UsbDevContext[Index + 1].SlotId != 0) &&
974 (Xhc->UsbDevContext[Index + 1].BusDevAddr == BusDevAddr)) {
975 break;
976 }
977 }
978
979 if (Index == 255) {
980 return 0;
981 }
982
983 return Xhc->UsbDevContext[Index + 1].SlotId;
984 }
985
986 /**
987 Find out the slot id according to the device's route string.
988
989 @param Xhc The XHCI device.
990 @param RouteString The route string described the device location.
991
992 @return The slot id used by the device.
993
994 **/
995 UINT8
996 XhcPeiRouteStringToSlotId (
997 IN PEI_XHC_DEV *Xhc,
998 IN USB_DEV_ROUTE RouteString
999 )
1000 {
1001 UINT8 Index;
1002
1003 for (Index = 0; Index < 255; Index++) {
1004 if (Xhc->UsbDevContext[Index + 1].Enabled &&
1005 (Xhc->UsbDevContext[Index + 1].SlotId != 0) &&
1006 (Xhc->UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword)) {
1007 break;
1008 }
1009 }
1010
1011 if (Index == 255) {
1012 return 0;
1013 }
1014
1015 return Xhc->UsbDevContext[Index + 1].SlotId;
1016 }
1017
1018 /**
1019 Ring the door bell to notify XHCI there is a transaction to be executed.
1020
1021 @param Xhc The XHCI device.
1022 @param SlotId The slot id of the target device.
1023 @param Dci The device context index of the target slot or endpoint.
1024
1025 **/
1026 VOID
1027 XhcPeiRingDoorBell (
1028 IN PEI_XHC_DEV *Xhc,
1029 IN UINT8 SlotId,
1030 IN UINT8 Dci
1031 )
1032 {
1033 if (SlotId == 0) {
1034 XhcPeiWriteDoorBellReg (Xhc, 0, 0);
1035 } else {
1036 XhcPeiWriteDoorBellReg (Xhc, SlotId * sizeof (UINT32), Dci);
1037 }
1038 }
1039
1040 /**
1041 Assign and initialize the device slot for a new device.
1042
1043 @param Xhc The XHCI device.
1044 @param ParentRouteChart The route string pointed to the parent device.
1045 @param ParentPort The port at which the device is located.
1046 @param RouteChart The route string pointed to the device.
1047 @param DeviceSpeed The device speed.
1048
1049 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1050 @retval Others Fail to initialize device slot.
1051
1052 **/
1053 EFI_STATUS
1054 XhcPeiInitializeDeviceSlot (
1055 IN PEI_XHC_DEV *Xhc,
1056 IN USB_DEV_ROUTE ParentRouteChart,
1057 IN UINT16 ParentPort,
1058 IN USB_DEV_ROUTE RouteChart,
1059 IN UINT8 DeviceSpeed
1060 )
1061 {
1062 EFI_STATUS Status;
1063 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
1064 INPUT_CONTEXT *InputContext;
1065 DEVICE_CONTEXT *OutputContext;
1066 TRANSFER_RING *EndpointTransferRing;
1067 CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;
1068 UINT8 DeviceAddress;
1069 CMD_TRB_ENABLE_SLOT CmdTrb;
1070 UINT8 SlotId;
1071 UINT8 ParentSlotId;
1072 DEVICE_CONTEXT *ParentDeviceContext;
1073 EFI_PHYSICAL_ADDRESS PhyAddr;
1074
1075 ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));
1076 CmdTrb.CycleBit = 1;
1077 CmdTrb.Type = TRB_TYPE_EN_SLOT;
1078
1079 Status = XhcPeiCmdTransfer (
1080 Xhc,
1081 (TRB_TEMPLATE *) (UINTN) &CmdTrb,
1082 XHC_GENERIC_TIMEOUT,
1083 (TRB_TEMPLATE **) (UINTN) &EvtTrb
1084 );
1085 if (EFI_ERROR (Status)) {
1086 DEBUG ((EFI_D_ERROR, "XhcPeiInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status));
1087 return Status;
1088 }
1089 ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
1090 DEBUG ((EFI_D_INFO, "XhcPeiInitializeDeviceSlot: Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
1091 SlotId = (UINT8) EvtTrb->SlotId;
1092 ASSERT (SlotId != 0);
1093
1094 ZeroMem (&Xhc->UsbDevContext[SlotId], sizeof (USB_DEV_CONTEXT));
1095 Xhc->UsbDevContext[SlotId].Enabled = TRUE;
1096 Xhc->UsbDevContext[SlotId].SlotId = SlotId;
1097 Xhc->UsbDevContext[SlotId].RouteString.Dword = RouteChart.Dword;
1098 Xhc->UsbDevContext[SlotId].ParentRouteString.Dword = ParentRouteChart.Dword;
1099
1100 //
1101 // 4.3.3 Device Slot Initialization
1102 // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
1103 //
1104 InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT));
1105 ASSERT (InputContext != NULL);
1106 ASSERT (((UINTN) InputContext & 0x3F) == 0);
1107 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
1108
1109 Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;
1110
1111 //
1112 // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
1113 // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input
1114 // Context are affected by the command.
1115 //
1116 InputContext->InputControlContext.Dword2 |= (BIT0 | BIT1);
1117
1118 //
1119 // 3) Initialize the Input Slot Context data structure
1120 //
1121 InputContext->Slot.RouteString = RouteChart.Route.RouteString;
1122 InputContext->Slot.Speed = DeviceSpeed + 1;
1123 InputContext->Slot.ContextEntries = 1;
1124 InputContext->Slot.RootHubPortNum = RouteChart.Route.RootPortNum;
1125
1126 if (RouteChart.Route.RouteString != 0) {
1127 //
1128 // The device is behind of hub device.
1129 //
1130 ParentSlotId = XhcPeiRouteStringToSlotId (Xhc, ParentRouteChart);
1131 ASSERT (ParentSlotId != 0);
1132 //
1133 // If the Full/Low device attached to a High Speed Hub, init the TTPortNum and TTHubSlotId field of slot context
1134 //
1135 ParentDeviceContext = (DEVICE_CONTEXT *) Xhc->UsbDevContext[ParentSlotId].OutputContext;
1136 if ((ParentDeviceContext->Slot.TTPortNum == 0) &&
1137 (ParentDeviceContext->Slot.TTHubSlotId == 0)) {
1138 if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {
1139 //
1140 // Full/Low device attached to High speed hub port that isolates the high speed signaling
1141 // environment from Full/Low speed signaling environment for a device
1142 //
1143 InputContext->Slot.TTPortNum = ParentPort;
1144 InputContext->Slot.TTHubSlotId = ParentSlotId;
1145 }
1146 } else {
1147 //
1148 // Inherit the TT parameters from parent device.
1149 //
1150 InputContext->Slot.TTPortNum = ParentDeviceContext->Slot.TTPortNum;
1151 InputContext->Slot.TTHubSlotId = ParentDeviceContext->Slot.TTHubSlotId;
1152 //
1153 // If the device is a High speed device then down the speed to be the same as its parent Hub
1154 //
1155 if (DeviceSpeed == EFI_USB_SPEED_HIGH) {
1156 InputContext->Slot.Speed = ParentDeviceContext->Slot.Speed;
1157 }
1158 }
1159 }
1160
1161 //
1162 // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
1163 //
1164 EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
1165 Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;
1166 XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
1167 //
1168 // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
1169 //
1170 InputContext->EP[0].EPType = ED_CONTROL_BIDIR;
1171
1172 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
1173 InputContext->EP[0].MaxPacketSize = 512;
1174 } else if (DeviceSpeed == EFI_USB_SPEED_HIGH) {
1175 InputContext->EP[0].MaxPacketSize = 64;
1176 } else {
1177 InputContext->EP[0].MaxPacketSize = 8;
1178 }
1179 //
1180 // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
1181 // 1KB, and Bulk and Isoch endpoints 3KB.
1182 //
1183 InputContext->EP[0].AverageTRBLength = 8;
1184 InputContext->EP[0].MaxBurstSize = 0;
1185 InputContext->EP[0].Interval = 0;
1186 InputContext->EP[0].MaxPStreams = 0;
1187 InputContext->EP[0].Mult = 0;
1188 InputContext->EP[0].CErr = 3;
1189
1190 //
1191 // Init the DCS(dequeue cycle state) as the transfer ring's CCS
1192 //
1193 PhyAddr = UsbHcGetPciAddrForHostAddr (
1194 Xhc->MemPool,
1195 ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,
1196 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
1197 );
1198 InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;
1199 InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);
1200
1201 //
1202 // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
1203 //
1204 OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT));
1205 ASSERT (OutputContext != NULL);
1206 ASSERT (((UINTN) OutputContext & 0x3F) == 0);
1207 ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT));
1208
1209 Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;
1210 //
1211 // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
1212 // a pointer to the Output Device Context data structure (6.2.1).
1213 //
1214 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT));
1215 //
1216 // Fill DCBAA with PCI device address
1217 //
1218 Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;
1219
1220 //
1221 // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
1222 // Context data structure described above.
1223 //
1224 // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request
1225 // to device.
1226 //
1227 MicroSecondDelay (XHC_RESET_RECOVERY_DELAY);
1228 ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
1229 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
1230 CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
1231 CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);
1232 CmdTrbAddr.CycleBit = 1;
1233 CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;
1234 CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
1235 Status = XhcPeiCmdTransfer (
1236 Xhc,
1237 (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,
1238 XHC_GENERIC_TIMEOUT,
1239 (TRB_TEMPLATE **) (UINTN) &EvtTrb
1240 );
1241 if (!EFI_ERROR (Status)) {
1242 DeviceAddress = (UINT8) OutputContext->Slot.DeviceAddress;
1243 DEBUG ((EFI_D_INFO, "XhcPeiInitializeDeviceSlot: Address %d assigned successfully\n", DeviceAddress));
1244 Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
1245 }
1246
1247 DEBUG ((EFI_D_INFO, "XhcPeiInitializeDeviceSlot: Enable Slot, Status = %r\n", Status));
1248 return Status;
1249 }
1250
1251 /**
1252 Assign and initialize the device slot for a new device.
1253
1254 @param Xhc The XHCI device.
1255 @param ParentRouteChart The route string pointed to the parent device.
1256 @param ParentPort The port at which the device is located.
1257 @param RouteChart The route string pointed to the device.
1258 @param DeviceSpeed The device speed.
1259
1260 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1261 @retval Others Fail to initialize device slot.
1262
1263 **/
1264 EFI_STATUS
1265 XhcPeiInitializeDeviceSlot64 (
1266 IN PEI_XHC_DEV *Xhc,
1267 IN USB_DEV_ROUTE ParentRouteChart,
1268 IN UINT16 ParentPort,
1269 IN USB_DEV_ROUTE RouteChart,
1270 IN UINT8 DeviceSpeed
1271 )
1272 {
1273 EFI_STATUS Status;
1274 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
1275 INPUT_CONTEXT_64 *InputContext;
1276 DEVICE_CONTEXT_64 *OutputContext;
1277 TRANSFER_RING *EndpointTransferRing;
1278 CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;
1279 UINT8 DeviceAddress;
1280 CMD_TRB_ENABLE_SLOT CmdTrb;
1281 UINT8 SlotId;
1282 UINT8 ParentSlotId;
1283 DEVICE_CONTEXT_64 *ParentDeviceContext;
1284 EFI_PHYSICAL_ADDRESS PhyAddr;
1285
1286 ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));
1287 CmdTrb.CycleBit = 1;
1288 CmdTrb.Type = TRB_TYPE_EN_SLOT;
1289
1290 Status = XhcPeiCmdTransfer (
1291 Xhc,
1292 (TRB_TEMPLATE *) (UINTN) &CmdTrb,
1293 XHC_GENERIC_TIMEOUT,
1294 (TRB_TEMPLATE **) (UINTN) &EvtTrb
1295 );
1296 if (EFI_ERROR (Status)) {
1297 DEBUG ((EFI_D_ERROR, "XhcPeiInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status));
1298 return Status;
1299 }
1300 ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
1301 DEBUG ((EFI_D_INFO, "XhcPeiInitializeDeviceSlot64: Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
1302 SlotId = (UINT8)EvtTrb->SlotId;
1303 ASSERT (SlotId != 0);
1304
1305 ZeroMem (&Xhc->UsbDevContext[SlotId], sizeof (USB_DEV_CONTEXT));
1306 Xhc->UsbDevContext[SlotId].Enabled = TRUE;
1307 Xhc->UsbDevContext[SlotId].SlotId = SlotId;
1308 Xhc->UsbDevContext[SlotId].RouteString.Dword = RouteChart.Dword;
1309 Xhc->UsbDevContext[SlotId].ParentRouteString.Dword = ParentRouteChart.Dword;
1310
1311 //
1312 // 4.3.3 Device Slot Initialization
1313 // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
1314 //
1315 InputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (INPUT_CONTEXT_64));
1316 ASSERT (InputContext != NULL);
1317 ASSERT (((UINTN) InputContext & 0x3F) == 0);
1318 ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
1319
1320 Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;
1321
1322 //
1323 // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
1324 // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input
1325 // Context are affected by the command.
1326 //
1327 InputContext->InputControlContext.Dword2 |= (BIT0 | BIT1);
1328
1329 //
1330 // 3) Initialize the Input Slot Context data structure
1331 //
1332 InputContext->Slot.RouteString = RouteChart.Route.RouteString;
1333 InputContext->Slot.Speed = DeviceSpeed + 1;
1334 InputContext->Slot.ContextEntries = 1;
1335 InputContext->Slot.RootHubPortNum = RouteChart.Route.RootPortNum;
1336
1337 if (RouteChart.Route.RouteString != 0) {
1338 //
1339 // The device is behind of hub device.
1340 //
1341 ParentSlotId = XhcPeiRouteStringToSlotId (Xhc, ParentRouteChart);
1342 ASSERT (ParentSlotId != 0);
1343 //
1344 //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
1345 //
1346 ParentDeviceContext = (DEVICE_CONTEXT_64 *) Xhc->UsbDevContext[ParentSlotId].OutputContext;
1347 if ((ParentDeviceContext->Slot.TTPortNum == 0) &&
1348 (ParentDeviceContext->Slot.TTHubSlotId == 0)) {
1349 if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {
1350 //
1351 // Full/Low device attached to High speed hub port that isolates the high speed signaling
1352 // environment from Full/Low speed signaling environment for a device
1353 //
1354 InputContext->Slot.TTPortNum = ParentPort;
1355 InputContext->Slot.TTHubSlotId = ParentSlotId;
1356 }
1357 } else {
1358 //
1359 // Inherit the TT parameters from parent device.
1360 //
1361 InputContext->Slot.TTPortNum = ParentDeviceContext->Slot.TTPortNum;
1362 InputContext->Slot.TTHubSlotId = ParentDeviceContext->Slot.TTHubSlotId;
1363 //
1364 // If the device is a High speed device then down the speed to be the same as its parent Hub
1365 //
1366 if (DeviceSpeed == EFI_USB_SPEED_HIGH) {
1367 InputContext->Slot.Speed = ParentDeviceContext->Slot.Speed;
1368 }
1369 }
1370 }
1371
1372 //
1373 // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
1374 //
1375 EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
1376 Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;
1377 XhcPeiCreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);
1378 //
1379 // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
1380 //
1381 InputContext->EP[0].EPType = ED_CONTROL_BIDIR;
1382
1383 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
1384 InputContext->EP[0].MaxPacketSize = 512;
1385 } else if (DeviceSpeed == EFI_USB_SPEED_HIGH) {
1386 InputContext->EP[0].MaxPacketSize = 64;
1387 } else {
1388 InputContext->EP[0].MaxPacketSize = 8;
1389 }
1390 //
1391 // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
1392 // 1KB, and Bulk and Isoch endpoints 3KB.
1393 //
1394 InputContext->EP[0].AverageTRBLength = 8;
1395 InputContext->EP[0].MaxBurstSize = 0;
1396 InputContext->EP[0].Interval = 0;
1397 InputContext->EP[0].MaxPStreams = 0;
1398 InputContext->EP[0].Mult = 0;
1399 InputContext->EP[0].CErr = 3;
1400
1401 //
1402 // Init the DCS(dequeue cycle state) as the transfer ring's CCS
1403 //
1404 PhyAddr = UsbHcGetPciAddrForHostAddr (
1405 Xhc->MemPool,
1406 ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,
1407 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
1408 );
1409 InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;
1410 InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);
1411
1412 //
1413 // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
1414 //
1415 OutputContext = UsbHcAllocateMem (Xhc->MemPool, sizeof (DEVICE_CONTEXT_64));
1416 ASSERT (OutputContext != NULL);
1417 ASSERT (((UINTN) OutputContext & 0x3F) == 0);
1418 ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT_64));
1419
1420 Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;
1421 //
1422 // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
1423 // a pointer to the Output Device Context data structure (6.2.1).
1424 //
1425 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT_64));
1426 //
1427 // Fill DCBAA with PCI device address
1428 //
1429 Xhc->DCBAA[SlotId] = (UINT64) (UINTN) PhyAddr;
1430
1431 //
1432 // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
1433 // Context data structure described above.
1434 //
1435 // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request
1436 // to device.
1437 //
1438 MicroSecondDelay (XHC_RESET_RECOVERY_DELAY);
1439 ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
1440 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
1441 CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
1442 CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);
1443 CmdTrbAddr.CycleBit = 1;
1444 CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;
1445 CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
1446 Status = XhcPeiCmdTransfer (
1447 Xhc,
1448 (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,
1449 XHC_GENERIC_TIMEOUT,
1450 (TRB_TEMPLATE **) (UINTN) &EvtTrb
1451 );
1452 if (!EFI_ERROR (Status)) {
1453 DeviceAddress = (UINT8) OutputContext->Slot.DeviceAddress;
1454 DEBUG ((EFI_D_INFO, "XhcPeiInitializeDeviceSlot64: Address %d assigned successfully\n", DeviceAddress));
1455 Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
1456 }
1457
1458 DEBUG ((EFI_D_INFO, "XhcPeiInitializeDeviceSlot64: Enable Slot, Status = %r\n", Status));
1459 return Status;
1460 }
1461
1462
1463 /**
1464 Disable the specified device slot.
1465
1466 @param Xhc The XHCI device.
1467 @param SlotId The slot id to be disabled.
1468
1469 @retval EFI_SUCCESS Successfully disable the device slot.
1470
1471 **/
1472 EFI_STATUS
1473 XhcPeiDisableSlotCmd (
1474 IN PEI_XHC_DEV *Xhc,
1475 IN UINT8 SlotId
1476 )
1477 {
1478 EFI_STATUS Status;
1479 TRB_TEMPLATE *EvtTrb;
1480 CMD_TRB_DISABLE_SLOT CmdTrbDisSlot;
1481 UINT8 Index;
1482 VOID *RingSeg;
1483
1484 //
1485 // Disable the device slots occupied by these devices on its downstream ports.
1486 // Entry 0 is reserved.
1487 //
1488 for (Index = 0; Index < 255; Index++) {
1489 if (!Xhc->UsbDevContext[Index + 1].Enabled ||
1490 (Xhc->UsbDevContext[Index + 1].SlotId == 0) ||
1491 (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {
1492 continue;
1493 }
1494
1495 Status = XhcPeiDisableSlotCmd (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
1496
1497 if (EFI_ERROR (Status)) {
1498 DEBUG ((EFI_D_ERROR, "XhcPeiDisableSlotCmd: failed to disable child, ignore error\n"));
1499 Xhc->UsbDevContext[Index + 1].SlotId = 0;
1500 }
1501 }
1502
1503 //
1504 // Construct the disable slot command
1505 //
1506 DEBUG ((EFI_D_INFO, "XhcPeiDisableSlotCmd: Disable device slot %d!\n", SlotId));
1507
1508 ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));
1509 CmdTrbDisSlot.CycleBit = 1;
1510 CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;
1511 CmdTrbDisSlot.SlotId = SlotId;
1512 Status = XhcPeiCmdTransfer (
1513 Xhc,
1514 (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,
1515 XHC_GENERIC_TIMEOUT,
1516 (TRB_TEMPLATE **) (UINTN) &EvtTrb
1517 );
1518 if (EFI_ERROR (Status)) {
1519 DEBUG ((EFI_D_ERROR, "XhcPeiDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status));
1520 return Status;
1521 }
1522 //
1523 // Free the slot's device context entry
1524 //
1525 Xhc->DCBAA[SlotId] = 0;
1526
1527 //
1528 // Free the slot related data structure
1529 //
1530 for (Index = 0; Index < 31; Index++) {
1531 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {
1532 RingSeg = ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;
1533 if (RingSeg != NULL) {
1534 UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
1535 }
1536 FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
1537 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;
1538 }
1539 }
1540
1541 for (Index = 0; Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {
1542 if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] != NULL) {
1543 FreePool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]);
1544 }
1545 }
1546
1547 if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {
1548 UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
1549 }
1550
1551 if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {
1552 UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT));
1553 }
1554 //
1555 // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
1556 // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
1557 // remove urb from XHCI's asynchronous transfer list.
1558 //
1559 Xhc->UsbDevContext[SlotId].Enabled = FALSE;
1560 Xhc->UsbDevContext[SlotId].SlotId = 0;
1561
1562 DEBUG ((EFI_D_INFO, "XhcPeiDisableSlotCmd: Disable Slot Command, Status = %r\n", Status));
1563 return Status;
1564 }
1565
1566 /**
1567 Disable the specified device slot.
1568
1569 @param Xhc The XHCI device.
1570 @param SlotId The slot id to be disabled.
1571
1572 @retval EFI_SUCCESS Successfully disable the device slot.
1573
1574 **/
1575 EFI_STATUS
1576 XhcPeiDisableSlotCmd64 (
1577 IN PEI_XHC_DEV *Xhc,
1578 IN UINT8 SlotId
1579 )
1580 {
1581 EFI_STATUS Status;
1582 TRB_TEMPLATE *EvtTrb;
1583 CMD_TRB_DISABLE_SLOT CmdTrbDisSlot;
1584 UINT8 Index;
1585 VOID *RingSeg;
1586
1587 //
1588 // Disable the device slots occupied by these devices on its downstream ports.
1589 // Entry 0 is reserved.
1590 //
1591 for (Index = 0; Index < 255; Index++) {
1592 if (!Xhc->UsbDevContext[Index + 1].Enabled ||
1593 (Xhc->UsbDevContext[Index + 1].SlotId == 0) ||
1594 (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {
1595 continue;
1596 }
1597
1598 Status = XhcPeiDisableSlotCmd64 (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);
1599
1600 if (EFI_ERROR (Status)) {
1601 DEBUG ((EFI_D_ERROR, "XhcPeiDisableSlotCmd64: failed to disable child, ignore error\n"));
1602 Xhc->UsbDevContext[Index + 1].SlotId = 0;
1603 }
1604 }
1605
1606 //
1607 // Construct the disable slot command
1608 //
1609 DEBUG ((EFI_D_INFO, "XhcPeiDisableSlotCmd64: Disable device slot %d!\n", SlotId));
1610
1611 ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));
1612 CmdTrbDisSlot.CycleBit = 1;
1613 CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;
1614 CmdTrbDisSlot.SlotId = SlotId;
1615 Status = XhcPeiCmdTransfer (
1616 Xhc,
1617 (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,
1618 XHC_GENERIC_TIMEOUT,
1619 (TRB_TEMPLATE **) (UINTN) &EvtTrb
1620 );
1621 if (EFI_ERROR (Status)) {
1622 DEBUG ((EFI_D_ERROR, "XhcPeiDisableSlotCmd64: Disable Slot Command Failed, Status = %r\n", Status));
1623 return Status;
1624 }
1625 //
1626 // Free the slot's device context entry
1627 //
1628 Xhc->DCBAA[SlotId] = 0;
1629
1630 //
1631 // Free the slot related data structure
1632 //
1633 for (Index = 0; Index < 31; Index++) {
1634 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {
1635 RingSeg = ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;
1636 if (RingSeg != NULL) {
1637 UsbHcFreeMem (Xhc->MemPool, RingSeg, sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER);
1638 }
1639 FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);
1640 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] = NULL;
1641 }
1642 }
1643
1644 for (Index = 0; Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {
1645 if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] != NULL) {
1646 FreePool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]);
1647 }
1648 }
1649
1650 if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {
1651 UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
1652 }
1653
1654 if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {
1655 UsbHcFreeMem (Xhc->MemPool, Xhc->UsbDevContext[SlotId].OutputContext, sizeof (DEVICE_CONTEXT_64));
1656 }
1657 //
1658 // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
1659 // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
1660 // remove urb from XHCI's asynchronous transfer list.
1661 //
1662 Xhc->UsbDevContext[SlotId].Enabled = FALSE;
1663 Xhc->UsbDevContext[SlotId].SlotId = 0;
1664
1665 DEBUG ((EFI_D_INFO, "XhcPeiDisableSlotCmd64: Disable Slot Command, Status = %r\n", Status));
1666 return Status;
1667 }
1668
1669 /**
1670 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
1671
1672 @param Xhc The XHCI device.
1673 @param SlotId The slot id to be configured.
1674 @param DeviceSpeed The device's speed.
1675 @param ConfigDesc The pointer to the usb device configuration descriptor.
1676
1677 @retval EFI_SUCCESS Successfully configure all the device endpoints.
1678
1679 **/
1680 EFI_STATUS
1681 XhcPeiSetConfigCmd (
1682 IN PEI_XHC_DEV *Xhc,
1683 IN UINT8 SlotId,
1684 IN UINT8 DeviceSpeed,
1685 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
1686 )
1687 {
1688 EFI_STATUS Status;
1689 USB_INTERFACE_DESCRIPTOR *IfDesc;
1690 USB_ENDPOINT_DESCRIPTOR *EpDesc;
1691 UINT8 Index;
1692 UINTN NumEp;
1693 UINTN EpIndex;
1694 UINT8 EpAddr;
1695 EFI_USB_DATA_DIRECTION Direction;
1696 UINT8 Dci;
1697 UINT8 MaxDci;
1698 EFI_PHYSICAL_ADDRESS PhyAddr;
1699 UINT8 Interval;
1700
1701 TRANSFER_RING *EndpointTransferRing;
1702 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
1703 INPUT_CONTEXT *InputContext;
1704 DEVICE_CONTEXT *OutputContext;
1705 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
1706 //
1707 // 4.6.6 Configure Endpoint
1708 //
1709 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
1710 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
1711 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
1712 CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT));
1713
1714 ASSERT (ConfigDesc != NULL);
1715
1716 MaxDci = 0;
1717
1718 IfDesc = (USB_INTERFACE_DESCRIPTOR *) (ConfigDesc + 1);
1719 for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {
1720 while ((IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) || (IfDesc->AlternateSetting != 0)) {
1721 IfDesc = (USB_INTERFACE_DESCRIPTOR *) ((UINTN) IfDesc + IfDesc->Length);
1722 }
1723
1724 NumEp = IfDesc->NumEndpoints;
1725
1726 EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDesc + 1);
1727 for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
1728 while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
1729 EpDesc = (USB_ENDPOINT_DESCRIPTOR *) ((UINTN) EpDesc + EpDesc->Length);
1730 }
1731
1732 EpAddr = (UINT8) (EpDesc->EndpointAddress & 0x0F);
1733 Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
1734
1735 Dci = XhcPeiEndpointToDci (EpAddr, Direction);
1736 if (Dci > MaxDci) {
1737 MaxDci = Dci;
1738 }
1739
1740 InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);
1741 InputContext->EP[Dci-1].MaxPacketSize = EpDesc->MaxPacketSize;
1742
1743 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
1744 //
1745 // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
1746 //
1747 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
1748 } else {
1749 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
1750 }
1751
1752 switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {
1753 case USB_ENDPOINT_BULK:
1754 if (Direction == EfiUsbDataIn) {
1755 InputContext->EP[Dci-1].CErr = 3;
1756 InputContext->EP[Dci-1].EPType = ED_BULK_IN;
1757 } else {
1758 InputContext->EP[Dci-1].CErr = 3;
1759 InputContext->EP[Dci-1].EPType = ED_BULK_OUT;
1760 }
1761
1762 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
1763 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
1764 EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
1765 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
1766 XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
1767 }
1768
1769 break;
1770 case USB_ENDPOINT_ISO:
1771 if (Direction == EfiUsbDataIn) {
1772 InputContext->EP[Dci-1].CErr = 0;
1773 InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;
1774 } else {
1775 InputContext->EP[Dci-1].CErr = 0;
1776 InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
1777 }
1778 //
1779 // Get the bInterval from descriptor and init the the interval field of endpoint context.
1780 // Refer to XHCI 1.1 spec section 6.2.3.6.
1781 //
1782 if (DeviceSpeed == EFI_USB_SPEED_FULL) {
1783 Interval = EpDesc->Interval;
1784 ASSERT (Interval >= 1 && Interval <= 16);
1785 InputContext->EP[Dci-1].Interval = Interval + 2;
1786 } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
1787 Interval = EpDesc->Interval;
1788 ASSERT (Interval >= 1 && Interval <= 16);
1789 InputContext->EP[Dci-1].Interval = Interval - 1;
1790 }
1791
1792 //
1793 // Do not support isochronous transfer now.
1794 //
1795 DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
1796 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
1797 continue;
1798 case USB_ENDPOINT_INTERRUPT:
1799 if (Direction == EfiUsbDataIn) {
1800 InputContext->EP[Dci-1].CErr = 3;
1801 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;
1802 } else {
1803 InputContext->EP[Dci-1].CErr = 3;
1804 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
1805 }
1806 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
1807 InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;
1808 //
1809 // Get the bInterval from descriptor and init the interval field of endpoint context
1810 //
1811 if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {
1812 Interval = EpDesc->Interval;
1813 //
1814 // Calculate through the bInterval field of Endpoint descriptor.
1815 //
1816 ASSERT (Interval != 0);
1817 InputContext->EP[Dci-1].Interval = (UINT32) HighBitSet32 ((UINT32) Interval) + 3;
1818 } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
1819 Interval = EpDesc->Interval;
1820 ASSERT (Interval >= 1 && Interval <= 16);
1821 //
1822 // Refer to XHCI 1.0 spec section 6.2.3.6, table 61
1823 //
1824 InputContext->EP[Dci-1].Interval = Interval - 1;
1825 }
1826
1827 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
1828 EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
1829 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
1830 XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
1831 }
1832 break;
1833
1834 case USB_ENDPOINT_CONTROL:
1835 //
1836 // Do not support control transfer now.
1837 //
1838 DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd: Unsupport Control EP found, Transfer ring is not allocated.\n"));
1839 default:
1840 DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd: Unknown EP found, Transfer ring is not allocated.\n"));
1841 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
1842 continue;
1843 }
1844
1845 PhyAddr = UsbHcGetPciAddrForHostAddr (
1846 Xhc->MemPool,
1847 ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
1848 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
1849 );
1850 PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
1851 PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
1852 InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
1853 InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
1854
1855 EpDesc = (USB_ENDPOINT_DESCRIPTOR *) ((UINTN) EpDesc + EpDesc->Length);
1856 }
1857 IfDesc = (USB_INTERFACE_DESCRIPTOR *) ((UINTN) IfDesc + IfDesc->Length);
1858 }
1859
1860 InputContext->InputControlContext.Dword2 |= BIT0;
1861 InputContext->Slot.ContextEntries = MaxDci;
1862 //
1863 // configure endpoint
1864 //
1865 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
1866 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
1867 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
1868 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
1869 CmdTrbCfgEP.CycleBit = 1;
1870 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
1871 CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
1872 DEBUG ((EFI_D_INFO, "XhcSetConfigCmd: Configure Endpoint\n"));
1873 Status = XhcPeiCmdTransfer (
1874 Xhc,
1875 (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
1876 XHC_GENERIC_TIMEOUT,
1877 (TRB_TEMPLATE **) (UINTN) &EvtTrb
1878 );
1879 if (EFI_ERROR (Status)) {
1880 DEBUG ((EFI_D_ERROR, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status));
1881 }
1882 return Status;
1883 }
1884
1885 /**
1886 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
1887
1888 @param Xhc The XHCI device.
1889 @param SlotId The slot id to be configured.
1890 @param DeviceSpeed The device's speed.
1891 @param ConfigDesc The pointer to the usb device configuration descriptor.
1892
1893 @retval EFI_SUCCESS Successfully configure all the device endpoints.
1894
1895 **/
1896 EFI_STATUS
1897 XhcPeiSetConfigCmd64 (
1898 IN PEI_XHC_DEV *Xhc,
1899 IN UINT8 SlotId,
1900 IN UINT8 DeviceSpeed,
1901 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
1902 )
1903 {
1904 EFI_STATUS Status;
1905 USB_INTERFACE_DESCRIPTOR *IfDesc;
1906 USB_ENDPOINT_DESCRIPTOR *EpDesc;
1907 UINT8 Index;
1908 UINTN NumEp;
1909 UINTN EpIndex;
1910 UINT8 EpAddr;
1911 EFI_USB_DATA_DIRECTION Direction;
1912 UINT8 Dci;
1913 UINT8 MaxDci;
1914 EFI_PHYSICAL_ADDRESS PhyAddr;
1915 UINT8 Interval;
1916
1917 TRANSFER_RING *EndpointTransferRing;
1918 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
1919 INPUT_CONTEXT_64 *InputContext;
1920 DEVICE_CONTEXT_64 *OutputContext;
1921 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
1922 //
1923 // 4.6.6 Configure Endpoint
1924 //
1925 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
1926 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
1927 ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
1928 CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT_64));
1929
1930 ASSERT (ConfigDesc != NULL);
1931
1932 MaxDci = 0;
1933
1934 IfDesc = (USB_INTERFACE_DESCRIPTOR *) (ConfigDesc + 1);
1935 for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {
1936 while ((IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) || (IfDesc->AlternateSetting != 0)) {
1937 IfDesc = (USB_INTERFACE_DESCRIPTOR *) ((UINTN) IfDesc + IfDesc->Length);
1938 }
1939
1940 NumEp = IfDesc->NumEndpoints;
1941
1942 EpDesc = (USB_ENDPOINT_DESCRIPTOR *) (IfDesc + 1);
1943 for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
1944 while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
1945 EpDesc = (USB_ENDPOINT_DESCRIPTOR *) ((UINTN) EpDesc + EpDesc->Length);
1946 }
1947
1948 EpAddr = (UINT8) (EpDesc->EndpointAddress & 0x0F);
1949 Direction = (UINT8) ((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
1950
1951 Dci = XhcPeiEndpointToDci (EpAddr, Direction);
1952 ASSERT (Dci < 32);
1953 if (Dci > MaxDci) {
1954 MaxDci = Dci;
1955 }
1956
1957 InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);
1958 InputContext->EP[Dci-1].MaxPacketSize = EpDesc->MaxPacketSize;
1959
1960 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
1961 //
1962 // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
1963 //
1964 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
1965 } else {
1966 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
1967 }
1968
1969 switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {
1970 case USB_ENDPOINT_BULK:
1971 if (Direction == EfiUsbDataIn) {
1972 InputContext->EP[Dci-1].CErr = 3;
1973 InputContext->EP[Dci-1].EPType = ED_BULK_IN;
1974 } else {
1975 InputContext->EP[Dci-1].CErr = 3;
1976 InputContext->EP[Dci-1].EPType = ED_BULK_OUT;
1977 }
1978
1979 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
1980 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
1981 EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
1982 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
1983 XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
1984 }
1985
1986 break;
1987 case USB_ENDPOINT_ISO:
1988 if (Direction == EfiUsbDataIn) {
1989 InputContext->EP[Dci-1].CErr = 0;
1990 InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;
1991 } else {
1992 InputContext->EP[Dci-1].CErr = 0;
1993 InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
1994 }
1995 //
1996 // Get the bInterval from descriptor and init the the interval field of endpoint context.
1997 // Refer to XHCI 1.1 spec section 6.2.3.6.
1998 //
1999 if (DeviceSpeed == EFI_USB_SPEED_FULL) {
2000 Interval = EpDesc->Interval;
2001 ASSERT (Interval >= 1 && Interval <= 16);
2002 InputContext->EP[Dci-1].Interval = Interval + 2;
2003 } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
2004 Interval = EpDesc->Interval;
2005 ASSERT (Interval >= 1 && Interval <= 16);
2006 InputContext->EP[Dci-1].Interval = Interval - 1;
2007 }
2008
2009 //
2010 // Do not support isochronous transfer now.
2011 //
2012 DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
2013 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2014 continue;
2015 case USB_ENDPOINT_INTERRUPT:
2016 if (Direction == EfiUsbDataIn) {
2017 InputContext->EP[Dci-1].CErr = 3;
2018 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;
2019 } else {
2020 InputContext->EP[Dci-1].CErr = 3;
2021 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
2022 }
2023 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2024 InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;
2025 //
2026 // Get the bInterval from descriptor and init the the interval field of endpoint context
2027 //
2028 if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {
2029 Interval = EpDesc->Interval;
2030 //
2031 // Calculate through the bInterval field of Endpoint descriptor.
2032 //
2033 ASSERT (Interval != 0);
2034 InputContext->EP[Dci-1].Interval = (UINT32) HighBitSet32( (UINT32) Interval) + 3;
2035 } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
2036 Interval = EpDesc->Interval;
2037 ASSERT (Interval >= 1 && Interval <= 16);
2038 //
2039 // Refer to XHCI 1.0 spec section 6.2.3.6, table 61
2040 //
2041 InputContext->EP[Dci-1].Interval = Interval - 1;
2042 }
2043
2044 if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
2045 EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));
2046 Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
2047 XhcPeiCreateTransferRing (Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
2048 }
2049 break;
2050
2051 case USB_ENDPOINT_CONTROL:
2052 //
2053 // Do not support control transfer now.
2054 //
2055 DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd64: Unsupport Control EP found, Transfer ring is not allocated.\n"));
2056 default:
2057 DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd64: Unknown EP found, Transfer ring is not allocated.\n"));
2058 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2059 continue;
2060 }
2061
2062 PhyAddr = UsbHcGetPciAddrForHostAddr (
2063 Xhc->MemPool,
2064 ((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
2065 sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
2066 );
2067
2068 PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
2069 PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *) (UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
2070
2071 InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
2072 InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
2073
2074 EpDesc = (USB_ENDPOINT_DESCRIPTOR *) ((UINTN)EpDesc + EpDesc->Length);
2075 }
2076 IfDesc = (USB_INTERFACE_DESCRIPTOR *) ((UINTN)IfDesc + IfDesc->Length);
2077 }
2078
2079 InputContext->InputControlContext.Dword2 |= BIT0;
2080 InputContext->Slot.ContextEntries = MaxDci;
2081 //
2082 // configure endpoint
2083 //
2084 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
2085 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
2086 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
2087 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
2088 CmdTrbCfgEP.CycleBit = 1;
2089 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
2090 CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
2091 DEBUG ((EFI_D_INFO, "XhcSetConfigCmd64: Configure Endpoint\n"));
2092 Status = XhcPeiCmdTransfer (
2093 Xhc,
2094 (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
2095 XHC_GENERIC_TIMEOUT,
2096 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2097 );
2098 if (EFI_ERROR (Status)) {
2099 DEBUG ((EFI_D_ERROR, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status));
2100 }
2101
2102 return Status;
2103 }
2104
2105
2106 /**
2107 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
2108
2109 @param Xhc The XHCI device.
2110 @param SlotId The slot id to be evaluated.
2111 @param MaxPacketSize The max packet size supported by the device control transfer.
2112
2113 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
2114
2115 **/
2116 EFI_STATUS
2117 XhcPeiEvaluateContext (
2118 IN PEI_XHC_DEV *Xhc,
2119 IN UINT8 SlotId,
2120 IN UINT32 MaxPacketSize
2121 )
2122 {
2123 EFI_STATUS Status;
2124 CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;
2125 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
2126 INPUT_CONTEXT *InputContext;
2127 EFI_PHYSICAL_ADDRESS PhyAddr;
2128
2129 ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
2130
2131 //
2132 // 4.6.7 Evaluate Context
2133 //
2134 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
2135 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
2136
2137 InputContext->InputControlContext.Dword2 |= BIT1;
2138 InputContext->EP[0].MaxPacketSize = MaxPacketSize;
2139
2140 ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
2141 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
2142 CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);
2143 CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);
2144 CmdTrbEvalu.CycleBit = 1;
2145 CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;
2146 CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
2147 DEBUG ((EFI_D_INFO, "XhcEvaluateContext: Evaluate context\n"));
2148 Status = XhcPeiCmdTransfer (
2149 Xhc,
2150 (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,
2151 XHC_GENERIC_TIMEOUT,
2152 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2153 );
2154 if (EFI_ERROR (Status)) {
2155 DEBUG ((EFI_D_ERROR, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status));
2156 }
2157 return Status;
2158 }
2159
2160 /**
2161 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
2162
2163 @param Xhc The XHCI device.
2164 @param SlotId The slot id to be evaluated.
2165 @param MaxPacketSize The max packet size supported by the device control transfer.
2166
2167 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
2168
2169 **/
2170 EFI_STATUS
2171 XhcPeiEvaluateContext64 (
2172 IN PEI_XHC_DEV *Xhc,
2173 IN UINT8 SlotId,
2174 IN UINT32 MaxPacketSize
2175 )
2176 {
2177 EFI_STATUS Status;
2178 CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;
2179 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
2180 INPUT_CONTEXT_64 *InputContext;
2181 EFI_PHYSICAL_ADDRESS PhyAddr;
2182
2183 ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
2184
2185 //
2186 // 4.6.7 Evaluate Context
2187 //
2188 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
2189 ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
2190
2191 InputContext->InputControlContext.Dword2 |= BIT1;
2192 InputContext->EP[0].MaxPacketSize = MaxPacketSize;
2193
2194 ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
2195 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
2196 CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);
2197 CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);
2198 CmdTrbEvalu.CycleBit = 1;
2199 CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;
2200 CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
2201 DEBUG ((EFI_D_INFO, "XhcEvaluateContext64: Evaluate context 64\n"));
2202 Status = XhcPeiCmdTransfer (
2203 Xhc,
2204 (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,
2205 XHC_GENERIC_TIMEOUT,
2206 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2207 );
2208 if (EFI_ERROR (Status)) {
2209 DEBUG ((EFI_D_ERROR, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status));
2210 }
2211 return Status;
2212 }
2213
2214 /**
2215 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
2216
2217 @param Xhc The XHCI device.
2218 @param SlotId The slot id to be configured.
2219 @param PortNum The total number of downstream port supported by the hub.
2220 @param TTT The TT think time of the hub device.
2221 @param MTT The multi-TT of the hub device.
2222
2223 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
2224
2225 **/
2226 EFI_STATUS
2227 XhcPeiConfigHubContext (
2228 IN PEI_XHC_DEV *Xhc,
2229 IN UINT8 SlotId,
2230 IN UINT8 PortNum,
2231 IN UINT8 TTT,
2232 IN UINT8 MTT
2233 )
2234 {
2235 EFI_STATUS Status;
2236 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
2237 INPUT_CONTEXT *InputContext;
2238 DEVICE_CONTEXT *OutputContext;
2239 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
2240 EFI_PHYSICAL_ADDRESS PhyAddr;
2241
2242 ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
2243 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
2244 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
2245
2246 //
2247 // 4.6.7 Evaluate Context
2248 //
2249 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
2250
2251 InputContext->InputControlContext.Dword2 |= BIT0;
2252
2253 //
2254 // Copy the slot context from OutputContext to Input context
2255 //
2256 CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT));
2257 InputContext->Slot.Hub = 1;
2258 InputContext->Slot.PortNum = PortNum;
2259 InputContext->Slot.TTT = TTT;
2260 InputContext->Slot.MTT = MTT;
2261
2262 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
2263 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
2264 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
2265 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
2266 CmdTrbCfgEP.CycleBit = 1;
2267 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
2268 CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
2269 DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));
2270 Status = XhcPeiCmdTransfer (
2271 Xhc,
2272 (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
2273 XHC_GENERIC_TIMEOUT,
2274 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2275 );
2276 if (EFI_ERROR (Status)) {
2277 DEBUG ((EFI_D_ERROR, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status));
2278 }
2279 return Status;
2280 }
2281
2282 /**
2283 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
2284
2285 @param Xhc The XHCI device.
2286 @param SlotId The slot id to be configured.
2287 @param PortNum The total number of downstream port supported by the hub.
2288 @param TTT The TT think time of the hub device.
2289 @param MTT The multi-TT of the hub device.
2290
2291 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
2292
2293 **/
2294 EFI_STATUS
2295 XhcPeiConfigHubContext64 (
2296 IN PEI_XHC_DEV *Xhc,
2297 IN UINT8 SlotId,
2298 IN UINT8 PortNum,
2299 IN UINT8 TTT,
2300 IN UINT8 MTT
2301 )
2302 {
2303 EFI_STATUS Status;
2304 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
2305 INPUT_CONTEXT_64 *InputContext;
2306 DEVICE_CONTEXT_64 *OutputContext;
2307 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;
2308 EFI_PHYSICAL_ADDRESS PhyAddr;
2309
2310 ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
2311 InputContext = Xhc->UsbDevContext[SlotId].InputContext;
2312 OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
2313
2314 //
2315 // 4.6.7 Evaluate Context
2316 //
2317 ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
2318
2319 InputContext->InputControlContext.Dword2 |= BIT0;
2320
2321 //
2322 // Copy the slot context from OutputContext to Input context
2323 //
2324 CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT_64));
2325 InputContext->Slot.Hub = 1;
2326 InputContext->Slot.PortNum = PortNum;
2327 InputContext->Slot.TTT = TTT;
2328 InputContext->Slot.MTT = MTT;
2329
2330 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
2331 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
2332 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
2333 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
2334 CmdTrbCfgEP.CycleBit = 1;
2335 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
2336 CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;
2337 DEBUG ((EFI_D_INFO, "Configure Hub Slot Context 64\n"));
2338 Status = XhcPeiCmdTransfer (
2339 Xhc,
2340 (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,
2341 XHC_GENERIC_TIMEOUT,
2342 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2343 );
2344 if (EFI_ERROR (Status)) {
2345 DEBUG ((EFI_D_ERROR, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status));
2346 }
2347 return Status;
2348 }
2349
2350 /**
2351 Stop endpoint through XHCI's Stop_Endpoint cmd.
2352
2353 @param Xhc The XHCI device.
2354 @param SlotId The slot id of the target device.
2355 @param Dci The device context index of the target slot or endpoint.
2356
2357 @retval EFI_SUCCESS Stop endpoint successfully.
2358 @retval Others Failed to stop endpoint.
2359
2360 **/
2361 EFI_STATUS
2362 EFIAPI
2363 XhcPeiStopEndpoint (
2364 IN PEI_XHC_DEV *Xhc,
2365 IN UINT8 SlotId,
2366 IN UINT8 Dci
2367 )
2368 {
2369 EFI_STATUS Status;
2370 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
2371 CMD_TRB_STOP_ENDPOINT CmdTrbStopED;
2372
2373 DEBUG ((EFI_D_INFO, "XhcPeiStopEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
2374
2375 //
2376 // Send stop endpoint command to transit Endpoint from running to stop state
2377 //
2378 ZeroMem (&CmdTrbStopED, sizeof (CmdTrbStopED));
2379 CmdTrbStopED.CycleBit = 1;
2380 CmdTrbStopED.Type = TRB_TYPE_STOP_ENDPOINT;
2381 CmdTrbStopED.EDID = Dci;
2382 CmdTrbStopED.SlotId = SlotId;
2383 Status = XhcPeiCmdTransfer (
2384 Xhc,
2385 (TRB_TEMPLATE *) (UINTN) &CmdTrbStopED,
2386 XHC_GENERIC_TIMEOUT,
2387 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2388 );
2389 if (EFI_ERROR(Status)) {
2390 DEBUG ((EFI_D_ERROR, "XhcPeiStopEndpoint: Stop Endpoint Failed, Status = %r\n", Status));
2391 }
2392
2393 return Status;
2394 }
2395
2396 /**
2397 Reset endpoint through XHCI's Reset_Endpoint cmd.
2398
2399 @param Xhc The XHCI device.
2400 @param SlotId The slot id of the target device.
2401 @param Dci The device context index of the target slot or endpoint.
2402
2403 @retval EFI_SUCCESS Reset endpoint successfully.
2404 @retval Others Failed to reset endpoint.
2405
2406 **/
2407 EFI_STATUS
2408 EFIAPI
2409 XhcPeiResetEndpoint (
2410 IN PEI_XHC_DEV *Xhc,
2411 IN UINT8 SlotId,
2412 IN UINT8 Dci
2413 )
2414 {
2415 EFI_STATUS Status;
2416 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
2417 CMD_TRB_RESET_ENDPOINT CmdTrbResetED;
2418
2419 DEBUG ((EFI_D_INFO, "XhcPeiResetEndpoint: Slot = 0x%x, Dci = 0x%x\n", SlotId, Dci));
2420
2421 //
2422 // Send stop endpoint command to transit Endpoint from running to stop state
2423 //
2424 ZeroMem (&CmdTrbResetED, sizeof (CmdTrbResetED));
2425 CmdTrbResetED.CycleBit = 1;
2426 CmdTrbResetED.Type = TRB_TYPE_RESET_ENDPOINT;
2427 CmdTrbResetED.EDID = Dci;
2428 CmdTrbResetED.SlotId = SlotId;
2429 Status = XhcPeiCmdTransfer (
2430 Xhc,
2431 (TRB_TEMPLATE *) (UINTN) &CmdTrbResetED,
2432 XHC_GENERIC_TIMEOUT,
2433 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2434 );
2435 if (EFI_ERROR(Status)) {
2436 DEBUG ((EFI_D_ERROR, "XhcPeiResetEndpoint: Reset Endpoint Failed, Status = %r\n", Status));
2437 }
2438
2439 return Status;
2440 }
2441
2442 /**
2443 Set transfer ring dequeue pointer through XHCI's Set_Tr_Dequeue_Pointer cmd.
2444
2445 @param Xhc The XHCI device.
2446 @param SlotId The slot id of the target device.
2447 @param Dci The device context index of the target slot or endpoint.
2448 @param Urb The dequeue pointer of the transfer ring specified
2449 by the urb to be updated.
2450
2451 @retval EFI_SUCCESS Set transfer ring dequeue pointer succeeds.
2452 @retval Others Failed to set transfer ring dequeue pointer.
2453
2454 **/
2455 EFI_STATUS
2456 EFIAPI
2457 XhcPeiSetTrDequeuePointer (
2458 IN PEI_XHC_DEV *Xhc,
2459 IN UINT8 SlotId,
2460 IN UINT8 Dci,
2461 IN URB *Urb
2462 )
2463 {
2464 EFI_STATUS Status;
2465 EVT_TRB_COMMAND_COMPLETION *EvtTrb;
2466 CMD_SET_TR_DEQ_POINTER CmdSetTRDeq;
2467 EFI_PHYSICAL_ADDRESS PhyAddr;
2468
2469 DEBUG ((EFI_D_INFO, "XhcPeiSetTrDequeuePointer: Slot = 0x%x, Dci = 0x%x, Urb = 0x%x\n", SlotId, Dci, Urb));
2470
2471 //
2472 // Send stop endpoint command to transit Endpoint from running to stop state
2473 //
2474 ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));
2475 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));
2476 CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS;
2477 CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (PhyAddr);
2478 CmdSetTRDeq.CycleBit = 1;
2479 CmdSetTRDeq.Type = TRB_TYPE_SET_TR_DEQUE;
2480 CmdSetTRDeq.Endpoint = Dci;
2481 CmdSetTRDeq.SlotId = SlotId;
2482 Status = XhcPeiCmdTransfer (
2483 Xhc,
2484 (TRB_TEMPLATE *) (UINTN) &CmdSetTRDeq,
2485 XHC_GENERIC_TIMEOUT,
2486 (TRB_TEMPLATE **) (UINTN) &EvtTrb
2487 );
2488 if (EFI_ERROR(Status)) {
2489 DEBUG ((EFI_D_ERROR, "XhcPeiSetTrDequeuePointer: Set TR Dequeue Pointer Failed, Status = %r\n", Status));
2490 }
2491
2492 return Status;
2493 }
2494
2495 /**
2496 Check if there is a new generated event.
2497
2498 @param Xhc The XHCI device.
2499 @param EvtRing The event ring to check.
2500 @param NewEvtTrb The new event TRB found.
2501
2502 @retval EFI_SUCCESS Found a new event TRB at the event ring.
2503 @retval EFI_NOT_READY The event ring has no new event.
2504
2505 **/
2506 EFI_STATUS
2507 XhcPeiCheckNewEvent (
2508 IN PEI_XHC_DEV *Xhc,
2509 IN EVENT_RING *EvtRing,
2510 OUT TRB_TEMPLATE **NewEvtTrb
2511 )
2512 {
2513 ASSERT (EvtRing != NULL);
2514
2515 *NewEvtTrb = EvtRing->EventRingDequeue;
2516
2517 if (EvtRing->EventRingDequeue == EvtRing->EventRingEnqueue) {
2518 return EFI_NOT_READY;
2519 }
2520
2521 EvtRing->EventRingDequeue++;
2522 //
2523 // If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.
2524 //
2525 if ((UINTN) EvtRing->EventRingDequeue >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
2526 EvtRing->EventRingDequeue = EvtRing->EventRingSeg0;
2527 }
2528
2529 return EFI_SUCCESS;
2530 }
2531
2532 /**
2533 Synchronize the specified event ring to update the enqueue and dequeue pointer.
2534
2535 @param Xhc The XHCI device.
2536 @param EvtRing The event ring to sync.
2537
2538 @retval EFI_SUCCESS The event ring is synchronized successfully.
2539
2540 **/
2541 EFI_STATUS
2542 XhcPeiSyncEventRing (
2543 IN PEI_XHC_DEV *Xhc,
2544 IN EVENT_RING *EvtRing
2545 )
2546 {
2547 UINTN Index;
2548 TRB_TEMPLATE *EvtTrb;
2549
2550 ASSERT (EvtRing != NULL);
2551
2552 //
2553 // Calculate the EventRingEnqueue and EventRingCCS.
2554 // Note: only support single Segment
2555 //
2556 EvtTrb = EvtRing->EventRingDequeue;
2557
2558 for (Index = 0; Index < EvtRing->TrbNumber; Index++) {
2559 if (EvtTrb->CycleBit != EvtRing->EventRingCCS) {
2560 break;
2561 }
2562
2563 EvtTrb++;
2564
2565 if ((UINTN) EvtTrb >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {
2566 EvtTrb = EvtRing->EventRingSeg0;
2567 EvtRing->EventRingCCS = (EvtRing->EventRingCCS) ? 0 : 1;
2568 }
2569 }
2570
2571 if (Index < EvtRing->TrbNumber) {
2572 EvtRing->EventRingEnqueue = EvtTrb;
2573 } else {
2574 ASSERT (FALSE);
2575 }
2576
2577 return EFI_SUCCESS;
2578 }
2579
2580 /**
2581 Free XHCI event ring.
2582
2583 @param Xhc The XHCI device.
2584 @param EventRing The event ring to be freed.
2585
2586 **/
2587 VOID
2588 XhcPeiFreeEventRing (
2589 IN PEI_XHC_DEV *Xhc,
2590 IN EVENT_RING *EventRing
2591 )
2592 {
2593 if(EventRing->EventRingSeg0 == NULL) {
2594 return;
2595 }
2596
2597 //
2598 // Free EventRing Segment 0
2599 //
2600 UsbHcFreeMem (Xhc->MemPool, EventRing->EventRingSeg0, sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER);
2601
2602 //
2603 // Free ERST table
2604 //
2605 UsbHcFreeMem (Xhc->MemPool, EventRing->ERSTBase, sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER);
2606 }
2607
2608 /**
2609 Create XHCI event ring.
2610
2611 @param Xhc The XHCI device.
2612 @param EventRing The created event ring.
2613
2614 **/
2615 VOID
2616 XhcPeiCreateEventRing (
2617 IN PEI_XHC_DEV *Xhc,
2618 OUT EVENT_RING *EventRing
2619 )
2620 {
2621 VOID *Buf;
2622 EVENT_RING_SEG_TABLE_ENTRY *ERSTBase;
2623 UINTN Size;
2624 EFI_PHYSICAL_ADDRESS ERSTPhy;
2625 EFI_PHYSICAL_ADDRESS DequeuePhy;
2626
2627 ASSERT (EventRing != NULL);
2628
2629 Size = sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER;
2630 Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
2631 ASSERT (Buf != NULL);
2632 ASSERT (((UINTN) Buf & 0x3F) == 0);
2633 ZeroMem (Buf, Size);
2634
2635 DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);
2636
2637 EventRing->EventRingSeg0 = Buf;
2638 EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;
2639 EventRing->EventRingDequeue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
2640 EventRing->EventRingEnqueue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;
2641
2642 //
2643 // Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'
2644 // and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.
2645 //
2646 EventRing->EventRingCCS = 1;
2647
2648 Size = sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER;
2649 Buf = UsbHcAllocateMem (Xhc->MemPool, Size);
2650 ASSERT (Buf != NULL);
2651 ASSERT (((UINTN) Buf & 0x3F) == 0);
2652 ZeroMem (Buf, Size);
2653
2654 ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *) Buf;
2655 EventRing->ERSTBase = ERSTBase;
2656 ERSTBase->PtrLo = XHC_LOW_32BIT (DequeuePhy);
2657 ERSTBase->PtrHi = XHC_HIGH_32BIT (DequeuePhy);
2658 ERSTBase->RingTrbSize = EVENT_RING_TRB_NUMBER;
2659
2660 ERSTPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);
2661
2662 //
2663 // Program the Interrupter Event Ring Segment Table Size (ERSTSZ) register (5.5.2.3.1)
2664 //
2665 XhcPeiWriteRuntimeReg (
2666 Xhc,
2667 XHC_ERSTSZ_OFFSET,
2668 ERST_NUMBER
2669 );
2670 //
2671 // Program the Interrupter Event Ring Dequeue Pointer (ERDP) register (5.5.2.3.3)
2672 //
2673 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
2674 // So divide it to two 32-bytes width register access.
2675 //
2676 XhcPeiWriteRuntimeReg (
2677 Xhc,
2678 XHC_ERDP_OFFSET,
2679 XHC_LOW_32BIT ((UINT64) (UINTN) DequeuePhy)
2680 );
2681 XhcPeiWriteRuntimeReg (
2682 Xhc,
2683 XHC_ERDP_OFFSET + 4,
2684 XHC_HIGH_32BIT ((UINT64) (UINTN) DequeuePhy)
2685 );
2686 //
2687 // Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register (5.5.2.3.2)
2688 //
2689 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
2690 // So divide it to two 32-bytes width register access.
2691 //
2692 XhcPeiWriteRuntimeReg (
2693 Xhc,
2694 XHC_ERSTBA_OFFSET,
2695 XHC_LOW_32BIT ((UINT64) (UINTN) ERSTPhy)
2696 );
2697 XhcPeiWriteRuntimeReg (
2698 Xhc,
2699 XHC_ERSTBA_OFFSET + 4,
2700 XHC_HIGH_32BIT ((UINT64) (UINTN) ERSTPhy)
2701 );
2702 //
2703 // Need set IMAN IE bit to enable the ring interrupt
2704 //
2705 XhcPeiSetRuntimeRegBit (Xhc, XHC_IMAN_OFFSET, XHC_IMAN_IE);
2706 }
2707
2708 /**
2709 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
2710
2711 @param Xhc The XHCI device.
2712 @param TrsRing The transfer ring to sync.
2713
2714 @retval EFI_SUCCESS The transfer ring is synchronized successfully.
2715
2716 **/
2717 EFI_STATUS
2718 XhcPeiSyncTrsRing (
2719 IN PEI_XHC_DEV *Xhc,
2720 IN TRANSFER_RING *TrsRing
2721 )
2722 {
2723 UINTN Index;
2724 TRB_TEMPLATE *TrsTrb;
2725
2726 ASSERT (TrsRing != NULL);
2727 //
2728 // Calculate the latest RingEnqueue and RingPCS
2729 //
2730 TrsTrb = TrsRing->RingEnqueue;
2731 ASSERT (TrsTrb != NULL);
2732
2733 for (Index = 0; Index < TrsRing->TrbNumber; Index++) {
2734 if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {
2735 break;
2736 }
2737 TrsTrb++;
2738 if ((UINT8) TrsTrb->Type == TRB_TYPE_LINK) {
2739 ASSERT (((LINK_TRB *) TrsTrb)->TC != 0);
2740 //
2741 // set cycle bit in Link TRB as normal
2742 //
2743 ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
2744 //
2745 // Toggle PCS maintained by software
2746 //
2747 TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1;
2748 TrsTrb = (TRB_TEMPLATE *) TrsRing->RingSeg0; // Use host address
2749 }
2750 }
2751
2752 ASSERT (Index != TrsRing->TrbNumber);
2753
2754 if (TrsTrb != TrsRing->RingEnqueue) {
2755 TrsRing->RingEnqueue = TrsTrb;
2756 }
2757
2758 //
2759 // Clear the Trb context for enqueue, but reserve the PCS bit
2760 //
2761 TrsTrb->Parameter1 = 0;
2762 TrsTrb->Parameter2 = 0;
2763 TrsTrb->Status = 0;
2764 TrsTrb->RsvdZ1 = 0;
2765 TrsTrb->Type = 0;
2766 TrsTrb->Control = 0;
2767
2768 return EFI_SUCCESS;
2769 }
2770
2771 /**
2772 Create XHCI transfer ring.
2773
2774 @param Xhc The XHCI Device.
2775 @param TrbNum The number of TRB in the ring.
2776 @param TransferRing The created transfer ring.
2777
2778 **/
2779 VOID
2780 XhcPeiCreateTransferRing (
2781 IN PEI_XHC_DEV *Xhc,
2782 IN UINTN TrbNum,
2783 OUT TRANSFER_RING *TransferRing
2784 )
2785 {
2786 VOID *Buf;
2787 LINK_TRB *EndTrb;
2788 EFI_PHYSICAL_ADDRESS PhyAddr;
2789
2790 Buf = UsbHcAllocateMem (Xhc->MemPool, sizeof (TRB_TEMPLATE) * TrbNum);
2791 ASSERT (Buf != NULL);
2792 ASSERT (((UINTN) Buf & 0x3F) == 0);
2793 ZeroMem (Buf, sizeof (TRB_TEMPLATE) * TrbNum);
2794
2795 TransferRing->RingSeg0 = Buf;
2796 TransferRing->TrbNumber = TrbNum;
2797 TransferRing->RingEnqueue = (TRB_TEMPLATE *) TransferRing->RingSeg0;
2798 TransferRing->RingDequeue = (TRB_TEMPLATE *) TransferRing->RingSeg0;
2799 TransferRing->RingPCS = 1;
2800 //
2801 // 4.9.2 Transfer Ring Management
2802 // To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to
2803 // point to the first TRB in the ring.
2804 //
2805 EndTrb = (LINK_TRB *) ((UINTN) Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));
2806 EndTrb->Type = TRB_TYPE_LINK;
2807 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);
2808 EndTrb->PtrLo = XHC_LOW_32BIT (PhyAddr);
2809 EndTrb->PtrHi = XHC_HIGH_32BIT (PhyAddr);
2810 //
2811 // Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
2812 //
2813 EndTrb->TC = 1;
2814 //
2815 // Set Cycle bit as other TRB PCS init value
2816 //
2817 EndTrb->CycleBit = 0;
2818 }
2819
2820 /**
2821 Initialize the XHCI host controller for schedule.
2822
2823 @param Xhc The XHCI device to be initialized.
2824
2825 **/
2826 VOID
2827 XhcPeiInitSched (
2828 IN PEI_XHC_DEV *Xhc
2829 )
2830 {
2831 VOID *Dcbaa;
2832 EFI_PHYSICAL_ADDRESS DcbaaPhy;
2833 UINTN Size;
2834 EFI_PHYSICAL_ADDRESS CmdRingPhy;
2835 UINT32 MaxScratchpadBufs;
2836 UINT64 *ScratchBuf;
2837 EFI_PHYSICAL_ADDRESS ScratchPhy;
2838 UINT64 *ScratchEntry;
2839 EFI_PHYSICAL_ADDRESS ScratchEntryPhy;
2840 UINT32 Index;
2841 UINTN *ScratchEntryMap;
2842 EFI_STATUS Status;
2843
2844 //
2845 // Initialize memory management.
2846 //
2847 Xhc->MemPool = UsbHcInitMemPool ();
2848 ASSERT (Xhc->MemPool != NULL);
2849
2850 //
2851 // Program the Max Device Slots Enabled (MaxSlotsEn) field in the CONFIG register (5.4.7)
2852 // to enable the device slots that system software is going to use.
2853 //
2854 Xhc->MaxSlotsEn = Xhc->HcSParams1.Data.MaxSlots;
2855 ASSERT (Xhc->MaxSlotsEn >= 1 && Xhc->MaxSlotsEn <= 255);
2856 XhcPeiWriteOpReg (Xhc, XHC_CONFIG_OFFSET, (XhcPeiReadOpReg (Xhc, XHC_CONFIG_OFFSET) & ~XHC_CONFIG_MASK) | Xhc->MaxSlotsEn);
2857
2858 //
2859 // The Device Context Base Address Array entry associated with each allocated Device Slot
2860 // shall contain a 64-bit pointer to the base of the associated Device Context.
2861 // The Device Context Base Address Array shall contain MaxSlotsEn + 1 entries.
2862 // Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.
2863 //
2864 Size = (Xhc->MaxSlotsEn + 1) * sizeof (UINT64);
2865 Dcbaa = UsbHcAllocateMem (Xhc->MemPool, Size);
2866 ASSERT (Dcbaa != NULL);
2867
2868 //
2869 // A Scratchpad Buffer is a PAGESIZE block of system memory located on a PAGESIZE boundary.
2870 // System software shall allocate the Scratchpad Buffer(s) before placing the xHC in to Run
2871 // mode (Run/Stop(R/S) ='1').
2872 //
2873 MaxScratchpadBufs = ((Xhc->HcSParams2.Data.ScratchBufHi) << 5) | (Xhc->HcSParams2.Data.ScratchBufLo);
2874 Xhc->MaxScratchpadBufs = MaxScratchpadBufs;
2875 ASSERT (MaxScratchpadBufs <= 1023);
2876 if (MaxScratchpadBufs != 0) {
2877 //
2878 // Allocate the buffer to record the Mapping for each scratch buffer in order to Unmap them
2879 //
2880 ScratchEntryMap = AllocateZeroPool (sizeof (UINTN) * MaxScratchpadBufs);
2881 ASSERT (ScratchEntryMap != NULL);
2882 Xhc->ScratchEntryMap = ScratchEntryMap;
2883
2884 //
2885 // Allocate the buffer to record the host address for each entry
2886 //
2887 ScratchEntry = AllocateZeroPool (sizeof (UINT64) * MaxScratchpadBufs);
2888 ASSERT (ScratchEntry != NULL);
2889 Xhc->ScratchEntry = ScratchEntry;
2890
2891 ScratchPhy = 0;
2892 Status = UsbHcAllocateAlignedPages (
2893 EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)),
2894 Xhc->PageSize,
2895 (VOID **) &ScratchBuf,
2896 &ScratchPhy,
2897 &Xhc->ScratchMap
2898 );
2899 ASSERT_EFI_ERROR (Status);
2900
2901 ZeroMem (ScratchBuf, MaxScratchpadBufs * sizeof (UINT64));
2902 Xhc->ScratchBuf = ScratchBuf;
2903
2904 //
2905 // Allocate each scratch buffer
2906 //
2907 for (Index = 0; Index < MaxScratchpadBufs; Index++) {
2908 ScratchEntryPhy = 0;
2909 Status = UsbHcAllocateAlignedPages (
2910 EFI_SIZE_TO_PAGES (Xhc->PageSize),
2911 Xhc->PageSize,
2912 (VOID **) &ScratchEntry[Index],
2913 &ScratchEntryPhy,
2914 (VOID **) &ScratchEntryMap[Index]
2915 );
2916 ASSERT_EFI_ERROR (Status);
2917 ZeroMem ((VOID *) (UINTN) ScratchEntry[Index], Xhc->PageSize);
2918 //
2919 // Fill with the PCI device address
2920 //
2921 *ScratchBuf++ = ScratchEntryPhy;
2922 }
2923 //
2924 // The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the
2925 // Device Context Base Address Array points to the Scratchpad Buffer Array.
2926 //
2927 *(UINT64 *) Dcbaa = (UINT64) (UINTN) ScratchPhy;
2928 }
2929
2930 //
2931 // Program the Device Context Base Address Array Pointer (DCBAAP) register (5.4.6) with
2932 // a 64-bit address pointing to where the Device Context Base Address Array is located.
2933 //
2934 Xhc->DCBAA = (UINT64 *) (UINTN) Dcbaa;
2935 //
2936 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
2937 // So divide it to two 32-bytes width register access.
2938 //
2939 DcbaaPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Size);
2940 XhcPeiWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT (DcbaaPhy));
2941 XhcPeiWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (DcbaaPhy));
2942
2943 DEBUG ((EFI_D_INFO, "XhcPeiInitSched:DCBAA=0x%x\n", Xhc->DCBAA));
2944
2945 //
2946 // Define the Command Ring Dequeue Pointer by programming the Command Ring Control Register
2947 // (5.4.5) with a 64-bit address pointing to the starting address of the first TRB of the Command Ring.
2948 // Note: The Command Ring is 64 byte aligned, so the low order 6 bits of the Command Ring Pointer shall
2949 // always be '0'.
2950 //
2951 XhcPeiCreateTransferRing (Xhc, CMD_RING_TRB_NUMBER, &Xhc->CmdRing);
2952 //
2953 // The xHC uses the Enqueue Pointer to determine when a Transfer Ring is empty. As it fetches TRBs from a
2954 // Transfer Ring it checks for a Cycle bit transition. If a transition detected, the ring is empty.
2955 // So we set RCS as inverted PCS init value to let Command Ring empty
2956 //
2957 CmdRingPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->CmdRing.RingSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);
2958 ASSERT ((CmdRingPhy & 0x3F) == 0);
2959 CmdRingPhy |= XHC_CRCR_RCS;
2960 //
2961 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
2962 // So divide it to two 32-bytes width register access.
2963 //
2964 XhcPeiWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT (CmdRingPhy));
2965 XhcPeiWriteOpReg (Xhc, XHC_CRCR_OFFSET + 4, XHC_HIGH_32BIT (CmdRingPhy));
2966
2967 DEBUG ((EFI_D_INFO, "XhcPeiInitSched:XHC_CRCR=0x%x\n", Xhc->CmdRing.RingSeg0));
2968
2969 //
2970 // Disable the 'interrupter enable' bit in USB_CMD
2971 // and clear IE & IP bit in all Interrupter X Management Registers.
2972 //
2973 XhcPeiClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_INTE);
2974 for (Index = 0; Index < (UINT16)(Xhc->HcSParams1.Data.MaxIntrs); Index++) {
2975 XhcPeiClearRuntimeRegBit (Xhc, XHC_IMAN_OFFSET + (Index * 32), XHC_IMAN_IE);
2976 XhcPeiSetRuntimeRegBit (Xhc, XHC_IMAN_OFFSET + (Index * 32), XHC_IMAN_IP);
2977 }
2978
2979 //
2980 // Allocate EventRing for Cmd, Ctrl, Bulk, Interrupt, AsynInterrupt transfer
2981 //
2982 XhcPeiCreateEventRing (Xhc, &Xhc->EventRing);
2983 DEBUG ((EFI_D_INFO, "XhcPeiInitSched:XHC_EVENTRING=0x%x\n", Xhc->EventRing.EventRingSeg0));
2984 }
2985
2986 /**
2987 Free the resouce allocated at initializing schedule.
2988
2989 @param Xhc The XHCI device.
2990
2991 **/
2992 VOID
2993 XhcPeiFreeSched (
2994 IN PEI_XHC_DEV *Xhc
2995 )
2996 {
2997 UINT32 Index;
2998 UINT64 *ScratchEntry;
2999
3000 if (Xhc->ScratchBuf != NULL) {
3001 ScratchEntry = Xhc->ScratchEntry;
3002 for (Index = 0; Index < Xhc->MaxScratchpadBufs; Index++) {
3003 //
3004 // Free Scratchpad Buffers
3005 //
3006 UsbHcFreeAlignedPages ((VOID*) (UINTN) ScratchEntry[Index], EFI_SIZE_TO_PAGES (Xhc->PageSize), (VOID *) Xhc->ScratchEntryMap[Index]);
3007 }
3008 //
3009 // Free Scratchpad Buffer Array
3010 //
3011 UsbHcFreeAlignedPages (Xhc->ScratchBuf, EFI_SIZE_TO_PAGES (Xhc->MaxScratchpadBufs * sizeof (UINT64)), Xhc->ScratchMap);
3012 FreePool (Xhc->ScratchEntryMap);
3013 FreePool (Xhc->ScratchEntry);
3014 }
3015
3016 if (Xhc->CmdRing.RingSeg0 != NULL) {
3017 UsbHcFreeMem (Xhc->MemPool, Xhc->CmdRing.RingSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);
3018 Xhc->CmdRing.RingSeg0 = NULL;
3019 }
3020
3021 XhcPeiFreeEventRing (Xhc,&Xhc->EventRing);
3022
3023 if (Xhc->DCBAA != NULL) {
3024 UsbHcFreeMem (Xhc->MemPool, Xhc->DCBAA, (Xhc->MaxSlotsEn + 1) * sizeof (UINT64));
3025 Xhc->DCBAA = NULL;
3026 }
3027
3028 //
3029 // Free memory pool at last
3030 //
3031 if (Xhc->MemPool != NULL) {
3032 UsbHcFreeMemPool (Xhc->MemPool);
3033 Xhc->MemPool = NULL;
3034 }
3035 }
3036
EFI Development Kit II mirror for PVE