MdeModulePkg/Core/DxeIplPeim/Ia32/VirtualMemory.h

   1 /*++
   2
   3 Copyright (c) 2006, Intel Corporation
   4 All rights reserved. This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 Module Name:
  13   VirtualMemory.h
  14
  15 Abstract:
  16
  17   x64 Long Mode Virtual Memory Management Definitions
  18
  19   References:
  20     1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel
  21     2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
  22     3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
  23     4) AMD64 Architecture Programmer's Manual Volume 2: System Programming
  24 --*/
  25 #ifndef _VIRTUAL_MEMORY_H_
  26 #define _VIRTUAL_MEMORY_H_
  27
  28
  29 #define SYS_CODE64_SEL 0x38
  30
  31 #pragma pack(1)
  32
  33 typedef union {
  34   struct {
  35     UINT32  LimitLow    : 16;
  36     UINT32  BaseLow     : 16;
  37     UINT32  BaseMid     : 8;
  38     UINT32  Type        : 4;
  39     UINT32  System      : 1;
  40     UINT32  Dpl         : 2;
  41     UINT32  Present     : 1;
  42     UINT32  LimitHigh   : 4;
  43     UINT32  Software    : 1;
  44     UINT32  Reserved    : 1;
  45     UINT32  DefaultSize : 1;
  46     UINT32  Granularity : 1;
  47     UINT32  BaseHigh    : 8;
  48   } Bits;
  49   UINT64  Uint64;
  50 } IA32_GDT;
  51
  52 typedef struct {
  53   IA32_IDT_GATE_DESCRIPTOR  Ia32IdtEntry;
  54   UINT32                    Offset32To63;
  55   UINT32                    Reserved;
  56 } X64_IDT_GATE_DESCRIPTOR;
  57
  58 //
  59 // Page-Map Level-4 Offset (PML4) and
  60 // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
  61 //
  62
  63 typedef union {
  64   struct {
  65     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  66     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  67     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  68     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  69     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  70     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  71     UINT64  Reserved:1;               // Reserved
  72     UINT64  MustBeZero:2;             // Must Be Zero
  73     UINT64  Available:3;              // Available for use by system software
  74     UINT64  PageTableBaseAddress:40;  // Page Table Base Address
  75     UINT64  AvabilableHigh:11;        // Available for use by system software
  76     UINT64  Nx:1;                     // No Execute bit
  77   } Bits;
  78   UINT64    Uint64;
  79 } PAGE_MAP_AND_DIRECTORY_POINTER;
  80
  81 //
  82 // Page Table Entry 2MB
  83 //
  84 typedef union {
  85   struct {
  86     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  87     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  88     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  89     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  90     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  91     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  92     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
  93     UINT64  MustBe1:1;                // Must be 1
  94     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
  95     UINT64  Available:3;              // Available for use by system software
  96     UINT64  PAT:1;                    //
  97     UINT64  MustBeZero:8;             // Must be zero;
  98     UINT64  PageTableBaseAddress:31;  // Page Table Base Address
  99     UINT64  AvabilableHigh:11;        // Available for use by system software
 100     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
 101   } Bits;
 102   UINT64    Uint64;
 103 } PAGE_TABLE_ENTRY;
 104
 105 #pragma pack()
 106
 107 UINTN
 108 CreateIdentityMappingPageTables (
 109   VOID
 110   )
 111 ;
 112
 113
 114 /**
 115
 116   Fix up the vector number in the vector code.
 117
 118   @param VectorBase   Base address of the vector handler.
 119
 120   @param VectorNum    Index of vector.
 121
 122 **/
 123 VOID
 124 EFIAPI
 125 AsmVectorFixup (
 126   VOID    *VectorBase,
 127   UINT8   VectorNum
 128   );
 129
 130
 131 /**
 132
 133   Get the information of vector template.
 134
 135   @param TemplateBase   Base address of the template code.
 136
 137   @return               Size of the Template code.
 138
 139 **/
 140 UINTN
 141 EFIAPI
 142 AsmGetVectorTemplatInfo (
 143   OUT   VOID  **TemplateBase
 144   );
 145
 146
 147 #endif