Enable Nt32 platform boot to DXE phase.
[mirror_edk2.git] / MdeModulePkg / Core / DxeIplPeim / Ia32 / VirtualMemory.h
1 /*++
2
3 Copyright (c) 2006, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
8
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11
12 Module Name:
13 VirtualMemory.h
14
15 Abstract:
16
17 x64 Long Mode Virtual Memory Management Definitions
18
19 References:
20 1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel
21 2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
22 3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
23 4) AMD64 Architecture Programmer's Manual Volume 2: System Programming
24 --*/
25 #ifndef _VIRTUAL_MEMORY_H_
26 #define _VIRTUAL_MEMORY_H_
27
28
29 //
30 // Include common header file for this module.
31 //
32 #include "CommonHeader.h"
33
34 #define SYS_CODE64_SEL 0x38
35
36 #pragma pack(1)
37
38 typedef union {
39 struct {
40 UINT32 LimitLow : 16;
41 UINT32 BaseLow : 16;
42 UINT32 BaseMid : 8;
43 UINT32 Type : 4;
44 UINT32 System : 1;
45 UINT32 Dpl : 2;
46 UINT32 Present : 1;
47 UINT32 LimitHigh : 4;
48 UINT32 Software : 1;
49 UINT32 Reserved : 1;
50 UINT32 DefaultSize : 1;
51 UINT32 Granularity : 1;
52 UINT32 BaseHigh : 8;
53 } Bits;
54 UINT64 Uint64;
55 } IA32_GDT;
56
57 //
58 // Page-Map Level-4 Offset (PML4) and
59 // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
60 //
61
62 typedef union {
63 struct {
64 UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
65 UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
66 UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
67 UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
68 UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
69 UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
70 UINT64 Reserved:1; // Reserved
71 UINT64 MustBeZero:2; // Must Be Zero
72 UINT64 Available:3; // Available for use by system software
73 UINT64 PageTableBaseAddress:40; // Page Table Base Address
74 UINT64 AvabilableHigh:11; // Available for use by system software
75 UINT64 Nx:1; // No Execute bit
76 } Bits;
77 UINT64 Uint64;
78 } PAGE_MAP_AND_DIRECTORY_POINTER;
79
80 //
81 // Page Table Entry 2MB
82 //
83 typedef union {
84 struct {
85 UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
86 UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
87 UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
88 UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
89 UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
90 UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
91 UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
92 UINT64 MustBe1:1; // Must be 1
93 UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
94 UINT64 Available:3; // Available for use by system software
95 UINT64 PAT:1; //
96 UINT64 MustBeZero:8; // Must be zero;
97 UINT64 PageTableBaseAddress:31; // Page Table Base Address
98 UINT64 AvabilableHigh:11; // Available for use by system software
99 UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
100 } Bits;
101 UINT64 Uint64;
102 } PAGE_TABLE_ENTRY;
103
104 #pragma pack()
105
106 UINTN
107 CreateIdentityMappingPageTables (
108 VOID
109 )
110 ;
111
112 #endif