2 x64 Virtual Memory Management Services in the form of an IA-32 driver.
3 Used to establish a 1:1 Virtual to Physical Mapping that is required to
4 enter Long Mode (x64 64-bit mode).
6 While we make a 1:1 mapping (identity mapping) for all physical pages
7 we still need to use the MTRR's to ensure that the cachability attributes
8 for all memory regions is correct.
10 The basic idea is to use 2MB page table entries where ever possible. If
11 more granularity of cachability is required then 4K page tables are used.
14 1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel
15 2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
16 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
18 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
19 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
21 This program and the accompanying materials
22 are licensed and made available under the terms and conditions of the BSD License
23 which accompanies this distribution. The full text of the license may be found at
24 http://opensource.org/licenses/bsd-license.php
26 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
27 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
32 #include "VirtualMemory.h"
35 // Global variable to keep track current available memory used as page table.
37 PAGE_TABLE_POOL
*mPageTablePool
= NULL
;
40 Clear legacy memory located at the first 4K-page, if available.
42 This function traverses the whole HOB list to check if memory from 0 to 4095
43 exists and has not been allocated, and then clear it if so.
45 @param HobStart The start of HobList passed to DxeCore.
53 EFI_PEI_HOB_POINTERS RscHob
;
54 EFI_PEI_HOB_POINTERS MemHob
;
57 RscHob
.Raw
= HobStart
;
58 MemHob
.Raw
= HobStart
;
62 // Check if page 0 exists and free
64 while ((RscHob
.Raw
= GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR
,
65 RscHob
.Raw
)) != NULL
) {
66 if (RscHob
.ResourceDescriptor
->ResourceType
== EFI_RESOURCE_SYSTEM_MEMORY
&&
67 RscHob
.ResourceDescriptor
->PhysicalStart
== 0) {
70 // Make sure memory at 0-4095 has not been allocated.
72 while ((MemHob
.Raw
= GetNextHob (EFI_HOB_TYPE_MEMORY_ALLOCATION
,
73 MemHob
.Raw
)) != NULL
) {
74 if (MemHob
.MemoryAllocation
->AllocDescriptor
.MemoryBaseAddress
79 MemHob
.Raw
= GET_NEXT_HOB (MemHob
);
83 RscHob
.Raw
= GET_NEXT_HOB (RscHob
);
87 DEBUG ((DEBUG_INFO
, "Clearing first 4K-page!\r\n"));
88 SetMem (NULL
, EFI_PAGE_SIZE
, 0);
95 Return configure status of NULL pointer detection feature.
97 @return TRUE NULL pointer detection feature is enabled
98 @return FALSE NULL pointer detection feature is disabled
102 IsNullDetectionEnabled (
106 return ((PcdGet8 (PcdNullPointerDetectionPropertyMask
) & BIT0
) != 0);
110 Enable Execute Disable Bit.
114 EnableExecuteDisableBit (
120 MsrRegisters
= AsmReadMsr64 (0xC0000080);
121 MsrRegisters
|= BIT11
;
122 AsmWriteMsr64 (0xC0000080, MsrRegisters
);
126 The function will check if page table entry should be splitted to smaller
129 @param Address Physical memory address.
130 @param Size Size of the given physical memory.
131 @param StackBase Base address of stack.
132 @param StackSize Size of stack.
134 @retval TRUE Page table should be split.
135 @retval FALSE Page table should not be split.
139 IN EFI_PHYSICAL_ADDRESS Address
,
141 IN EFI_PHYSICAL_ADDRESS StackBase
,
145 if (IsNullDetectionEnabled () && Address
== 0) {
149 if (PcdGetBool (PcdCpuStackGuard
)) {
150 if (StackBase
>= Address
&& StackBase
< (Address
+ Size
)) {
155 if (PcdGetBool (PcdSetNxForStack
)) {
156 if ((Address
< StackBase
+ StackSize
) && ((Address
+ Size
) > StackBase
)) {
164 Initialize a buffer pool for page table use only.
166 To reduce the potential split operation on page table, the pages reserved for
167 page table should be allocated in the times of PAGE_TABLE_POOL_UNIT_PAGES and
168 at the boundary of PAGE_TABLE_POOL_ALIGNMENT. So the page pool is always
169 initialized with number of pages greater than or equal to the given PoolPages.
171 Once the pages in the pool are used up, this method should be called again to
172 reserve at least another PAGE_TABLE_POOL_UNIT_PAGES. But usually this won't
175 @param PoolPages The least page number of the pool to be created.
177 @retval TRUE The pool is initialized successfully.
178 @retval FALSE The memory is out of resource.
181 InitializePageTablePool (
188 // Always reserve at least PAGE_TABLE_POOL_UNIT_PAGES, including one page for
191 PoolPages
+= 1; // Add one page for header.
192 PoolPages
= ((PoolPages
- 1) / PAGE_TABLE_POOL_UNIT_PAGES
+ 1) *
193 PAGE_TABLE_POOL_UNIT_PAGES
;
194 Buffer
= AllocateAlignedPages (PoolPages
, PAGE_TABLE_POOL_ALIGNMENT
);
195 if (Buffer
== NULL
) {
196 DEBUG ((DEBUG_ERROR
, "ERROR: Out of aligned pages\r\n"));
201 // Link all pools into a list for easier track later.
203 if (mPageTablePool
== NULL
) {
204 mPageTablePool
= Buffer
;
205 mPageTablePool
->NextPool
= mPageTablePool
;
207 ((PAGE_TABLE_POOL
*)Buffer
)->NextPool
= mPageTablePool
->NextPool
;
208 mPageTablePool
->NextPool
= Buffer
;
209 mPageTablePool
= Buffer
;
213 // Reserve one page for pool header.
215 mPageTablePool
->FreePages
= PoolPages
- 1;
216 mPageTablePool
->Offset
= EFI_PAGES_TO_SIZE (1);
222 This API provides a way to allocate memory for page table.
224 This API can be called more than once to allocate memory for page tables.
226 Allocates the number of 4KB pages and returns a pointer to the allocated
227 buffer. The buffer returned is aligned on a 4KB boundary.
229 If Pages is 0, then NULL is returned.
230 If there is not enough memory remaining to satisfy the request, then NULL is
233 @param Pages The number of 4 KB pages to allocate.
235 @return A pointer to the allocated buffer or NULL if allocation fails.
239 AllocatePageTableMemory (
250 // Renew the pool if necessary.
252 if (mPageTablePool
== NULL
||
253 Pages
> mPageTablePool
->FreePages
) {
254 if (!InitializePageTablePool (Pages
)) {
259 Buffer
= (UINT8
*)mPageTablePool
+ mPageTablePool
->Offset
;
261 mPageTablePool
->Offset
+= EFI_PAGES_TO_SIZE (Pages
);
262 mPageTablePool
->FreePages
-= Pages
;
270 @param[in] PhysicalAddress Start physical address the 2M page covered.
271 @param[in, out] PageEntry2M Pointer to 2M page entry.
272 @param[in] StackBase Stack base address.
273 @param[in] StackSize Stack size.
278 IN EFI_PHYSICAL_ADDRESS PhysicalAddress
,
279 IN OUT UINT64
*PageEntry2M
,
280 IN EFI_PHYSICAL_ADDRESS StackBase
,
284 EFI_PHYSICAL_ADDRESS PhysicalAddress4K
;
285 UINTN IndexOfPageTableEntries
;
286 PAGE_TABLE_4K_ENTRY
*PageTableEntry
;
287 UINT64 AddressEncMask
;
290 // Make sure AddressEncMask is contained to smallest supported address field
292 AddressEncMask
= PcdGet64 (PcdPteMemoryEncryptionAddressOrMask
) & PAGING_1G_ADDRESS_MASK_64
;
294 PageTableEntry
= AllocatePageTableMemory (1);
295 ASSERT (PageTableEntry
!= NULL
);
298 // Fill in 2M page entry.
300 *PageEntry2M
= (UINT64
) (UINTN
) PageTableEntry
| AddressEncMask
| IA32_PG_P
| IA32_PG_RW
;
302 PhysicalAddress4K
= PhysicalAddress
;
303 for (IndexOfPageTableEntries
= 0; IndexOfPageTableEntries
< 512; IndexOfPageTableEntries
++, PageTableEntry
++, PhysicalAddress4K
+= SIZE_4KB
) {
305 // Fill in the Page Table entries
307 PageTableEntry
->Uint64
= (UINT64
) PhysicalAddress4K
| AddressEncMask
;
308 PageTableEntry
->Bits
.ReadWrite
= 1;
310 if ((IsNullDetectionEnabled () && PhysicalAddress4K
== 0) ||
311 (PcdGetBool (PcdCpuStackGuard
) && PhysicalAddress4K
== StackBase
)) {
312 PageTableEntry
->Bits
.Present
= 0;
314 PageTableEntry
->Bits
.Present
= 1;
317 if (PcdGetBool (PcdSetNxForStack
)
318 && (PhysicalAddress4K
>= StackBase
)
319 && (PhysicalAddress4K
< StackBase
+ StackSize
)) {
321 // Set Nx bit for stack.
323 PageTableEntry
->Bits
.Nx
= 1;
331 @param[in] PhysicalAddress Start physical address the 1G page covered.
332 @param[in, out] PageEntry1G Pointer to 1G page entry.
333 @param[in] StackBase Stack base address.
334 @param[in] StackSize Stack size.
339 IN EFI_PHYSICAL_ADDRESS PhysicalAddress
,
340 IN OUT UINT64
*PageEntry1G
,
341 IN EFI_PHYSICAL_ADDRESS StackBase
,
345 EFI_PHYSICAL_ADDRESS PhysicalAddress2M
;
346 UINTN IndexOfPageDirectoryEntries
;
347 PAGE_TABLE_ENTRY
*PageDirectoryEntry
;
348 UINT64 AddressEncMask
;
351 // Make sure AddressEncMask is contained to smallest supported address field
353 AddressEncMask
= PcdGet64 (PcdPteMemoryEncryptionAddressOrMask
) & PAGING_1G_ADDRESS_MASK_64
;
355 PageDirectoryEntry
= AllocatePageTableMemory (1);
356 ASSERT (PageDirectoryEntry
!= NULL
);
359 // Fill in 1G page entry.
361 *PageEntry1G
= (UINT64
) (UINTN
) PageDirectoryEntry
| AddressEncMask
| IA32_PG_P
| IA32_PG_RW
;
363 PhysicalAddress2M
= PhysicalAddress
;
364 for (IndexOfPageDirectoryEntries
= 0; IndexOfPageDirectoryEntries
< 512; IndexOfPageDirectoryEntries
++, PageDirectoryEntry
++, PhysicalAddress2M
+= SIZE_2MB
) {
365 if (ToSplitPageTable (PhysicalAddress2M
, SIZE_2MB
, StackBase
, StackSize
)) {
367 // Need to split this 2M page that covers NULL or stack range.
369 Split2MPageTo4K (PhysicalAddress2M
, (UINT64
*) PageDirectoryEntry
, StackBase
, StackSize
);
372 // Fill in the Page Directory entries
374 PageDirectoryEntry
->Uint64
= (UINT64
) PhysicalAddress2M
| AddressEncMask
;
375 PageDirectoryEntry
->Bits
.ReadWrite
= 1;
376 PageDirectoryEntry
->Bits
.Present
= 1;
377 PageDirectoryEntry
->Bits
.MustBe1
= 1;
383 Set one page of page table pool memory to be read-only.
385 @param[in] PageTableBase Base address of page table (CR3).
386 @param[in] Address Start address of a page to be set as read-only.
387 @param[in] Level4Paging Level 4 paging flag.
391 SetPageTablePoolReadOnly (
392 IN UINTN PageTableBase
,
393 IN EFI_PHYSICAL_ADDRESS Address
,
394 IN BOOLEAN Level4Paging
399 UINT64 AddressEncMask
;
400 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
402 UINT64
*NewPageTable
;
410 ASSERT (PageTableBase
!= 0);
413 // Since the page table is always from page table pool, which is always
414 // located at the boundary of PcdPageTablePoolAlignment, we just need to
415 // set the whole pool unit to be read-only.
417 Address
= Address
& PAGE_TABLE_POOL_ALIGN_MASK
;
419 LevelShift
[1] = PAGING_L1_ADDRESS_SHIFT
;
420 LevelShift
[2] = PAGING_L2_ADDRESS_SHIFT
;
421 LevelShift
[3] = PAGING_L3_ADDRESS_SHIFT
;
422 LevelShift
[4] = PAGING_L4_ADDRESS_SHIFT
;
424 LevelMask
[1] = PAGING_4K_ADDRESS_MASK_64
;
425 LevelMask
[2] = PAGING_2M_ADDRESS_MASK_64
;
426 LevelMask
[3] = PAGING_1G_ADDRESS_MASK_64
;
427 LevelMask
[4] = PAGING_1G_ADDRESS_MASK_64
;
429 LevelSize
[1] = SIZE_4KB
;
430 LevelSize
[2] = SIZE_2MB
;
431 LevelSize
[3] = SIZE_1GB
;
432 LevelSize
[4] = SIZE_512GB
;
434 AddressEncMask
= PcdGet64 (PcdPteMemoryEncryptionAddressOrMask
) &
435 PAGING_1G_ADDRESS_MASK_64
;
436 PageTable
= (UINT64
*)(UINTN
)PageTableBase
;
437 PoolUnitSize
= PAGE_TABLE_POOL_UNIT_SIZE
;
439 for (Level
= (Level4Paging
) ? 4 : 3; Level
> 0; --Level
) {
440 Index
= ((UINTN
)RShiftU64 (Address
, LevelShift
[Level
]));
441 Index
&= PAGING_PAE_INDEX_MASK
;
443 PageAttr
= PageTable
[Index
];
444 if ((PageAttr
& IA32_PG_PS
) == 0) {
446 // Go to next level of table.
448 PageTable
= (UINT64
*)(UINTN
)(PageAttr
& ~AddressEncMask
&
449 PAGING_4K_ADDRESS_MASK_64
);
453 if (PoolUnitSize
>= LevelSize
[Level
]) {
455 // Clear R/W bit if current page granularity is not larger than pool unit
458 if ((PageAttr
& IA32_PG_RW
) != 0) {
459 while (PoolUnitSize
> 0) {
461 // PAGE_TABLE_POOL_UNIT_SIZE and PAGE_TABLE_POOL_ALIGNMENT are fit in
462 // one page (2MB). Then we don't need to update attributes for pages
463 // crossing page directory. ASSERT below is for that purpose.
465 ASSERT (Index
< EFI_PAGE_SIZE
/sizeof (UINT64
));
467 PageTable
[Index
] &= ~(UINT64
)IA32_PG_RW
;
468 PoolUnitSize
-= LevelSize
[Level
];
478 // The smaller granularity of page must be needed.
482 NewPageTable
= AllocatePageTableMemory (1);
483 ASSERT (NewPageTable
!= NULL
);
485 PhysicalAddress
= PageAttr
& LevelMask
[Level
];
487 EntryIndex
< EFI_PAGE_SIZE
/sizeof (UINT64
);
489 NewPageTable
[EntryIndex
] = PhysicalAddress
| AddressEncMask
|
490 IA32_PG_P
| IA32_PG_RW
;
492 NewPageTable
[EntryIndex
] |= IA32_PG_PS
;
494 PhysicalAddress
+= LevelSize
[Level
- 1];
497 PageTable
[Index
] = (UINT64
)(UINTN
)NewPageTable
| AddressEncMask
|
498 IA32_PG_P
| IA32_PG_RW
;
499 PageTable
= NewPageTable
;
505 Prevent the memory pages used for page table from been overwritten.
507 @param[in] PageTableBase Base address of page table (CR3).
508 @param[in] Level4Paging Level 4 paging flag.
512 EnablePageTableProtection (
513 IN UINTN PageTableBase
,
514 IN BOOLEAN Level4Paging
517 PAGE_TABLE_POOL
*HeadPool
;
518 PAGE_TABLE_POOL
*Pool
;
520 EFI_PHYSICAL_ADDRESS Address
;
522 if (mPageTablePool
== NULL
) {
527 // Disable write protection, because we need to mark page table to be write
530 AsmWriteCr0 (AsmReadCr0() & ~CR0_WP
);
533 // SetPageTablePoolReadOnly might update mPageTablePool. It's safer to
534 // remember original one in advance.
536 HeadPool
= mPageTablePool
;
539 Address
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)Pool
;
540 PoolSize
= Pool
->Offset
+ EFI_PAGES_TO_SIZE (Pool
->FreePages
);
543 // The size of one pool must be multiple of PAGE_TABLE_POOL_UNIT_SIZE, which
544 // is one of page size of the processor (2MB by default). Let's apply the
545 // protection to them one by one.
547 while (PoolSize
> 0) {
548 SetPageTablePoolReadOnly(PageTableBase
, Address
, Level4Paging
);
549 Address
+= PAGE_TABLE_POOL_UNIT_SIZE
;
550 PoolSize
-= PAGE_TABLE_POOL_UNIT_SIZE
;
553 Pool
= Pool
->NextPool
;
554 } while (Pool
!= HeadPool
);
557 // Enable write protection, after page table attribute updated.
559 AsmWriteCr0 (AsmReadCr0() | CR0_WP
);
563 Allocates and fills in the Page Directory and Page Table Entries to
564 establish a 1:1 Virtual to Physical mapping.
566 @param[in] StackBase Stack base address.
567 @param[in] StackSize Stack size.
569 @return The address of 4 level page map.
573 CreateIdentityMappingPageTables (
574 IN EFI_PHYSICAL_ADDRESS StackBase
,
580 UINT8 PhysicalAddressBits
;
581 EFI_PHYSICAL_ADDRESS PageAddress
;
582 UINTN IndexOfPml4Entries
;
583 UINTN IndexOfPdpEntries
;
584 UINTN IndexOfPageDirectoryEntries
;
585 UINT32 NumberOfPml4EntriesNeeded
;
586 UINT32 NumberOfPdpEntriesNeeded
;
587 PAGE_MAP_AND_DIRECTORY_POINTER
*PageMapLevel4Entry
;
588 PAGE_MAP_AND_DIRECTORY_POINTER
*PageMap
;
589 PAGE_MAP_AND_DIRECTORY_POINTER
*PageDirectoryPointerEntry
;
590 PAGE_TABLE_ENTRY
*PageDirectoryEntry
;
592 UINTN BigPageAddress
;
594 BOOLEAN Page1GSupport
;
595 PAGE_TABLE_1G_ENTRY
*PageDirectory1GEntry
;
596 UINT64 AddressEncMask
;
599 // Make sure AddressEncMask is contained to smallest supported address field
601 AddressEncMask
= PcdGet64 (PcdPteMemoryEncryptionAddressOrMask
) & PAGING_1G_ADDRESS_MASK_64
;
603 Page1GSupport
= FALSE
;
604 if (PcdGetBool(PcdUse1GPageTable
)) {
605 AsmCpuid (0x80000000, &RegEax
, NULL
, NULL
, NULL
);
606 if (RegEax
>= 0x80000001) {
607 AsmCpuid (0x80000001, NULL
, NULL
, NULL
, &RegEdx
);
608 if ((RegEdx
& BIT26
) != 0) {
609 Page1GSupport
= TRUE
;
615 // Get physical address bits supported.
617 Hob
= GetFirstHob (EFI_HOB_TYPE_CPU
);
619 PhysicalAddressBits
= ((EFI_HOB_CPU
*) Hob
)->SizeOfMemorySpace
;
621 AsmCpuid (0x80000000, &RegEax
, NULL
, NULL
, NULL
);
622 if (RegEax
>= 0x80000008) {
623 AsmCpuid (0x80000008, &RegEax
, NULL
, NULL
, NULL
);
624 PhysicalAddressBits
= (UINT8
) RegEax
;
626 PhysicalAddressBits
= 36;
631 // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.
633 ASSERT (PhysicalAddressBits
<= 52);
634 if (PhysicalAddressBits
> 48) {
635 PhysicalAddressBits
= 48;
639 // Calculate the table entries needed.
641 if (PhysicalAddressBits
<= 39 ) {
642 NumberOfPml4EntriesNeeded
= 1;
643 NumberOfPdpEntriesNeeded
= (UINT32
)LShiftU64 (1, (PhysicalAddressBits
- 30));
645 NumberOfPml4EntriesNeeded
= (UINT32
)LShiftU64 (1, (PhysicalAddressBits
- 39));
646 NumberOfPdpEntriesNeeded
= 512;
650 // Pre-allocate big pages to avoid later allocations.
652 if (!Page1GSupport
) {
653 TotalPagesNum
= (NumberOfPdpEntriesNeeded
+ 1) * NumberOfPml4EntriesNeeded
+ 1;
655 TotalPagesNum
= NumberOfPml4EntriesNeeded
+ 1;
657 BigPageAddress
= (UINTN
) AllocatePageTableMemory (TotalPagesNum
);
658 ASSERT (BigPageAddress
!= 0);
661 // By architecture only one PageMapLevel4 exists - so lets allocate storage for it.
663 PageMap
= (VOID
*) BigPageAddress
;
664 BigPageAddress
+= SIZE_4KB
;
666 PageMapLevel4Entry
= PageMap
;
668 for (IndexOfPml4Entries
= 0; IndexOfPml4Entries
< NumberOfPml4EntriesNeeded
; IndexOfPml4Entries
++, PageMapLevel4Entry
++) {
670 // Each PML4 entry points to a page of Page Directory Pointer entires.
671 // So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.
673 PageDirectoryPointerEntry
= (VOID
*) BigPageAddress
;
674 BigPageAddress
+= SIZE_4KB
;
679 PageMapLevel4Entry
->Uint64
= (UINT64
)(UINTN
)PageDirectoryPointerEntry
| AddressEncMask
;
680 PageMapLevel4Entry
->Bits
.ReadWrite
= 1;
681 PageMapLevel4Entry
->Bits
.Present
= 1;
684 PageDirectory1GEntry
= (VOID
*) PageDirectoryPointerEntry
;
686 for (IndexOfPageDirectoryEntries
= 0; IndexOfPageDirectoryEntries
< 512; IndexOfPageDirectoryEntries
++, PageDirectory1GEntry
++, PageAddress
+= SIZE_1GB
) {
687 if (ToSplitPageTable (PageAddress
, SIZE_1GB
, StackBase
, StackSize
)) {
688 Split1GPageTo2M (PageAddress
, (UINT64
*) PageDirectory1GEntry
, StackBase
, StackSize
);
691 // Fill in the Page Directory entries
693 PageDirectory1GEntry
->Uint64
= (UINT64
)PageAddress
| AddressEncMask
;
694 PageDirectory1GEntry
->Bits
.ReadWrite
= 1;
695 PageDirectory1GEntry
->Bits
.Present
= 1;
696 PageDirectory1GEntry
->Bits
.MustBe1
= 1;
700 for (IndexOfPdpEntries
= 0; IndexOfPdpEntries
< NumberOfPdpEntriesNeeded
; IndexOfPdpEntries
++, PageDirectoryPointerEntry
++) {
702 // Each Directory Pointer entries points to a page of Page Directory entires.
703 // So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.
705 PageDirectoryEntry
= (VOID
*) BigPageAddress
;
706 BigPageAddress
+= SIZE_4KB
;
709 // Fill in a Page Directory Pointer Entries
711 PageDirectoryPointerEntry
->Uint64
= (UINT64
)(UINTN
)PageDirectoryEntry
| AddressEncMask
;
712 PageDirectoryPointerEntry
->Bits
.ReadWrite
= 1;
713 PageDirectoryPointerEntry
->Bits
.Present
= 1;
715 for (IndexOfPageDirectoryEntries
= 0; IndexOfPageDirectoryEntries
< 512; IndexOfPageDirectoryEntries
++, PageDirectoryEntry
++, PageAddress
+= SIZE_2MB
) {
716 if (ToSplitPageTable (PageAddress
, SIZE_2MB
, StackBase
, StackSize
)) {
718 // Need to split this 2M page that covers NULL or stack range.
720 Split2MPageTo4K (PageAddress
, (UINT64
*) PageDirectoryEntry
, StackBase
, StackSize
);
723 // Fill in the Page Directory entries
725 PageDirectoryEntry
->Uint64
= (UINT64
)PageAddress
| AddressEncMask
;
726 PageDirectoryEntry
->Bits
.ReadWrite
= 1;
727 PageDirectoryEntry
->Bits
.Present
= 1;
728 PageDirectoryEntry
->Bits
.MustBe1
= 1;
733 for (; IndexOfPdpEntries
< 512; IndexOfPdpEntries
++, PageDirectoryPointerEntry
++) {
735 PageDirectoryPointerEntry
,
736 sizeof(PAGE_MAP_AND_DIRECTORY_POINTER
)
743 // For the PML4 entries we are not using fill in a null entry.
745 for (; IndexOfPml4Entries
< 512; IndexOfPml4Entries
++, PageMapLevel4Entry
++) {
748 sizeof (PAGE_MAP_AND_DIRECTORY_POINTER
)
753 // Protect the page table by marking the memory used for page table to be
756 EnablePageTableProtection ((UINTN
)PageMap
, TRUE
);
758 if (PcdGetBool (PcdSetNxForStack
)) {
759 EnableExecuteDisableBit ();
762 return (UINTN
)PageMap
;