MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c

   1 /** @file
   2   x64 Virtual Memory Management Services in the form of an IA-32 driver.
   3   Used to establish a 1:1 Virtual to Physical Mapping that is required to
   4   enter Long Mode (x64 64-bit mode).
   5
   6   While we make a 1:1 mapping (identity mapping) for all physical pages
   7   we still need to use the MTRR's to ensure that the cachability attributes
   8   for all memory regions is correct.
   9
  10   The basic idea is to use 2MB page table entries where ever possible. If
  11   more granularity of cachability is required then 4K page tables are used.
  12
  13   References:
  14     1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel
  15     2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
  16     3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
  17
  18 Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
  19 This program and the accompanying materials
  20 are licensed and made available under the terms and conditions of the BSD License
  21 which accompanies this distribution.  The full text of the license may be found at
  22 http://opensource.org/licenses/bsd-license.php
  23
  24 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  25 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  26
  27 **/
  28
  29 #include "DxeIpl.h"
  30 #include "VirtualMemory.h"
  31
  32 /**
  33   Allocates and fills in the Page Directory and Page Table Entries to
  34   establish a 1:1 Virtual to Physical mapping.
  35
  36   @param  NumberOfProcessorPhysicalAddressBits  Number of processor address bits
  37                                                 to use. Limits the number of page
  38                                                 table entries  to the physical
  39                                                 address space.
  40
  41   @return The address of 4 level page map.
  42
  43 **/
  44 UINTN
  45 CreateIdentityMappingPageTables (
  46   VOID
  47   )
  48 {
  49   UINT32                                        RegEax;
  50   UINT32                                        RegEdx;
  51   UINT8                                         PhysicalAddressBits;
  52   EFI_PHYSICAL_ADDRESS                          PageAddress;
  53   UINTN                                         IndexOfPml4Entries;
  54   UINTN                                         IndexOfPdpEntries;
  55   UINTN                                         IndexOfPageDirectoryEntries;
  56   UINT32                                        NumberOfPml4EntriesNeeded;
  57   UINT32                                        NumberOfPdpEntriesNeeded;
  58   PAGE_MAP_AND_DIRECTORY_POINTER                *PageMapLevel4Entry;
  59   PAGE_MAP_AND_DIRECTORY_POINTER                *PageMap;
  60   PAGE_MAP_AND_DIRECTORY_POINTER                *PageDirectoryPointerEntry;
  61   PAGE_TABLE_ENTRY                              *PageDirectoryEntry;
  62   UINTN                                         TotalPagesNum;
  63   UINTN                                         BigPageAddress;
  64   VOID                                          *Hob;
  65   BOOLEAN                                       Page1GSupport;
  66   PAGE_TABLE_1G_ENTRY                           *PageDirectory1GEntry;
  67
  68   Page1GSupport = FALSE;
  69   if (PcdGetBool(PcdUse1GPageTable)) {
  70     AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
  71     if (RegEax >= 0x80000001) {
  72       AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
  73       if ((RegEdx & BIT26) != 0) {
  74         Page1GSupport = TRUE;
  75       }
  76     }
  77   }
  78
  79   //
  80   // Get physical address bits supported.
  81   //
  82   Hob = GetFirstHob (EFI_HOB_TYPE_CPU);
  83   if (Hob != NULL) {
  84     PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;
  85   } else {
  86     AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
  87     if (RegEax >= 0x80000008) {
  88       AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
  89       PhysicalAddressBits = (UINT8) RegEax;
  90     } else {
  91       PhysicalAddressBits = 36;
  92     }
  93   }
  94
  95   //
  96   // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.
  97   //
  98   ASSERT (PhysicalAddressBits <= 52);
  99   if (PhysicalAddressBits > 48) {
 100     PhysicalAddressBits = 48;
 101   }
 102
 103   //
 104   // Calculate the table entries needed.
 105   //
 106   if (PhysicalAddressBits <= 39 ) {
 107     NumberOfPml4EntriesNeeded = 1;
 108     NumberOfPdpEntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 30));
 109   } else {
 110     NumberOfPml4EntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 39));
 111     NumberOfPdpEntriesNeeded = 512;
 112   }
 113
 114   //
 115   // Pre-allocate big pages to avoid later allocations.
 116   //
 117   if (!Page1GSupport) {
 118     TotalPagesNum = (NumberOfPdpEntriesNeeded + 1) * NumberOfPml4EntriesNeeded + 1;
 119   } else {
 120     TotalPagesNum = NumberOfPml4EntriesNeeded + 1;
 121   }
 122   BigPageAddress = (UINTN) AllocatePages (TotalPagesNum);
 123   ASSERT (BigPageAddress != 0);
 124
 125   //
 126   // By architecture only one PageMapLevel4 exists - so lets allocate storage for it.
 127   //
 128   PageMap         = (VOID *) BigPageAddress;
 129   BigPageAddress += SIZE_4KB;
 130
 131   PageMapLevel4Entry = PageMap;
 132   PageAddress        = 0;
 133   for (IndexOfPml4Entries = 0; IndexOfPml4Entries < NumberOfPml4EntriesNeeded; IndexOfPml4Entries++, PageMapLevel4Entry++) {
 134     //
 135     // Each PML4 entry points to a page of Page Directory Pointer entires.
 136     // So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.
 137     //
 138     PageDirectoryPointerEntry = (VOID *) BigPageAddress;
 139     BigPageAddress += SIZE_4KB;
 140
 141     //
 142     // Make a PML4 Entry
 143     //
 144     PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry;
 145     PageMapLevel4Entry->Bits.ReadWrite = 1;
 146     PageMapLevel4Entry->Bits.Present = 1;
 147
 148     if (Page1GSupport) {
 149       PageDirectory1GEntry = (VOID *) PageDirectoryPointerEntry;
 150
 151       for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) {
 152         //
 153         // Fill in the Page Directory entries
 154         //
 155         PageDirectory1GEntry->Uint64 = (UINT64)PageAddress;
 156         PageDirectory1GEntry->Bits.ReadWrite = 1;
 157         PageDirectory1GEntry->Bits.Present = 1;
 158         PageDirectory1GEntry->Bits.MustBe1 = 1;
 159       }
 160     } else {
 161       for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {
 162         //
 163         // Each Directory Pointer entries points to a page of Page Directory entires.
 164         // So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.
 165         //
 166         PageDirectoryEntry = (VOID *) BigPageAddress;
 167         BigPageAddress += SIZE_4KB;
 168
 169         //
 170         // Fill in a Page Directory Pointer Entries
 171         //
 172         PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry;
 173         PageDirectoryPointerEntry->Bits.ReadWrite = 1;
 174         PageDirectoryPointerEntry->Bits.Present = 1;
 175
 176         for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += SIZE_2MB) {
 177           //
 178           // Fill in the Page Directory entries
 179           //
 180           PageDirectoryEntry->Uint64 = (UINT64)PageAddress;
 181           PageDirectoryEntry->Bits.ReadWrite = 1;
 182           PageDirectoryEntry->Bits.Present = 1;
 183           PageDirectoryEntry->Bits.MustBe1 = 1;
 184         }
 185       }
 186
 187       for (; IndexOfPdpEntries < 512; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {
 188         ZeroMem (
 189           PageDirectoryPointerEntry,
 190           sizeof(PAGE_MAP_AND_DIRECTORY_POINTER)
 191           );
 192       }
 193     }
 194   }
 195
 196   //
 197   // For the PML4 entries we are not using fill in a null entry.
 198   //
 199   for (; IndexOfPml4Entries < 512; IndexOfPml4Entries++, PageMapLevel4Entry++) {
 200     ZeroMem (
 201       PageMapLevel4Entry,
 202       sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)
 203       );
 204   }
 205
 206   return (UINTN)PageMap;
 207 }
 208