2 x64 Virtual Memory Management Services in the form of an IA-32 driver.
3 Used to establish a 1:1 Virtual to Physical Mapping that is required to
4 enter Long Mode (x64 64-bit mode).
6 While we make a 1:1 mapping (identity mapping) for all physical pages
7 we still need to use the MTRR's to ensure that the cachability attributes
8 for all memory regions is correct.
10 The basic idea is to use 2MB page table entries where ever possible. If
11 more granularity of cachability is required then 4K page tables are used.
14 1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel
15 2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
16 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
18 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
19 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
21 This program and the accompanying materials
22 are licensed and made available under the terms and conditions of the BSD License
23 which accompanies this distribution. The full text of the license may be found at
24 http://opensource.org/licenses/bsd-license.php
26 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
27 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
32 #include "VirtualMemory.h"
35 // Global variable to keep track current available memory used as page table.
37 PAGE_TABLE_POOL
*mPageTablePool
= NULL
;
40 Clear legacy memory located at the first 4K-page, if available.
42 This function traverses the whole HOB list to check if memory from 0 to 4095
43 exists and has not been allocated, and then clear it if so.
45 @param HobStart The start of HobList passed to DxeCore.
53 EFI_PEI_HOB_POINTERS RscHob
;
54 EFI_PEI_HOB_POINTERS MemHob
;
57 RscHob
.Raw
= HobStart
;
58 MemHob
.Raw
= HobStart
;
62 // Check if page 0 exists and free
64 while ((RscHob
.Raw
= GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR
,
65 RscHob
.Raw
)) != NULL
) {
66 if (RscHob
.ResourceDescriptor
->ResourceType
== EFI_RESOURCE_SYSTEM_MEMORY
&&
67 RscHob
.ResourceDescriptor
->PhysicalStart
== 0) {
70 // Make sure memory at 0-4095 has not been allocated.
72 while ((MemHob
.Raw
= GetNextHob (EFI_HOB_TYPE_MEMORY_ALLOCATION
,
73 MemHob
.Raw
)) != NULL
) {
74 if (MemHob
.MemoryAllocation
->AllocDescriptor
.MemoryBaseAddress
79 MemHob
.Raw
= GET_NEXT_HOB (MemHob
);
83 RscHob
.Raw
= GET_NEXT_HOB (RscHob
);
87 DEBUG ((DEBUG_INFO
, "Clearing first 4K-page!\r\n"));
88 SetMem (NULL
, EFI_PAGE_SIZE
, 0);
95 Return configure status of NULL pointer detection feature.
97 @return TRUE NULL pointer detection feature is enabled
98 @return FALSE NULL pointer detection feature is disabled
102 IsNullDetectionEnabled (
106 return ((PcdGet8 (PcdNullPointerDetectionPropertyMask
) & BIT0
) != 0);
110 Enable Execute Disable Bit.
114 EnableExecuteDisableBit (
120 MsrRegisters
= AsmReadMsr64 (0xC0000080);
121 MsrRegisters
|= BIT11
;
122 AsmWriteMsr64 (0xC0000080, MsrRegisters
);
126 The function will check if page table entry should be splitted to smaller
129 @retval TRUE Page table should be split.
130 @retval FALSE Page table should not be split.
134 IN EFI_PHYSICAL_ADDRESS Address
,
136 IN EFI_PHYSICAL_ADDRESS StackBase
,
140 if (IsNullDetectionEnabled () && Address
== 0) {
144 if (PcdGetBool (PcdCpuStackGuard
)) {
145 if (StackBase
>= Address
&& StackBase
< (Address
+ Size
)) {
150 if (PcdGetBool (PcdSetNxForStack
)) {
151 if ((Address
< StackBase
+ StackSize
) && ((Address
+ Size
) > StackBase
)) {
159 Initialize a buffer pool for page table use only.
161 To reduce the potential split operation on page table, the pages reserved for
162 page table should be allocated in the times of PAGE_TABLE_POOL_UNIT_PAGES and
163 at the boundary of PAGE_TABLE_POOL_ALIGNMENT. So the page pool is always
164 initialized with number of pages greater than or equal to the given PoolPages.
166 Once the pages in the pool are used up, this method should be called again to
167 reserve at least another PAGE_TABLE_POOL_UNIT_PAGES. But usually this won't
170 @param PoolPages The least page number of the pool to be created.
172 @retval TRUE The pool is initialized successfully.
173 @retval FALSE The memory is out of resource.
176 InitializePageTablePool (
183 // Always reserve at least PAGE_TABLE_POOL_UNIT_PAGES, including one page for
186 PoolPages
+= 1; // Add one page for header.
187 PoolPages
= ((PoolPages
- 1) / PAGE_TABLE_POOL_UNIT_PAGES
+ 1) *
188 PAGE_TABLE_POOL_UNIT_PAGES
;
189 Buffer
= AllocateAlignedPages (PoolPages
, PAGE_TABLE_POOL_ALIGNMENT
);
190 if (Buffer
== NULL
) {
191 DEBUG ((DEBUG_ERROR
, "ERROR: Out of aligned pages\r\n"));
196 // Link all pools into a list for easier track later.
198 if (mPageTablePool
== NULL
) {
199 mPageTablePool
= Buffer
;
200 mPageTablePool
->NextPool
= mPageTablePool
;
202 ((PAGE_TABLE_POOL
*)Buffer
)->NextPool
= mPageTablePool
->NextPool
;
203 mPageTablePool
->NextPool
= Buffer
;
204 mPageTablePool
= Buffer
;
208 // Reserve one page for pool header.
210 mPageTablePool
->FreePages
= PoolPages
- 1;
211 mPageTablePool
->Offset
= EFI_PAGES_TO_SIZE (1);
217 This API provides a way to allocate memory for page table.
219 This API can be called more than once to allocate memory for page tables.
221 Allocates the number of 4KB pages and returns a pointer to the allocated
222 buffer. The buffer returned is aligned on a 4KB boundary.
224 If Pages is 0, then NULL is returned.
225 If there is not enough memory remaining to satisfy the request, then NULL is
228 @param Pages The number of 4 KB pages to allocate.
230 @return A pointer to the allocated buffer or NULL if allocation fails.
234 AllocatePageTableMemory (
245 // Renew the pool if necessary.
247 if (mPageTablePool
== NULL
||
248 Pages
> mPageTablePool
->FreePages
) {
249 if (!InitializePageTablePool (Pages
)) {
254 Buffer
= (UINT8
*)mPageTablePool
+ mPageTablePool
->Offset
;
256 mPageTablePool
->Offset
+= EFI_PAGES_TO_SIZE (Pages
);
257 mPageTablePool
->FreePages
-= Pages
;
265 @param[in] PhysicalAddress Start physical address the 2M page covered.
266 @param[in, out] PageEntry2M Pointer to 2M page entry.
267 @param[in] StackBase Stack base address.
268 @param[in] StackSize Stack size.
273 IN EFI_PHYSICAL_ADDRESS PhysicalAddress
,
274 IN OUT UINT64
*PageEntry2M
,
275 IN EFI_PHYSICAL_ADDRESS StackBase
,
279 EFI_PHYSICAL_ADDRESS PhysicalAddress4K
;
280 UINTN IndexOfPageTableEntries
;
281 PAGE_TABLE_4K_ENTRY
*PageTableEntry
;
282 UINT64 AddressEncMask
;
285 // Make sure AddressEncMask is contained to smallest supported address field
287 AddressEncMask
= PcdGet64 (PcdPteMemoryEncryptionAddressOrMask
) & PAGING_1G_ADDRESS_MASK_64
;
289 PageTableEntry
= AllocatePageTableMemory (1);
290 ASSERT (PageTableEntry
!= NULL
);
293 // Fill in 2M page entry.
295 *PageEntry2M
= (UINT64
) (UINTN
) PageTableEntry
| AddressEncMask
| IA32_PG_P
| IA32_PG_RW
;
297 PhysicalAddress4K
= PhysicalAddress
;
298 for (IndexOfPageTableEntries
= 0; IndexOfPageTableEntries
< 512; IndexOfPageTableEntries
++, PageTableEntry
++, PhysicalAddress4K
+= SIZE_4KB
) {
300 // Fill in the Page Table entries
302 PageTableEntry
->Uint64
= (UINT64
) PhysicalAddress4K
| AddressEncMask
;
303 PageTableEntry
->Bits
.ReadWrite
= 1;
305 if ((IsNullDetectionEnabled () && PhysicalAddress4K
== 0) ||
306 (PcdGetBool (PcdCpuStackGuard
) && PhysicalAddress4K
== StackBase
)) {
307 PageTableEntry
->Bits
.Present
= 0;
309 PageTableEntry
->Bits
.Present
= 1;
312 if (PcdGetBool (PcdSetNxForStack
)
313 && (PhysicalAddress4K
>= StackBase
)
314 && (PhysicalAddress4K
< StackBase
+ StackSize
)) {
316 // Set Nx bit for stack.
318 PageTableEntry
->Bits
.Nx
= 1;
326 @param[in] PhysicalAddress Start physical address the 1G page covered.
327 @param[in, out] PageEntry1G Pointer to 1G page entry.
328 @param[in] StackBase Stack base address.
329 @param[in] StackSize Stack size.
334 IN EFI_PHYSICAL_ADDRESS PhysicalAddress
,
335 IN OUT UINT64
*PageEntry1G
,
336 IN EFI_PHYSICAL_ADDRESS StackBase
,
340 EFI_PHYSICAL_ADDRESS PhysicalAddress2M
;
341 UINTN IndexOfPageDirectoryEntries
;
342 PAGE_TABLE_ENTRY
*PageDirectoryEntry
;
343 UINT64 AddressEncMask
;
346 // Make sure AddressEncMask is contained to smallest supported address field
348 AddressEncMask
= PcdGet64 (PcdPteMemoryEncryptionAddressOrMask
) & PAGING_1G_ADDRESS_MASK_64
;
350 PageDirectoryEntry
= AllocatePageTableMemory (1);
351 ASSERT (PageDirectoryEntry
!= NULL
);
354 // Fill in 1G page entry.
356 *PageEntry1G
= (UINT64
) (UINTN
) PageDirectoryEntry
| AddressEncMask
| IA32_PG_P
| IA32_PG_RW
;
358 PhysicalAddress2M
= PhysicalAddress
;
359 for (IndexOfPageDirectoryEntries
= 0; IndexOfPageDirectoryEntries
< 512; IndexOfPageDirectoryEntries
++, PageDirectoryEntry
++, PhysicalAddress2M
+= SIZE_2MB
) {
360 if (ToSplitPageTable (PhysicalAddress2M
, SIZE_2MB
, StackBase
, StackSize
)) {
362 // Need to split this 2M page that covers NULL or stack range.
364 Split2MPageTo4K (PhysicalAddress2M
, (UINT64
*) PageDirectoryEntry
, StackBase
, StackSize
);
367 // Fill in the Page Directory entries
369 PageDirectoryEntry
->Uint64
= (UINT64
) PhysicalAddress2M
| AddressEncMask
;
370 PageDirectoryEntry
->Bits
.ReadWrite
= 1;
371 PageDirectoryEntry
->Bits
.Present
= 1;
372 PageDirectoryEntry
->Bits
.MustBe1
= 1;
378 Set one page of page table pool memory to be read-only.
380 @param[in] PageTableBase Base address of page table (CR3).
381 @param[in] Address Start address of a page to be set as read-only.
382 @param[in] Level4Paging Level 4 paging flag.
386 SetPageTablePoolReadOnly (
387 IN UINTN PageTableBase
,
388 IN EFI_PHYSICAL_ADDRESS Address
,
389 IN BOOLEAN Level4Paging
394 UINT64 AddressEncMask
;
395 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
397 UINT64
*NewPageTable
;
405 ASSERT (PageTableBase
!= 0);
408 // Since the page table is always from page table pool, which is always
409 // located at the boundary of PcdPageTablePoolAlignment, we just need to
410 // set the whole pool unit to be read-only.
412 Address
= Address
& PAGE_TABLE_POOL_ALIGN_MASK
;
414 LevelShift
[1] = PAGING_L1_ADDRESS_SHIFT
;
415 LevelShift
[2] = PAGING_L2_ADDRESS_SHIFT
;
416 LevelShift
[3] = PAGING_L3_ADDRESS_SHIFT
;
417 LevelShift
[4] = PAGING_L4_ADDRESS_SHIFT
;
419 LevelMask
[1] = PAGING_4K_ADDRESS_MASK_64
;
420 LevelMask
[2] = PAGING_2M_ADDRESS_MASK_64
;
421 LevelMask
[3] = PAGING_1G_ADDRESS_MASK_64
;
422 LevelMask
[4] = PAGING_1G_ADDRESS_MASK_64
;
424 LevelSize
[1] = SIZE_4KB
;
425 LevelSize
[2] = SIZE_2MB
;
426 LevelSize
[3] = SIZE_1GB
;
427 LevelSize
[4] = SIZE_512GB
;
429 AddressEncMask
= PcdGet64 (PcdPteMemoryEncryptionAddressOrMask
) &
430 PAGING_1G_ADDRESS_MASK_64
;
431 PageTable
= (UINT64
*)(UINTN
)PageTableBase
;
432 PoolUnitSize
= PAGE_TABLE_POOL_UNIT_SIZE
;
434 for (Level
= (Level4Paging
) ? 4 : 3; Level
> 0; --Level
) {
435 Index
= ((UINTN
)RShiftU64 (Address
, LevelShift
[Level
]));
436 Index
&= PAGING_PAE_INDEX_MASK
;
438 PageAttr
= PageTable
[Index
];
439 if ((PageAttr
& IA32_PG_PS
) == 0) {
441 // Go to next level of table.
443 PageTable
= (UINT64
*)(UINTN
)(PageAttr
& ~AddressEncMask
&
444 PAGING_4K_ADDRESS_MASK_64
);
448 if (PoolUnitSize
>= LevelSize
[Level
]) {
450 // Clear R/W bit if current page granularity is not larger than pool unit
453 if ((PageAttr
& IA32_PG_RW
) != 0) {
454 while (PoolUnitSize
> 0) {
456 // PAGE_TABLE_POOL_UNIT_SIZE and PAGE_TABLE_POOL_ALIGNMENT are fit in
457 // one page (2MB). Then we don't need to update attributes for pages
458 // crossing page directory. ASSERT below is for that purpose.
460 ASSERT (Index
< EFI_PAGE_SIZE
/sizeof (UINT64
));
462 PageTable
[Index
] &= ~(UINT64
)IA32_PG_RW
;
463 PoolUnitSize
-= LevelSize
[Level
];
473 // The smaller granularity of page must be needed.
477 NewPageTable
= AllocatePageTableMemory (1);
478 ASSERT (NewPageTable
!= NULL
);
480 PhysicalAddress
= PageAttr
& LevelMask
[Level
];
482 EntryIndex
< EFI_PAGE_SIZE
/sizeof (UINT64
);
484 NewPageTable
[EntryIndex
] = PhysicalAddress
| AddressEncMask
|
485 IA32_PG_P
| IA32_PG_RW
;
487 NewPageTable
[EntryIndex
] |= IA32_PG_PS
;
489 PhysicalAddress
+= LevelSize
[Level
- 1];
492 PageTable
[Index
] = (UINT64
)(UINTN
)NewPageTable
| AddressEncMask
|
493 IA32_PG_P
| IA32_PG_RW
;
494 PageTable
= NewPageTable
;
500 Prevent the memory pages used for page table from been overwritten.
502 @param[in] PageTableBase Base address of page table (CR3).
503 @param[in] Level4Paging Level 4 paging flag.
507 EnablePageTableProtection (
508 IN UINTN PageTableBase
,
509 IN BOOLEAN Level4Paging
512 PAGE_TABLE_POOL
*HeadPool
;
513 PAGE_TABLE_POOL
*Pool
;
515 EFI_PHYSICAL_ADDRESS Address
;
517 if (mPageTablePool
== NULL
) {
522 // Disable write protection, because we need to mark page table to be write
525 AsmWriteCr0 (AsmReadCr0() & ~CR0_WP
);
528 // SetPageTablePoolReadOnly might update mPageTablePool. It's safer to
529 // remember original one in advance.
531 HeadPool
= mPageTablePool
;
534 Address
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)Pool
;
535 PoolSize
= Pool
->Offset
+ EFI_PAGES_TO_SIZE (Pool
->FreePages
);
538 // The size of one pool must be multiple of PAGE_TABLE_POOL_UNIT_SIZE, which
539 // is one of page size of the processor (2MB by default). Let's apply the
540 // protection to them one by one.
542 while (PoolSize
> 0) {
543 SetPageTablePoolReadOnly(PageTableBase
, Address
, Level4Paging
);
544 Address
+= PAGE_TABLE_POOL_UNIT_SIZE
;
545 PoolSize
-= PAGE_TABLE_POOL_UNIT_SIZE
;
548 Pool
= Pool
->NextPool
;
549 } while (Pool
!= HeadPool
);
552 // Enable write protection, after page table attribute updated.
554 AsmWriteCr0 (AsmReadCr0() | CR0_WP
);
558 Allocates and fills in the Page Directory and Page Table Entries to
559 establish a 1:1 Virtual to Physical mapping.
561 @param[in] StackBase Stack base address.
562 @param[in] StackSize Stack size.
564 @return The address of 4 level page map.
568 CreateIdentityMappingPageTables (
569 IN EFI_PHYSICAL_ADDRESS StackBase
,
575 UINT8 PhysicalAddressBits
;
576 EFI_PHYSICAL_ADDRESS PageAddress
;
577 UINTN IndexOfPml4Entries
;
578 UINTN IndexOfPdpEntries
;
579 UINTN IndexOfPageDirectoryEntries
;
580 UINT32 NumberOfPml4EntriesNeeded
;
581 UINT32 NumberOfPdpEntriesNeeded
;
582 PAGE_MAP_AND_DIRECTORY_POINTER
*PageMapLevel4Entry
;
583 PAGE_MAP_AND_DIRECTORY_POINTER
*PageMap
;
584 PAGE_MAP_AND_DIRECTORY_POINTER
*PageDirectoryPointerEntry
;
585 PAGE_TABLE_ENTRY
*PageDirectoryEntry
;
587 UINTN BigPageAddress
;
589 BOOLEAN Page1GSupport
;
590 PAGE_TABLE_1G_ENTRY
*PageDirectory1GEntry
;
591 UINT64 AddressEncMask
;
594 // Make sure AddressEncMask is contained to smallest supported address field
596 AddressEncMask
= PcdGet64 (PcdPteMemoryEncryptionAddressOrMask
) & PAGING_1G_ADDRESS_MASK_64
;
598 Page1GSupport
= FALSE
;
599 if (PcdGetBool(PcdUse1GPageTable
)) {
600 AsmCpuid (0x80000000, &RegEax
, NULL
, NULL
, NULL
);
601 if (RegEax
>= 0x80000001) {
602 AsmCpuid (0x80000001, NULL
, NULL
, NULL
, &RegEdx
);
603 if ((RegEdx
& BIT26
) != 0) {
604 Page1GSupport
= TRUE
;
610 // Get physical address bits supported.
612 Hob
= GetFirstHob (EFI_HOB_TYPE_CPU
);
614 PhysicalAddressBits
= ((EFI_HOB_CPU
*) Hob
)->SizeOfMemorySpace
;
616 AsmCpuid (0x80000000, &RegEax
, NULL
, NULL
, NULL
);
617 if (RegEax
>= 0x80000008) {
618 AsmCpuid (0x80000008, &RegEax
, NULL
, NULL
, NULL
);
619 PhysicalAddressBits
= (UINT8
) RegEax
;
621 PhysicalAddressBits
= 36;
626 // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.
628 ASSERT (PhysicalAddressBits
<= 52);
629 if (PhysicalAddressBits
> 48) {
630 PhysicalAddressBits
= 48;
634 // Calculate the table entries needed.
636 if (PhysicalAddressBits
<= 39 ) {
637 NumberOfPml4EntriesNeeded
= 1;
638 NumberOfPdpEntriesNeeded
= (UINT32
)LShiftU64 (1, (PhysicalAddressBits
- 30));
640 NumberOfPml4EntriesNeeded
= (UINT32
)LShiftU64 (1, (PhysicalAddressBits
- 39));
641 NumberOfPdpEntriesNeeded
= 512;
645 // Pre-allocate big pages to avoid later allocations.
647 if (!Page1GSupport
) {
648 TotalPagesNum
= (NumberOfPdpEntriesNeeded
+ 1) * NumberOfPml4EntriesNeeded
+ 1;
650 TotalPagesNum
= NumberOfPml4EntriesNeeded
+ 1;
652 BigPageAddress
= (UINTN
) AllocatePageTableMemory (TotalPagesNum
);
653 ASSERT (BigPageAddress
!= 0);
656 // By architecture only one PageMapLevel4 exists - so lets allocate storage for it.
658 PageMap
= (VOID
*) BigPageAddress
;
659 BigPageAddress
+= SIZE_4KB
;
661 PageMapLevel4Entry
= PageMap
;
663 for (IndexOfPml4Entries
= 0; IndexOfPml4Entries
< NumberOfPml4EntriesNeeded
; IndexOfPml4Entries
++, PageMapLevel4Entry
++) {
665 // Each PML4 entry points to a page of Page Directory Pointer entires.
666 // So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.
668 PageDirectoryPointerEntry
= (VOID
*) BigPageAddress
;
669 BigPageAddress
+= SIZE_4KB
;
674 PageMapLevel4Entry
->Uint64
= (UINT64
)(UINTN
)PageDirectoryPointerEntry
| AddressEncMask
;
675 PageMapLevel4Entry
->Bits
.ReadWrite
= 1;
676 PageMapLevel4Entry
->Bits
.Present
= 1;
679 PageDirectory1GEntry
= (VOID
*) PageDirectoryPointerEntry
;
681 for (IndexOfPageDirectoryEntries
= 0; IndexOfPageDirectoryEntries
< 512; IndexOfPageDirectoryEntries
++, PageDirectory1GEntry
++, PageAddress
+= SIZE_1GB
) {
682 if (ToSplitPageTable (PageAddress
, SIZE_1GB
, StackBase
, StackSize
)) {
683 Split1GPageTo2M (PageAddress
, (UINT64
*) PageDirectory1GEntry
, StackBase
, StackSize
);
686 // Fill in the Page Directory entries
688 PageDirectory1GEntry
->Uint64
= (UINT64
)PageAddress
| AddressEncMask
;
689 PageDirectory1GEntry
->Bits
.ReadWrite
= 1;
690 PageDirectory1GEntry
->Bits
.Present
= 1;
691 PageDirectory1GEntry
->Bits
.MustBe1
= 1;
695 for (IndexOfPdpEntries
= 0; IndexOfPdpEntries
< NumberOfPdpEntriesNeeded
; IndexOfPdpEntries
++, PageDirectoryPointerEntry
++) {
697 // Each Directory Pointer entries points to a page of Page Directory entires.
698 // So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.
700 PageDirectoryEntry
= (VOID
*) BigPageAddress
;
701 BigPageAddress
+= SIZE_4KB
;
704 // Fill in a Page Directory Pointer Entries
706 PageDirectoryPointerEntry
->Uint64
= (UINT64
)(UINTN
)PageDirectoryEntry
| AddressEncMask
;
707 PageDirectoryPointerEntry
->Bits
.ReadWrite
= 1;
708 PageDirectoryPointerEntry
->Bits
.Present
= 1;
710 for (IndexOfPageDirectoryEntries
= 0; IndexOfPageDirectoryEntries
< 512; IndexOfPageDirectoryEntries
++, PageDirectoryEntry
++, PageAddress
+= SIZE_2MB
) {
711 if (ToSplitPageTable (PageAddress
, SIZE_2MB
, StackBase
, StackSize
)) {
713 // Need to split this 2M page that covers NULL or stack range.
715 Split2MPageTo4K (PageAddress
, (UINT64
*) PageDirectoryEntry
, StackBase
, StackSize
);
718 // Fill in the Page Directory entries
720 PageDirectoryEntry
->Uint64
= (UINT64
)PageAddress
| AddressEncMask
;
721 PageDirectoryEntry
->Bits
.ReadWrite
= 1;
722 PageDirectoryEntry
->Bits
.Present
= 1;
723 PageDirectoryEntry
->Bits
.MustBe1
= 1;
728 for (; IndexOfPdpEntries
< 512; IndexOfPdpEntries
++, PageDirectoryPointerEntry
++) {
730 PageDirectoryPointerEntry
,
731 sizeof(PAGE_MAP_AND_DIRECTORY_POINTER
)
738 // For the PML4 entries we are not using fill in a null entry.
740 for (; IndexOfPml4Entries
< 512; IndexOfPml4Entries
++, PageMapLevel4Entry
++) {
743 sizeof (PAGE_MAP_AND_DIRECTORY_POINTER
)
748 // Protect the page table by marking the memory used for page table to be
751 EnablePageTableProtection ((UINTN
)PageMap
, TRUE
);
753 if (PcdGetBool (PcdSetNxForStack
)) {
754 EnableExecuteDisableBit ();
757 return (UINTN
)PageMap
;