2 x64 Virtual Memory Management Services in the form of an IA-32 driver.
3 Used to establish a 1:1 Virtual to Physical Mapping that is required to
4 enter Long Mode (x64 64-bit mode).
6 While we make a 1:1 mapping (identity mapping) for all physical pages
7 we still need to use the MTRR's to ensure that the cachability attributes
8 for all memory regions is correct.
10 The basic idea is to use 2MB page table entries where ever possible. If
11 more granularity of cachability is required then 4K page tables are used.
14 1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel
15 2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
16 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
18 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
19 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
21 SPDX-License-Identifier: BSD-2-Clause-Patent
25 #include <Register/Intel/Cpuid.h>
27 #include "VirtualMemory.h"
30 // Global variable to keep track current available memory used as page table.
32 PAGE_TABLE_POOL
*mPageTablePool
= NULL
;
35 Clear legacy memory located at the first 4K-page, if available.
37 This function traverses the whole HOB list to check if memory from 0 to 4095
38 exists and has not been allocated, and then clear it if so.
40 @param HobStart The start of HobList passed to DxeCore.
48 EFI_PEI_HOB_POINTERS RscHob
;
49 EFI_PEI_HOB_POINTERS MemHob
;
52 RscHob
.Raw
= HobStart
;
53 MemHob
.Raw
= HobStart
;
57 // Check if page 0 exists and free
59 while ((RscHob
.Raw
= GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR
,
60 RscHob
.Raw
)) != NULL
) {
61 if (RscHob
.ResourceDescriptor
->ResourceType
== EFI_RESOURCE_SYSTEM_MEMORY
&&
62 RscHob
.ResourceDescriptor
->PhysicalStart
== 0) {
65 // Make sure memory at 0-4095 has not been allocated.
67 while ((MemHob
.Raw
= GetNextHob (EFI_HOB_TYPE_MEMORY_ALLOCATION
,
68 MemHob
.Raw
)) != NULL
) {
69 if (MemHob
.MemoryAllocation
->AllocDescriptor
.MemoryBaseAddress
74 MemHob
.Raw
= GET_NEXT_HOB (MemHob
);
78 RscHob
.Raw
= GET_NEXT_HOB (RscHob
);
82 DEBUG ((DEBUG_INFO
, "Clearing first 4K-page!\r\n"));
83 SetMem (NULL
, EFI_PAGE_SIZE
, 0);
90 Return configure status of NULL pointer detection feature.
92 @return TRUE NULL pointer detection feature is enabled
93 @return FALSE NULL pointer detection feature is disabled
97 IsNullDetectionEnabled (
101 return ((PcdGet8 (PcdNullPointerDetectionPropertyMask
) & BIT0
) != 0);
105 The function will check if Execute Disable Bit is available.
107 @retval TRUE Execute Disable Bit is available.
108 @retval FALSE Execute Disable Bit is not available.
112 IsExecuteDisableBitAvailable (
121 AsmCpuid (0x80000000, &RegEax
, NULL
, NULL
, NULL
);
122 if (RegEax
>= 0x80000001) {
123 AsmCpuid (0x80000001, NULL
, NULL
, NULL
, &RegEdx
);
124 if ((RegEdx
& BIT20
) != 0) {
126 // Bit 20: Execute Disable Bit available.
136 Check if Execute Disable Bit (IA32_EFER.NXE) should be enabled or not.
138 @retval TRUE IA32_EFER.NXE should be enabled.
139 @retval FALSE IA32_EFER.NXE should not be enabled.
143 IsEnableNonExecNeeded (
147 if (!IsExecuteDisableBitAvailable ()) {
152 // XD flag (BIT63) in page table entry is only valid if IA32_EFER.NXE is set.
153 // Features controlled by Following PCDs need this feature to be enabled.
155 return (PcdGetBool (PcdSetNxForStack
) ||
156 PcdGet64 (PcdDxeNxMemoryProtectionPolicy
) != 0 ||
157 PcdGet32 (PcdImageProtectionPolicy
) != 0);
161 Enable Execute Disable Bit.
165 EnableExecuteDisableBit (
171 MsrRegisters
= AsmReadMsr64 (0xC0000080);
172 MsrRegisters
|= BIT11
;
173 AsmWriteMsr64 (0xC0000080, MsrRegisters
);
177 The function will check if page table entry should be splitted to smaller
180 @param Address Physical memory address.
181 @param Size Size of the given physical memory.
182 @param StackBase Base address of stack.
183 @param StackSize Size of stack.
185 @retval TRUE Page table should be split.
186 @retval FALSE Page table should not be split.
190 IN EFI_PHYSICAL_ADDRESS Address
,
192 IN EFI_PHYSICAL_ADDRESS StackBase
,
196 if (IsNullDetectionEnabled () && Address
== 0) {
200 if (PcdGetBool (PcdCpuStackGuard
)) {
201 if (StackBase
>= Address
&& StackBase
< (Address
+ Size
)) {
206 if (PcdGetBool (PcdSetNxForStack
)) {
207 if ((Address
< StackBase
+ StackSize
) && ((Address
+ Size
) > StackBase
)) {
215 Initialize a buffer pool for page table use only.
217 To reduce the potential split operation on page table, the pages reserved for
218 page table should be allocated in the times of PAGE_TABLE_POOL_UNIT_PAGES and
219 at the boundary of PAGE_TABLE_POOL_ALIGNMENT. So the page pool is always
220 initialized with number of pages greater than or equal to the given PoolPages.
222 Once the pages in the pool are used up, this method should be called again to
223 reserve at least another PAGE_TABLE_POOL_UNIT_PAGES. But usually this won't
226 @param PoolPages The least page number of the pool to be created.
228 @retval TRUE The pool is initialized successfully.
229 @retval FALSE The memory is out of resource.
232 InitializePageTablePool (
239 // Always reserve at least PAGE_TABLE_POOL_UNIT_PAGES, including one page for
242 PoolPages
+= 1; // Add one page for header.
243 PoolPages
= ((PoolPages
- 1) / PAGE_TABLE_POOL_UNIT_PAGES
+ 1) *
244 PAGE_TABLE_POOL_UNIT_PAGES
;
245 Buffer
= AllocateAlignedPages (PoolPages
, PAGE_TABLE_POOL_ALIGNMENT
);
246 if (Buffer
== NULL
) {
247 DEBUG ((DEBUG_ERROR
, "ERROR: Out of aligned pages\r\n"));
252 // Link all pools into a list for easier track later.
254 if (mPageTablePool
== NULL
) {
255 mPageTablePool
= Buffer
;
256 mPageTablePool
->NextPool
= mPageTablePool
;
258 ((PAGE_TABLE_POOL
*)Buffer
)->NextPool
= mPageTablePool
->NextPool
;
259 mPageTablePool
->NextPool
= Buffer
;
260 mPageTablePool
= Buffer
;
264 // Reserve one page for pool header.
266 mPageTablePool
->FreePages
= PoolPages
- 1;
267 mPageTablePool
->Offset
= EFI_PAGES_TO_SIZE (1);
273 This API provides a way to allocate memory for page table.
275 This API can be called more than once to allocate memory for page tables.
277 Allocates the number of 4KB pages and returns a pointer to the allocated
278 buffer. The buffer returned is aligned on a 4KB boundary.
280 If Pages is 0, then NULL is returned.
281 If there is not enough memory remaining to satisfy the request, then NULL is
284 @param Pages The number of 4 KB pages to allocate.
286 @return A pointer to the allocated buffer or NULL if allocation fails.
290 AllocatePageTableMemory (
301 // Renew the pool if necessary.
303 if (mPageTablePool
== NULL
||
304 Pages
> mPageTablePool
->FreePages
) {
305 if (!InitializePageTablePool (Pages
)) {
310 Buffer
= (UINT8
*)mPageTablePool
+ mPageTablePool
->Offset
;
312 mPageTablePool
->Offset
+= EFI_PAGES_TO_SIZE (Pages
);
313 mPageTablePool
->FreePages
-= Pages
;
321 @param[in] PhysicalAddress Start physical address the 2M page covered.
322 @param[in, out] PageEntry2M Pointer to 2M page entry.
323 @param[in] StackBase Stack base address.
324 @param[in] StackSize Stack size.
329 IN EFI_PHYSICAL_ADDRESS PhysicalAddress
,
330 IN OUT UINT64
*PageEntry2M
,
331 IN EFI_PHYSICAL_ADDRESS StackBase
,
335 EFI_PHYSICAL_ADDRESS PhysicalAddress4K
;
336 UINTN IndexOfPageTableEntries
;
337 PAGE_TABLE_4K_ENTRY
*PageTableEntry
;
338 UINT64 AddressEncMask
;
341 // Make sure AddressEncMask is contained to smallest supported address field
343 AddressEncMask
= PcdGet64 (PcdPteMemoryEncryptionAddressOrMask
) & PAGING_1G_ADDRESS_MASK_64
;
345 PageTableEntry
= AllocatePageTableMemory (1);
346 ASSERT (PageTableEntry
!= NULL
);
349 // Fill in 2M page entry.
351 *PageEntry2M
= (UINT64
) (UINTN
) PageTableEntry
| AddressEncMask
| IA32_PG_P
| IA32_PG_RW
;
353 PhysicalAddress4K
= PhysicalAddress
;
354 for (IndexOfPageTableEntries
= 0; IndexOfPageTableEntries
< 512; IndexOfPageTableEntries
++, PageTableEntry
++, PhysicalAddress4K
+= SIZE_4KB
) {
356 // Fill in the Page Table entries
358 PageTableEntry
->Uint64
= (UINT64
) PhysicalAddress4K
| AddressEncMask
;
359 PageTableEntry
->Bits
.ReadWrite
= 1;
361 if ((IsNullDetectionEnabled () && PhysicalAddress4K
== 0) ||
362 (PcdGetBool (PcdCpuStackGuard
) && PhysicalAddress4K
== StackBase
)) {
363 PageTableEntry
->Bits
.Present
= 0;
365 PageTableEntry
->Bits
.Present
= 1;
368 if (PcdGetBool (PcdSetNxForStack
)
369 && (PhysicalAddress4K
>= StackBase
)
370 && (PhysicalAddress4K
< StackBase
+ StackSize
)) {
372 // Set Nx bit for stack.
374 PageTableEntry
->Bits
.Nx
= 1;
382 @param[in] PhysicalAddress Start physical address the 1G page covered.
383 @param[in, out] PageEntry1G Pointer to 1G page entry.
384 @param[in] StackBase Stack base address.
385 @param[in] StackSize Stack size.
390 IN EFI_PHYSICAL_ADDRESS PhysicalAddress
,
391 IN OUT UINT64
*PageEntry1G
,
392 IN EFI_PHYSICAL_ADDRESS StackBase
,
396 EFI_PHYSICAL_ADDRESS PhysicalAddress2M
;
397 UINTN IndexOfPageDirectoryEntries
;
398 PAGE_TABLE_ENTRY
*PageDirectoryEntry
;
399 UINT64 AddressEncMask
;
402 // Make sure AddressEncMask is contained to smallest supported address field
404 AddressEncMask
= PcdGet64 (PcdPteMemoryEncryptionAddressOrMask
) & PAGING_1G_ADDRESS_MASK_64
;
406 PageDirectoryEntry
= AllocatePageTableMemory (1);
407 ASSERT (PageDirectoryEntry
!= NULL
);
410 // Fill in 1G page entry.
412 *PageEntry1G
= (UINT64
) (UINTN
) PageDirectoryEntry
| AddressEncMask
| IA32_PG_P
| IA32_PG_RW
;
414 PhysicalAddress2M
= PhysicalAddress
;
415 for (IndexOfPageDirectoryEntries
= 0; IndexOfPageDirectoryEntries
< 512; IndexOfPageDirectoryEntries
++, PageDirectoryEntry
++, PhysicalAddress2M
+= SIZE_2MB
) {
416 if (ToSplitPageTable (PhysicalAddress2M
, SIZE_2MB
, StackBase
, StackSize
)) {
418 // Need to split this 2M page that covers NULL or stack range.
420 Split2MPageTo4K (PhysicalAddress2M
, (UINT64
*) PageDirectoryEntry
, StackBase
, StackSize
);
423 // Fill in the Page Directory entries
425 PageDirectoryEntry
->Uint64
= (UINT64
) PhysicalAddress2M
| AddressEncMask
;
426 PageDirectoryEntry
->Bits
.ReadWrite
= 1;
427 PageDirectoryEntry
->Bits
.Present
= 1;
428 PageDirectoryEntry
->Bits
.MustBe1
= 1;
434 Set one page of page table pool memory to be read-only.
436 @param[in] PageTableBase Base address of page table (CR3).
437 @param[in] Address Start address of a page to be set as read-only.
438 @param[in] Level4Paging Level 4 paging flag.
442 SetPageTablePoolReadOnly (
443 IN UINTN PageTableBase
,
444 IN EFI_PHYSICAL_ADDRESS Address
,
445 IN BOOLEAN Level4Paging
450 UINT64 AddressEncMask
;
451 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
453 UINT64
*NewPageTable
;
461 ASSERT (PageTableBase
!= 0);
464 // Since the page table is always from page table pool, which is always
465 // located at the boundary of PcdPageTablePoolAlignment, we just need to
466 // set the whole pool unit to be read-only.
468 Address
= Address
& PAGE_TABLE_POOL_ALIGN_MASK
;
470 LevelShift
[1] = PAGING_L1_ADDRESS_SHIFT
;
471 LevelShift
[2] = PAGING_L2_ADDRESS_SHIFT
;
472 LevelShift
[3] = PAGING_L3_ADDRESS_SHIFT
;
473 LevelShift
[4] = PAGING_L4_ADDRESS_SHIFT
;
475 LevelMask
[1] = PAGING_4K_ADDRESS_MASK_64
;
476 LevelMask
[2] = PAGING_2M_ADDRESS_MASK_64
;
477 LevelMask
[3] = PAGING_1G_ADDRESS_MASK_64
;
478 LevelMask
[4] = PAGING_1G_ADDRESS_MASK_64
;
480 LevelSize
[1] = SIZE_4KB
;
481 LevelSize
[2] = SIZE_2MB
;
482 LevelSize
[3] = SIZE_1GB
;
483 LevelSize
[4] = SIZE_512GB
;
485 AddressEncMask
= PcdGet64 (PcdPteMemoryEncryptionAddressOrMask
) &
486 PAGING_1G_ADDRESS_MASK_64
;
487 PageTable
= (UINT64
*)(UINTN
)PageTableBase
;
488 PoolUnitSize
= PAGE_TABLE_POOL_UNIT_SIZE
;
490 for (Level
= (Level4Paging
) ? 4 : 3; Level
> 0; --Level
) {
491 Index
= ((UINTN
)RShiftU64 (Address
, LevelShift
[Level
]));
492 Index
&= PAGING_PAE_INDEX_MASK
;
494 PageAttr
= PageTable
[Index
];
495 if ((PageAttr
& IA32_PG_PS
) == 0) {
497 // Go to next level of table.
499 PageTable
= (UINT64
*)(UINTN
)(PageAttr
& ~AddressEncMask
&
500 PAGING_4K_ADDRESS_MASK_64
);
504 if (PoolUnitSize
>= LevelSize
[Level
]) {
506 // Clear R/W bit if current page granularity is not larger than pool unit
509 if ((PageAttr
& IA32_PG_RW
) != 0) {
510 while (PoolUnitSize
> 0) {
512 // PAGE_TABLE_POOL_UNIT_SIZE and PAGE_TABLE_POOL_ALIGNMENT are fit in
513 // one page (2MB). Then we don't need to update attributes for pages
514 // crossing page directory. ASSERT below is for that purpose.
516 ASSERT (Index
< EFI_PAGE_SIZE
/sizeof (UINT64
));
518 PageTable
[Index
] &= ~(UINT64
)IA32_PG_RW
;
519 PoolUnitSize
-= LevelSize
[Level
];
529 // The smaller granularity of page must be needed.
533 NewPageTable
= AllocatePageTableMemory (1);
534 ASSERT (NewPageTable
!= NULL
);
536 PhysicalAddress
= PageAttr
& LevelMask
[Level
];
538 EntryIndex
< EFI_PAGE_SIZE
/sizeof (UINT64
);
540 NewPageTable
[EntryIndex
] = PhysicalAddress
| AddressEncMask
|
541 IA32_PG_P
| IA32_PG_RW
;
543 NewPageTable
[EntryIndex
] |= IA32_PG_PS
;
545 PhysicalAddress
+= LevelSize
[Level
- 1];
548 PageTable
[Index
] = (UINT64
)(UINTN
)NewPageTable
| AddressEncMask
|
549 IA32_PG_P
| IA32_PG_RW
;
550 PageTable
= NewPageTable
;
556 Prevent the memory pages used for page table from been overwritten.
558 @param[in] PageTableBase Base address of page table (CR3).
559 @param[in] Level4Paging Level 4 paging flag.
563 EnablePageTableProtection (
564 IN UINTN PageTableBase
,
565 IN BOOLEAN Level4Paging
568 PAGE_TABLE_POOL
*HeadPool
;
569 PAGE_TABLE_POOL
*Pool
;
571 EFI_PHYSICAL_ADDRESS Address
;
573 if (mPageTablePool
== NULL
) {
578 // Disable write protection, because we need to mark page table to be write
581 AsmWriteCr0 (AsmReadCr0() & ~CR0_WP
);
584 // SetPageTablePoolReadOnly might update mPageTablePool. It's safer to
585 // remember original one in advance.
587 HeadPool
= mPageTablePool
;
590 Address
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)Pool
;
591 PoolSize
= Pool
->Offset
+ EFI_PAGES_TO_SIZE (Pool
->FreePages
);
594 // The size of one pool must be multiple of PAGE_TABLE_POOL_UNIT_SIZE, which
595 // is one of page size of the processor (2MB by default). Let's apply the
596 // protection to them one by one.
598 while (PoolSize
> 0) {
599 SetPageTablePoolReadOnly(PageTableBase
, Address
, Level4Paging
);
600 Address
+= PAGE_TABLE_POOL_UNIT_SIZE
;
601 PoolSize
-= PAGE_TABLE_POOL_UNIT_SIZE
;
604 Pool
= Pool
->NextPool
;
605 } while (Pool
!= HeadPool
);
608 // Enable write protection, after page table attribute updated.
610 AsmWriteCr0 (AsmReadCr0() | CR0_WP
);
614 Allocates and fills in the Page Directory and Page Table Entries to
615 establish a 1:1 Virtual to Physical mapping.
617 @param[in] StackBase Stack base address.
618 @param[in] StackSize Stack size.
620 @return The address of 4 level page map.
624 CreateIdentityMappingPageTables (
625 IN EFI_PHYSICAL_ADDRESS StackBase
,
630 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX EcxFlags
;
632 UINT8 PhysicalAddressBits
;
633 EFI_PHYSICAL_ADDRESS PageAddress
;
634 UINTN IndexOfPml5Entries
;
635 UINTN IndexOfPml4Entries
;
636 UINTN IndexOfPdpEntries
;
637 UINTN IndexOfPageDirectoryEntries
;
638 UINT32 NumberOfPml5EntriesNeeded
;
639 UINT32 NumberOfPml4EntriesNeeded
;
640 UINT32 NumberOfPdpEntriesNeeded
;
641 PAGE_MAP_AND_DIRECTORY_POINTER
*PageMapLevel5Entry
;
642 PAGE_MAP_AND_DIRECTORY_POINTER
*PageMapLevel4Entry
;
643 PAGE_MAP_AND_DIRECTORY_POINTER
*PageMap
;
644 PAGE_MAP_AND_DIRECTORY_POINTER
*PageDirectoryPointerEntry
;
645 PAGE_TABLE_ENTRY
*PageDirectoryEntry
;
647 UINTN BigPageAddress
;
649 BOOLEAN Page5LevelSupport
;
650 BOOLEAN Page1GSupport
;
651 PAGE_TABLE_1G_ENTRY
*PageDirectory1GEntry
;
652 UINT64 AddressEncMask
;
656 // Make sure AddressEncMask is contained to smallest supported address field
658 AddressEncMask
= PcdGet64 (PcdPteMemoryEncryptionAddressOrMask
) & PAGING_1G_ADDRESS_MASK_64
;
660 Page1GSupport
= FALSE
;
661 if (PcdGetBool(PcdUse1GPageTable
)) {
662 AsmCpuid (0x80000000, &RegEax
, NULL
, NULL
, NULL
);
663 if (RegEax
>= 0x80000001) {
664 AsmCpuid (0x80000001, NULL
, NULL
, NULL
, &RegEdx
);
665 if ((RegEdx
& BIT26
) != 0) {
666 Page1GSupport
= TRUE
;
672 // Get physical address bits supported.
674 Hob
= GetFirstHob (EFI_HOB_TYPE_CPU
);
676 PhysicalAddressBits
= ((EFI_HOB_CPU
*) Hob
)->SizeOfMemorySpace
;
678 AsmCpuid (0x80000000, &RegEax
, NULL
, NULL
, NULL
);
679 if (RegEax
>= 0x80000008) {
680 AsmCpuid (0x80000008, &RegEax
, NULL
, NULL
, NULL
);
681 PhysicalAddressBits
= (UINT8
) RegEax
;
683 PhysicalAddressBits
= 36;
687 Page5LevelSupport
= FALSE
;
688 if (PcdGetBool (PcdUse5LevelPageTable
)) {
690 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS
, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO
, NULL
,
691 &EcxFlags
.Uint32
, NULL
, NULL
693 if (EcxFlags
.Bits
.FiveLevelPage
!= 0) {
694 Page5LevelSupport
= TRUE
;
698 DEBUG ((DEBUG_INFO
, "AddressBits=%u 5LevelPaging=%u 1GPage=%u\n", PhysicalAddressBits
, Page5LevelSupport
, Page1GSupport
));
701 // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses
702 // when 5-Level Paging is disabled,
703 // due to either unsupported by HW, or disabled by PCD.
705 ASSERT (PhysicalAddressBits
<= 52);
706 if (!Page5LevelSupport
&& PhysicalAddressBits
> 48) {
707 PhysicalAddressBits
= 48;
711 // Calculate the table entries needed.
713 NumberOfPml5EntriesNeeded
= 1;
714 if (PhysicalAddressBits
> 48) {
715 NumberOfPml5EntriesNeeded
= (UINT32
) LShiftU64 (1, PhysicalAddressBits
- 48);
716 PhysicalAddressBits
= 48;
719 NumberOfPml4EntriesNeeded
= 1;
720 if (PhysicalAddressBits
> 39) {
721 NumberOfPml4EntriesNeeded
= (UINT32
) LShiftU64 (1, PhysicalAddressBits
- 39);
722 PhysicalAddressBits
= 39;
725 NumberOfPdpEntriesNeeded
= 1;
726 ASSERT (PhysicalAddressBits
> 30);
727 NumberOfPdpEntriesNeeded
= (UINT32
) LShiftU64 (1, PhysicalAddressBits
- 30);
730 // Pre-allocate big pages to avoid later allocations.
732 if (!Page1GSupport
) {
733 TotalPagesNum
= ((NumberOfPdpEntriesNeeded
+ 1) * NumberOfPml4EntriesNeeded
+ 1) * NumberOfPml5EntriesNeeded
+ 1;
735 TotalPagesNum
= (NumberOfPml4EntriesNeeded
+ 1) * NumberOfPml5EntriesNeeded
+ 1;
739 // Substract the one page occupied by PML5 entries if 5-Level Paging is disabled.
741 if (!Page5LevelSupport
) {
745 DEBUG ((DEBUG_INFO
, "Pml5=%u Pml4=%u Pdp=%u TotalPage=%Lu\n",
746 NumberOfPml5EntriesNeeded
, NumberOfPml4EntriesNeeded
,
747 NumberOfPdpEntriesNeeded
, (UINT64
)TotalPagesNum
));
749 BigPageAddress
= (UINTN
) AllocatePageTableMemory (TotalPagesNum
);
750 ASSERT (BigPageAddress
!= 0);
753 // By architecture only one PageMapLevel4 exists - so lets allocate storage for it.
755 PageMap
= (VOID
*) BigPageAddress
;
756 if (Page5LevelSupport
) {
758 // By architecture only one PageMapLevel5 exists - so lets allocate storage for it.
760 PageMapLevel5Entry
= PageMap
;
761 BigPageAddress
+= SIZE_4KB
;
765 for ( IndexOfPml5Entries
= 0
766 ; IndexOfPml5Entries
< NumberOfPml5EntriesNeeded
767 ; IndexOfPml5Entries
++, PageMapLevel5Entry
++) {
769 // Each PML5 entry points to a page of PML4 entires.
770 // So lets allocate space for them and fill them in in the IndexOfPml4Entries loop.
771 // When 5-Level Paging is disabled, below allocation happens only once.
773 PageMapLevel4Entry
= (VOID
*) BigPageAddress
;
774 BigPageAddress
+= SIZE_4KB
;
776 if (Page5LevelSupport
) {
780 PageMapLevel5Entry
->Uint64
= (UINT64
) (UINTN
) PageMapLevel4Entry
| AddressEncMask
;
781 PageMapLevel5Entry
->Bits
.ReadWrite
= 1;
782 PageMapLevel5Entry
->Bits
.Present
= 1;
785 for ( IndexOfPml4Entries
= 0
786 ; IndexOfPml4Entries
< (NumberOfPml5EntriesNeeded
== 1 ? NumberOfPml4EntriesNeeded
: 512)
787 ; IndexOfPml4Entries
++, PageMapLevel4Entry
++) {
789 // Each PML4 entry points to a page of Page Directory Pointer entires.
790 // So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.
792 PageDirectoryPointerEntry
= (VOID
*) BigPageAddress
;
793 BigPageAddress
+= SIZE_4KB
;
798 PageMapLevel4Entry
->Uint64
= (UINT64
)(UINTN
)PageDirectoryPointerEntry
| AddressEncMask
;
799 PageMapLevel4Entry
->Bits
.ReadWrite
= 1;
800 PageMapLevel4Entry
->Bits
.Present
= 1;
803 PageDirectory1GEntry
= (VOID
*) PageDirectoryPointerEntry
;
805 for (IndexOfPageDirectoryEntries
= 0; IndexOfPageDirectoryEntries
< 512; IndexOfPageDirectoryEntries
++, PageDirectory1GEntry
++, PageAddress
+= SIZE_1GB
) {
806 if (ToSplitPageTable (PageAddress
, SIZE_1GB
, StackBase
, StackSize
)) {
807 Split1GPageTo2M (PageAddress
, (UINT64
*) PageDirectory1GEntry
, StackBase
, StackSize
);
810 // Fill in the Page Directory entries
812 PageDirectory1GEntry
->Uint64
= (UINT64
)PageAddress
| AddressEncMask
;
813 PageDirectory1GEntry
->Bits
.ReadWrite
= 1;
814 PageDirectory1GEntry
->Bits
.Present
= 1;
815 PageDirectory1GEntry
->Bits
.MustBe1
= 1;
819 for ( IndexOfPdpEntries
= 0
820 ; IndexOfPdpEntries
< (NumberOfPml4EntriesNeeded
== 1 ? NumberOfPdpEntriesNeeded
: 512)
821 ; IndexOfPdpEntries
++, PageDirectoryPointerEntry
++) {
823 // Each Directory Pointer entries points to a page of Page Directory entires.
824 // So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.
826 PageDirectoryEntry
= (VOID
*) BigPageAddress
;
827 BigPageAddress
+= SIZE_4KB
;
830 // Fill in a Page Directory Pointer Entries
832 PageDirectoryPointerEntry
->Uint64
= (UINT64
)(UINTN
)PageDirectoryEntry
| AddressEncMask
;
833 PageDirectoryPointerEntry
->Bits
.ReadWrite
= 1;
834 PageDirectoryPointerEntry
->Bits
.Present
= 1;
836 for (IndexOfPageDirectoryEntries
= 0; IndexOfPageDirectoryEntries
< 512; IndexOfPageDirectoryEntries
++, PageDirectoryEntry
++, PageAddress
+= SIZE_2MB
) {
837 if (ToSplitPageTable (PageAddress
, SIZE_2MB
, StackBase
, StackSize
)) {
839 // Need to split this 2M page that covers NULL or stack range.
841 Split2MPageTo4K (PageAddress
, (UINT64
*) PageDirectoryEntry
, StackBase
, StackSize
);
844 // Fill in the Page Directory entries
846 PageDirectoryEntry
->Uint64
= (UINT64
)PageAddress
| AddressEncMask
;
847 PageDirectoryEntry
->Bits
.ReadWrite
= 1;
848 PageDirectoryEntry
->Bits
.Present
= 1;
849 PageDirectoryEntry
->Bits
.MustBe1
= 1;
855 // Fill with null entry for unused PDPTE
857 ZeroMem (PageDirectoryPointerEntry
, (512 - IndexOfPdpEntries
) * sizeof(PAGE_MAP_AND_DIRECTORY_POINTER
));
862 // For the PML4 entries we are not using fill in a null entry.
864 ZeroMem (PageMapLevel4Entry
, (512 - IndexOfPml4Entries
) * sizeof (PAGE_MAP_AND_DIRECTORY_POINTER
));
867 if (Page5LevelSupport
) {
868 Cr4
.UintN
= AsmReadCr4 ();
870 AsmWriteCr4 (Cr4
.UintN
);
872 // For the PML5 entries we are not using fill in a null entry.
874 ZeroMem (PageMapLevel5Entry
, (512 - IndexOfPml5Entries
) * sizeof (PAGE_MAP_AND_DIRECTORY_POINTER
));
878 // Protect the page table by marking the memory used for page table to be
881 EnablePageTableProtection ((UINTN
)PageMap
, TRUE
);
884 // Set IA32_EFER.NXE if necessary.
886 if (IsEnableNonExecNeeded ()) {
887 EnableExecuteDisableBit ();
890 return (UINTN
)PageMap
;