MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h

   1 /** @file
   2   x64 Long Mode Virtual Memory Management Definitions
   3
   4   References:
   5     1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel
   6     2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
   7     3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
   8     4) AMD64 Architecture Programmer's Manual Volume 2: System Programming
   9
  10 Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
  11 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
  12
  13 This program and the accompanying materials
  14 are licensed and made available under the terms and conditions of the BSD License
  15 which accompanies this distribution.  The full text of the license may be found at
  16 http://opensource.org/licenses/bsd-license.php
  17
  18 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  19 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  20
  21 **/
  22 #ifndef _VIRTUAL_MEMORY_H_
  23 #define _VIRTUAL_MEMORY_H_
  24
  25
  26 #define SYS_CODE64_SEL 0x38
  27
  28
  29 #pragma pack(1)
  30
  31 typedef union {
  32   struct {
  33     UINT32  LimitLow    : 16;
  34     UINT32  BaseLow     : 16;
  35     UINT32  BaseMid     : 8;
  36     UINT32  Type        : 4;
  37     UINT32  System      : 1;
  38     UINT32  Dpl         : 2;
  39     UINT32  Present     : 1;
  40     UINT32  LimitHigh   : 4;
  41     UINT32  Software    : 1;
  42     UINT32  Reserved    : 1;
  43     UINT32  DefaultSize : 1;
  44     UINT32  Granularity : 1;
  45     UINT32  BaseHigh    : 8;
  46   } Bits;
  47   UINT64  Uint64;
  48 } IA32_GDT;
  49
  50 typedef struct {
  51   IA32_IDT_GATE_DESCRIPTOR  Ia32IdtEntry;
  52   UINT32                    Offset32To63;
  53   UINT32                    Reserved;
  54 } X64_IDT_GATE_DESCRIPTOR;
  55
  56 //
  57 // Page-Map Level-4 Offset (PML4) and
  58 // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
  59 //
  60
  61 typedef union {
  62   struct {
  63     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  64     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  65     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  66     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  67     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  68     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  69     UINT64  Reserved:1;               // Reserved
  70     UINT64  MustBeZero:2;             // Must Be Zero
  71     UINT64  Available:3;              // Available for use by system software
  72     UINT64  PageTableBaseAddress:40;  // Page Table Base Address
  73     UINT64  AvabilableHigh:11;        // Available for use by system software
  74     UINT64  Nx:1;                     // No Execute bit
  75   } Bits;
  76   UINT64    Uint64;
  77 } PAGE_MAP_AND_DIRECTORY_POINTER;
  78
  79 //
  80 // Page Table Entry 4KB
  81 //
  82 typedef union {
  83   struct {
  84     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  85     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  86     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  87     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  88     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  89     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  90     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
  91     UINT64  PAT:1;                    //
  92     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
  93     UINT64  Available:3;              // Available for use by system software
  94     UINT64  PageTableBaseAddress:40;  // Page Table Base Address
  95     UINT64  AvabilableHigh:11;        // Available for use by system software
  96     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
  97   } Bits;
  98   UINT64    Uint64;
  99 } PAGE_TABLE_4K_ENTRY;
 100
 101 //
 102 // Page Table Entry 2MB
 103 //
 104 typedef union {
 105   struct {
 106     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
 107     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
 108     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
 109     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
 110     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
 111     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
 112     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
 113     UINT64  MustBe1:1;                // Must be 1
 114     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
 115     UINT64  Available:3;              // Available for use by system software
 116     UINT64  PAT:1;                    //
 117     UINT64  MustBeZero:8;             // Must be zero;
 118     UINT64  PageTableBaseAddress:31;  // Page Table Base Address
 119     UINT64  AvabilableHigh:11;        // Available for use by system software
 120     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
 121   } Bits;
 122   UINT64    Uint64;
 123 } PAGE_TABLE_ENTRY;
 124
 125 //
 126 // Page Table Entry 1GB
 127 //
 128 typedef union {
 129   struct {
 130     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
 131     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
 132     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
 133     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
 134     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
 135     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
 136     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
 137     UINT64  MustBe1:1;                // Must be 1
 138     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
 139     UINT64  Available:3;              // Available for use by system software
 140     UINT64  PAT:1;                    //
 141     UINT64  MustBeZero:17;            // Must be zero;
 142     UINT64  PageTableBaseAddress:22;  // Page Table Base Address
 143     UINT64  AvabilableHigh:11;        // Available for use by system software
 144     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
 145   } Bits;
 146   UINT64    Uint64;
 147 } PAGE_TABLE_1G_ENTRY;
 148
 149 #pragma pack()
 150
 151 #define IA32_PG_P                   BIT0
 152 #define IA32_PG_RW                  BIT1
 153
 154 #define PAGING_1G_ADDRESS_MASK_64   0x000FFFFFC0000000ull
 155
 156 /**
 157   Enable Execute Disable Bit.
 158
 159 **/
 160 VOID
 161 EnableExecuteDisableBit (
 162   VOID
 163   );
 164
 165 /**
 166   Split 2M page to 4K.
 167
 168   @param[in]      PhysicalAddress       Start physical address the 2M page covered.
 169   @param[in, out] PageEntry2M           Pointer to 2M page entry.
 170   @param[in]      StackBase             Stack base address.
 171   @param[in]      StackSize             Stack size.
 172
 173 **/
 174 VOID
 175 Split2MPageTo4K (
 176   IN EFI_PHYSICAL_ADDRESS               PhysicalAddress,
 177   IN OUT UINT64                         *PageEntry2M,
 178   IN EFI_PHYSICAL_ADDRESS               StackBase,
 179   IN UINTN                              StackSize
 180   );
 181
 182 /**
 183   Allocates and fills in the Page Directory and Page Table Entries to
 184   establish a 1:1 Virtual to Physical mapping.
 185
 186   @param[in] StackBase  Stack base address.
 187   @param[in] StackSize  Stack size.
 188
 189   @return The address of 4 level page map.
 190
 191 **/
 192 UINTN
 193 CreateIdentityMappingPageTables (
 194   IN EFI_PHYSICAL_ADDRESS   StackBase,
 195   IN UINTN                  StackSize
 196   );
 197
 198
 199 /**
 200
 201   Fix up the vector number in the vector code.
 202
 203   @param VectorBase   Base address of the vector handler.
 204   @param VectorNum    Index of vector.
 205
 206 **/
 207 VOID
 208 EFIAPI
 209 AsmVectorFixup (
 210   VOID    *VectorBase,
 211   UINT8   VectorNum
 212   );
 213
 214
 215 /**
 216
 217   Get the information of vector template.
 218
 219   @param TemplateBase   Base address of the template code.
 220
 221   @return               Size of the Template code.
 222
 223 **/
 224 UINTN
 225 EFIAPI
 226 AsmGetVectorTemplatInfo (
 227   OUT   VOID  **TemplateBase
 228   );
 229
 230 /**
 231   Clear legacy memory located at the first 4K-page.
 232
 233   This function traverses the whole HOB list to check if memory from 0 to 4095
 234   exists and has not been allocated, and then clear it if so.
 235
 236   @param HobStart         The start of HobList passed to DxeCore.
 237
 238 **/
 239 VOID
 240 ClearFirst4KPage (
 241   IN  VOID *HobStart
 242   );
 243
 244 /**
 245   Return configure status of NULL pointer detection feature.
 246
 247   @return TRUE   NULL pointer detection feature is enabled
 248   @return FALSE  NULL pointer detection feature is disabled
 249 **/
 250 BOOLEAN
 251 IsNullDetectionEnabled (
 252   VOID
 253   );
 254
 255 #endif