MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h

   1 /** @file
   2   x64 Long Mode Virtual Memory Management Definitions
   3
   4   References:
   5     1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel
   6     2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
   7     3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
   8     4) AMD64 Architecture Programmer's Manual Volume 2: System Programming
   9
  10 Copyright (c) 2006 - 2008, Intel Corporation. <BR>
  11 All rights reserved. This program and the accompanying materials
  12 are licensed and made available under the terms and conditions of the BSD License
  13 which accompanies this distribution.  The full text of the license may be found at
  14 http://opensource.org/licenses/bsd-license.php
  15
  16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  18
  19 **/
  20 #ifndef _VIRTUAL_MEMORY_H_
  21 #define _VIRTUAL_MEMORY_H_
  22
  23
  24 #define SYS_CODE64_SEL 0x38
  25
  26 #pragma pack(1)
  27
  28 typedef union {
  29   struct {
  30     UINT32  LimitLow    : 16;
  31     UINT32  BaseLow     : 16;
  32     UINT32  BaseMid     : 8;
  33     UINT32  Type        : 4;
  34     UINT32  System      : 1;
  35     UINT32  Dpl         : 2;
  36     UINT32  Present     : 1;
  37     UINT32  LimitHigh   : 4;
  38     UINT32  Software    : 1;
  39     UINT32  Reserved    : 1;
  40     UINT32  DefaultSize : 1;
  41     UINT32  Granularity : 1;
  42     UINT32  BaseHigh    : 8;
  43   } Bits;
  44   UINT64  Uint64;
  45 } IA32_GDT;
  46
  47 typedef struct {
  48   IA32_IDT_GATE_DESCRIPTOR  Ia32IdtEntry;
  49   UINT32                    Offset32To63;
  50   UINT32                    Reserved;
  51 } X64_IDT_GATE_DESCRIPTOR;
  52
  53 //
  54 // Page-Map Level-4 Offset (PML4) and
  55 // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
  56 //
  57
  58 typedef union {
  59   struct {
  60     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  61     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  62     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  63     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  64     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  65     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  66     UINT64  Reserved:1;               // Reserved
  67     UINT64  MustBeZero:2;             // Must Be Zero
  68     UINT64  Available:3;              // Available for use by system software
  69     UINT64  PageTableBaseAddress:40;  // Page Table Base Address
  70     UINT64  AvabilableHigh:11;        // Available for use by system software
  71     UINT64  Nx:1;                     // No Execute bit
  72   } Bits;
  73   UINT64    Uint64;
  74 } PAGE_MAP_AND_DIRECTORY_POINTER;
  75
  76 //
  77 // Page Table Entry 2MB
  78 //
  79 typedef union {
  80   struct {
  81     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  82     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  83     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  84     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  85     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  86     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  87     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
  88     UINT64  MustBe1:1;                // Must be 1
  89     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
  90     UINT64  Available:3;              // Available for use by system software
  91     UINT64  PAT:1;                    //
  92     UINT64  MustBeZero:8;             // Must be zero;
  93     UINT64  PageTableBaseAddress:31;  // Page Table Base Address
  94     UINT64  AvabilableHigh:11;        // Available for use by system software
  95     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
  96   } Bits;
  97   UINT64    Uint64;
  98 } PAGE_TABLE_ENTRY;
  99
 100 #pragma pack()
 101
 102
 103
 104 /**
 105   Allocates and fills in the Page Directory and Page Table Entries to
 106   establish a 1:1 Virtual to Physical mapping.
 107
 108   @param  NumberOfProcessorPhysicalAddressBits  Number of processor address bits
 109                                                 to use. Limits the number of page
 110                                                 table entries  to the physical
 111                                                 address space.
 112
 113   @return EFI_SUCCESS           The 1:1 Virtual to Physical identity mapping was created
 114
 115 **/
 116 UINTN
 117 CreateIdentityMappingPageTables (
 118   VOID
 119   );
 120
 121
 122
 123
 124
 125 /**
 126
 127   Fix up the vector number in the vector code.
 128
 129   @param VectorBase   Base address of the vector handler.
 130
 131   @param VectorNum    Index of vector.
 132
 133 **/
 134 VOID
 135 EFIAPI
 136 AsmVectorFixup (
 137   VOID    *VectorBase,
 138   UINT8   VectorNum
 139   );
 140
 141
 142
 143
 144
 145 /**
 146
 147   Get the information of vector template.
 148
 149   @param TemplateBase   Base address of the template code.
 150
 151   @return               Size of the Template code.
 152
 153 **/
 154 UINTN
 155 EFIAPI
 156 AsmGetVectorTemplatInfo (
 157   OUT   VOID  **TemplateBase
 158   );
 159
 160
 161 #endif