2 // Copyright (c) 2006, Intel Corporation
3 // All rights reserved. This program and the accompanying materials
4 // are licensed and made available under the terms and conditions of the BSD License
5 // which accompanies this distribution. The full text of the license may be found at
6 // http://opensource.org/licenses/bsd-license.php
8 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 // IPF CPU definitions
20 #ifndef _IPF_CPU_CORE_
21 #define _IPF_CPU_CORE_
24 // Include common header file for this module.
26 #include "CommonHeader.h"
28 #define PEI_BSP_STORE_SIZE 0x4000
30 #define MachineCheckFn 0x01
32 #define RecoveryFn 0x03
33 #define GuardBand 0x10
36 // Define hardware RSE Configuration Register
40 // RS Configuration (RSC) bit field positions
46 // RSC bits 5-15 reserved
49 #define RSC_MBZ0_V 0x3ff
51 #define RSC_LOADRS_LEN 14
53 // RSC bits 30-63 reserved
56 #define RSC_MBZ1_V 0x3ffffffffULL
65 #define RSC_MODE_LY (0x0)
69 #define RSC_MODE_SI (0x1)
73 #define RSC_MODE_LI (0x2)
77 #define RSC_MODE_EA (0x3)
80 // RSC Endian bit values
82 #define RSC_BE_LITTLE 0
86 // RSC while in kernel: enabled, little endian, pl = 0, eager mode
88 #define RSC_KERNEL ((RSC_MODE_EA<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
90 // Lazy RSC in kernel: enabled, little endian, pl = 0, lazy mode
92 #define RSC_KERNEL_LAZ ((RSC_MODE_LY<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
94 // RSE disabled: disabled, pl = 0, little endian, eager mode
96 #define RSC_KERNEL_DISABLED ((RSC_MODE_LY<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))